1
®
FN8215.2
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 |Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2005, 2008. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
X96011
Temperature Sensor with Look-Up Table
Memory and DAC
The X96011 is a highly integrated bias controller which
incorporates a digitally controlled Pro grammable Current
Generator and temperature compensation using one look-up
table. All functions of the device are controlled via a 2-wire
digital serial interface.
The temperature compensa ted Programmable Current
Generator varies the output current with temperature
according to the contents of the associated nonvolatile
look-up table. The look-up table may be programmed with
arbitrary data by the user, via the 2-wire serial port, and an
internal temperature sensor is used to control the output
current response.
Pinout X96011
(14 LD TSSOP)
TOP VIEW
Features
Single Programmable Current Generator
1.6mA Max.
- 8-bit (256 Step) Resolution
- Internally Programmable Full Scale Current Outputs
Internal Voltage Reference
Integrated 8-bit A/D Converter
Temperature Compensation
- Internal Sensor
- -40°C to +100°C R a ng e
- 2.2°C/step resolution
- EEPROM Look-up Table
Hot Pluggable
Write Protection Circuitry
- Intersil BlockLoc k™
- Logic Controlled Protection
2-wire Bus with 3 Slave Address Bits
3V to 5.5V, Single Supply Operation
Package
- 14 LD TSSOP
Pb-Free available (RoHS Compliant)
Applications
PIN Diode Bias Control
RF PA Bias Control
Temperature Compensated Process Control
Laser Diod e Bias C on tr ol
Fan Control
Motor Control
Sensor Signal Conditioning
Data Aquisition Applications
Gain vs Temperature Control
High Power Audio
Open Loop Temperature Compensation
Close Loop Current, Voltage, Pressure, Temperature,
Speed, Position Programmable Voltage Sources,
Electronic Loads, Output Amplifiers or Function Generator
Ordering Information
PART
NUMBER PART
MARKING TEMP
RANGE (°C) PACKAGE PKG.
DWG. #
X96011V14I X9601 1V I -40 to +100 14 Ld TSSOP M14.173
X96011V14IZ
(Note) X9601 1VIZ -40 to +100 14 Ld TSSOP
(Pb-free) M14.173
NOTE: These Intersil Pb-free plastic packaged products employ special
Pb-free material sets; molding compounds/die attach materials and 100%
matte tin plate PLUS ANNEAL - e3 termination finish, which is RoHS
compliant and compatible with both SnPb and Pb-free soldering
operations. Intersil Pb-free products are MSL classified at Pb-free peak
reflow temperatures that meet or exceed the Pb- f ree requirements of
IPC/JEDEC J STD-020.
VSS
A2
NC
NC
NC
VCC
A0
SCL
A1
WP
NC
NC
IOUT
SDA
1
2
3
4
5
6
7
14
13
12
11
10
9
8
Data Sheet February 25, 2008
2FN8215.2
February 25, 2008
Block Diagram
Pin Description
SDA
SCL
WP
2-WIRE
IOUT
INTERFACE
A2, A1, A0
DAC
ADC
LOOK-UP
TABLE
CONTROL
AND STATUS
MUX
MUX
TEMPERATURE
SENSOR
VOLTAGE
REFERENCE
PIN
NUMBER PIN
NAME DESCRIPTION
1A0Device Address Select Pin 0. This pin determines the LSB of the device address
required to communicate using the 2-wire interface. The A0 pin has an on-chip pull-down resistor.
2A1Device Address Select Pin 1. This pin determines the intermediate bit of the device address required to communicate
using the 2-wire interface. The A1 pin has an on-chip pull-down resistor.
3A2Device Address Select Pin 2. This pin determines the MSB of the device address required to communicate using the
2-wire interface. The A2 pin has an on-chip pull-down resistor.
4V
CC Supply Voltage.
5WPWrite Protect Control Pin. This pin is a CMOS compatible input. When LOW, Write Protection is enabled preventing
any “Write” operation. When HIGH, various areas of the memory can be protected using the Block Lock bits BL1 and
BL0. The WP pin has an on-chip pull-down resistor, which enables the Write Protection when this pin is left floating.
6SCLSerial Clock. This is a TTL compatible input pin. This input is the 2-wire interface clock controlling data input and output
at the SDA pin.
7SDASerial Data. This pin is the 2-wire interface data into or out of the device. It is TTL
compatible when used as an input, and it is Open Drain when used as an output. This pin requires an external pull up
resistor.
8I
OUT Current Generator Output. This pin sinks or sources current. The magnitude and direction of the current is fully
programmable and adaptive. The resolution is 8 bits.
9, 10,
12,13,14 NC No Connect.
11 VSS Ground.
X96011
3FN8215.2
February 25, 2008
Absolute Maximum Ratings Thermal Information
All voltages are referred to VSS.
Temperature under Bias . . . . . . . . . . . . . . . . . . . . . -65°C to +100°C
Storage temperature . . . . . . . . . . . . . . . . . . . . . . . -65°C to +150°C
Voltage on every pin except VCC . . . . . . . . . . . . . . . . . -1.0V to +7V
Voltage on VCC Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0mA to 5.5V
DC Output Current at pin SDA . . . . . . . . . . . . . . . . . . . 0mA to 5mA
DC Output Current at pins Iout . . . . . . . . . . . . . . . . . . . . . -3 to 3mA
Lead temperature (soldering, 10s) . . . . . . . . . . . . . . . . . . . . +300°C
Thermal Resistance (Typical, Note 1) θJA (°C/W)
14 Lead TSSOP . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Pb-free reflow profile. . . . . . . . . . . . . . . . . . . . . . . . . . see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Recommended Operating Conditions
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . -40°C to +100°C
Temperature While Writing to Memory . . . . . . . . . . . . .0°C to +70°C
Voltage on VCC Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3V to 5.5V
Voltage on any other Pin. . . . . . . . . . . . . . . . . . . . . . . . . VCC ± 0.3V
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
NOTE:
1. θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
Electrical Specifications All typical values are for +25°C ambient temperature and 5V at pin VCC. Maximum and minimum specifications
are over the recommended operating conditions. All voltages are referred to the voltage at pin VSS. Bit 7 in
control register 0 is “1”, while other bits in control registers are “0”. 400kHz TTL input at SCL. SDA pulled to VCC
through an external 2kΩ resistor. 2-wire interface in “standby” (Notes 2 and 3 ). WP, A0, A1, and A2 floating.
SYMBOL PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Iccstby Standby Current Into VCC Pin IOUT floating, sink mode 2 mA
Iccfull Full Operation Current Into VCC Pin 2-wire interface reading from
memory, Iout connected to VSS, DAC
input bytes: FFh
6mA
Iccwrite Nonvolatile Write Current Into VCC Pin Average from START condition until tWP
after the STOP condition
WP: Vcc, Iout floating, sink mode
VRef unloaded.
4mA
IPLDN On-chip Pull Down Current At Wp, A0,
A1,and A2 V(WP), V(A0), V(A1), and V(A2) from
0V to Vcc 012A
VILTTL Scl And Sda, Input Low
Voltage 0.8 V
VIHTTL Scl And Sda, Input High
Voltage 2.0 V
IINTTL Scl And Sda Input Current Pin voltage between 0 and VCC, and
SDA as an input. -1 10 µA
VOLSDA Sda Output Low Voltage I(SDA) = 2 mA 0 0.4 V
IOHSDA Sda Output High Current V(SDA) = VCC 0 100 µA
VILCMOS Wp, A0, A1, And A2 Input Low V oltage 0 0.2 x VCC V
VIHCMOS Wp, A0, A1, And A2 Input High
Voltage 0.8 x VCC VCC V
TSenseRange Temperature Sensor Range (Note 7) -40 100 °C
TSenseAccuracy Temperature Sensor Accuracy ±2 °C
VPOR Power-on Reset Threshold Voltage 1.5 2.8 V
VccRamp VCC Ramp Rate 0.2 50 mV/µs
VADCOK Adc Enable Minimum Voltage (Figure 8) 2.6 2.8 V
NOTES:
2. The device goes into Standby: 200 ns after any STOP, except those that initiate a nonvolatile write cycle. It goes into Standby tWC after a STOP
that initiates a nonvolatile write cycle. It also goes into St andby 9 clock cycles after any STAR T that is not followed by the correct Slave Address
Byte.
3. tWC is the time from a valid STOP condition at the end of a write sequence to the end of the self-timed internal nonvolatile write cycle. It is the
minimum cycle time to be allowed for any nonvolatile write by the user, unless Acknowledge Polling is used.
4. This parameter is periodically sampled and not 100% tested.
X96011
4FN8215.2
February 25, 2008
D/A Converter Characteristics (See pg. 5 for standard conditions)
SYMBOL PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
IFS Iout Full Scale Current DAC input Byte = FFh,
Source or sink mode, V(IOUT) is
VCC -1.2V in source mode and 1.2V in
sink mode.
(Notes 5, 6 )
1.56 1.58 1.6 mA
OffsetDAC Iout D/a Converter Offset Error 1 1 LSB
FSErrorDAC Iout D/a Converter Full Scale Error -2 2 LSB
DNLDAC Iout D/a Converter
Differential Nonlinearity -0.5 0.5 LSB
INLDAC Iout D/a Converter Integral
Nonlinearity With Respect To A S traight Line
Through 0 And The Full Scale Value
-1 1 LSB
VISink I1 Sink V oltage Compliance In this range the current at I1 vary < 1% 1.2 VCC V
VISource I1 Source V oltage Compliance In this range the current at I1 vary < 1% 0 VCC - 1.2 V
IOVER I1 Overshoot On D/a Converter Data Byte
Transition DAC input byte changing from 00h to
FFh and vice versa, V(I1) is VCC - 1.2V
in source mode and 1.2V in sink mode.
(Note 7)
A
IUNDER I1 Undershoot On D/a Converter Data Byte
Transition A
trDAC I1 Rise Time On D/a Converter Data Byte
Transition; 10% To 90% 530µs
TCOI1I2 Temperature Coefficient Of Output
Current Iout See Figure 5 ±200 ppm/°C
NOTES:
5. LSB is defined as divided by the resistance between R1 or R2 to Vss.
6. OffsetDAC: The Offset of a DAC is defined as the deviation between the measured and ideal output, when the DAC input is 01h. It is expressed
in LSB.
FSErrorDAC: The Full Scale Error of a DAC is defined as the deviation between the measured and ideal output, when the input is FFh. It is
expressed in LSB. The OffsetDAC is subtracted from the measured value before calculating FSErrorDAC.
DNLDAC: The Differential Non-Linearity of a DAC is defined as the deviation between the measured and ideal incremental change in the output
of the DAC, when the input changes by one code step. It is expressed in LSB. The measured values are adjusted for Offset and Full Scale Error
before calculating DNLDAC.
INLDAC: The Integral Non-Linearity of a DAC is defined as the deviation between the measured and ideal transfer curves, after adjusting the
measured transfer curve for Offset and Full Scale Error. It is expressed in LSB.
7. These parameters are periodically sampled and not 100% tested.
2
3
V(VRef)
255
x
[]
2-Wire Interface AC Characteristics
SYMBOL PARAMETER TEST CONDITIONS MIN TYP MAX UNITS
fSCL Scl Clock Frequency See Table 2-Wire Interface Test
Conditions on page 5
(Figure 1, 2 and 3)
1 (Note 10) 400 kHz
tIN
(Note 11) Pulse Width Suppression Time At
Inputs 50 ns
tAA
(Note 11) Scl Low To Sda Data Out Valid 900 ns
tBUF
(Note 11) Time The Bus Free Before Start Of New
Transmission 1300 ns
tLOW Clock Low Time 1.3 1200
(Note 10) µs
tHIGH Clock High Time 0.6 1200
(Note 10) µs
tSU:STA Start Condition Setup Time 600 ns
tHD:STA Start Condition Hold Time 600 ns
X96011
5FN8215.2
February 25, 2008
Timing Diagrams
tSU:DAT Data In Setup Time See Table 2-Wire Interface Test
Conditions on page 5
(Figure 1, 2 and 3)
100 ns
tHD:DAT Data In Hold Ti me s
tSU:STO Stop Condition Setup Time 600 ns
tDH Data Output Hold Time 50 ns
tR
(Note 11) Sda And Scl Rise Time 20 + 0.1Cb
(Note 8) 300 ns
tF
(Note 11) Sda And Scl Fall Time 20 + 0.1Cb
(Note 8) 300 ns
tSU:WP
(Note 11) Wp Setup Time 600 ns
tHD:WP
(Note 11) Wp Hold Time 600 ns
Cb
(Note 11) Capacitive Load For Each Bus Line 400 pF
2-Wire Interface AC Characteristics (Continued)
SYMBOL PARAMETER TEST CONDITIONS MIN TYP MAX UNITS
2-Wire Interface Test Conditions
Input Pulse Levels 10% to 90% of VCC
Input Rise and Fall Times, between 10% and 90% 10ns
Input and Output Timing Threshold Level 1.4V
External Load at pin SDA 2.3kΩ to VCC and 100pF to VSS
Nonvolatile WRITE Cycle Timing
SYMBOL PARAMETER TEST CONDITIONS MIN TYP MAX UNITS
tWC
(Note 9) Nonvolatile Write Cycle Time See Figure 3 5 10 ms
NOTES:
8. Cb = total capacitance of one bus line (SDA or SCL) in pF.
9. tWC is the time from a valid STOP condition at the end of a write sequence to the end of the self-timed internal nonvolatile write cycle. It is the
minimum cycle time to be allowed for any nonvolatile write by the user, unless Acknowledge Polling is used.
10. The minimum frequency requirement applies between a START and a STOP condition.
11. These parameters are periodically sampled and not 100% tested.
tSU:STO
tDH
tHIGH
tSU:STA tHD:STA
tHD:DAT
tSU:DAT
SCL
SDA IN
SDA OUT
tFtLOW
tBUF
tAA
tR
FIGURE 1. BUS TIMING
X96011
6FN8215.2
February 25, 2008
622
tHD:WP
SCL
SDA IN
WP
tSU:WP
CLK 1
START STOP
FIGURE 2. WP PIN TIMING
SCL
SDA
tWC
8TH BIT OF LAST BYTE ACK
STOP
CONDITION
START
CONDITION
FIGURE 3. NON-VOLATILE WRITE CYCLE TIMING
Intersil Sensor Conditioner Product Family
DEVICE TITLE
FEATURES/FUNCTIONS
INTERNAL
TEMPERATURE
SENSOR
EXTERNAL
SENSOR
INPUT
INTERNAL
VOLTAGE
REFERENCE
VREF
INPUT/
OUPUT
GENERAL
PURPOSE
EEPROM
LOOK-UP
TABLE
ORGANIZATION # OF
DACS
FSO
CURRENT
DAC
SETTING
RESISTORS
X96010 Sensor Conditioner
with Dual Look-Up
Table Memory and
DACs
No Yes Yes Yes No Dual Bank Dual Ext
X96011 Temperature
Sensor with Look-
Up Table Memory
and DAC
Yes No Yes No No Single Bank Single Int
X96012 Universal Sensor
Conditioner with
Dual Look-Up T able
Memory and DACs
Yes Yes Yes Yes Yes Dual Bank Dual Ext / Int
NOTE: FSO = Full Scale Output, Ext = External, Int = Internal
X96011
7FN8215.2
February 25, 2008
Device Description
The combination of the X96011 functionality and Intersil’s
QFN package lowers system cost, increases reliability, and
reduces board space requirements.
The on-chip Programmable Current Generator may be
independently programmed to either sink or source current.
The maximum current generated is determined by using an
externally connected programming resistor, or by selecting
one of three predefined values. Both current generators
have a maximum output of ±1.6 mA, and may be controlled
to an absolute resolution of 0.39% (256 steps/8 bit).
The current generator is driven us ing either an on-board
temperature sensor or control registe r s. The internal
temperature sensor operates over a very broad temperature
range (-40°C to +100°C). The sensor output drives an 8-bit
A/D converter. The six MSBs of the ADC output selects one
of 64 bytes from the nonvolatile look-up table (LUT).
The contents of the selected LUT row (8-bit wide) drives the
input of an 8-bit D/A converter, which generates the output
current. All control and setup parameters of the X96011,
including the look-up table, are programmable via the 2-wire
serial port.
Principles of Operation
Control and Status Registers
The Control and Status Registers provide the user with a
mechanism for changing and reading the value of various
parameters of the X96011. The X9 6011 contains five
Controls, one Status, and several Reserved registers, each
being one Byte wide (See Figure 4). The Control registers 0
through 6 are located at memory addresses 80h through 86h
respectively. The Status register is at memory address 87h,
and the Reserved registers at memory address 82h, 84h,
and 88h through 8Fh.
All bits in Control reg ister 6 always power-up to the logi c state
“0”. All bits in Control registers 0 through 5 powe r-up to the
logic state value kep t in their corresponding non vol atile
memory cells. The nonvolatile bits of a register ret ain their
stored values even when the X96011 is powered down, then
powered back up. The nonvolatile bit s in Control 0 through
Control 5 registers are all preprog rammed to the logic st ate “0”
at the factory, except the cases that indi cate “1” in Figure 1.
Bits indicated as “Reserved” are ignored when read, and
must be written as “0”, if any Write operation is performed to
their registers.
A detailed description of the function of each of the Control
and Status register bits follows.
Control Register 0
This register is accessed by performing a Read or Write
operation to address 80h of memory.
ADCFILTOFF: ADC FILTERING CONTROL
(NON-VOLATILE)
When this bit is “1”, the status register at 87h is updated after
every conversion of the ADC. When this bit is “0” (default),
the status register is updated after four consecutive
conversions with the same re sult, on the 6 MSBs.
NV13: CONTROL REGISTERS 1 AND 3 VOLATILITY
MODE SELECTION BIT (NON-VOLATILE)
When the NV13 bit is set to “0” (default), bytes written to
Control registers 1 and 3 are stored in volatile cells, and their
content is lost when the X96011 is powered down. When the
NV13 bit is set to “1”, bytes written to Control registers 1 and
3 are stored in both volatile and nonvolatile cells, and their
value doesn’t change when the X96011 is powered down
and powered back up. See “Writing to Control Registers” on
page 16.
IDS: CURRENT GENERATOR DIRECTION SELECT BIT
(NON-VOLATILE)
The IDS bit sets the polarity of the Current Generator . When
this bit is set to “0” (default), the Current Generator of the
X96011 is configured as a Current Source. The Current
Generator is configured as a Current Sink when the IDS bit
is set to “1”. See Figure 5.
X96011
8FN8215.2
February 25, 2008
BYTE MSB LSB
80h
REGISTER
CONTROL 0
00IDS NV131 ADCfiltOff 0 0
NON-VOLATILE
81h CONTROL 1
VOLATILE OR RESERVED RESERVED LDA5 LDA4 LDA3 LDA2 LDA1 LDA0
83h CONTROL 3
VOLATILE OR DDA7 DDA6 DDA5 DDA4 DDA3 DDA2 DDA1 DDA0
NON-VOLATILE
NON-VOLATILE
85h CONTROL 5
NON-VOLATILE 0 0 DDAS LDAS 0 0 IFSO1 IFSO 0
86h CONTROL 6
VOLATILE WEL RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED
87H STATUS
VOLATILE AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0
7654321 0NAME
ADDRESS
REGISTERS IN BYTE ADDRESSES 82H, 84H, AND 88H THROUGH 8FH ARE RESERVED.
DIRECT ACCESS TO THE LUT
DIRECT ACCESS TO THE DAC
ADC OUTPUT
Iout
0: Source
1: Sink
CONTROL
1, 3
VOLATILITY
0: VOLATILE
1: NON-
VOLATILE
Direct Direct
Access
to dac
Access
to lut
0: Disabled 0: Disabled
1: Enabled 1: Enabled
R Selection
00: Reserved
01: Low Internal
10: Middle Internal
11: High Internal (Default)
Write Enable
Latch
0: Write
Disabled
1: Write
Enabled
ADC
0: On
1: Off
filtering
Direction
REGISTERS BITS SHOWN AS 0 OR 1 SHOULD ALWAYS USE THESE VALUES FOR PROPER OPERATION.
FIGURE 4. CONTROL AND STATUS REGISTER FORMULA
X96011
9FN8215.2
February 25, 2008
Control Register 1
This register is accessed by performing a Read or Write
operation to address 81h of memory. This byte’s volatility is
determined by bit NV13 in Control register 0.
LDA5 - LDA0: LUT DIRECT ACCESS BITS
When bit LDAS (bit 4 in Control register 5) is set to “1”, the LUT
is addressed by these six bits, and it is not addressed by the
output of the on-chip A/D converter . When bit LDAS is set to
“0”, these six bits are ignored by the X96011. See Figure 7.
A value between 00h (0010) and 3Fh (6310) may be written to
these register bits, to select the corresponding row in the
LUT. The written value is added to the base address of the
LUT (90h).
Control Register 3
This register is accessed by performing a Read or Write
operation to address 83h of memory. This byte’s volatility is
determined by bit NV13 in Control register 0.
DDA7 - DDA0: D/A DIRECT ACCESS BITS
When bit DDAS (bit 5 in Control register 5) is set to “1”, the
input to the D/A converter is the content of bits DDA7-DDA0,
and it is not a row of LUT. When bit DDAS is set to “0” (default)
these eight bits are ignored by the X96011. See Figure 6.
Control Register 5
This register is accessed by performing a Read or Write
operation to address 85h of memory.
IFSO1 - IFSO0: CURRENT GENERATOR FULL SCALE
OUTPUT SET BITS (NON-VOLATILE)
These two bits are used to set the full scale output current at
the Current Generator pin, Iout, according to the following
table. The direction of this current is set by bit IDS in Control
register 0. See Figure 5.
LDAS: LUT DIRECT ACCESS SELECT BIT
(NON-VOLATILE)
When bit LDAS is set to “0” (default), the LUT is addressed
by the output of the on-chip A/D converter . When bit LDAS is
set to “1”, LUT is addressed by bits LDA5 - LDA0.
DDAS: D/A DIRECT ACCESS SELECT BIT
(NON-VOLATILE)
When bit DDAS is set to “0” (default), the input to the D/A
converter is a row of the LUT. When bit DDAS is set to “1”,
that input is the content of the Control register 3.
Control Register 6
This register is accessed by performing a Read or Write
operation to address 86h of memory.
WEL: WRITE ENABLE LATCH (VOLATILE)
The WEL bit controls the Write Enab le st a tus of the en tire
X96011 device. This bit must be set to “1” before any other
Write operation (volatile or nonvolatil e). Otherwise, an y
proceeding Wr ite operation to memory is aborted and no ACK
is issued after a Data Byte.
The WEL bit is a volatile latch that powers up in the “0”
state (disabled). The WEL bit is enabled by writing
100000002 to Control register 6. Once enabled, the WEL
bit remains set to “1” until the X96011 is powered down,
and then up again, or until it is reset to “0” by writing
000000002 to Control register 6.
A Write operation that modifies the value of the WEL bit will not
cause a change i n other bit s of Control register 6.
S tatus Register - ADC Output
This register is accessed by performing a Read operation to
address 87h of memory.
AD7 - AD0: A/D CONVERTER OUTPUT BITS (READ
ONLY)
This byte is the binary output of the on-chip digital
thermometer. The output is 000000002 for -40°C and
111111112 for +100°C. The six MSBs select a row of the LUT.
Look-Up Table
The X96011 memory array contains a 64-byte look-up table.
The look-up table is associated to pin Iout’s output current
generator through the D/A converter . The output of the look-up
table is the byte contained in the selected row. By default this
byte is the input to the D/A converter driving pin IOUT.
The byte address of the selected row is obtained by adding
the look-up table base address 90h, and the appropriate row
selection bits. See Figure 6.
By default the look-up table selection bits are the 6
MSBs of the digital thermometer output. Alternatively, the
A/D converter can be bypassed and the six row selection
bits are the six LSBs of Control Register 1 for the LUT.
The selection between the se options is illustrated in
Figure 6.
Current Generator Block
The Current Generator pin Iout is the output of the current
mode D/A converter.
D/A Converter Operation
The Block Diagram for the D/A converter is shown in
Figure 5.
The input byte of the D/A converter selects a voltage on the
non-inverting input of an operational amplifier. The output of
the amplifier drives the gate of a FET. This node is also fed
back to the inverting input of the amplifier. The drain of the
FET is connected to the output current pin (IOUT) via a
“polarity select” circuit block.
I1FSO1 I1FSO0 I1 Full Scale Output Current
0 0 Reserved (Don’t Use)
01 ±0.4mA
10 ±0.85 mA
11 ±1.3 mA (Default)
X96011
10 FN8215.2
February 25, 2008
+
-
IOUT PIN
IDS: BIT
VSS VSS
IFSO[1:0]
LOW_CURRENT
MIDDLE_CURRENT
HIGH_CURRENT
INTERNAL
SELECT
CIRCUIT
POLARITY
VCC
VOLTAGE
6 IN CONTROL
REGISTER 0.
DIVIDER
DAC
INPUT BYTE
VSS
BITS 1 AND 0
IN CONTROL
REGISTER 5
11
10 01
REFERENCE
VOLTAGE
FIGURE 5. D/A CONVERTER BLOCK DIAGRAM
DAC
8
90h 90h
CFh
8
LUT
6
LUT Row
Out
D1
D0
Select
DDAS: Bit 5 of
DDA[7:0] : Control register 3
Selection bits A
D
D
E
R
8
8
Input Byte
Control register 5
FIGURE 6. LOOK-UP TABLE (LUT) OPERATION
D1
D0
SELECT
ADC
AD[7:0]
LUT ROW
VOLTAGE
VOLTAGE INPUT SELECTION BITS
REFERENCE
OUT
LDA[5:0]:
CONTROL
REGISTER 1
LDAS: BIT 4 IN
CONTROL REGISTER 5
6
6
STATUS
REGISTER
8
FROM INTERNAL
TEMPERATURE
SENSOR
FIGURE 7. LOOK-UP TABLE ADDRESSING
X96011
11 FN8215.2
February 25, 2008
By examining the block diagram in Figure 5, we see that the
maximum current through pin IOUT is set by fixing values for
V(VRef) and R. The output current can then be varied by
changing the data byte at the D/A converter input.
In general, the magnitude of the current at the D/A converter
output pin may be calculated by Equation 1:
where N is the decimal representation of the input byte to the
corresponding D/A converter.
The value for the resistor determines the full scale output
current that the D/A converter may sink or source. Bits
IFSO1 and IFSO 0 sel e ct th e fu l l scale output current setting
for Iout as described in “IFSO1 - IFSO0: Current Generator
Full Scale Output Set Bits (Non-volatile)” on page 9.
Bit IDS and in control register 0 select the direction of the
currents through pins Iout (See “IDS: Current Generator
Direction Select Bit (Non-volatile)” on page 7, and )“The IDS
bit sets the polarity of the Current Generator. When this bit is
set to “0” (default), the Current Generator of the X96011 is
configured as a Current Source. The Current Generator is
configured as a Current Sink when the IDS bit is set to “1”.
See Figure 5.”
D/A Converter Output Current Response
When the D/A converter input data byte changes by an
arbitrary number of bits, the output current changes from an
intial current level (Ix) to some final level (Ix+ΔIx). The
transition is monotonic and glitchless.
D/A Converter Control
The data byte inputs of the D/A converters can be controlled
in three ways:
1) With the A/D converter an d through the look-up tables
(default)
2) Bypassing the A/D converter and directly accessing the
look-up tables
3) Bypassing both the A/D converter and look-up tables, and
directly setting the D/A converter input byte
The options are summarized in Table 1.
Bit DDAS is used to bypass the A/D converter and look-up
table, allowing direct access to the input of the D/A converter
with the byte in control register 3. See Figure 6, and the
descript io n s of th e co nt rol bits.
Bit IDS in Control Register 0 select the direction of the
current through pin Iout. See Figure 5, and the descriptions
of the control bits.
Power-on Reset
When power is applied to the VCC pin of the X9601 1, the device
undergoes a strict sequence of events before the current
outputs of the D/A converters are enabled.
When the voltage at VCC becomes larger than the power-on
reset threshold voltage (VPOR), the device recalls all control
bits from non-volatile memory into volatile registers. Next,
the analog circuits are powered up. When the voltage at VCC
becomes larger than a second voltage threshold (VADCOK),
the ADC is enabled. In the default case, after the ADC
performs four consecutive conversions with the same exact
result, the ADC output is used to select a byte from the
look-up table. The byte becomes the input of the DAC.
During all the previous sequence the input of the DAC is
00h. If bit ADCfiltOff is “1”, only one ADC conversion is
necessary. Bit DDAS and LDAS, also modify the way the
DAC is accessed the first time after power-up, as described
in “Control Register 5” on page 9.
The X96011 is a hot pluggable device. V oltage distrubances
on the VCC pin are handled by the power-on reset circuit,
allowing proper operation during hot plug-in applications.
Serial Interface
Serial Interface Conventions
The device supports a bidirectional bus oriented protoco l.
The protocol defines any device that sends data onto the
bus as a transmitter, and the receiving device as the
receiver. The device controlling the transfer is called the
master and the device being controlled is called the slave.
The master always initiates data transfers, and provides the
clock for both transmit and receive operations. The X96011
operates as a slave in all applications.
Serial Clock and Data
Data states on the SDA line can change only while SCL is
LOW. SDA state changes while SCL is HIGH are reserved
for indicating START and STOP conditions. See Figure 10.
On power-up of the X96011, the SDA pin is in the input
mode.
Serial Start Condition
All commands are preceded by the START condition, which
is a HIGH to LOW transition of SDA while SCL is HIGH. The
device continuously monitors the SDA and SCL lines for the
START condition and does not respond to any command
until this condition has been met. See Figure 9.
TABLE 1. D/A CONVERTER ACCESS SUMMARY
LDAS DDAS CONTROL SOURCE
0 0 A/D converter through LUT
(Default)
1 0 Bits LDA5 - LDA0 through LUT
X 1 Bits DDA7 - DDA0
“X” = Don’t Care Condition (May be either “1” or “0”)
I = (V(VRef) / (384 * R)) *N (EQ. 1)
X96011
12 FN8215.2
February 25, 2008
Serial Stop Condition
All communications must be terminated by a STOP
condition, which is a LOW to HIGH transition of SDA while
SCL is HIGH. The STOP condition is also used to place the
device into the S tandby power mode after a read sequence.
A STOP condition can only be issued after the transmitting
device ha s rel e a s ed th e bu s. See Figure 9.
Serial Acknowledge
An ACK (Acknowledge), is a software convention used to
indicate a successful data transfer. The transmitting device,
either master or slave, releases the bus after transmitting
eight bits. During the ninth clock cycle, the receiver pulls the
SDA line LOW to acknowledge the reception of the eight bits
of dat a. See Figure 11.
The device responds with an ACK after recognition of a
START condition followed by a valid Slave Address byte. A
valid Slave Address byte must contain the Device Type
Identifier 1010, and the Device Address bits matching the
logic state of pins A2, A1, and A0. See Figure 13.
If a write operation is selected, the device responds with an
ACK after the receipt of each subsequent eight-bit word.
In the read mode, the device transmits eight bits of data,
releases the SDA line, and then monito rs the line for an
ACK. The device continues transmitting data if an ACK is
detected. The device terminates further data transmissions if
an ACK is not detected. The master must then issue a STOP
condition to place the device into a known state.
1. The X96011 acknowledg es all incoming data and
address bytes except: 1) The “Slave Address Byte” when
the “Device Identifier” or “Device Address” are wrong; 2)
All “Data Bytes” when the “WEL” bit is “0”, with the
exception of a “Data Byte” addresses to location 86h; 3)
“Data Bytes” following a “Data Byte” addressed to
locations 80h, 85h, or 86h.
Ix
IX X 10%
ADC TIME
CURRENT
TIME
TIME
VCC
VADCOK
0V
VOLTAGE
FIGURE 8. CONVERTER POWER-ON RESET RESPONSE
X96011
13 FN8215.2
February 25, 2008
SCL
SDA
START STOP
FIGURE 9. VALID START AND STOP CONDITIONS
SCL
SDA
DATA STABLE DATA CHANGE DATA STABLE
FIGURE 10. VALID DATA CHANGES ON THE BUS
SDA OUTPUT FROM
TRANSMITTER
SDA OUTPUT FROM
RECEIVER
81 9
START ACK
SCL FROM
MASTER
FIGURE 11. ACKNOWLEDGE RESPONSE FROM RECEIVER
X96011
14 FN8215.2
February 25, 2008
X96011 Memory Map
The X96011 contains a 80 byte array of mixed volatile and
nonvolatile memory. This array is split up into two distinct
parts, namely: (Refer to Figure 12).
Look-up Table (LUT)
Control and Status Registe rs
The Control and Status registers of the X96011 are used in
the test and setup of the device in a system. These registers
are realized as a combination of both volatile and nonvolatile
memory. These registers reside in the memory locations 80h
through 8Fh. The reserved bits within registers 80h through
86h, must be written as “0” if writing to them, and should be
ignored when reading. Register bits shown as 0 or 1, in
Figure 4, must be written with the indicated value if writing to
them. The reserved registers, 82h, 84h, and from 88h
through 8Fh, must not be written, and their con ten t should
be ignored.
The LUT is realized as nonvolatile EEPROM, and extend
from memory locations 90h–CFh. This LUT is dedicated to
storing data solely for the purpose of setting the outputs of
Current Generators IOUT.
All bits in the LUT are preprogrammed to “0” at the factory.
Addressing Protocol Overview
All Serial Interface operations must begin with a START,
followed by a Slave Address Byte. The Slave ad dress
selects the X96011, and specifies if a Read or Write
operation is to be performed.
It should be noted that the Write Enable Latch (WEL) bit
must first be set in order to perform a Write operation to any
other bit. See “WEL: Write Enable Latch (Volatile)” on
page 9. Also, all communication to the X96011 over the
2-wire serial bus is conducted by sending the MSB of each
byte of data first.
The memory is physically realized as one contiguous array,
organized as 5 pages of 16 bytes each.
The X96011 2-wire protocol provides one address byte. The
next few sections explain how to access the different areas
for reading and writing.
Slave Address Byte
Following a START condition, the master must output a
Slave Address Byte (Refer to Figure 13). This byte includes
three parts:
The four MSBs (SA7 - SA4) are the Device Type
Identifier, which must always be set to 1010 in order to
select the X96011.
The next three bits (SA3 - SA1) are the Device Address
bits (AS2 - AS0). To access any part of the X96011’s
memory, the value of bits AS2, AS1, and AS0 must
correspond to the logic levels at pins A2, A1, and A0
respectively.
The LSB (SA0) is the R/W bit. This bit defines the
operation to be performed on the device being addressed.
When the R/W bit is “1”, then a Read operation is
selected. A “0” selects a Write operation
(Refer to Figure 13)
Nonvolatile Write Acknowledge Polling
After a nonvolatile write command sequence is correctly
issued (including the final STOP condition), the X96011
initiates an internal high voltage write cycle. This cycle
typically requires 5ms. During this time, any Read or Write
command is ignored by the X96011. Write Acknowledge
Polling is used to determine whether a high voltage write
cycle is completed.
During acknowledge polling, the master first issues a ST ART
condition followed by a Slave Address Byte. The Slave
Address Byte contains the X96011’s Device Type Identifier
and Device Address. The LSB of the Slave Address (R/W)
can be set to either 1 or 0 in this case. If the device is busy
within the high voltage cycle, then no ACK is returned. If the
high voltage cycle is completed, an ACK is returned and the
master can then proceed with a new Read or Write
operation. (Refer to Figure 14)
ADDRESS SIZE
64 Bytes
16 Bytes
80h
8Fh
90h
CFh LOOK-UP TABLE
(LUT)
CONTROL AND STATUS
REGISTERS
FIGURE 12. X96011 MEMORY MAP
SA6SA7 SA5 SA3 SA2 SA1 SA0
Device Type
Identifier
Read or
SA4
SLAVE ADDRESS
BIT(s) DESCRIPTION
SA7 - SA4 Device Type Identifier
SA3 - SA1 Device Address
R/W1010
Address
Device
AS0AS1AS2
Write
FIGURE 13. SLAVE ADDRESS (SA) FORMAT
X96011
15 FN8215.2
February 25, 2008
Byte Write Operation
In order to perform a Byte Write operation to the memory
array, the Write Enable Latch (WEL) bit of the Control 6
Register must first be set to “1”. See “WEL: Write Enable
Latch (Volatile)” on page 9.
For any Byte Write operation, the X96011 requires the Slave
Address Byte, an Address Byte, and a D at a Byte (See Figu re
15). After each of them, the X9 6011 responds with an ACK.
The master then terminates the transfer by generating a
STOP condition. At this time, if all data bit s are volatil e, the
X96011 is ready for the next read or write operation. If some
bits are nonvolatile, the X960 11 begins the internal writ e cycle
to the nonvolatile memory . During the internal nonvolatile write
cycle, the X96011 does not respond to any requests from the
master. The SDA output is at high impedance.
Writing to Control bytes which are located at byte addresses
80h through 8Fh is a special case described in the section
“Writing to Control Registers” .
ACK RETURNED?
ISSUE SLAVE
ADDRESS BYTE
(READ OR WRITE)
BYTE LOAD COMPLETED BY
ISSUING STOP. ENTER ACK POLLING
ISSUE “STOP
ISSUE “START”
NO
YES
NO
CONTINUE NORMAL READ OR
WRITE COMMAND SEQUENCE
PROCEED
YES
COMPLETE. CONTINUE COMMAND
SEQUENCE.
HIGH VOLTAGE
ISSUE “STOP”
FIGURE 14. ACKNOWLEDGE POLLING SEQUENCE
S
T
A
R
T
S
T
O
P
SLAVE
ADDRESS ADDRESS
BYTE DATA
BYTE
A
C
K
SIGNALS FROM
the MASTER
SIGNALS FROM
THE SLAVE A
C
K
10
100
A
C
K
WRITE
SIGNAL AT SDA
FIGURE 15. BYTE WRITE SEQUENCE
X96011
16 FN8215.2
February 25, 2008
Page Write Operation
The 80-byte memory array is physically realized as one
contiguous array, organized as 5 pages of 16 bytes each. A
“Page Write” operation can be performed to any of the four
LUT pages. In order to perform a Page Write operation, the
Write Enable Latch (WEL) bit in Control register 6 must first
be set (See “WEL: Write Enable Latch (Volatile )” on page 9.)
A Page Write operation is initiated in the same manner as
the byte write operation; but instead of terminating the write
cycle after the first data byte is transferred, the master can
transmit up to 16 bytes (See Figure 16). After the receipt of
each byte, the X96011 responds with an ACK, and the
internal byte address counter is incremented by one. The
page address remains constant. When the counter reaches
the end of the page, it “rolls over” and goes back to the first
byte of the same page.
For example, if the master writes 12 bytes to a 16-byte page
starting at location 11 (decimal), the first 5 bytes are written
to locations 11 through 15, while the last 7 bytes are written
to locations 0 through 6 within that page. Afterwards, the
address counter would point to location 7. If the master
supplies more than 16 bytes of data, then new data
overwrites the previous data, one byte at a time.
(See Figure 17).
The master terminates the loading of Data Bytes by issuing
a STOP condition, which initiates the nonvolatile write cycle.
As with the Byte Write operation, all inputs are disabled until
completion of the internal write cycle.
A Page Write operation cannot be performed on the page at
locations 80h through 8F h. The next section describes the
special cases within that page.
Writing to Control Registers
The bytes at locations 80h, 81h , 83h, 85h, and 86h are
written using Byte Write operations. They cannot be written
using a Page Write operation.
Registers Control 1 and 3 have a nonvolatile an d a volatile cell
for each bit. At power-up, the content of the n onvolatile cells is
automatically recalled and written to the volatile cells. The
content of the volatile ce lls controls the X96011’s fun ctionality.
If bit NV13 in the Control 0 register is set to “1”, a Write
operation to these registers writes to both the volatile and
nonvolatile cells. If bit NV13 in the Control 0 register is set to
“0”, a Write operatio n to these registe rs only writes to the
volatile cells. In both cases the newly written values ef fectively
control the X96011, but in the second case , those value s are
lost when the part is p owered down.
If bit NV13 is set to “0”, a Byte Write operation to Control
registers 0 or 5 causes the value in the nonvolatile cells of
Control registers 1 and 3 to be recalled into their
corresponding volatile cells, as during power-up. This
doesn’t happen when the WP pin is LOW, because Write
Protection is enabled. It is generally recommen ded to
configure Control registers 0 and 5 before writing to Control
registers 1 or 3.
2 < n < 16
SIGNALS FROM
THE MASTER
SIGNALS FROM
THE SLAVE
SIGNAL AT SDA
S
T
A
R
T
SLAVE
ADDRESS
ADDRESS
BYTE
A
C
K
A
C
K
10
100
DATA BYTE (1)
S
T
O
P
A
C
K
A
C
K
DATA BYTE (n)
WRITE
FIGURE 16. PAGE WRITE OPERATION
5 bytes
7 BYTES
ADDRESS = 6
5 BYTES
ADDRESS POINTER
ADDRESS = 15
ADDRESS = 11
ENDS UP HERE
ADDRESS = 7
ADDRESS = 0
FIGURE 17. EXAMPLE: WRITING 12 BYTES TO A 16-BYTE PAGE STARTING AT LOCATION 11.
X96011
17 FN8215.2
February 25, 2008
A “Byte Write” operation to Control register 1 or 3, causes
the value in the nonvolatile cells of the other to be recalled
into the corresponding volatile cells, as during power-up.
When reading either of the control registers 1 or 3, the Data
Bytes are always the content of the corresponding
nonvolatile cells, even if bit NV13 is “0” (Figure 5).
Read Operation
A Read operation consist of a three byte instruction followed
by one or more Data Bytes (See Figure 18). The master
initiates the operation issuing the following sequence: a
START, the Slave Address byte with the R/W bit set to “0”,
an Address Byte, a second START, and a second Sl ave
Address byte with the R/W bit set to “1”. After each of the
three bytes, the X96011 responds with an ACK. Then the
X96011 transmits Data Bytes as long as the master
responds with an ACK during the SCL cycle following the
eigth bit of each byte. The master terminates the read
operation (issuing a STOP condition) following the last bit of
the last Data Byte (Figure 18).
The Data Bytes are from the memory location indicated by
an internal pointer . This pointer initial value is determined by
the Address Byte in the Read operation instruction, and
increments by one during transmission of each Data Byte.
After reaching the memory location CFh a stop should be
issued. If the read operation continues the output bytes are
unpredictable. If the byte address is set between 00h and
7Fh, or higher than CFh, the output bytes are unpredictable.
A Read operation internal pointer can start at any memory
location from 80 h through CFh, when the Address Byte is
80h through CFh respectively.
When reading any of the control registers 1, 2, 3, or 4, the
Data Bytes are always the content of the corresponding
nonvolatile cells, even if bit NV13 is "0". See “IDS: Current
Generator Direction Select Bit (Non-volatile)”. See Figure 5.
Data Protection
There are three levels of data protection designed into the
X96011: 1- Any Write to the device first requires setting of
the WEL bit in Control 6 register; 2- The Write Protection pin
disables any writing to the X9601 1; 3- The proper clock count,
data bit sequence, and STOP condition is required in order to
start a nonvolatile write cycle, otherwise the X96011 ignores
the Write operation.
WP: Write Protection Pin
When the Write Protection (WP) pin is active (LOW), any
Write operations to the X96011 is disabled, except the
writing of the WEL bit. See
SIGNALS
FROM THE
MASTER
SIGNALS FROM
THE SLAVE
SIGNAL AT
SDA
S
T
A
R
T
SLAVE
ADDRESS
WITH
R/W = 0 ADDRESS
BYTE
A
C
K
A
C
K
10
100
S
T
O
P
A
C
K
11
100
SLAVE
ADDRESS
WITH
R/W = 1
A
C
K
S
T
A
R
T
LAST READ
DATA BYTE
FIRST READ
DATA BYTE
A
C
K
FIGURE 18. READ SEQUENCE
X96011
18
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Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
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For information regarding Intersil Corporation and its products, see www.intersil.com
FN8215.2
February 25, 2008
X96011
Thin Shrink Small Outline Plastic Packages (TSSOP)
α
INDEX
AREA E1
D
N
123
-B-
0.10(0.004) C AMBS
e
-A-
b
M
-C-
A1
A
SEATING PLANE
0.10(0.004)
c
E0.25(0.010) BM M
L
0.25
0.010
GAUGE
PLANE
A2
NOTES:
1. These package dimensions are within allowable dimensions of
JEDEC MO-153-AC, Issue E.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm
(0.006 inch) per side.
4. Dimension “E1” does not include interlead flash or protrusions. Inter-
lead flash and protrusions shall not exceed 0.15mm (0.006 inch) per
side.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. Dimension “b” does not include dambar protrusion. Allowable dambar
protrusion shall be 0.08mm (0.003 inch) total in excess of “b” dimen-
sion at maximum material condition. Minimum space between protru-
sion and adjacent lead is 0.07mm (0.0027 inch).
10. Controlling dimension: MILLIMETER. Converted inch dimensions
are not necessarily exact. (Angles in degrees)
0.05(0.002)
M14.173
14 LEAD THIN SHRINK SMALL OUTLINE PLASTIC
PACKAGE
SYMBOL
INCHES MILLIMETERS
NOTESMIN MAX MIN MAX
A - 0.047 - 1.20 -
A1 0.002 0.006 0.05 0.15 -
A2 0.031 0.041 0.80 1.05 -
b 0.0075 0.0118 0.19 0.30 9
c 0.0035 0.0079 0.09 0.20 -
D 0.195 0.199 4.95 5.05 3
E1 0.169 0.177 4.30 4.50 4
e 0.026 BSC 0.65 BSC -
E 0.246 0.256 6.25 6.50 -
L 0.0177 0.0295 0.45 0.75 6
N14 147
α0o8o0o8o-
Rev. 2 4/06