HEF4516BTD-T - NXP Semiconductors / Philips Semiconductors

1. General description

The HEF4516B is an edge-triggered synchro nous 4-bit binary up/down counter with a

clock input (CP), an up/down count control input (UP/DN), an active LOW count enable

input (CE), an asynchronous active HIGH parallel load input (PL), four parallel inputs

(D0 to D3), four parallel ou tputs (Q0 to Q3), an active LOW terminal count output (TC),

and an overriding asynchronous master reset input (MR).

Information on D0 to D3 is loaded into the counter while PL is HIGH, independent of all

other input conditions except for MR which must be LOW. When PL and CE are LOW , the

counter chan ge s on the LOW-to-HIG H transition of CP. Input UP/DN determines the

direction of the co unt, counting up when HIGH an d coun tin g do wn whe n LO W. When

counting up, TC is LOW when Q0 and Q3 are HIGH and CE is LOW. When counting

down, TC is LOW when Q0 to Q3 and CE are LOW. A HIGH on MR resets the counte r

(Q0 to Q3 = LOW) independent of all other input conditions.

It operates over a recommended VDD power supply r ange of 3 V to 15 V referenced to VSS

(usually ground). Unused inputs must be connected to VDD, VSS, or another input. It is

also suitable for use over the full industrial (−40 °C to +85 °C) temperature range.

2. Features

Fully static operation

5 V, 10 V, and 15 V parametric ratings

Standardized symmetrical output characteristics

Operates across the full industrial temperature range −40 °C to +85 °C

Complies with JEDEC standard JESD 13-B

3. Applications

Industrial

4. Ordering information

HEF4516B

Binary up/down counter

Rev. 06 — 11 December 2009 Product data sheet

Table 1. Ordering information

All types operate from

−

C to +85

Type number Package

Name Description Version

HEF4516BP DIP16 plastic dual in-line package; 16-leads (300 mil) SOT38-4

HEF4516BT SO16 plastic small outline package; 16 leads; body width 3.9 mm SOT109-1

Product data sheet Rev. 06 — 11 December 2009 2 of 16

NXP Semiconductors HEF4516B

Binary up/down counter

5. Functional diagram

Fig 1. Functional di agram

001aae66

D0 D1 D2

PARALLEL LOAD CIRCUITRY

Q0 Q1 Q2 Q3

412133

611142

CP S

UP/DOWN

COUNTER

UP/DN

Product data sheet Rev. 06 — 11 December 2009 3 of 16

NXP Semiconductors HEF4516B

Binary up/down counter

Fig 2. Logic diag ram

FF1

UP/DN

001aaj79

FF2

FF3

FF4

Product data sheet Rev. 06 — 11 December 2009 4 of 16

NXP Semiconductors HEF4516B

Binary up/down counter

6. Pinning information

6.1 Pinning

6.2 Pin description

Fig 3. Pin configuratio n

HEF4516B

PL VDD

Q3 CP

D3 Q2

D0 D2

CE D1

Q0 Q1

TC UP/DN

VSS MR

001aae689

Table 2. Pin description

Symbol Pin Description

PL 1 parallel load input (active HIGH)

D0 to D3 4, 12, 13, 3 parallel input

CE 5 count enable input (active LOW)

Q0 to Q3 6, 11, 14, 2 parallel output

VSS 8 ground supply voltage

TC 7 terminal count output (active LOW)

MR 9 master reset input

UP/DN 10 up/down coun t co ntrol input

CP 15 clock pulse input (LOW to HIGH, edge triggered)

VDD 16 supply voltage

Product data sheet Rev. 06 — 11 December 2009 5 of 16

NXP Semiconductors HEF4516B

Binary up/down counter

7. Functional description

[1] H = HIGH voltage level; L = LOW voltage level; X = don’t care; ↑ = positive-going transition.

Table 3. Function table[1]

MR PL UP/DN CE CP MODE

LHXXXparallel load

L L X H X no change

LLLL↑count down

LLHL↑count up

HXXXXreset

Fig 4. Timing diagram

001aae693

UP/DN

D0 V

5678910111213141598765432100150

count

Product data sheet Rev. 06 — 11 December 2009 6 of 16

NXP Semiconductors HEF4516B

Binary up/down counter

8. Limiting values

[1] For DIP16 package: Ptot derates linearly with 12 mW/K above 70 °C.

[2] For SO16 package: Ptot derates linearly with 8 mW/K above 70 °C.

9. Recommended operating conditions

Logic equation for terminal count:

Fig 5. State diagram

001aae69

count up

count down

1 2 3 4

11 10 9 8

TC CE UP DN⁄()Q0•Q1•Q2•Q3•UP DN⁄()Q0•Q1•Q2 Q3••+{}•=

Table 4. Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).

Symbol Parameter Conditions Min Max Unit

VDD supply voltage −0.5 +18 V

IIK input clamping current VI<−0.5 V or VI>V

DD + 0.5 V - ±10 mA

VIinput voltage −0.5 VDD + 0.5 V

IOK output clamping current VO<−0.5 V or VO>V

DD + 0.5 V - ±10 mA

II/O input/output current - ±10 mA

IDD supply current - 50 mA

Tstg storage temperature −65 +150 °C

Tamb ambient temperature −40 +85 °C

Ptot tota l po wer di ssi pation DIP16 package [1] - 750 mW

SO16 package [2] - 500 mW

P power dissipation per output - 100 mW

Table 5. Recommended operating con ditions

Symbol Parameter Conditions Min Typ Max Unit

VDD supply voltage 3 - 15 V

VIinput voltage 0 - VDD V

Tamb ambient temperature in free air −40 - +85 °C

Product data sheet Rev. 06 — 11 December 2009 7 of 16

NXP Semiconductors HEF4516B

Binary up/down counter

10. Static characteristics

Δt/ΔV input transition rise and fall rate VDD = 5 V - - 3.75 μs/V

VDD = 10 V - - 0.5 μs/V

VDD = 15 V - - 0.08 μs/V

Table 5. Recommended operating con ditions …continued

Symbol Parameter Conditions Min Typ Max Unit

Table 6. Static characteristics

VSS = 0 V; VI = VSS or VDD unless otherwise specified.

Symbol Parameter Conditions VDD Tamb = −40 °C Tamb = 25 °C Tamb = 85 °CUnit

Min Max Min Max Min Max

VIH HIGH-level input voltage |IO| < 1 μA 5 V 3.5 - 3.5 - 3.5 - V

10 V 7.0 - 7.0 - 7.0 - V

15 V 11.0 - 11.0 - 11.0 - V

VIL LOW-level input voltage |IO| < 1 μA 5 V - 1.5 - 1.5 - 1.5 V

10 V - 3.0 - 3.0 - 3.0 V

15 V - 4.0 - 4.0 - 4.0 V

VOH HIGH-level output voltage |IO| < 1 μA;

VI=V

SS or VDD

5 V 4.95 - 4.95 - 4.95 - V

10 V 9.95 - 9.95 - 9.95 - V

15 V 14.95 - 14.95 - 14.95 - V

VOL LOW-level output voltage |IO| < 1 μA;

VI=V

SS or VDD

5 V - 0.05 - 0.05 - 0.05 V

10 V - 0.05 - 0.05 - 0.05 V

15 V - 0.05 - 0.05 - 0.05 V

IOH HIGH-level output current VO = 2.5 V 5 V −1.7 - −1.4 - −1.1 - mA

VO = 4.6 V 5 V −0.52 - −0.44 - −0.36 - mA

VO = 9.5 V 10 V −1.3 - −1.1 - −0.9 - mA

VO = 13.5 V 15 V −3.6 - −3.0 - −2.4 - mA

IOL LOW-level output current VO = 0.4 V 5 V 0.52 - 0.44 - 0.36 - mA

VO = 0.5 V 10 V 1.3 - 1.1 - 0.9 - mA

VO = 1.5 V 15 V 3.6 - 3.0 - 2.4 - mA

IIinput leakage current VDD = 15 V 15 V - ±0.3 - ±0.3 - ±1.0 μA

IDD supply current IO = 0 A;

VI=V

SS or VDD

5 V - 20 - 20 - 150 μA

10 V - 40 - 40 - 300 μA

15 V - 80 - 80 - 600 μA

CIinput capacitance - - - - 7.5 - - pF

Product data sheet Rev. 06 — 11 December 2009 8 of 16

NXP Semiconductors HEF4516B

Binary up/down counter

11. Dynamic characteristics

Table 7. Dy namic characteristics

VSS = 0 V; Tamb = 25

C; for test circuit see Figure 8; unless otherwise speci fied.

Symbol Parameter Conditions VDD Extrapolation formula Min Typ Max Unit

tPHL HIGH to LOW

propagation delay CP to Qn 5 V [1] 118 ns + (0.55 ns/pF)C L- 145 290 ns

10 V 49 ns + (0.23 ns/pF)CL- 60 120 ns

15 V 37 ns + (0.16 ns/pF)CL-4590ns

CP to TC 5 V 233 ns + (0.55 ns/pF )CL- 260 525 ns

10 V 94 ns + (0.23 ns/pF)CL- 105 210 ns

15 V 67 ns + (0.16 ns/pF)CL- 75 150 ns

PL to Qn 5 V 98 ns + (0.55 ns/pF)CL- 125 255 ns

10 V 44 ns + (0.23 ns/pF)CL- 55 110 ns

15 V 32 ns + (0.16 ns/pF)CL-4085ns

PL to TC 5 V 2 23 ns + (0.55 ns/pF)CL- 250 500 ns

10 V 99 ns + (0.23 ns/pF)CL- 110 220 ns

15 V 72 ns + (0.16 ns/pF)CL- 80 160 ns

CE to TC 5 V 138 ns + (0.55 ns/pF)CL- 165 330 ns

10 V 54 ns + (0.23 ns/pF)CL- 65 135 ns

15 V 42 ns + (0.16 ns/pF)CL- 50 100 ns

MR to Qn, TC 5 V 178 ns + (0.55 ns/pF)CL- 205 405 ns

10 V 54 ns + (0.23 ns/pF)CL- 65 130 ns

15 V 37 ns + (0.16 ns/pF)CL-4585ns

tPLH LOW to HIGH

propagation delay CP to Qn 5 V [1] 128 ns + (0.55 ns/pF)CL- 155 310 ns

10 V 54 ns + (0.23 ns/pF)CL- 65 130 ns

15 V 37 ns + (0.16 ns/pF)CL-4590ns

CP to TC 5 V 153 ns + (0.55 ns/pF )CL- 180 360 ns

10 V 64 ns + (0.23 ns/pF)CL- 75 150 ns

15 V 47 ns + (0.16 ns/pF)CL- 55 115 ns

PL to Qn 5 V 143 ns + (0.55 ns/pF)CL- 170 340 ns

10 V 59 ns + (0.23 ns/pF)CL- 70 140 ns

15 V 42 ns + (0.16 ns/pF)CL- 50 105 ns

PL to TC 5 V 2 23 ns + (0.55 ns/pF)CL- 250 500 ns

10 V 99 ns + (0.23 ns/pF)CL- 110 220 ns

15 V 72 ns + (0.16 ns/pF)CL- 80 160 ns

CE to TC 5 V 118 ns + (0.55 ns/pF)CL- 145 290 ns

10 V 49 ns + (0.23 ns/pF)CL- 60 125 ns

15 V 37 ns + (0.16 ns/pF)CL-4595ns

MR to TC 5 V 198 ns + (0.55 ns/pF)CL- 225 450 ns

10 V 64 ns + (0.23 ns/pF)CL- 75 150 ns

15 V 42 ns + (0.16 ns/pF)CL- 50 100 ns

Product data sheet Rev. 06 — 11 December 2009 9 of 16

NXP Semiconductors HEF4516B

Binary up/down counter

[1] The typical values of the propagation delay and transition times are calculated from the extrapolation formulas shown (CL in pF).

tttransition time 5 V [1] 10 ns + (1.00 ns/pF)CL- 60 120 ns

10 V 9 ns + (0.42 ns/pF)CL-3060ns

15 V 6 ns + (0.28 ns/pF)CL-2040ns

fmax maximum frequency see Figure 6 5 V 3 6 - MHz

10 V 7 14 - MHz

15 V 9 18 - MHz

tWpulse width CP input LOW;

minimum width;

see Figure 6

5 V 95 45 - ns

10 V 35 20 - ns

15 V 25 15 - ns

PL input HIGH;

minimum width;

see Figure 7

5 V 105 55 - ns

10 V 45 25 - ns

15 V 35 15 - ns

MR input HIGH;

minimum width;

see Figure 7

5 V 120 60 - ns

10 V 50 25 - ns

15 V 40 20 - ns

trec recovery time MR input;

see Figure 7 5 V 130 65 - n s

10 V 45 20 - ns

15 V 30 15 - ns

PL input;

see Figure 7 5 V 150 75 - n s

10 V 50 25 - ns

15 V 30 15 - ns

tsu set-up time Dn to PL;

see Figure 7 5 V 100 50 - n s

10 V 50 25 - ns

15 V 40 20 - ns

UP/DN to CP;

see Figure 6 5 V 250 125 - ns

10 V 100 50 - ns

15 V 75 35 - ns

CE to CP;

see Figure 6 5 V 120 60 - n s

10 V 40 20 - ns

15 V 25 10 - ns

thhold time Dn to PL;

see Figure 7 5 V +10 −40 - ns

10 V +5 −20 - ns

15 V 0 −20 - ns

UP/DN to CP;

see Figure 6 5 V +35 −90 - ns

10 V +15 −35 - ns

15 V +15 −25 - ns

CE to CP;

see Figure 6 5 V +20 −40 - ns

10 V +5 −15 - ns

15 V +5 −10 - ns

Table 7. Dy namic characteristics …continued

VSS = 0 V; Tamb = 25

C; for test circuit see Figure 8; unless otherwise speci fied.

Symbol Parameter Conditions VDD Extrapolation formula Min Typ Max Unit

Product data sheet Rev. 06 — 11 December 2009 10 of 16

NXP Semiconductors HEF4516B

Binary up/down counter

12. Waveforms

Table 8. Dy namic power dissipation PD

PD can be calculated from the formulas shown. VSS = 0 V; CL = 50 pF; tr = tf

≤

20 ns; Tamb = 25

Symbol Parameter VDD Typical formula for PD (μW) Where:

PDdynamic power

dissipation 5 V PD = 1000 × fi + Σ(fo × CL) × VDD2fi = input frequency in MHz;

fo = output frequency in MHz;

CL = output load capacitance in pF;

VDD = supply voltage in V;

Σ(fo × CL) = sum of the outputs.

10 V PD = 4500 × fi + Σ(fo × CL) × VDD2

15 V PD = 11200 × fi + Σ(fo × CL) × VDD2

Measurement points are given in Table 9.

Fig 6. Waveforms sh owi ng minimum pu ls e wi dth for CP, set-up and hold times for CE to CP and UP/DN to CP

001aae6

CP input

CE input

UP/DN input

Measurement points are given in Table 9.

Fig 7. W ave forms showing PL an d MR minimum pulse wid ths and recovery times, and Dn to PL set-up and hold

times

001aae6

CP input

VSS

PL input

Dn input

tWtrec

MR input

trec

tsu

Product data sheet Rev. 06 — 11 December 2009 11 of 16

NXP Semiconductors HEF4516B

Binary up/down counter

a. Input waveforms

b. Test circuit

Test data is given in Table 9.

Definitions for test circuit:

DUT = Device Under Test

CL = Load capacitance including jig and probe capacitance;

RT = Termination resistance should be equal to output impedance Zo of the pulse generator.

Fig 8. Test circuit for measuring switching times

10 %

90 %

0 V

negative

pulse

positive

pulse

0 V

90 %

10 %

001aaj78

VDD

VIVO

001aag18

DUT

Table 9. Measurement points and test data

Supply voltage Input Load

VIVMtr, tfCL

5Vto15V V

DD 0.5VI≤ 20 ns 50 pF

Product data sheet Rev. 06 — 11 December 2009 12 of 16

NXP Semiconductors HEF4516B

Binary up/down counter

13. Package outline

Fig 9. Package outline SOT38-4 (DIP16)

REFERENCES

OUTLINE

VERSION EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC JEITA

SOT38-4 95-01-14

03-02-13

(e )

seating plane

pin 1 index

0 5 10 mm

scale

Note

1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included.

UNIT A

max. 12 b1(1) (1) (1)

b2cD E e M Z

DIMENSIONS (inch dimensions are derived from the original mm dimensions)

min. A

max. bmax.

1.73

1.30

0.53

0.38

0.36

0.23

19.50

18.55

6.48

6.20

3.60

3.05 0.2542.54 7.62 8.25

7.80

10.0

8.3 0.764.2 0.51 3.2

inches 0.068

0.051

0.021

0.015

0.014

0.009

1.25

0.85

0.049

0.033

0.77

0.73

0.26

0.24

0.14

0.12 0.010.1 0.3 0.32

0.31

0.39

0.33 0.030.17 0.02 0.13

IP16: plastic dual in-line package; 16 leads (300 mil) SOT38

-4

Product data sheet Rev. 06 — 11 December 2009 13 of 16

NXP Semiconductors HEF4516B

Binary up/down counter

Fig 10. Package outline SOT109-1 (SO16)

detail X

vMA

(A )

pin 1 index

UNIT A

max. A1A2A3bpcD

(1) E(1) (1)

ELL

pQZywv

REFERENCES

OUTLINE

VERSION EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC JEITA

inches

1.75 0.25

0.10

1.45

1.25 0.25 0.49

0.36

0.25

0.19

10.0

9.8

4.0

3.8 1.27 6.2

5.8

0.7

0.6

0.7

0.3 8

0.25 0.1

DIMENSIONS (inch dimensions are derived from the original mm dimensions)

Note

1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.

1.0

0.4

SOT109-1 99-12-27

03-02-19

076E07 MS-012

0.069 0.010

0.004

0.057

0.049 0.01 0.019

0.014

0.0100

0.0075

0.39

0.38

0.16

0.15 0.05

1.05

0.041

0.244

0.228

0.028

0.020

0.028

0.012

0.01

0.25

0.01 0.004

0.039

0.016

0 2.5 5 mm

scale

O16: plastic small outline package; 16 leads; body width 3.9 mm SOT109

-1

Product data sheet Rev. 06 — 11 December 2009 14 of 16

NXP Semiconductors HEF4516B

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14. Revision history

Table 10. Revision history

Document ID Release date Data sheet status Change notice Supersedes

HEF4516B_6 20091211 Product data sheet - HEF4516B_5

Modifications: •Section 9 “Recommended operating conditions” Δt/ΔV values updated.

HEF4516B_5 20090812 Product data sheet - HEF4516B_4

HEF4516B_4 20090312 Product data sheet - HEF4516B_CNV_3

HEF4516B_CNV_3 19950101 Product specification - HEF4516B_CNV_2

HEF4516B_CNV_2 19950101 Product specification - -

Product data sheet Rev. 06 — 11 December 2009 15 of 16

NXP Semiconductors HEF4516B

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15. Legal information

15.1 Data sheet status

[1] Please consult the most recently issued document before initiating or completing a design.

[2] The term ‘short data sheet’ is explained in section “Definitions”.

[3] The product status of de vice(s) descr ibed in th is document m ay have cha nged since thi s document w as publish ed and may di ffe r in case of multiple devices. The latest product status

information is available on the Internet at URL http://www.nxp.com.

15.2 Definitions

Draft — The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in

modifications or additions. NXP Semiconductors does not give any

representations or warrant ies as to t he accuracy or completeness of

information included herein and shall have no liab ility for the consequences of

use of such information.

Short data sheet — A short dat a sheet is an extract from a full data sheet

with the same product type number(s) and tit le. A short data sh eet is intended

for quick reference only and shou ld not b e relied u pon to cont ain det ailed and

full information. For detailed and full informatio n see the relevant full data

sheet, which is available on request via the local NXP Semiconductors sales

office. In case of any inconsistency or conflict with the short data sheet, the

full data sheet shall pre va il.

15.3 Disclaimers

General — In formation in this document is beli eved to be accurate and

reliable. However, NXP Semiconduct ors does not give any repr esentatio ns or

warranties, expressed or impli ed, as to the accuracy or completeness of such

information and shall have no liability for th e co nsequences of use of such

information.

Right to make changes — NXP Semiconductors reserves the right to make

changes to information published in this document, including without

limitation specifications and product descriptions, at any time and without

notice. This document supersedes and replaces all informa tion supplied prior

to the publication hereof .

Suitability for use — NXP Semiconductors products are not designed,

authorized or warranted to be suitable for use in medical, military, aircraft,

space or life support equipment, nor in app lications where failure or

malfunction of an NXP Semiconductors product can reasonably be expected

to result in personal injury, death or severe property or environmental

damage. NXP Semiconductors accepts no liab ility for inclusion and/or use of

NXP Semiconductors products in such equipment or applications and

therefore such inclusion and/or use is at the customer’s own risk.

Applications — Applications that are described herein for any of these

products are for il lustrative purposes only. NXP Semiconductors makes no

representation or warranty that such applications will be suitable for the

specified use without further testing or modification.

Limiting values — Stress above one or more limiting values (as defined in

the Absolute Maximum Ra tings System of IEC 60134) may cause permanent

damage to the device. Limiting values are stress ratings only and operation of

the device at these or any other co nditions above those given in the

Characteristics sections of this document is not implied. Exposure to limiting

values for extended periods may af fect device reliability.

Terms and conditions of sale — NXP Semiconductors products are sold

subject to the general terms and conditions of commercial sale, as published

at http://www.nxp.com/profile/terms, i ncluding those pertaining to warranty,

intellectual property rights infringement and limit ation of liability, unless

explicitly otherwise agreed to in writing by NXP Semiconductors. In case of

any inconsistency or conflict between inf ormation in this document and such

terms and conditions, the latter will prevail.

No offer to sell or license — Not hing in this document may be interpret ed or

construed as an of fer t o sell product s that is open for accept ance or the gr ant,

conveyance or implication of any license under any copyrights, patents or

other industrial or intellectual property rights.

Export control — This document as well as the item(s) described herein

may be subject to export control regulatio ns. Export might require a prior

authorization from national authorities.

15.4 Trademarks

Notice: All refe renced brands, produc t names, service names and trademarks

are the property of their respective ow ners.

16. Contact information

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

Document status[1][2] Product status[3] Definition

Objective [short] data sheet Development This document contain s data from the objective specification for product development .

Preliminary [short] dat a sheet Qualification This document contains data from the preliminary specification.

Product [short] data sheet Production This document contains t he product specification.

NXP Semiconductors HEF4516B

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For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

Date of release: 11 December 2009

Document identifier: HEF4516B_6

Please be aware that important notices concerning this document and the product(s)

described herein, have been included in section ‘Legal information’.

17. Contents

1 General description. . . . . . . . . . . . . . . . . . . . . . 1

2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

4 Ordering information. . . . . . . . . . . . . . . . . . . . . 1

5 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2

6 Pinning information. . . . . . . . . . . . . . . . . . . . . . 4

6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4

7 Functional description . . . . . . . . . . . . . . . . . . . 5

8 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 6

9 Recommended operating conditions. . . . . . . . 6

10 Static characteristics. . . . . . . . . . . . . . . . . . . . . 7

11 Dynamic characteristics . . . . . . . . . . . . . . . . . . 8

12 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

13 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 12

14 Revision history. . . . . . . . . . . . . . . . . . . . . . . . 14

15 Legal information. . . . . . . . . . . . . . . . . . . . . . . 15

15.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 15

15.2 Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

15.3 Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 15

15.4 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

16 Contact information. . . . . . . . . . . . . . . . . . . . . 15

17 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16