IRDC3640
1
USER GUIDE FOR IR3640 EVALUATION BOARD
DESCRIPTION
The IR3640 is a PWM controller for use in
high performance synchronous Buck DC/DC
applications. This is designed to drive a pair
of external NFETs using a programmable
switching frequency up to 1.5MHz in voltage
mode. It is housed in a in 20 Lead 3x4
MLPQ package.
Key features offered by the IR3640 include
programmable soft-start ramp, Pow er Good,
thermal protection, over voltage and over
current protection, programmable switching
frequency, tracking input, enable input, input
under-voltage lockout for proper start-up,
and pre-bias start-up.
An output over-current protection function is
implemented by sensing the voltage developed
across the on-resistance of the synchronous
rectifier MOSFET for optimum cost and
performance.
This user guide contains the schematic and bill
of materials for the IR3640 evaluation board.
The guide describes operation and use of the
evaluation board itself. Detailed application
information for IR3640 is available in the
IR3640 data sheet.
BOARD FEATURES
•Vin = +12V (13.2V Max)
•Vcc
= +5V (5.5V Max)
•Vout = +1.8V @ 0- 25A
•Fs = 600kHz
•L = 0.33uH
•Cin
= 4x10uF (ceramic 1210) + 2x330uF (electrolytic)
•Cout
= 10x47uF (ceramic 0805)
IRDC3640
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A well regulated +12V input suppl y shoul d be co nnected to V IN+ and VIN -. A maximum 25A loa d shoul d be
connected to VOUT+ and VOUT-. The connecti on diagram is shown in Fig. 1 and inputs and outputs of the
board are listed in Table I.
IR3640 has two input suppli es, one for biasi ng (Vcc) and the other as input voltage (Vin). Separate supplies
should be applied to these inputs. Vcc input should be a well regulated 4.5V-5.5V supply and it would be
connected to Vcc+ and Vcc-.
CONNECTIONS and OPERATING INSTRUCTIONS
LAYOUT
The PCB is a 6-layer board. All of layers are 2 Oz. copper. The IR3640 and other components are
mounted on the top and bottom side of the board.
Power supply decoupling capacitors, the Bootstrap capacitor and feedback components are located
close to IR3640. The feedback resistors are connected to the output voltage at the point of regulation
and are located close to IR3640. To improve efficiency, the circuit board is designed to minimize the
length of the on-board power ground current path.
Table I. Connections
Connection Signal Name
VIN+ Vin (+12V)
VIN- Ground of Vin
Vcc+ Vcc input
Vcc- Ground for Vcc input
VOUT+ Vout (+1.8V)
VOUT- Ground of Vout
Sync Synchronous input
PGood Power Good Signal
IRDC3640
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Connection Diagram
Fig. 1: Connection diagram of IR3640 evaluation board (top and bottom)
Vin = +12V
GROUND
GROUND
VOUT = +1.8V
GROUND
Vcc = +5V
IRDC3640
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Fig. 2: Board layout, top layer
Fig. 3: Board layout, bottom layer
IRDC3640
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Fig. 4: Board layout, mid-layer I
Fig. 5: Board layout, mid-layer II
Single point
connection
between AGND
and PGND.
IRDC3640
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Fig. 6: Board layout, mid-layer III
Fig. 7: Board layout, mid-layer IV
IRDC3640
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Fig.8: Schematic of the IR3640 evaluation board
C31
47uF C32
47uF
+
C36
N/S
+
C35
N/S
R10
N/S
PGND
1
C11
47uF C12
47uF
Sync
1
U1
IR3640
Vcc
19
PGood
17
Vp
9
Rt
14
SS/SD
15
HDrv 5
Vsns 11
Boot 7
LDrv 2
SW 4
Enable 8
OCset 16
Fb
10
Comp
12
Sync
18
LGnd
13
PGnd 3
NC6 6
NC1 1
PVcc 20
C13
47uF C14
47uF
C27
0.1uF
C16
47uF
C15
47uF
C9
47uF C28
0.1uF
PVcc
1
R6
4.99K
N3065200
C17
1.0uF
R3
4.99K
Enable
1
Q1
IRF6710SPbF
2
5
4
1
36
7
C6
N/S
+
C26
330uF
+
C25
330uF
R21
0
R5
0
Vout-
1
Vin
C19
N/S
L1
0.33uH
C8
0.1uF
C21
5600pF
C5
10uF
C1
N/S
Vout
R13
3.24K
C4
10uF
C3
10uF
C2
10uF
R19
2.55K
R14
130
R17
4.02K
C10
47uF
R18
20
C7
0.1uF
R20
0
R8
2.26K
R9
23.7K
R7
N/S
A
1
B
1
C23
2200pF
Vcc
1
Vin+
1
Vin-
1
Vout+
1
Vout-
1
R4
681
Vp
1
C22
160pF
Vin+
1
Vin-
1
Vout+
1
C30
N/S
R11
2.55K
SS
1
R12
4.12K
R22
0
Q2
IRF6795MPbF
2
5
4
1
36
7
PGood
1
AGND
1
C20
0.1uF
IRDC3640
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Bill of Materials
I tem Qu antity Refe r ence V al ue Descripti o n M anu factur er P art Number
1 10 VOUT-,VOUT+,VIN-,VIN+, 0.075" SQ_SMT SMT 0.075" Test Point
Sync,PVcc,PGood,PGND,B,A _TestPoint
2 4 C2,C3,C4,C5 10uF Ceramic,25V,1210,X5R,10% Taiyo-Yuden TMK325BJ106MN-T
3 5 C7,C8,C20,C27,C28 0.1uF Ceramic,50V,0603,X7R,10% Panasonic ECJ-1VB1H104K
4 10 C9,C10,C11, C12, C13, 47uF Cerami c,4V ,0805,X5R, 10% Mu rat a Elec troni cs GRM21BR60G476M E15 L
C14,C15,C16,C31,C32
5 1 C17 1. 0uF Cerami c,25V,0603,X5R, 10% Mu rat a Elec troni cs GRM188R61E105KA 12D
6 1 C21 5.6nF Ceramic,25V,0603,C0G,5% Panasonic-ECG C1608C0G1E562J
7 1 C22 160pF Cerami c, 50V,0603,C0G,5% Murat a El ectronics GRM1885C1H161JA 01D
8 1 C23 2200pF Cerami c, 50V,0603,C0G,5% TDK Corporat i on C1608C0G1H222J
9 2 C25, C26 330uF S MD E l ecrolyt i c , 25V , F -s i ze, 20% P anas oni c EE E-FK 1E331P
10 1 L1 0.33uH SMT-Inductor,1.5mOhms,10x11mm,20% Delta MPL104-R33IR
11 1 Q1 IRF6710S2TRPbF IRF6710 S Q 25V Internati o nal Rec ti fier IRF6710S2 TRPbF
12 1 Q2 IRF6795M Pb F IRF6795 M X 25V Internati o nal Rec ti fier IRF6795M PbF
13 3 R5,R21,R22 0 Thic k-fil m ,06 03, 1/10 W,5% V i shay /Dale CRCW 06030000Z0EA
14 2 R3,R6 4.99K Thick-film,0603,1/10W,1% Rohm MCR03EZPFX4991
15 1 R4 681 Thi ck-film ,0603, 1/10 W,1% V i shey/Dale CRCW 0603681RF K EA
16 1 R8 2.26K Thick-film,0603,1/10W,1% Rohm MCR03EZPFX2261
17 1 R9 23.7K Thick-film,0603,1/10W,1% Rohm MCR03EZPFX2372
18 2 R11, R19 2. 55K Thick-fil m ,0603,1/10 W,1% Rohm MCR03E ZPF X2551
19 1 R12 4. 12K Thick -fil m ,0603, 1/10 W,1% Rohm MCR03E ZPF X412 1
20 1 R13 3.24K Thick-film,0603,1/10W,1% Rohm MCR03EZPFX3241
21 1 R14 130 Thic k-fil m ,06 03, 1/10 W,1% Rohm MCR03E ZPF X130 0
22 1 R17 4. 02K Thick -fil m ,0603, 1/10 W,1% Rohm MCR03E ZPF X402 1
23 1 R18 20 Thic k-fil m ,06 03, 1/10 W, 1% V i shey/Dale CRCW 060320R0F K EA
24 4 TP11,TP12,TP 13, TP14 Label TP 0.250" x 0.300" test pad area
25 1 U1 IR3640 IR3640, Control l er, MLPQ, 3 x4m m Internati o nal Rec ti fier IR3640
IRDC3640
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TYPICAL OPERATING WAVEFORMS
Vin=12.0V, Vcc=5V, Vo=1.8V, Io=0- 25A, Room Temperature, No Air Flow
Fig. 12: Output Voltage Ripple, 25A load
Ch3
: Vout
Fig. 13: Inductor node at 25A load
Ch2
:SW Fig. 14: Short (Hiccup) Recovery
Ch2
:Vout
, Ch3
:VSS , Ch4
:Io
Fig. 9: Start up a t 0A L oa d (Note 1)
Ch1
:Vo
, Ch2
:PGood Ch3
:VSS Ch4
: Vin
Fig. 11: Start up with 1.5V Prebias,
0A Load, Ch2
:Vout Ch3
:VSS Ch4
: PGood
Fig. 10: Start up at 25A Load (Note 1)
Ch1
:Vo
, Ch2
:PGood Ch3
:VSS Ch4
: Vin
IRDC3640
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TYPICAL OPERATING WAVEFORMS
Vin=12V, Vcc=5V, Vo=1.8V, Room Temperature, No Air Flow
Note1: Enable is tied to Vin via a resistor divider and triggered when Vin is exceeding above 10V.
Fig. 15: Transient Response
0A-12.5A load Ch2
:Vout
, Ch4
:Io
IRDC3640
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TYPICAL OPERATING WAVEFORMS
Vin=12V, Vcc=5V, Vo=1.8V, Io=0-25A, Room Temperature, No Air Flow
Fig.16: Bode Plot at 25A load shows a bandwidth of 113.6kHz and phase margin of 50.4 degrees
IRDC3640
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Fig.17: Efficiency and power loss vs. load current
TYPICAL OPERATING WAVEFORMS
Vin=12V, Vo=1.8V, Io=0-25A, Room Temperature, No Air Flow
IR3640_IRF6710_IRF6795_0.33uH Efficiency vs. Io
70
75
80
85
90
95
1 3 5 7 9 11 13 15 17 19 21 23 25
Io(A)
Efficiency(%)
IR3640_IRF6710_IRF6795_0.33uH Power Loss vs. Io
0
1
2
3
4
5
6
7
1 3 5 7 91113151719212325
Io(A)
Ploss(W)
IRDC3640
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THERMAL IMAGES
Vin=12V, Vo=1.8V, Io=25A, Room Temperature, No Air Flow
Fig.18: Thermal Image at 25A load
Test Point 1: Ctrl FET IRF6710, Test Point 2: Sync FET IRF6795
Test Point 3: Inductor
2
IRDC3640
PCB Metal and Components Placement
Lead land width should be equal to nominal part lead width. The minimum lead to lead
spacing should be ≥0.2mm to minimize shorting.
Lead land length should be equal to maximum part lead length + 0.3 mm outboard
extension +0.05mm inboard extension. The outboard extension ensures a large and
inspectable toe fillet, and the inboard extension will accommodate any part misalignment and
ensure a fillet.
Center pad land length and width should be equal to maximum part pad length and width.
However, the minimum metal to metal spacing should be ≥0.17mm for 2 oz. Copper (≥
0.1mm for 1 oz. Copper and ≥0.23mm for 3 oz. Copper).
Four 0.30mm diameter via shall be placed in the center of the pad land and connected to
ground to minimize the noise effect on the IC.
IRDC3640
Solder Resist
The solder resist should be pulled away from the metal lead lands by a minimum of 0.06mm.
The solder resist mis-alignment is a maximum of 0.05mm and it is recommended that the lead
lands are all Non Solder Mask Defined (NSMD). Therefore pulling the S/R 0.06mm will always
ensure NSMD pads.
The minimum solder resist width is 0.13mm. At the inside corner of the solder resist where
the lead land groups meet, it is recommended to provide a fillet so a solder resist width of ≥
0.17mm remains.
The land pad should be Non Solder Mask Defined (NSMD), with a minimum pullback of the
solder resist off the copper of 0.06mm to accommodate solder resist mis-alignment.
Ensure that the solder resist in-between the lead lands and the pad land is ≥0.15mm due to
the high aspect ratio of the solder resist strip separating the lead lands from the pad land.
Each via in the land pad should be tented or plugged from bottom boardside with solder resist.
IRDC3640
Stencil Design
• The stencil apertures for the lead lands should be approximately 80% of the area of the
lead lands. Reducing the amount of solder deposited will minimize the occurrence of lead
shorts. Since for 0.5mmpitch devices the leads are only 0.25mm wide, the stencil
apertures should not be made narrower; openings in stencils < 0.25mm wide are difficult
to maintain repeatable solder release.
• The stencil lead land apertures should therefore be shortened in length by 80% and
centered on the lead land.
• The land pad aperture should deposit approximately 50% area of solder on the center
pad. If too much solder is deposited on the center pad the part will float and the lead
lands will be open.
• The maximum length and width of the land pad stencil aperture should be equal to the
solder resist opening minus an annular 0.2mm pull back to decrease the incidence of
shorting the center land to the lead lands when the part is pushed into the solder paste.
IRDC3640
IR W ORLD H EADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
This product has been designed and qualified for the Consumer market.
Visit us at www.irf.com for sales contact information
Data and specifications subject to change without notice. 11/07
