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NXP Semiconductors
PESDxS2UQ series
Double ESD protection diodes in SOT663 package
Rev. 03 — 11 September 2008 Product data sheet
NXP Semiconductors Product specification
Double ESD protection diodes
in SOT663 package PESDxS2UQ series
FEATURES
•Uni-directional ESD protection of up to two lines
•Max. peak pulse power: Ppp = 150 W at tp= 8/20 µs
•Low clamping voltage: V(CL)R = 20 V at Ipp =15A
•Low reverse leakage current: IRM <1nA
•ESD protection > 30 kV
•IEC 61000-4-2; level 4 (ESD)
•IEC 61000-4-5 (surge); Ipp = 15 A at tp= 8/20 µs.
APPLICATIONS
•Computers and peripherals
•Communication systems
•Audio and video equipment
•High speed data lines
•Parallel ports.
DESCRIPTION
Uni-directionaldoubleESDprotectiondiodesinaSOT663
plastic package. Designed to protect up to two
transmission or data lines from ElectroStatic Discharge
(ESD) damage.
MARKING
QUICK REFERENCE DATA
PINNING
TYPE NUMBER MARKING CODE
PESD3V3S2UQ E1
PESD5V0S2UQ E2
PESD12VS2UQ E3
PESD15VS2UQ E4
PESD24VS2UQ E5
SYMBOL PARAMETER VALUE UNIT
VRWM reverse stand-off
voltage 3.3, 5, 12, 15
and 24 V
Cddiode capacitance
VR=0V;
f = 1 MHz
200,150,38,32
and 23 pF
number of
protected lines 2
PIN DESCRIPTION
1 cathode 1
2 cathode 2
3 common anode
sym022
2
1
3
1 2
3
001aaa732
Fig.1 Simplified outline (SOT663) and symbol.
Rev. 03 - 11 September 2008
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NXP Semiconductors Product specification
Double ESD protection diodes
in SOT663 package PESDxS2UQ series
ORDERING INFORMATION
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 60134).
Notes
1. Non-repetitive current pulse 8/20 µs exponential decaying waveform; see Fig.2.
2. Measured across either pins 1 and 3 or pins 2 and 3.
TYPE NUMBER PACKAGE
NAME DESCRIPTION VERSION
PESD3V3S2UQ −plastic surface mounted package; 3 leads SOT663
PESD5V0S2UQ
PESD12VS2UQ
PESD15VS2UQ
PESD24VS2UQ
SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT
Ppp peak pulse power 8/20 µs pulse; notes 1 and 2 −150 W
Ipp peak pulse current 8/20 µs pulse; notes 1 and 2
PESD3V3S2UQ −15 A
PESD5V0S2UQ −15 A
PESD12VS2UQ −5A
PESD15VS2UQ −5A
PESD24VS2UQ −3A
Tjjunction temperature −150 °C
Tamb operating ambient temperature −65 +150 °C
Tstg storage temperature −65 +150 °C
Rev. 03 - 11 September 2008
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NXP Semiconductors Product specification
Double ESD protection diodes
in SOT663 package PESDxS2UQ series
ESD maximum ratings
Notes
1. Device stressed with ten non-repetitive ElectroStatic Discharge (ESD) pulses; see Fig.3.
2. Measured across either pins 1 and 3 or pins 2 and 3.
SYMBOL PARAMETER CONDITIONS VALUE UNIT
ESD electrostatic discharge
capability IEC 61000-4-2 (contact discharge);
notes 1 and 2
PESD3V3S2UQ 30 kV
PESD5V0S2UQ 30 kV
PESD12VS2UQ 30 kV
PESD15VS2UQ 30 kV
PESD24VS2UQ 23 kV
HBM MIL-Std 883
PESDxS2UQ series 10 kV
ESD standards compliance
ESD STANDARD CONDITIONS
IEC 61000-4-2; level 4 (ESD); see Fig.3 >15 kV (air); > 8 kV (contact)
HBM MIL-Std 883; class 3 >4 kV
handbook, halfpage
010
e−t
20 t (µs)
Ipp
(%)
40
120
0
40
80
30
MLE218
100 % Ipp; 8 µs
50 % Ipp; 20 µs
Fig.2 8/20 µs pulse waveform according to
IEC 61000-4-5.
001aaa191
Ipp
100 %
90 %
t
30 ns 60 ns
10 %
tr = 0.7 to 1 ns
Fig.3 ElectroStatic Discharge (ESD) pulse
waveform according to IEC 61000-4-2.
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NXP Semiconductors Product specification
Double ESD protection diodes
in SOT663 package PESDxS2UQ series
ELECTRICAL CHARACTERISTICS
Tj=25°C unless otherwise specified.
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
VRWM reverse stand-off voltage
PESD3V3S2UQ −−3.3 V
PESD5V0S2UQ −−5V
PESD12VS2UQ −−12 V
PESD15VS2UQ −−15 V
PESD24VS2UQ −−24 V
IRM reverse leakage current
PESD3V3S2UQ VRWM = 3.3 V −0.55 3 µA
PESD5V0S2UQ VRWM = 5 V −50 300 nA
PESD12VS2UQ VRWM = 12 V −<1 30 nA
PESD15VS2UQ VRWM = 15 V −<1 50 nA
PESD24VS2UQ VRWM = 24 V −<1 50 nA
VBR breakdown voltage IZ = 5 mA
PESD3V3S2UQ 5.2 5.6 6.0 V
PESD5V0S2UQ 6.4 6.8 7.2 V
PESD12VS2UQ 14.7 15.0 15.3 V
PESD15VS2UQ 17.6 18.0 18.4 V
PESD24VS2UQ 26.5 27.0 27.5 V
Cddiode capacitance f = 1 MHz; VR=0V
PESD3V3S2UQ −200 275 pF
PESD5V0S2UQ −150 215 pF
PESD12VS2UQ −38 100 pF
PESD15VS2UQ −32 70 pF
PESD24VS2UQ −23 50 pF
V(CL)R clamping voltage notes 1 and 2
PESD3V3S2UQ Ipp =1A −−8V
Ipp =15A −−20 V
PESD5V0S2UQ Ipp =1A −−9V
Ipp =15A −−20 V
PESD12VS2UQ Ipp =1A −−19 V
Ipp =5A −−35 V
PESD15VS2UQ Ipp =1A −−23 V
Ipp =5A −−40 V
PESD24VS2UQ Ipp =1A −−36 V
Ipp =3A −−70 V
Rev. 03 - 11 September 2008
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NXP Semiconductors Product specification
Double ESD protection diodes
in SOT663 package PESDxS2UQ series
Notes
1. Non-repetitive current pulse 8/20 µs exponential decay waveform; see Fig.2.
2. Measured either across pins 1 and 3 or pins 2 and 3.
Rdiff differential resistance
PESD3V3S2UQ IR=5mA −−40 Ω
PESD5V0S2UQ IR=5mA −−15 Ω
PESD12VS2UQ IR=5mA −−15 Ω
PESD15VS2UQ IR=1mA −−225 Ω
PESD24VS2UQ IR= 0.5 mA −−300 Ω
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
GRAPHICAL DATA
tp (µs)
110
3
102
10
001aaa726
103
102
104
Ppp
(W)
10
Fig.4 Peak pulse power dissipation as a function
of pulse time; typical values.
Tamb =25°C.
tp= 8/20 µs exponential decaying waveform; see Fig.2.
Tj (°C)
0 20015050 100
001aaa193
0.4
0.8
1.2
Ppp
0
Ppp(25˚C)
Fig.5 Relative variation of peak pulse power as a
function of junction temperature; typical
values.
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NXP Semiconductors Product specification
Double ESD protection diodes
in SOT663 package PESDxS2UQ series
VR (V)
054231
001aaa727
120
160
80
200
240
Cd
(pF)
40
(1)
(2)
Fig.6 Diode capacitance as a function of reverse
voltage; typical values.
Tamb = 25 °C; f = 1 MHz.
(1) PESD3V3S2UQ; VRWM = 3.3 V.
(2) PESD5V0S2UQ; VRWM =5V.
VR (V)
0252010 155
001aaa728
20
30
10
40
50
Cd
(pF)
0
(1)
(3)
(2)
Fig.7 Diode capacitance as a function of reverse
voltage; typical values.
Tamb = 25 °C; f = 1 MHz.
(1) PESD12VS2UQ; VRWM =12V.
(2) PESD15VS2UQ; VRWM =15V.
(3) PESD24VS2UQ; VRWM =24V.
Rev. 03 - 11 September 2008
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NXP Semiconductors Product specification
Double ESD protection diodes
in SOT663 package PESDxS2UQ series
001aaa729
1
10
10−1
Tj (°C)
−100 150100050−50
IR
IR(25°C)
(1)
(2)
Fig.8 Relative variation of reverse leakage
current as a function of junction
temperature; typical values.
IR is less than 15 nA at 150 °C for:
PESD12VS2UQ; VRWM =12V.
PESD15VS2UQ; VRWM =15V.
PESD24VS2UQ; VRWM =24V.
(1) PESD3V3S2UQ; VRWM = 3.3 V.
(2) PESD5V0S2UQ; VRWM =5V.
Rev. 03 - 11 September 2008
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NXP Semiconductors Product specification
Double ESD protection diodes
in SOT663 package PESDxS2UQ series
001aaa731
450 Ω
50 Ω
Note 1: IEC61000-4-2 network
CZ = 150 pF; RZ = 330 Ω
D.U.T.: PESDxS2UQ
RG 223/U
50 Ω coax
RZ
CZ
ESD TESTER 4 GHz DIGITAL
OSCILLOSCOPE
10×
ATTENUATOR
vertical scale = 200 V/div
horizontal scale = 50 ns/div vertical scale = 20 V/div
horizontal scale = 50 ns/div
vertical scale = 200 V/div
horizontal scale = 50 ns/div vertical scale = 10 V/div
horizontal scale = 50 ns/div
GND
GND
GND
GND
GND
GND
GND
unclamped +1 kV ESD voltage waveform
(IEC61000-4-2 network) clamped +1 kV ESD voltage waveform
(IEC61000-4-2 network)
GND
unclamped −1 kV ESD voltage waveform
(IEC61000-4-2 network) clamped −1 kV ESD voltage waveform
(IEC61000-4-2 network)
note 1
PESD24VS2UQ
PESD15VS2UQ
PESD12VS2UQ
PESD5V2S2UQ
PESD3V3S2UQ
Fig.9 ESD clamping test set-up and waveforms.
Rev. 03 - 11 September 2008
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NXP Semiconductors Product specification
Double ESD protection diodes
in SOT663 package PESDxS2UQ series
APPLICATION INFORMATION
The PESDxS2UQ series is designed for uni-directional protection for up to two data lines against damage caused by
ElectroStatic Discharge (ESD) and surge pulses. The PESDxS2UQ series may be used on lines where the signal
polarities are below ground. PESDxS2UQ series provide a surge capability of up to 150 W (Ppp) per line for an 8/20 µs
waveform.
Circuit board layout and protection device placement
Circuit board layout is critical for the suppression of ESD, Electrical Fast Transient (EFT) and surge transients. The
following guidelines are recommended:
•Place the PESDxS2UQ as close as possible to the input terminal or connector.
•The path length between the PESDxS2UQ and the protected line should be minimized.
•Keep parallel signal paths to a minimum.
•Avoid running protected conductors in parallel with unprotected conductors.
•Minimize all printed-circuit board conductive loops including power and ground loops.
•Minimize the length of transient return paths to ground.
•Avoid using shared return paths to a common ground point.
•Ground planes should be used whenever possible. For multilayer printed-circuit boards use ground vias.
001aaa730
PESDxS2UQ
line 1 to be protected
uni-directional protection
of two lines bi-directional protection
of one line
line 2 to be protected
ground
PESDxS2UQ
line 1 to be protected
ground
Fig.10 Typical application: ESD protection of data lines.
Rev. 03 - 11 September 2008
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NXP Semiconductors Product specification
Double ESD protection diodes
in SOT663 package PESDxS2UQ series
PACKAGE OUTLINE
UNIT b
p
cDE e
1
H
E
L
p
w
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
01-12-04
02-05-21
IEC JEDEC JEITA
mm 0.33
0.23 0.18
0.08 1.7
1.5 1.3
1.1 0.5
e
1.0 1.7
1.5 0.1
y
0.1
DIMENSIONS (mm are the original dimensions)
0.3
0.1
SOT663
bp
D
e1
e
A
Lp
detail X
HE
E
B
0 1 2 mm
scale
A
0.6
0.5
c
X
12
3
Plastic surface mounted package; 3 leads SOT663
Y
w
M
B
Rev. 03 - 11 September 2008
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NXP Semiconductors PESDxS2UQ series
Double ESD protection diodes in SOT663 package
Legal information
Data sheet status
[1] Please consult the most recently issued document before initiating or completing a design.
[2] The term ‘short data sheet’ is explained in section “Definitions”.
[3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Disclaimers
General — Information in this document is believed to be accurate and
reliable. However, NXP Semiconductors does not give any representations or
warranties, expressed or implied, as to the accuracy or completeness of such
information and shall have no liability for the consequences of use of such
information.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
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malfunction of an NXP Semiconductors product can reasonably be expected
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therefore such inclusion and/or use is at the customer’s own risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) may cause permanent
damage to the device. Limiting values are stress ratings only and operation of
the device at these or any other conditions above those given in the
Characteristics sections of this document is not implied. Exposure to limiting
values for extended periods may affect device reliability.
Terms and conditions of sale — NXP Semiconductors products are sold
subject to the general terms and conditions of commercial sale, as published
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intellectual property rights infringement and limitation of liability, unless
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No offer to sell or license — Nothing in this document may be interpreted
or construed as an offer to sell products that is open for acceptance or the
grant, conveyance or implication of any license under any copyrights, patents
or other industrial or intellectual property rights.
Quick reference data — The Quick reference data is an extract of the
product data given in the Limiting values and Characteristics sections of this
document, and as such is not complete, exhaustive or legally binding.
Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Document status[1][2] Product status[3] Definition
Objective [short] data sheet Development This document contains data from the objective specification for product development.
Preliminary [short] data sheet Qualification This document contains data from the preliminary specification.
Product [short] data sheet Production This document contains the product specification.
Rev. 03 - 11 September 2008
12 of 13
NXP Semiconductors PESDxS2UQ series
Double ESD protection diodes in SOT663 package
© NXP B.V. 2008. All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 11 September 2008
Document identifier: PESDXS2UQ_SER_N_3
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
Revision history
Table 1. Revision history
Document ID Release date Data sheet status Change notice Supersedes
PESDXS2UQ_SER_N_3 20080911 Product data sheet - PESDXS2UQ_SERIES_2
Modifications: •Asterisks and note 1 removed in Marking Table
PESDXS2UQ_SERIES_2 20040427 Product specification - PESDXS2UQ_SERIES_1
PESDXS2UQ_SERIES_1 20031215 Product specification - -
