Features
• Short propagation delays for TTL and IPM applications
• 15 kV/μs minimum Common Mode Transient immu-
nity at V
CM = 1500 V for TTL/load drive
• High CTR at TA = 25°C
>25% for HCPL-4504/0454
>23% for HCNW4504
>19% for HCPL-J454
• Electrical specifi cations for common IPM applications
• TTL compatible
• Open collector output
• Safety approval:
UL recognized
– 3750 V rms/1min. for HCPL-4504/0454/J454
– 5000 V rms/1min. for HCPL-4504 Option 020 and
HCNW4504
CSA approved
IEC/EN/DIN EN 60747-5-2 approved
– VIORM = 560 Vpeak for HCPL-0454 Option 060
– VIORM = 630 Vpeak for HCPL-4504 Option 060
– VIORM = 891 Vpeak for HCPL-J454
– VIORM = 1414 Vpeak for HCNW4504
Applications
• Inverter circuits and Intelligent Power Module (IPM)
interfacing: High Common Mode Transient immunity
(> 10 kV/μs for an IPM load/drive) and (tPLH - tPHL)
Specifi ed (see Power Inverter Dead Time section)
• Line receivers: Short propagation delays and low in-
put-output capacitance
• High speed logic ground isolation: TTL/TTL, TTL/
CMOS, TTL/LSTTL
• Replaces pulse transformers: Save board space and
weight
• Analog signal ground isolation: Integrated photode-
tector provides improved linearity over phototransis-
tors
A 0.1 μF bypass capacitor between pins 5 and 8 is recommended.
7
1
2
3
45
6
8
NC
ANODE
CATHODE
NC
V
CC
NC
V
O
GND
TRUTH TABLE
LED
ON
OFF
V
O
LOW
HIGH
Description
The HCPL-4504 and HCPL-0454 contain a GaAsP LED
while the HCPL-J454 and HCNW4504 contain an AlGaAs
LED. The LED is optically coupled to an integrated high
gain photo detector.
The HCPL-4504 series has short propagation delays and
high CTR. The HCPL-4504 series also has a guaranteed
propagation delay diff erence (tPLH-tPHL). These features
make the HCPL-4504 series an excellent solution to IPM
inverter dead time and other switching problems. The
CTR, propagation delay, and CMR are specifi ed both for
TTL and IPM conditions which are provided for ease of
application. These single channel, diode-transistor opto-
couplers are available in 8-Pin DIP, SO-8, and Widebody
package confi gurations. An insulating layer between a
LED and an integrated photodetector provide electrical
insulation between input and output. Separate connec-
tions for the photodiode bias and output-transistor col-
lector increase the speed up to a hundred times that of
a conventional phototransistor coupler by reducing the
base collector capacitance.
Functional Diagram
HCPL-4504/J454/0454, HCNW4504
High CMR, High Speed Optocouplers
Data Sheet
CAUTION: It is advised that normal static precautions be taken in handling and assembly
of this component to prevent damage and/or degradation which may be induced by ESD.
Lead (Pb) Free
RoHS 6 fully
compliant
RoHS 6 fully compliant options available;
-xxxE denotes a lead-free product
Schematic
IF
SHIELD
8
6
5GND
VCC
2
3
VO
ICC
VFIO
ANODE
CATHODE
+
–
2
Ordering Information
HCPL-0454, HCPL-4504 and HCPL-J454 are UL Recognized with 3750 Vrms for 1 minute per UL1577.
HCNW4504 is UL Recognized with 5000 Vrms for 1 minute per UL1577. HCPL-0454, HCPL-4504, HCPL-J454 and
HCNW4504 are approved under CSA Component Acceptance Notice #5, File CA 88324.
Part
Number
Option
Package
Surface
Mount
Gull
Wing
Tape
& Reel
UL 1577
5000 Vrms/
1 Minute
rating
IEC/EN/DIN
EN 60747-5-2 Quantity
RoHS
Compliant
non RoHS
Compliant
HCPL-4504
-000E no option
300 mil
DIP-8
50 per tube
-300E #300 X X 50 per tube
-500E #500 X X X 1000 per reel
-020E #020 X 50 per tube
-320E #320 X X X 50 per tube
-520E #520 X X X X 1000 per reel
-060E #060 X 50 per tube
-360E #360 X X X 50 per tube
-560E #560 X X X X 1000 per reel
HCPL-J454
-000E no option
300 mil
DIP-8
X 50 per tube
-300E #300 X X X 50 per tube
-400E NA X X X 50 per tube
-500E #500 X X X X 1000 per reel
-600E NA X X X X 750 per reel
HCPL-0454
-000E no option
SO-8
X 100 per tube
-500E #500 X X 1500 per reel
-060E #060 X X 100 per tube
-560E #560 X X X 1500 per reel
HCNW4504
-000E no option 400 mil
Widebody
DIP-8
X X 42 per tube
-300E #300 X X X X 42 per tube
-500E #500 X X X X X 750 per reel
To order, choose a part number from the part number column and combine with the desired option from the option
column to form an order entry.
Example 1:
HCPL-4504-560E to order product of 300 mil DIP Gull Wing Surface Mount package in Tape and Reel packaging
with IEC/EN/DIN EN 60747-5-2 Safety Approval and RoHS compliant.
Example 2:
HCPL-4504 to order product of 300 mil DIP package in Tube packaging and non RoHS compliant.
Option datasheets are available. Contact your Avago sales representative or authorized distributor for information.
Remarks: The notation ‘#XXX’ is used for existing products, while (new) products launched since July 15, 2001 and
RoHS compliant will use ‘–XXXE.’
3
Package Outline Drawings
HCPL-4504 Outline Drawing
HCPL-4504 Gull Wing Surface Mount Option 300 Outline Drawing
1.080 ± 0.320
(0.043 ± 0.013) 2.54 ± 0.25
(0.100 ± 0.010)
0.51 (0.020) MIN.
0.65 (0.025) MAX.
4.70 (0.185) MAX.
2.92 (0.115) MIN.
5° TYP. 0.254 + 0.076
- 0.051
(0.010+ 0.003)
- 0.002)
7.62 ± 0.25
(0.300 ± 0.010)
6.35 ± 0.25
(0.250 ± 0.010)
9.65 ± 0.25
(0.380 ± 0.010)
1.78 (0.070) MAX.
1.19 (0.047) MAX.
A XXXXZ
YYWW
DATE CODE
DIMENSIONS IN MILLIMETERS AND (INCHES).
5678
4321
OPTION CODE*
UL
RECOGNITION
UR
TYPE NUMBER
* MARKING CODE LETTER FOR OPTION NUMBERS
"L" = OPTION 020
"V" = OPTION 060
OPTION NUMBERS 300 AND 500 NOT MARKED.
NOTE: FLOATING LEAD PROTRUSION IS 0.25 mm (10 mils) MAX.
3.56 ± 0.13
(0.140 ± 0.005)
0.635 ± 0.25
(0.025 ± 0.010) 12° NOM.
9.65 ± 0.25
(0.380 ± 0.010)
0.635 ± 0.130
(0.025 ± 0.005)
7.62 ± 0.25
(0.300 ± 0.010)
5
6
7
8
4
3
2
1
9.65 ± 0.25
(0.380 ± 0.010)
6.350 ± 0.25
(0.250 ± 0.010)
1.016 (0.040)
1.27 (0.050)
10.9 (0.430)
2.0 (0.080)
LAND PATTERN RECOMMENDATION
1.080 ± 0.320
(0.043 ± 0.013)
3.56 ± 0.13
(0.140 ± 0.005)
1.780
(0.070)
MAX.
1.19
(0.047)
MAX.
2.54
(0.100)
BSC
DIMENSIONS IN MILLIMETERS (INCHES).
LEAD COPLANARITY = 0.10 mm (0.004 INCHES).
NOTE: FLOATING LEAD PROTRUSION IS 0.25 mm (10 mils) MAX.
0.254 + 0.076
- 0.051
(0.010+ 0.003)
- 0.002)
4
Package Outline Drawings
HCPL-J454 Outline Drawing
HCPL-J454 Gull Wing Surface Mount Option 300 Outline Drawing
1.080 ± 0.320
(0.043 ± 0.013) 2.54 ± 0.25
(0.100 ± 0.010)
0.51 (0.020) MIN.
0.65 (0.025) MAX.
4.70 (0.185) MAX.
2.92 (0.115) MIN.
5 TYP. 0.254 + 0.076
- 0.051
(0.010+ 0.003)
- 0.002)
7.62 ± 0.25
(0.300 ± 0.010)
6.35 ± 0.25
(0.250 ± 0.010)
9.80 ± 0.25
(0.386 ± 0.010)
1.78 (0.070) MAX.
1.19 (0.047) MAX.
A XXXX
YYWW
DATE CODE
DIMENSIONS IN MILLIMETERS AND (INCHES).
5678
4321
UL
RECOGNITION
UR
TYPE NUMBER
OPTION NUMBERS 300 AND 500 NOT MARKED.
NOTE: FLOATING LEAD PROTRUSION IS 0.5 mm (20 mils) MAX.
3.56 ± 0.13
(0.140 ± 0.005)
0.635 ± 0.25
(0.025 ± 0.010) 12° NOM.
9.65 ± 0.25
(0.380 ± 0.010)
0.635 ± 0.130
(0.025 ± 0.005)
7.62 ± 0.25
(0.300 ± 0.010)
5
6
7
8
4
3
2
1
9.80 ± 0.25
(0.386 ± 0.010)
6.350 ± 0.25
(0.250 ± 0.010)
1.016 (0.040)
1.27 (0.050)
10.9 (0.430)
2.0 (0.080)
LAND PATTERN RECOMMENDATION
1.080 ± 0.320
(0.043 ± 0.013)
1.780
(0.070)
MAX.
1.19
(0.047)
MAX.
2.54
(0.100)
BSC
DIMENSIONS IN MILLIMETERS (INCHES).
LEAD COPLANARITY = 0.10 mm (0.004 INCHES).
0.254 + 0.076
- 0.051
(0.010+ 0.003)
- 0.002)
NOTE: FLOATING LEAD PROTRUSION IS 0.5 mm (20 mils) MAX.
3.56 ± 0.13
(0.140 ± 0.005)
5
HCPL-J454-400E/600E Widelead Gullwing Surface Mount Outline Drawing
HCPL-0454 Outline Drawing (8-Pin Small Outline Package)
XXX
YWW
8765
4321
5.994 ± 0.203
(0.236 ± 0.008)
3.937 ± 0.127
(0.155 ± 0.005)
0.406 ± 0.076
(0.016 ± 0.003) 1.270
(0.050)BSC
5.080 ± 0.127
(0.200 ± 0.005)
3.175 ± 0.127
(0.125 ± 0.005) 1.524
(0.060)
45 X 0.432
(0.017)
0.228 ± 0.025
(0.009 ± 0.001)
TYPE NUMBER
(LAST 3 DIGITS)
DATE CODE
0.305
(0.012)MIN.
TOTAL PACKAGE LENGTH (INCLUSIVE OF MOLD FLASH)
5.207 ± 0.254 (0.205 ± 0.010)
DIMENSIONS IN MILLIMETERS (INCHES).
LEAD COPLANARITY = 0.10 mm (0.004 INCHES) MAX.
NOTE: FLOATING LEAD PROTRUSION IS 0.15 mm (6 mils) MAX.
0.203 ± 0.102
(0.008 ± 0.004)
7
PIN ONE
0 ~ 7
*
*
7.49 (0.295)
1.9 (0.075)
0.64 (0.025)
LAND PATTERN RECOMMENDATION
[0.65] 0.025 MAX
0.250 ±0.010
6.35 ±0.25
0.386 ±0.010
9.80 ±0.25
MAX.
[1.19]
0.047
0.140 ±0.005
3.56±0.13
0.100
BSC
2.54
0.043 0.013
[1.080] 0.320
DIMENSIONS IN [MILLIMETERS] INCHES
OPTION NUMBERS 400 AND 600 NOT MARKED.
NOTE: FLOATING LEAD PROTRUSION IS 0.5 mm (20 mils) MAX.
LEAD COPLANARITY
MAXIMUM: [0.102] 0.004
LAND PATTERN RECOMMENDATION
0.460 0.010
[11.75 0.25]
[0.406] 0.016
[0.152] 0.006
0.025 ±0.010
0.625 ±0.254
0.300±0.020
7.62±0.51
[0.33] 0.013
[0.20] 0.008
30° NOM.
0.040
1.016
0.508
12.9
0.08
2.0
0.050
1.27
A XXXX
YYWW
DATE CODE
UR
TYPE NUMBER
UL
RECOGNITION
6
HCNW4504 Outline Drawing (8-Pin Widebody Package)
5
6
7
8
4
3
2
1
11.15 ± 0.15
(0.442 ± 0.006)
1.78 ± 0.15
(0.070 ± 0.006)
5.10
(0.201)MAX.
1.55
(0.061)
MAX.
2.54 (0.100)
TYP.
DIMENSIONS IN MILLIMETERS (INCHES).
NOTE: FLOATING LEAD PROTRUSION IS 0.25 mm (10 mils) MAX.
7° TYP. 0.254 + 0.076
- 0.0051
(0.010+ 0.003)
- 0.002)
11.00
(0.433)
9.00 ± 0.15
(0.354 ± 0.006)
MAX.
10.16 (0.400)
TYP.
A
HCNWXXXX
YYWW
DATE CODE
TYPE NUMBER
0.51 (0.021) MIN.
0.40 (0.016)
0.56 (0.022)
3.10 (0.122)
3.90 (0.154)
HCNW4504 Gull Wing Surface Mount Option 300 Outline Drawing
1.00 ± 0.15
(0.039 ± 0.006)
7° NOM.
12.30 ± 0.30
(0.484 ± 0.012)
0.75 ± 0.25
(0.030 ± 0.010)
11.00
(0.433)
5
6
7
8
4
3
2
1
11.15 ± 0.15
(0.442 ± 0.006)
9.00 ± 0.15
(0.354 ± 0.006)
1.3
(0.051)
13.56
(0.534)
2.29
(0.09)
LAND PATTERN RECOMMENDATION
1.78 ± 0.15
(0.070 ± 0.006)
4.00
(0.158)MAX.
1.55
(0.061)
MAX.
2.54
(0.100)
BSC
DIMENSIONS IN MILLIMETERS (INCHES).
LEAD COPLANARITY = 0.10 mm (0.004 INCHES).
NOTE: FLOATING LEAD PROTRUSION IS 0.25 mm (10 mils) MAX.
0.254 + 0.076
- 0.0051
(0.010+ 0.003)
- 0.002)
MAX.
7
Solder Refl ow Temperature Profi le
Recommended Pb-Free IR Profi le
0
TIME (SECONDS)
TEMPERATURE (°C)
200
100
50 150100 200 250
300
0
30
SEC.
50 SEC.
30
SEC.
160 °C
140 °C
150 °C
PEAK
TEMP.
245 °C
PEAK
TEMP.
240 °CPEAK
TEMP.
230 °C
SOLDERING
TIME
200 °C
PREHEATING TIME
150 °C, 90 + 30 SEC.
2.5 C ± 0.5 °C/SEC.
3 °C + 1 °C/–0.5 °C
TIGHT
TYPICAL
LOOSE
ROOM
TEMPERATURE
PREHEATING RATE 3 °C + 1 °C/–0.5 °C/SEC.
REFLOW HEATING RATE 2.5 °C ± 0.5 °C/SEC.
NOTE: NON-HALIDE FLUX SHOULD BE USED.
217 °C
RAMP-DOWN
6 °C/SEC. MAX.
RAMP-UP
3 °C/SEC. MAX.
150 - 200 °C
* 260 +0/-5 °C
t 25 °C to PEAK
60 to 150 SEC.
15 SEC.
TIME WITHIN 5 °C of ACTUAL
PEAK TEMPERATURE
tp
ts
PREHEAT
60 to 180 SEC.
tL
TL
Tsmax
Tsmin
25
Tp
TIME
TEMPERATURE
NOTES:
THE TIME FROM 25 °C to PEAK TEMPERATURE = 8 MINUTES MAX.
Tsmax = 200 °C, Tsmin = 150 °C
NOTE: NON-HALIDE FLUX SHOULD BE USED.
* RECOMMENDED PEAK TEMPERATURE FOR WIDEBODY 400mils PACKAGE IS 245 °C
8
All Avago data sheets report the creepage and clearance
inherent to the optocoupler component itself. These di-
mensions are needed as a starting point for the equip-
ment designer when determining the circuit insulation
requirements.
However, once mounted on a printed circuit board, mini-
mum creepage and clearance requirements must be
met as specifi ed for individual equipment standards. For
Insulation and Safety Related Specifi cations
Parameter Symbol
Value
Units Conditions
HCPL-
4504
HCPL-
J454
-400E/-600E
HCPL-J454
All other
options
HCPL-
0454
HCNW
4504
Minimum External
Air Gap
(External Clearance)
L(101) 7.1 8.0 7.4 4.9 9.6 mm Measured from input ter-
minals to output terminals,
shortest distance through air.
Minimum External
Tracking
(External Creepage)
L(102) 7.4 8.0 8.0 4.8 10.0 mm Measured from input ter-
minals to output terminals,
shortest distance path along
body.
Minimum Internal
Plastic Gap
(Internal Clearance)
0.08 0.5 0.5 0.08 1.0 mm Through insulation distance,
conductor to conductor,
usually the direct distance
between the photoemitter
and photodetector inside the
optocoupler cavity.
Minimum Internal
Tracking (Internal
Creepage)
NA NA NA NA 4.0 mm Measured from input ter-
minals to output terminals,
along internal cavity.
Tracking Resistance
(Comparative
Tracking Index)
CTI ≥175 ≥175 ≥175 ≥175 ≥200 Volts DIN IEC 112/VDE 0303 Part 1
Isolation Group IIIa IIIa IIIa IIIa IIIa Material Group (DIN VDE
0110, 1/89, Table 1)
creepage, the shortest distance path along the surface
of a printed circuit board between the solder fi llets of
the input and output leads must be considered. There
are recommended techniques such as grooves and ribs
which may be used on a printed circuit board to achieve
desired creepage and clearances. Creepage and clear-
ance distances will also change depending on factors
such as pollution degree and insulation level.
Regulatory Information
The devices contained in this data sheet have been approved by the following agencies:
Agency/Standard HCPL-4504 HCPL-J454 HCPL-0454 HCNW4504
Underwriters Laboratories (UL)
Recognized under UL1577,
Component Recognition Program,
Category FPQU2, File E55361
UL1577 3750 Vrms /
1 minute,
Option 020 5000
Vrms / 1 minute
3750 Vrms /
1 minute
3750 Vrms /
1 minute
5000 Vrms /
1 minute
Canadian Standards Association (CSA)
File CA88324
Component
Acceptance
Notice #5
3750 Vrms /
1 minute,
Option 020 5000
Vrms / 1 minute
3750 Vrms /
1 minute
3750 Vrms /
1 minute
5000 Vrms /
1 minute
IEC/EN/DIN EN 60747-5-2
Approved under:
IEC 60747-5-2:1997 + A1:2002
EN 60747-5-2:2001 + A1:2002
DIN EN 60747-5-2 (VDE 0884 Teil 2):2003-01
Option 060
VIORM = 630 Vpeak
VIORM = 891
Vpeak
Option 060
VIORM = 560
Vpeak
VIORM = 1414
Vpeak
9
IEC/EN/DIN EN 60747-5-2 Insulation Related Characteristics
Description Symbol
HCPL-0454 HCPL-4504
HCPL-J454 HCNW4504 UnitOPTION 060 OPTION 060
Installation classifi cation per
DIN VDE 0110/1.89, Table 1
for rated mains voltage ≤150 V rms
for rated mains voltage ≤300 V rms
for rated mains voltage ≤450 V rms
for rated mains voltage ≤600 V rms
for rated mains voltage ≤1000 V rms
I-IV
I-III
I-IV
I-IV
I-III
I-IV
I-IV
I-III
I-III
I-IV
I-IV
I-IV
I-IV
I-III
Climatic Classifi cation 55/100/21 55/100/21 55/100/21 55/85/21
Pollution Degree (DIN VDE 0110/1.89) 2 2 2 2
Maximum Working Insulation Voltage VIORM 560 630 891 1414 V peak
Input to Output Test Voltage, Method b*
V
IORM x 1.875 = VPR, 100% Production
Test with tm = 1 sec,
Partial Discharge < 5 pC
VPR 1050 1181 1670 2652 V peak
Input to Output Test Voltage, Method a*
V
IORM x 1.5 = VPR, Type and Sample
Test, tm = 60 sec,
Partial Discharge < 5 pC
VPR 840 945 1336 2121 V peak
Highest Allowable Overvoltage*
(Transient Overvoltage, tini = 10 sec)
Safety Limiting Values - Maximum
Values Allowed in the Event of a Failure,
also see Thermal Derating curve
VIOTM 4000 6000 6000 8000 V peak
Case Temperature TS150 175 175 150 °C
Input Current IS,INPUT 150 230 400 400 mA
Output Power PS,OUTPUT 600 600 600 700 mW
Insulation Resistance at TS,
V
IO = 500 V
RS≥109≥109≥109≥109Ω
*Refer to the optocoupler section of the Designer's Catalog, under regulatory information (IEC/EN/DIN EN 60747-5-2) for a detailed description of
Method a and Method b partial discharge test profi les.
NOTE: These optocouplers are suitable for "safe electrical isolation" only within the safety limit data. Maintenance of the safety data shall be ensured
by means of protective circuits.
NOTE: Insulation Characteristics are per IEC/EN/DIN EN 60747-5-2.
NOTE: Surface mount classifi cation is Class A in accordance with CECC 00802.
10
Absolute Maximum Ratings
Parameter Symbol Device Min.Max. Units Note
Storage Temperature TS-55 125 °C
Operating Temperature TAHCPL-4504
HCPL-0454
HCPL-J454
-55 100 °C
HCNW4504 -55 85
Average Forward Input Current IF(AVG) 25 mA 1
Peak Forward Input Current
(50% duty cycle, 1 ms pulse width)
IF(PEAK) HCPL-4504
HCPL-0454
50 mA 2
HCPL-J454
HCNW4504
40
Peak Transient Input Current
(≤1 μs pulse width, 300 pps)
IF(TRANS) HCPL-4504
HCPL-0454
1A
HCPL-J454
HCNW4504
0.1
Reverse LED Input Voltage (Pin 3-2)
VRHCPL-4504
HCPL-0454
5V
HCPL-J454
HCNW4504
3
Input Power Dissipation
PIN HCPL-4504
HCPL-0454
45 mW 3
HCPL-J454
HCNW4504
40
Average Output Current (Pin 6) IO(AVG) 8mA
Peak Output Current IO(PEAK) 16 mA
Supply Voltage (Pin 8-5) VCC -0.5 30 V
Output Voltage (Pin 6-5) VO-0.5 20 V
Output Power Dissipation PO100 mW 4
Lead Solder Temperature
(Through-Hole Parts Only)
1.6 mm below seating plane, 10 seconds
TLS HCPL-4504
HCPL-J454
260 °C
Up to seating plane, 10 seconds HCNW4504 260
Refl ow Temperature Profi le TRP HCPL-0454,
Option 300 ,
Option 500,
Option 400E
& Option 600E.
See Package Outline Drawings
section
11
Electrical Specifi cations (DC)
Over recommended temperature (TA = 0°C to 70°C) unless otherwise specifi ed. See note 12.
Parameter Symbol Device Min.Typ.* Max. Units Test Conditions Fig.Note
Current
Transfer
Ratio
CTR HCPL-4504
HCPL-0454
25 32 60 % TA = 25°C VO = 0.4 V IF = 16 mA,
VCC = 4.5 V
1, 2,
4
5
21 34 VO = 0.5 V
HCPL-J454 19 37 60 TA = 25°C VO = 0.4 V
13 39 VO = 0.5 V
HCNW4504 23 29 60 TA = 25°C VO = 0.4 V
19 31 63 VO = 0.5 V
Current
Transfer
Ratio
CTR HCPL-4504
HCPL-0454
26 35 65 % TA = 25°C VO = 0.4 V IF = 12 mA,
VCC = 4.5 V
1, 2,
4
5
22 37 VO = 0.5 V
HCPL-J454 21 43 65 TA = 25°C VO = 0.4 V
16 45 VO = 0.5 V
HCNW4504 25 33 65 TA = 25°C VO = 0.4 V
21 35 68 VO = 0.5 V
Logic Low
Output
Voltage
VOL HCPL-4504
HCPL-0454
0.2 0.4 V TA = 25°C IO = 4.0 mA IF = 16 mA,
VCC = 4.5 V
0.5 IO = 3.3 mA
HCPL-J454 0.2 0.4 TA = 25°C IO = 3.6 mA
0.5 IO = 3.0 mA
HCNW4504 0.2 0.4 TA = 25°C IO = 3.6 mA
0.5 IO = 3.0 mA
Logic High
Output
Current
IOH 0.003 0.5 μA TA = 25°C VO = VCC = 5.5 V IF = 0 mA 5
0.01 1 TA = 25°C VO = VCC = 15 V
50
Logic Low
Supply
Current
ICCL HCPL-4504
HCPL-0454
HCNW4504
50 200 μA IF = 16 mA, VO = Open, VCC = 15 V 12
HCPL-J454 70
Logic High
Supply Current
ICCH 0.02 1 μA TA = 25°C IF = 0 mA, VO = Open, 12
2V
CC = 15 V
Input Forward
Voltage
VFHCPL-4504
HCPL-0454
1.5 1.7 V TA = 25°C IF = 16 mA 3
1.8
HCPL-J454
HCNW4504
1.45 1.59 1.85 TA = 25°C IF = 16 mA
1.35 1.95
Input Reverse
Breakdown
Voltage
BVRHCPL-4504
HCPL-0454
5VI
R = 10 μA
HCPL-J454
HCNW4504
3I
R = 100 μA
Temperature
Coeffi cient
of Forward
Voltage
∆VF
∆TA
HCPL-4504
HCPL-0454
-1.6 mV/°C IF = 16 mA
HCPL-J454
HCNW4504
-1.4
Input
Capacitance
CIN HCPL-4504
HCPL-0454
60 pF f = 1 MHz, VF = 0 V
HCPL-J454
HCNW4504
70
*All typicals at TA = 25°C.
12
AC Switching Specifi cations
Over recommended temperature (TA = 0°C to 70°C) unless otherwise specifi ed.
Parameter Symbol Device Min.Typ.Max. Units Test Conditions Fig.Note
Propagation Delay
Time to Logic Low
at Output
tPHL 0.2 0.3 μs TA = 25°C Pulse: f = 20 kHz,
Duty Cycle = 10%,
IF = 16 mA, VCC = 5.0 V,
RL = 1.9 kΩ, CL = 15 pF,
VTHHL = 1.5 V
6,
8, 9
9
0.2 0.5
tPHL 0.2 0.5 0.7 μs TA = 25°C Pulse: f = 10 kHz,
Duty Cycle = 50%,
IF = 12 mA, VCC = 15.0 V,
RL = 20 kΩ, CL = 100 pF,
VTHHL = 1.5 V
6,
10-14
10
HCPL-
J454
0.05 1.0
Others 0.1
Propagation Delay
Time to Logic High
at Output
tPLH 0.3 0.5 μs TA = 25°C Pulse: f = 20 kHz,
Duty Cycle = 10%,
IF = 16 mA, VCC = 5.0 V,
RL = 1.9 kΩ, CL = 15 pF,
VTHLH = 1.5 V
6,
8, 9
9
0.3 0.7
tPLH 0.3 0.8 1.1 μs TA = 25°C Pulse: f = 10 kHz,
Duty Cycle = 50%,
IF = 12 mA, VCC = 15.0 V,
RL = 20 kΩ, CL = 100 pF,
VTHLH = 2.0 V
6,
10-14
10
0.2 0.8 1.4
Propagation Delay
Diff erence Be-
tween Any 2 Parts
tPLH-
tPHL
-0.4 0.3 0.9 μs TA = 25°C Pulse: f = 10 kHz,
Duty Cycle = 50%,
IF = 12 mA, VCC = 15.0 V,
RL = 20 kΩ, CL = 100 pF,
VTHHL = 1.5 V, VTHLH = 2.0 V
6,
10-14
17
-0.7 0.3 1.3
Common Mode
Transient Immu-
nity at Logic High
|CMH| 15 30 kV/μs TA = 25°C
VCM =
1500 VP-P
VCC = 5.0 V, RL = 1.9 kΩ,
CL = 15 pF, IF = 0 mA
7 7, 9
|CMH|
15 30 kV/μs VCC = 15.0 V, RL = 20 kΩ,
CL = 100 pF, IF = 0 mA
7 8, 10
Level Output
Common Mode
Transient Immu-
nity at Logic Low
Level Output
|CML| 15 30 kV/μs TA = 25°C
VCM =
1500 VP-P
VCC = 5.0 V, RL = 1.9 kΩ,
CL = 15 pF, IF = 16 mA
7 7, 9
|CML| HCPL-
J454
15 30 kV/μs VCC = 15.0 V, RL = 20 kΩ,
CL = 100 pF, IF = 12 mA
7 8, 10
Others 10
|CML| 15 30 kV/μs VCC = 15.0 V, RL = 20 kΩ,
CL = 100 pF, IF = 16 mA
7 8, 10
*All typicals at TA = 25°C.
13
Package Characteristics
Over recommended temperature (TA = 0°C to 25°C) unless otherwise specifi ed.
Parameter Symbol Device Min.Typ.* Max. Units Test Conditions Figure Note
Input-Output
Momentary
Withstand
Voltage†
VISO HCPL-4504
HCPL-0454
3750 V rms RH ≤50%,
t = 1 min.,
TA = 25°C
6, 13,
16
HCPL-J454 3750 6, 14,
16
HCPL-4504
Option 020
5000 6, 11,
15
HCNW4504 5000 6, 15,
16
Input-Output
Resistance
RI-O HCPL-4504
HCPL-0454
HCPL-J454
1012 ΩV
I-O = 500 Vdc 6
HCNW4504 1012 1013 TA = 25°C
1011 TA = 100°C
Capacitance
(Input-Output)
CI-O HCPL-4504
HCPL-0454
0.6 pF f = 1 MHz 6
HCPL-J454 0.8
HCNW4504 0.5 0.6
All typicals at TA = 25°C..
†The Input-Output Momentary Withstand Voltage is a dielectric voltage rating that should not be interpreted as an input-output continuous
voltage rating. For the continuous voltage rating refer to the IEC/EN/DIN EN 60747-5-2 Insulation Related Characteristics Table (if applicable), your
equipment level safety specifi cation or Avago Application Note 1074 entitled “Optocoupler Input-Output Endurance Voltage.”
Notes:
1. Derate linearly above 70°C free-air temperature at a rate of 0.8 mA/°C (8-Pin DIP).
Derate linearly above 85°C free-air temperature at a rate of 0.5 mA/°C (SO-8).
2. Derate linearly above 70°C free-air temperature at a rate of 1.6 mA/°C (8-Pin DIP).
Derate linearly above 85°C free-air temperature at a rate of 1.0 mA/°C (SO-8).
3. Derate linearly above 70°C free-air temperature at a rate of 0.9 mW/°C (8-Pin DIP).
Derate linearly above 85°C free-air temperature at a rate of 1.1 mW/°C (SO-8).
4. Derate linearly above 70°C free-air temperature at a rate of 2.0 mW/°C (8-Pin DIP).
Derate linearly above 85°C free-air temperature at a rate of 2.3 mW/°C (SO-8).
5. CURRENT TRANSFER RATIO in percent is defi ned as the ratio of output collector current, IO, to the forward LED input current, IF, times 100.
6. Device considered a two-terminal device: Pins 1, 2, 3, and 4 shorted together and Pins 5, 6, 7, and 8 shorted together.
7. Under TTL load and drive conditions: Common mode transient immunity in a Logic High level is the maximum tolerable (positive) dVCM/dt on
the leading edge of the common mode pulse, VCM, to assure that the output will remain in a Logic High state (i.e., V
O > 2.0 V). Common mode
transient immunity in a Logic Low level is the maximum tolerable (negative) dVCM/dt on the trailing edge of the common mode pulse signal,
VCM, to assure that the output will remain in a Logic Low state (i.e., VO < 0.8 V).
8. Under IPM (Intelligent Power Module) load and LED drive conditions: Common mode transient immunity in a Logic High level is the maximum
tolerable dVCM/dt on the leading edge of the common mode pulse, VCM, to assure that the output will remain in a Logic High state (i.e., VO > 3.0
V). Common mode transient immunity in a Logic Low level is the maximum tolerable dVCM/dt on the trailing edge of the common mode pulse
signal, VCM, to assure that the output will remain in a Logic Low state (i.e., VO < 1.0 V).
9. The 1.9 kΩ load represents 1 TTL unit load of 1.6 mA and the 5.6 kΩ pull-up resistor.
10. The RL = 20 kΩ, CL = 100 pF load represents an IPM (Intelligent Power Module) load.
11. See Option 020 data sheet for more information.
12. Use of a 0.1 μF bypass capacitor connected between Pins 5 and 8 is recommended.
13. In accordance with UL 1577, each optocoupler is proof tested by applying an insulation test voltage ≥4500 V rms for 1 second (leakage detection
current limit, Ii-o ≤5 μA).
14. In accordance with UL 1577, each optocoupler is proof tested by applying an insulation test voltage ≥4500 V rms for 1 second (leakage detection
current limit, Ii-o ≤ 5 μA).
15. In accordance with UL 1577, each optocoupler is proof tested by applying an insulation test voltage ≥6000 V rms for 1 second (leakage detection
current limit, Ii-o ≤5 μA).
16. This test is performed before the 100% Production test shown in the VDE 0884 Insulation Related Characteristics Table, if applicable.
17. The diff erence between tPLH and tPHL between any two devices (same part number) under the same test condition. (See Power Inverter Dead
Time and Propagation Delay Specifi cations section.)
14
Figure 1. DC and pulsed transfer characteristics.
Figure 2. Current transfer ratio vs. input current.
Figure 3. Input current vs. forward voltage.
010 20
VO – OUTPUT VOLTAGE – V
IO – OUTPUT CURRENT – mA
10
5
0
T = 25°C
V = 5.0 V
A
CC
40 mA
35 mA
30 mA
25 mA
20 mA
15 mA
10 mA
I = 5 mA
F
HCPL-4504/0454
010 20
V
O
– OUTPUT VOLTAGE – V
I
O
– OUTPUT CURRENT – mA
20
10
0
T = 25°C
V = 5.0 V
A
CC
40 mA
35 mA
30 mA
25 mA
20 mA
15 mA
10 mA
I = 5 mA
F
HCNW4504
2
4
6
8
12
14
16
18
I
F
– INPUT CURRENT – mA
NORMALIZED CURRENT TRANSFER RATIO
1.5
1.0
0.5
0.0 2 4 6 8 10 12 14 16 18
020 22 24 26
I
F
= 16 mA
V
O
= 0.4 V
V
CC
= 5.0 V
T
A
= 25°C
NORMALIZED
HCPL-4504/0454
I
F
– INPUT CURRENT – mA
NORMALIZED CURRENT TRANSFER RATIO
1.6
0.8
051015020 25
I
F
= 16 mA
V
O
= 0.4 V
V
CC
= 5.0 V
T
A
= 25°C
NORMALIZED
HCNW4504
0.4
1.2
2.0
V
F
– FORWARD VOLTAGE – VOLTS
100
10
0.1
0.01
1.1 1.2 1.3 1.4
I
F
– FORWARD CURRENT – mA
1.61.5
1.0
0.001
1000
I
F
V
F
+T = 25°C
A
–
HCPL-4504/0454
V
F
– FORWARD VOLTAGE – VOLTS
100
10
0.1
0.01
1.2 1.3 1.4 1.5
I
F
– FORWARD CURRENT – mA
1.71.6
1.0
0.001
1000
I
F
V
F
+
T = 25°C
A
–
HCPL-J454/HCNW4504
15
Figure 6. Switching test circuit.
Figure 4. Current transfer ratio vs. temperature.
Figure 5. Logic high output current vs. temperature.
Figure 7. Test circuit for transient immunity and typical waveforms.
T
A
– TEMPERATURE – °C
NORMALIZED CURRENT TRANSFER RATIO
1.0
0.8
0.6
1.1
0.7
0.9
-40 -20 020 40 60 80 100 120-60
I
F
= 16 mA
V
O
= 0.4 V
V
CC
= 5.0 V
T
A
= 25°C
NORMALIZED
HCPL-4504/0454
NORMALIZED CURRENT TRANSFER RATIO
-60
0.85
T
A
– TEMPERATURE – °C
10060
1.05
0.9
-20 20
1.0
0.95
NORMALIZED
I
F
= 16 mA
V
O
= 0.4 V
V
CC
= 5.0 V
T
A
= 25° C
80400-40
HCPL-J454
T
A
– TEMPERATURE – °C
NORMALIZED CURRENT TRANSFER RATIO
1.0
0.9
0.85
1.05
0.95
-40 -20 020 40 60 80 100 120-60
I
F
= 16 mA
V
O
= 0.4 V
V
CC
= 5.0 V
T
A
= 25°C
NORMALIZED
HCNW4504
T
A
– TEMPERATURE – °C
I
OH
– LOGIC HIGH OUTPUT CURRENT – nA
10 4
10 3
10 2
10 1
10 0
10-1
10-2
-40 -20 0 20 40 60 80 100 120
-60
I
F
= 0 mA
V
O
= V
CC
= 5.0 V
VO
PULSE
GEN.
Z = 50 Ω
t = 5 ns
O
r
I MONITOR
F
IF
0.1µF
L
R
C
L
RM
0
tPHL tPLH
O
V
IF
OL
V
THHL
VTHLH
V
VCC
VCC
1
2
3
4
8
7
6
5
VO
IF
0.1µF
L
R
A
B
PULSE GEN.
VCM
+
VFF L
C
O
V
OL
V
O
V
0 V 10%
90% 90%
10%
SWITCH AT A: I = 0 mA
F
SWITCH AT B: I = 12 mA, 16 mA
F
CM
V
trtf
CC
V
VCC
–
1
2
3
4
8
7
6
5
16
Figure 11. Propagation delay time vs. temperature.
Figure 8. Propagation delay time vs. temperature.
Figure 10. Propagation delay time vs. load
resistance.
Figure 9. Propagation delay time vs. load resis-
tance.
T
A
– TEMPERATURE – °C
t
p
– PROPAGATION DELAY – µs
0.50
0.45
0.40
0.35
0.30
0.25
0.20
0.15
0.10 -40 -20 0 20 40 60 80 100 120
-60
V
CC
= 5.0 V
R
L
= 1.9 kΩ
C
L
= 15 pF
V
THHL
t
PLH
t
PHL
I
F
= 10 mA
I
F
= 16 mA
= V
THLH
= 1.5 V
10% DUTY CYCLE
HCPL-4504/0454
T
A
– TEMPERATURE – °C
t
p
– PROPAGATION DELAY – µs
0.50
0.45
0.40
0.35
0.30
0.25
0.20
0.15
0.10 -40 -20 0 20 40 60 80 100 120
-60
V
CC
= 5.0 V
R
L
= 1.9 kΩ
C
L
= 15 pF
V
THHL
t
PLH
t
PHL
I
F
= 10 mA
I
F
= 16 mA
= V
THLH
= 1.5 V
10% DUTY CYCLE
HCPL-J454/HCNW4504
R
L
– LOAD RESISTANCE – kΩ
t
p
– PROPAGATION DELAY – µs
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0 2 4 6 8 10 12 14 16 180 20
1.6
1.8
2.0
2.2
2.4
2.6 V
CC
= 5.0 V
T
A
= 25° C
C
L
= 100 pF
V
THHL
= 1.5 V
V
THLH
= 2.0 V
I
F
= 10 mA
I
F
= 16 mA
t
PLH
t
PHL
50% DUTY CYCLE
T
A
– TEMPERATURE – °C
t
p
– PROPAGATION DELAY – µs
1.1
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3 -40 -20 0 20 40 60 80 100 120
-60
V
CC
= 15.0 V
R
L
= 20 kΩ
C
L
= 100 pF
V
THHL
= 1.5 V
V
THLH
= 2.0 V t
PLH
t
PHL
I
F
= 10 mA
I
F
= 16 mA
50% DUTY CYCLE
HCPL-4504/0454
T
A
– TEMPERATURE – °C
t
p
– PROPAGATION DELAY – µs
1.1
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3 -40 -20 0 20 40 60 80 100 120
-60
V
CC
= 15.0 V
R
L
= 20 kΩ
C
L
= 100 pF
V
THHL
= 1.5 V
V
THLH
= 2.0 V t
PLH
t
PHL
I
F
= 10 mA
I
F
= 16 mA
50% DUTY CYCLE
HCPL-J454/HCNW4504
Figure 14. Propagation delay time vs. supply
voltage.
Figure 13. Propagation delay time vs. load
capacitance.
Figure 12. Propagation delay time vs. load
resistance.
R
L
– LOAD RESISTANCE – kΩ
t
p
– PROPAGATION DELAY – µs
1.6
1.4
1.2
1.0
0.6
0.2
0.0 5 10152025303540450
V
CC
= 15.0 V
T
A
= 25° C
C
L
= 100 pF
V
THHL
= 1.5 V
V
THLH
= 2.0 V
50
t
PLH
t
PHL
1.8
0.4
0.8
I
F
= 10 mA
I
F
= 16 mA
50% DUTY CYCLE
C
L
– LOAD CAPACITANCE – pF
t
p
– PROPAGATION DELAY – µs
2.0
1.5
0.5
0.0
100 200 300 400 500 600 700 800 9000
V
CC
= 15.0 V
T
A
= 25° C
R
L
= 20 kΩ
V
THHL
= 1.5 V
V
THLH
= 2.0 V
1000
t
PLH
t
PHL
2.5
3.0
3.5
1.0
I
F
= 10 mA
I
F
= 16 mA
50% DUTY CYCLE
V
CC
– SUPPLY VOLTAGE – V
tp – PROPAGATION DELAY – µs
0.9
0.8
0.6
0.2 11 12 13 14 15 16 17 18 1910 20
1.0
1.1
1.2
0.7
T
A
= 25° C
R
L
= 20 kΩ
C
L
= 100 pF
V
V
0.5
0.4
0.3
t
PLH
t
PHL
I
F
= 10 mA
I
F
= 16 mA
50% DUTY CYCLE
THHL
= 1.5 V
= 2.0 V
THLH
17
Figure 15. Thermal derating curve, dependence of safety limiting valve with case temperature per
IEC/EN/DIN EN 60747-5-2.
OUTPUT POWER – PS, INPUT CURRENT – IS
0
0
TS – CASE TEMPERATURE – °C
20050
400
12525 75 100 150
600
800
200
100
300
500
700
HCPL-4504 OPTION 060/HCPL-J454
175
(230)
PS (mW)
IS (mA) for HCPL-4504
OPTION 060
IS (mA) for HCPL-J454
OUTPUT POWER – P
S
, INPUT CURRENT – I
S
0
0
T
S
– CASE TEMPERATURE – °C
175
1000
50
400
12525 75 100 150
600
800
200
100
300
500
700
900
HCPL-0454 OPTION 060/HCNW4504
P
S
(mW) for HCNW4504
I
S
(mA) for HCNW4504
P
S
(mW) for HCPL-0454
OPTION 060
I
S
(mA) for HCPL-0454
OPTION 060
(150)
Figure 16. Typical power inverter.
BASE/GATE
DRIVE CIRCUIT
HCPL-4504/0454/J454
HCNW4504
2
3
8
7
6
5
+HV
Q1
LED 1
OUT 1
BASE/GATE
DRIVE CIRCUIT
2
3
8
7
6
5
–HV
Q2
LED 2
OUT 2
+
+
HCPL-4504/0454/J454
HCNW4504
18
Power Inverter Dead Time and Propagation Delay Specifi ca-
tions
The HCPL-4504/0454/J454 and HCNW4504 include a
specifi ca tion intended to help designers minimize “dead
time” in their power inverter designs. The new “propaga-
tion delay diff erence” specifi cation (tPLH - tPHL) is useful for
deter min ing not only how much optocoupler switch-
ing delay is needed to prevent “shoot-through” current,
but also for determin ing the best achievable worst-case
dead time for a given design.
When inverter power transis tors switch (Q1 and Q2 in
Figure 17), it is essential that they never conduct at the
same time. Extremely large currents will fl ow if there is
any overlap in their conduction during switching tran-
sitions, poten tially damaging the transistors and even
the sur rounding circuitry. This “shoot-through” current is
eliminated by delay ing the turn-on of one transistor (Q2)
long enough to ensure that the opposing transistor (Q1)
has completely turned off . This delay intro duces a small
amount of “dead time” at the output of the inverter dur-
ing which both transistors are off during switching tran-
sitions. Minimiz ing this dead time is an important design
goal for an inverter designer.
The amount of turn-on delay needed depends on the
propa ga tion delay characteristics of the optocoupler, as
well as the characteristics of the transistor base/gate drive
circuit. Consid er ing only the delay characteris tics of the
optocoupler (the charac teristics of the base/gate drive
circuit can be analyzed in the same way), it is important
to know the minimum and maximum turn-on (tPHL) and
turnoff (tPLH) propagation delay specifi ca tions, prefer-
ably over the desired operating temperature range. The
importance of these specifi cations is illustrated in Figure
17. The waveforms labeled “LED1”, “LED2”, “OUT1”, and
“OUT2” are the input and output voltages of the opto-
coupler circuits driving Q1 and Q2 respectively. Most in-
verters are designed such that the power transistor turns
on when the optocoupler LED turns on; this ensures that
both power transistors will be off in the event of a power
loss in the control circuit. Inverters can also be designed
such that the power transistor turns off when the opto-
coupler LED turns on; this type of design, however, re-
quires additional fail-safe circuitry to turn off the power
transistor if an over-current condition is detected. The
timing illustrated in Figure 17 assumes that the power
transistor turns on when the optocoupler LED turns on.
Figure 17. LED delay and dead time diagram.
For product information and a complete list of distributors, please go to our website: www.avagotech.com
Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies in the United States and other countries.
Data subject to change. Copyright © 2005-2009 Avago Technologies. All rights reserved. Obsoletes AV01-0552EN
AV02-0867EN - January 4, 2010
This expression can be rearranged to obtain
[(tPLHmax-tPHLmin)-(tPHLmin-tPHLmax)],
and further rearranged to obtain
[(tPLH-tPHL)max-(tPLH-tPHL)min],
which is the maximum minus the minimum data sheet
values of (tPLH-tPHL). The diff erence between the maxi-
mum and minimum values depends directly on the total
spread in propagation delays and sets the limit on how
good the worst-case dead time can be for a given design.
Therefore, opto coup lers with tight propagation delay
specifi cations (and not just shorter delays or lower pulse-
width distortion) can achieve short dead times in power
inverters. The HCPL-4504/0454/J454 and HCNW4504
specify a minimum (tPLH - tPHL) of -0.7 μs over an operat-
ing temperature range of 0-70°C, resulting in a maximum
dead time of 2.0 μs when the LED turn-on delay is equal
to (tPLH-tPHL)max, or 1.3 μs.
It is important to maintain accurate LED turn-on delays
because delays shorter than (tPLH - tPHL)max may allow
shoot-through currents, while longer delays will increase
the worst-case dead time.
The LED signal to turn on Q2 should be delayed enough
so that an optocoupler with the very fastest turn-on
propagation delay (tPHLmin) will never turn on before an
optocoupler with the very slowest turn-off propagation
delay (tPLHmax) turns off . To ensure this, the turn-on of the
optocoupler should be delayed by an amount no less
than (tPLHmax - tPHLmin), which also happens to be the max-
imum data sheet value for the propagation delay diff er-
ence specifi cation, (tPLH - tPHL). The HCPL-4504/0454/J454
and HCNW4504 specify a maxi mum (tPLH - tPHL) of 1.3 μs
over an operating temperature range of 0-70°C.
Although (tPLH-tPHL)max tells the designer how much delay
is needed to prevent shoot-through current, it is insuffi -
cient to tell the designer how much dead time a design
will have. Assuming that the optocoupler turn-on delay
is exactly equal to (tPLH - tPHL)max, the minimum dead time
is zero (i.e., there is zero time between the turnoff of the
very slowest optocoupler and the turn-on of the very
fastest optocoupler).
Calculating the maximum dead time is slightly more
compli cated. Assuming that the LED turn-on delay is still
exactly equal to (tPLH - tPHL)max, it can be seen in Figure 17
that the maximum dead time is the sum of the maximum
diff erence in turn-on delay plus the maxi mum diff erence
in turnoff delay,
[(tPLHmax-tPLHmin)+(tPHLmax-tPHLmin)].