Integrated Silicon Solution, Inc. 1
Rev. 00B
06/23/09
Copyright © 2006 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without
notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the lat-
est version of this device specification before relying on any published information and before placing orders for products.
IS43LR16160D, IS43LR32800D
ADVANCED INFORMATION
JULY 2009
FEATURES:
• Double-dataratearchitecture;twodatatransfers
per clock cycle
• Bidirectional,datastrobe(DQS)istransmitted/
received with data, to be used in capturing data
at the receiver
• DQSisedge-alignedwithdataforREADsand
centre-alignedwithdataforWRITEs
• Differentialclockinputs(CKandCK)
• CommandsenteredoneachpositiveCKedge;
data and data mask referenced to both edges of
DQS
• Fourinternalbanksforconcurrentoperation
• DataMaskforwritedata.DMmaskswritedata
at both rising and falling edges of data strobe
• BurstLength:2,4,and8
• BurstType:SequentialandInterleavemode
• ProgrammableCASlatency:2and3
• AutoRefreshandSelfRefreshModes
• AutoPrecharge
MOBILE FEATURES:
• Vd d andVd d q :1.8V+0.1V
• LVCMOScompatibleinputs
• TemperatureCompensatedSelfRefresh(TCSR)
controlled by on-chip temperature sensor
• PartialArraySelfRefresh(PASR)
• SelectableOutputDriveStrength(DS)
• ClockStop,PowerDownandDeepPowerDown
(DPD)modes
OPTIONS:
• Dierevision:D
• Conguration(s):8Mx32,16Mx16
• Package(s):90BallBGA(x32),
60BallBGA(x16)
• Lead-freepackageavailable
• TemperatureRange:Commercial(0°Cto+70°C)
andIndustrial(-40°Cto+85°C)
8Mx32, 16Mx16
256Mb Mobile DDR SDRAM
DESCRIPTION
ISSI’s256-MbitMobileDDRSDRAMachieveshigh-
speed data transfer using pipeline architecture and two
datawordaccessesperclockcycle.The268,435,456-
bit memory array is internally organized as four banks
of64Mbtoallowconcurrentoperations.Thepipeline
allowsReadandWriteburstaccessestobevirtually
continuous, with the option to concatenate or truncate
thebursts.Theprogrammablefeaturesofburstlength,
burstsequenceandCASlatencyenablefurther
advantages.Thedeviceisavailablein16-bitand32-bit
datawordsizeInputdataisregisteredontheI/Opins
onbothedgesofDataStrobesignal(s),whileoutput
dataisreferencedtobothedgesofDataStrobeand
bothedgesofCLK.Commandsareregisteredonthe
positiveedgesofCLK.
AnAutoRefreshmodeisprovided,alongwithapower
savingPower-downmode.SelfRefreshmodesinclude
TemperatureCompensatedSelfRefresh(TCSR)and
PartialArraySelfRefresh(PASR)options,whichallow
userstoachieveadditionalpowersaving.TheTCSR
andPASRoptionscanbeprogrammedviatheextended
moderegister.AllinputsareLVCMOScompatible.
ADDRESS TABLE
Parameter 8Mx32 16Mx16
Configuration
2Mx32x4
banks
4Mx16x4
banks
BankAddress
Pins
BA0,BA1 BA0,BA1
Autoprecharge
Pins
A10/AP A10/AP
RowAddresses
4K/(A0–A11) 8K/(A0–A12)
Column
Addresses
512(A0–A8) 512(A0–A8)
RefreshCount 8K/64ms 8K/64ms
KEY TIMING PARAMETERS
SpeedGrade -5 -6 -75 Units
Fc k MAXCL=3 200 166 133 MHz
Fc k MAXCL=2 83.3 83.3 83.3 MHz
2 Integrated Silicon Solution, Inc.
Rev. 00B
06/23/09
IS43LR16160D, IS43LR32800D
CLK
CKE
CS
RAS
CAS
WE
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
BA0
BA1
A10
A12
COMMAND
DECODER
&
CLOCK
GENERATOR
MODE
REGISTER
REFRESH
CONTROLLER
REFRESH
COUNTER
SELF
REFRESH
CONTROLLER
ROW
ADDRESS
LATCH
MULTIPLEXER
COLUMN
ADDRESSLATCH
BURSTCOUNTER
COLUMN
ADDRESSBUFFER
COLUMNDECODER
DATA IN
BUFFER
DATA OUT
BUFFER
DQML
DQMH
DQ0-15
VDD/VDDQ
Vss/VssQ
13
13
9
13
13
9
16
16 16
16
512
(x16)
8192
8192
8192
ROWDECODER
8192 MEMORYCELL
ARRAY
BANK 0
SENSEAMPI/OGATE
BANKCONTROLLOGIC
ROW
ADDRESS
BUFFER
A11
2
MODEREGISTER
ANDEXTENDED
MODEREGISTER
FUNCTIONAL BLOCK DIAGRAM (FOR 16Mx16 BANKS SHOWN)
Integrated Silicon Solution, Inc. 3
Rev. 00B
06/23/09
IS43LR16160D, IS43LR32800D
60-Ball
1 2 3 7 8 9
AVSS DQ15 VSSQ VDDQ DQ0 VDD
BVDDQ DQ13 DQ14 DQ1 DQ2 VSSQ
CVSSQ DQ11DQ12 DQ3 DQ4 VDDQ
DVDDQ DQ9 DQ10 DQ5 DQ6 VSSQ
EVSSQ UDQS DQ8 DQ7 LDQS VDDQ
FVSS UDM NC NC LDM VDD
GCKE CK CK WE CAS RAS
HA9 A11 A12 CS BA0 BA1
JA6 A7 A8 A10/AP A0 A1
KVSS A4 A5 A2 A3 VDD
F
E
D
C
B
J
H
G
A
K
47936512 8
Top View
(Balls seen through the package)
PIN CONFIGURATION:
Package Code B: 60-ball TF-BGA (top view)
(8mmx10mmBody,0.8mmBallPitch)
A0-A12 RowAddressInput
A0-A8 Column Address Input
BA0,BA1 BankSelectAddress
DQ0–DQ15 DataI/O
CK,CK System Clock Input
CKE ClockEnable
CS Chip Select
CAS Column Address Strobe Command
RAS RowAddressStrobeCommand
WE WriteEnable
LDM,UDM DataWriteMask
LDQS,UDQS DataStrobe
VDD Power
VDDQ PowerSupplyforI/OPins
VSS Ground
VSSQ GroundforI/OPins
NC NoConnection
PIN DESCRIPTION: for x16
4 Integrated Silicon Solution, Inc.
Rev. 00B
06/23/09
IS43LR16160D, IS43LR32800D
PIN CONFIGURATION:
Package Code B: 90-ball FBGA (top view)
(8mmx13mmBody,0.8mmBallPitch)
F
E
D
C
B
J
H
G
A
K
47936512 8
Top View
(Balls seen through the package)
L
P
N
M
R
90-Ball
1 2 3 7 8 9
AVSS DQ31 VSSQ VDDQ DQ16 VDD
BVDDQ DQ29 DQ30 DQ17 DQ18 VSSQ
CVSSQ DQ27 DQ28 DQ19 DQ20 VDDQ
DVDDQ DQ25 DQ26 DQ21 DQ22 VSSQ
EVSSQDQS3DQ24DQ23DQS2VDDQ
FVDDDM3 NC NC DM2 VSS
GCKECKCKWE CASRAS
HA9 A11 NC CS BA0 BA1
JA6 A7 A8 A10/AP A0 A1
KA4 DM1A5A2DM0 A3
LVSSQ DQS1 DQ8DQ7 DQS0 VDDQ
MVDDQ DQ9DQ10DQ5 DQ6 VSSQ
NVSSQ DQ11 DQ12 DQ3DQ4 VDDQ
PVDDQ DQ13 DQ14 DQ1DQ2 VSSQ
RVSS DQ15 VSSQ VDDQ DQ0VDD
PIN DESCRIPTION: for x32
A0-A11 RowAddressInput
A0-A8 Column Address Input
BA0,BA1 BankSelectAddress
DQ0–DQ31 DataI/O
CK,CK System Clock Input
CKE ClockEnable
CS Chip Select
CAS Column Address Strobe Command
RAS RowAddressStrobeCommand
WE WriteEnable
DM0–DM3 DataWriteMask
DQS0–DQS3 DataStrobe
VDD Power
VDDQ PowerSupplyforI/OPins
VSS Ground
VSSQ GroundforI/OPins
NC NoConnection
Integrated Silicon Solution, Inc. 5
Rev. 00B
06/23/09
IS43LR16160D, IS43LR32800D
Symbol Type Description
CK,CK Input Clock:CKandCK are differential clock inputs. All address and control input signals
aresampledonthecrossingofthepositiveedgeofCKandnegativeedgeofCK.
InputandoutputdataisreferencedtothecrossingofCKandCK(bothdirectionsof
crossing).InternalclocksignalsarederivedfromCK/CK.
CKE Input ClockEnable:CKEHIGHactivates,andCKELOWdeactivatesinternalclocksignals,
anddeviceinputbuffersandoutputdrivers.TakingCKELOWprovidesPRECHARGE
POWER-DOWNandSELFREFRESHoperation(allbanksidle),orACTIVE
POWERDOWN(rowACTIVEinanybank).CKEissynchronousforallfunctionsexcept
forSELFREFRESHEXIT,whichisachievedasynchronously.Inputbuffers,excluding
CK,CKandCKE,aredisabledduringpower-downandselfrefreshmodewhichare
contrived for low standby power consumption.
CS Input ChipSelect:CSenables(registeredLOW)anddisables(registeredHIGH)the
command decoder. All commands are masked when CSisregisteredHIGH.CS
providesforexternalbankselectiononsystemswithmultiplebanks.CS is considered
part of the command code.
RAS, CAS,
WE
Input WEInputCommandInputs:RAS, CAS and WE(alongwithCS)denethecommand
being entered.
DMforx16;
LDM,UDM
forx32;
DM0-DM3
Input InputDataMask:DMisaninputmasksignalforwritedata.Inputdataismasked
whenDMissampledHIGHalongwiththatinputdataduringaWRITEaccess.DM
issampledonbothedgesofDQS.AlthoughDMpinsareinput-only,theDMloading
matchestheDQandDQSloading.
Forx16devices,LDMcorrespondstothedataonDQ0-DQ7,UDMcorrespondstothe
dataonDQ8-DQ15.
Forx32devices,DM0correspondstothedataonDQ0-DQ7,DM1correspondsto
thedataonDQ8-DQ15,DM2correspondstothedataonDQ16-DQ23,andDM3
correspondstothedataonDQ24-DQ31.
BA0,BA1 Input InputBankAddressInputs:BA0andBA1denetowhichbankanACTIVE,READ,
WRITEorPRECHARGEcommandisbeingapplied.
A[n:0] Input AddressInputs:providetherowaddressforACTIVEcommands,andthecolumn
addressandAUTOPRECHARGEbitforREAD/WRITEcommands,toselectone
locationoutofthememoryarrayintherespectivebank.Theaddressinputsalso
providetheopcodeduringaMODEREGISTERSETcommand.
DQforx16;
DQ0-DQ15
forx32;
DQ0-DQ31
I/O DataBus:Input/Output
DQSforx16:
LDQS,UDDS
forx32:
DQS0-DQS3
I/O DataStrobe:Outputwithreaddata,inputwithwritedata.Edge-alignedwithreaddata,
centered with write data. Used to capture write data.
Forx16device,LDQScorrespondstothedataonDQ0-DQ7,UDQScorrespondsto
thedataonDQ8-DQ15.
Forx32device,DQS0correspondstothedataonDQ0-DQ7,DQS1correspondsto
thedataonDQ8-DQ15,DQS2correspondstothedataonDQ16-DQ23,andDQS3
correspondstothedataonDQ24-DQ31.
NC —NoConnect:Shouldbeleftunconnected.
VDDQ Supply I/OPowerSupply
VSSQ Supply I/OGround
VDD Supply PowerSupply
VSS Supply Ground
6 Integrated Silicon Solution, Inc.
Rev. 00B
06/23/09
IS43LR16160D, IS43LR32800D
ACT=Active
BST=BurstTerminate
CKEL=EnterPower-Down
CKEH=ExitPower-Down
DPDS=EnterDeepPower-Down
DPDSX=ExitDeepPower-Down
EMRS=Ext.ModeReg.Set
MRS=ModeRegisterSet
PRE=Precharge
PREALL=PrechargeAllBanks
REFA=AutoRefresh
REFS=EnterSelfRefresh
REFSX=ExitSelfRefresh
READ=Readw/oAutoPrecharge
READA=ReadwithAutoPrecharge
WRITE=Writew/oAutoPrecharge
WRITEA=WritewithAutoPrecharge
Note:Usecautionwiththisdiagram.Itisindentedtoprovideaoorplanofthepossiblestatetransitionsandcommandstocontrol
them, not all details. In particular situations involving more than one bank are not captured in full detail.
SIMPLIFIED STATE DIAGRAM
Power
On
Po wer
applied
ACT
Auto
Refresh
Active
Power
Down
CKEH
CKEL
WRITE
WRITE A
READ
READ AWRITEA
READA
WRITEA
PRE
READA
PRE
Automatic Sequence
Command Sequen ce
READ
CKEL
CKEH
PRE
PRE
WRITEREAD
Burst
Stop
Pr echarge
PREA LL
READ A
READWRITE
Row
Ac tive
MRS
EMRS
BST
Idle
All banks
precharg ed
Precharge
Po wer
Down
Precharge
All Banks
REFA
MR S
Deep
Power
Down
DPDSX
DPDS
Self
Refresh
REFSX
REFS
SRRRead
SRR
Read
Integrated Silicon Solution, Inc. 7
Rev. 00B
06/23/09
IS43LR16160D, IS43LR32800D
ELECTRICAL SPECIFICATIONS
Absolute Maximum DC Ratings(3)
Parameter Symbol Min Max Units Notes
VDDsupplyvoltagerelativetoVSS VDD -0.5 2.4 V 1
VDDsupplyvoltagerelativetoVSSQ VDDQ -0.5 2.4 V 1
VoltageonanyballrelativetoVSS Vi n ,Vo u t -0.5 2.4 V 2
StorageTemperature ts t g -55 +150 oC
Notes:
1.VDD,VDDQmustbewithin300mVofeachotheratalltimes.
2.VoltageonanyI/OmaynotexceedvoltageonVDDQ
3.Stressesgreaterthanthoselistedmaycausepermanentdamagetothedevice.Thisisastressratingonly,andfunctional
operation of the device at these or any other conditions above those indicated in the operational sections of this specification
isnotimplied.Exposuretoabsolutemaximumratingconditionsforextendedperiodsmayaffectreliability.
AC/DC Electrical Characteristics and Operating Conditions
VDD=+1.8V±0.1V,VDDQ=+1.8V±0.1V
Parameter/Condition Symbol Min Max Units Notes
Supplyvoltage Vd d 1.7 1.9 V 1
I/Osupplyvoltage Vd d q 1.7 1.9 V 1
Address and Command Inputs
Inputvoltagehigh Vi h 0.8×VDDQ VDDQ+0.3 V 2,3
Inputvoltagelow Vi l –0.3 0.2×VDDQ V 2,3
Clock Inputs (CK, CK)
DCinputvoltage Vi n –0.3 VDDQ+0.3 V 4
DCinputdifferentialvoltage Vi d (d c ) 0.4×VDDQ VDDQ+0.36 V 4,5
ACinputdifferentialvoltage Vi d (a c ) 0.6×VDDQ VDDQ+0.6 V 4,5
ACdifferentialcrossingvoltage Vi x 0.4×VDDQ 0.6×VDDQ V 4,6
Data Inputs
DCinputhighvoltage Vi h (d c ) 0.7×VDDQ VDDQ+0.3 V 2,7,3
DCinputlowvoltage Vi l (d c ) –0.3 0.3×VDDQ V 2,7,3
ACinputhighvoltage Vi h (a c ) 0.8×VDDQ VDDQ+0.3 V 2,7,3
ACinputlowvoltage Vi l (a c ) –0.3 0.2×VDDQ V 2,7,3
Data Outputs
DCoutputhighvoltage:Logic1(Io h =-0.1mA) Vo h 0.9×VDDQ – V
DCoutputlowvoltage:Logic0(Io l =0.1mA) Vo l – 0.1×VDDQ V
Leakage Current
Inputleakagecurrent.Anyinput0V<VIN<VDD Ii -1 1 mA
(Allotherballsnotundertest=0V)
Output leakage current
(DQsaredisabled;0V≤Vo u t ≤ Vd d q ) Io z –5 5 μA
Operating Temperature
Commercial Ta 0 +70 oC
Industrial T
a -40 +85 oC
8 Integrated Silicon Solution, Inc.
Rev. 00B
06/23/09
IS43LR16160D, IS43LR32800D
Notes:
1.Anypositiveglitchmustbelessthan1/3oftheclockcycleandnotmorethan+200mVor2.0V,whicheverisless.Anynega-
tiveglitchmustbelessthan1/3oftheclockcycleandnotexceedeither-150mVor1.6V,whicheverismorepositive.
2.Tomaintainavalidlevel,thetransitioningedgeoftheinputmust:
a.SustainaconstantslewratefromthecurrentAClevelthroughtothetargetAClevel,Vi l (AC),orVi h (AC).
b.ReachatleastthetargetAClevel.
c.AftertheACtargetlevelisreached,continuetomaintainatleastthetargetDClevel,Vi l (DC)orVi h (DC).
3.Vi h overshoot:Vi h (MAX)=VDDQ+0.5Vforapulsewidth=3nsandthepulsewidthcannotbegreaterthan1/3ofthecycle
rate.Vi l undershoot:Vi l (MIN)=-0.5Vforapulsewidth=3nsandthepulsewidthcannotbegreaterthan1/3ofthecycle
rate.
4.CKandCKinputslewratemustbe=1V/ns(2V/nsifmeasureddifferentially).
5.VIDisthemagnitudeofthedifferencebetweentheinputlevelonCKandtheinputlevelonCK.
6.ThevalueofVi x isexpectedtoequalVd d q /2ofthetransmittingdeviceandmusttrackvariationsintheDClevelofthesame.
7.DQandDMinputslewratesmustnotdeviatefromDQSbymorethan10percent.IftheDQ/DM/DQSslewrateislessthan
0.5V/ns,timingmustbederated:50psmustbeaddedtotDSandtDHforeach100mv/nsreductioninslewrate.Ifslewrate-
exceeds4V/ns,functionalityisuncertain.
Integrated Silicon Solution, Inc. 9
Rev. 00B
06/23/09
IS43LR16160D, IS43LR32800D
Parameter Symbol Min Max Units Notes
Inputcapacitance:CK,CK CCK 1.5 3.0 pF
Deltainputcapacitance:CK,CK CDCK – 0.25 pF 2
Inputcapacitance:CommandAddress CI 1.5 3.0 pF
Deltainputcapacitance:Commandandaddress CDI – 0.5 pF 2
Input/outputcapacitance:DQs,DQS,DM CIO 2.0 4.5 pF
Deltainput/outputcapacitance:DQs,DQS,DM CDIO – 0.5 pF 1
CAPACITANCE CHARACTERISTICS
Notes:
1.TheI/OcapacitanceperDQSandDQbyte/groupwillnotdifferbymorethanthismaximumamountforanygivendevice.
2.Theinputcapacitanceperballgroupwillnotdifferbymorethanthismaximumamountforanygivendevice.
10 Integrated Silicon Solution, Inc.
Rev. 00B
06/23/09
IS43LR16160D, IS43LR32800D
IDD Specification Parameters and Test Conditions
Symbol Parameter/ Test Condition 16Mx16 Unit
-5 -6 -75
IDD0 Operatingonebankactive-prechargecurrent:tRC=tRC(MIN);tCK=tCK
(MIN);CKEisHIGH;CSisHIGHbetweenvalidcommands;Addressinputs
areswitchingeverytwoclockcycles;Databusinputsarestable
60 55 50 mA
IDD2P Prechargepower-downstandbycurrent:Allbanksidle;CKE=LOW;CS=
HIGH,tCK=tCK(MIN);Addressandcontrolinputsareswitching;Databus
inputs are stable
300 300 300 mA
IDD2PS Prechargepower-downstandbycurrentwithclockstopped:Allbanksidle;
CKE=LOW;CS=HIGH;CK=LOW,/CK=HIGH;Addressandcontrolinputs
areswitching;Databusinputsarestable
300 300 300 mA
IDD2N Prechargenon-power-downstandbycurrent:Allbanksidle;CKE=HIGH;CS
=HIGH;tCK=tCK(MIN);Addressandcontrolinputsareswitching;Databus
inputs are stable
25 25 25 mA
IDD2NS Prechargenon-power-downstandbycurrent:Clockstopped;Allbanksidle;
CKE=HIGH;CS=HIGH;CK=LOW;/CK=HIGH;Addressandcontrolinputs
areswitchingeverytwoclockcycles;Databusinputsarestable
15 15 15 mA
IDD3P Activepower-downstandbycurrent:Onebankactive;CKE=LOW;CS=HIGH;
tCK=tCK(MIN);Addressandcontrolinputsareswitching;Databusinputsare
stable
5 5 5 mA
IDD3PS Activepower-downstandbycurrentwithclockstopped:Onebankactive;CKE
=LOW;CS=HIGH;CK=LOW;/CK=HIGH;Addressandcontrolinputsare
switching;Databusinputsarestable
5 5 5 mA
IDD3N Activenon-power-downstandby:Onebankactive;CKE=HIGH;CS=HIGH;
tCK=tCK(MIN);Addressandcontrolinputsareswitching;Databusinputs
are stable
25 25 25 mA
IDD3NS Activenon-power-downstandbywithclockstopped:Onebankactive;CKE=
HIGH;CS=HIGH;CK=LOW;/CK=HIGH;Addressandcontrolinputsare
switching;Databusinputsarestable
20 20 20 mA
IDD4R Operatingburstread:Onebankactive;BL=4;tCK=tCK(MIN);Continuous
READbursts;IOUT=0mA;Addressinputsareswitchingeverytwoclock
cycles;50percentdatachangingeachburst
110 100 90 mA
IDD4W Operatingburstwrite:Onebankactive;BL=4;tCK=tCK(MIN);Continuous
WRITEbursts;Addressinputsareswitching;50percentdatachangingeach
burst
120 110 100 mA
IDD5 Autorefresh:Burstrefresh;CKE=HIGH;Addressandcontrol
inputsareswitching;Databusinputsarestable
tRFC=tRFC
(MIN)
100 100 100 mA
IDD5a Autorefresh:Burstrefresh;CKE=HIGH;Addressandcontrol
inputsareswitching;Databusinputsarestable
tRFC=tREFI TBD TBD TBD mA
IDD8 Deeppower-downcurrent:Addressandcontrolballsarestable;Databus
inputs are stable
10 10 10 mA
IDD6a Selfrefresh:CKE=LOW;tCK=tCK(MIN);Addressand
controlinputsarestable;Databusinputsarestable
Fullarray,85o300 300 300 mA
IDD6c Fullarray,45oTBD TBD TBD mA
IDD6a Halfarray,85oTBD TBD TBD mA
IDD6c Halfarray,45oTBD TBD TBD mA
IDD6a 1/4array,85oTBD TBD TBD mA
IDD6c 1/4array,45oTBD TBD TBD mA
Integrated Silicon Solution, Inc. 11
Rev. 00B
06/23/09
IS43LR16160D, IS43LR32800D
IDD Specification Parameters and Test Conditions
Symbol Parameter/ Test Condition 8Mx32 Unit
-5 -6 -75
IDD0 Operatingonebankactive-prechargecurrent:tRC=tRC(MIN);tCK=tCK
(MIN);CKEisHIGH;CSisHIGHbetweenvalidcommands;Addressinputs
areswitchingeverytwoclockcycles;Databusinputsarestable
80 75 70 mA
IDD2P Prechargepower-downstandbycurrent:Allbanksidle;CKE=LOW;CS=
HIGH,tCK=tCK(MIN);Addressandcontrolinputsareswitching;Databus
inputs are stable
300 300 300 mA
IDD2PS Prechargepower-downstandbycurrentwithclockstopped:Allbanksidle;
CKE=LOW;CS=HIGH;CK=LOW,/CK=HIGH;Addressandcontrolinputs
areswitching;Databusinputsarestable
300 300 300 mA
IDD2N Prechargenon-power-downstandbycurrent:Allbanksidle;CKE=HIGH;CS
=HIGH;tCK=tCK(MIN);Addressandcontrolinputsareswitching;Databus
inputs are stable
25 25 25 mA
IDD2NS Prechargenon-power-downstandbycurrent:Clockstopped;Allbanksidle;
CKE=HIGH;CS=HIGH;CK=LOW;/CK=HIGH;Addressandcontrolinputs
areswitchingeverytwoclockcycles;Databusinputsarestable
15 15 15 mA
IDD3P Activepower-downstandbycurrent:Onebankactive;CKE=LOW;CS=HIGH;
tCK=tCK(MIN);Addressandcontrolinputsareswitching;Databusinputsare
stable
5 5 5 mA
IDD3PS Activepower-downstandbycurrentwithclockstopped:Onebankactive;CKE
=LOW;CS=HIGH;CK=LOW;/CK=HIGH;Addressandcontrolinputsare
switching;Databusinputsarestable
5 5 5 mA
IDD3N Activenon-power-downstandby:Onebankactive;CKE=HIGH;CS=HIGH;
tCK=tCK(MIN);Addressandcontrolinputsareswitching;Databusinputs
are stable
25 25 25 mA
IDD3NS Activenon-power-downstandbywithclockstopped:Onebankactive;CKE=
HIGH;CS=HIGH;CK=LOW;/CK=HIGH;Addressandcontrolinputsare
switching;Databusinputsarestable
20 20 20 mA
IDD4R Operatingburstread:Onebankactive;BL=4;tCK=tCK(MIN);Continuous
READbursts;IOUT=0mA;Addressinputsareswitchingeverytwoclock
cycles;50percentdatachangingeachburst
140 120 100 mA
IDD4W Operatingburstwrite:Onebankactive;BL=4;tCK=tCK(MIN);Continuous
WRITEbursts;Addressinputsareswitching;50percentdatachangingeach
burst
160 140 120 mA
IDD5 Autorefresh:Burstrefresh;CKE=HIGH;Addressandcontrol
inputsareswitching;Databusinputsarestable
tRFC=tRFC
(MIN)
100 100 100 mA
IDD5a Autorefresh:Burstrefresh;CKE=HIGH;Addressandcontrol
inputsareswitching;Databusinputsarestable
tRFC=tREFI TBD TBD TBD mA
IDD8 Deeppower-downcurrent:Addressandcontrolballsarestable;Databus
inputs are stable
10 10 10 mA
IDD6a Selfrefresh:CKE=LOW;tCK=tCK(MIN);Addressand
controlinputsarestable;Databusinputsarestable
Fullarray,85o300 300 300 mA
IDD6c Fullarray,45oTBD TBD TBD mA
IDD6a Halfarray,85oTBD TBD TBD mA
IDD6c Halfarray,45oTBD TBD TBD mA
IDD6a 1/4array,85oTBD TBD TBD mA
IDD6c 1/4array,45oTBD TBD TBD mA
12 Integrated Silicon Solution, Inc.
Rev. 00B
06/23/09
IS43LR16160D, IS43LR32800D
Parameter Symbol -5 -6 -75 Unit Note
Min Max Min Max Min Max
DQOutputAccessTime(fromCK,/
CK)CL=3
tAC3 2 525.5 2 6 ns
DQOutputAccessTime(fromCK,/
CK)CL=2
tAC2 2 6.5 26.5 26.5 ns
DQSOutputAccessTime(from
CK,/CK)CL=3
tDQSCK3 25252 6 ns
DQSOutputAccessTime(from
CK,/CK)CL=2
tDQSCK2 26.5 26.5 26.5 ns
ClockHigh-levelWidth tCH 0.45 0.55 0.45 0.55 0.45 0.55 tCK
ClockLow-levelWidth tCL 0.45 0.55 0.45 0.55 0.45 0.55 tCK
ClockHalfPeriod tHP
Min
(tCL,tCH)
–
Min
(tCL,tCH)
– Min
(tCL,tCH)
–ns 1
SystemClockCycleTimeCL=3 tCK3 5 – 6– 7.5 – ns
SystemClockCycleTimeCL=2 tCK2 12 –12 –12 –ns
DQandDMInputSetupTime
(slow/fastslewrate)
tDS 0.58/
0.48
– 0.7/0.6 – 0.9/0.8 – ns 2,3
DQandDMInputHoldTime(slow/
fastslewrate)
tDH 0.58/
0.48
– 0.7/0.6 – 0.9/0.8 – ns 2,3
DQandDMInputPulseWidth tDIPW 1.8 – 2.1 – 1.6/1.8 – ns
Address and Control Input Setup
Time(slow/fastslewrate)
tIS 1.1/ 0.9 –1.3/ 1.1 – 1.5/1.3 – ns 4
AddressandControlInputHold
Time(slow/fastslewrate)
tIH 1.1/ 0.9 –1.3/ 1.1 – 1.5/1.3 – ns 4
AddressandControlInputPulse
Width
tIPW 2.3 –2.3 –2.6 –ns
DQ&DQSLow-impedancetime
fromCK,/CK
tLZ 1.0 –1.0 –1.0 –ns 5
DQ&DQSHigh-impedancetime
fromCK,/CK;CL=3
tHZ3 – 5.0 – 5.0 – 6.0 ns 5,6
DQ&DQSHigh-impedancetime
fromCK,/CK;CL=2
tHZ2 – 6.5 – 6.5 – 6.5 ns 5,6
DQS-DQSkew tDQSQ – 0.4 – 0.5 – 0.6 ns
DQ/DQSoutputholdtimefrom
DQS
tQH
tHP-
tQHS
– tHP-
tQHS
–
tHP-
tQHS
–ns
DataHoldSkewFactor tQHS
–
0.5
–
0.65 – 0.75 ns
WriteCommandto1stDQS
LatchingTransition
tDQSS 0.75 1.25 0.75 1.25 0.75 1.25 tCK
DQSInputHigh-LevelWidth tDQSH 0.4 0.6 0.4 0.6 0.4 0.6 tCK
DQSInputLow-LevelWidth tDQSL 0.4 0.6 0.4 0.6 0.4 0.6 tCK
DQSFallingEdgeofCKSetup
Time
tDSS 0.2
–
0.2
–
0.2 – tCK
DQSFallingEdgeHoldTimefrom
CK
tDSH 0.2
–
0.2
–
0.2 – tCK
AC CHARACTERISTICS (ACoperatingconditionsunlessotherwisenoted)(Sheet1of2)
Integrated Silicon Solution, Inc. 13
Rev. 00B
06/23/09
IS43LR16160D, IS43LR32800D
Parameter Symbol -5 -6 -75 Unit Note
Min Max Min Max Min Max
MODEREGISTERSETCommand
Period
tMRD 2
–
2
–
2– tCK
WritePreambleSetupTime tWPRES 0–0–0–ns
WritePostamble tWPST 0.4 – 0.4 – 0.4 – tCK
WritePreamble tWPRE 0.25 – 0.25 – 0.25 – tCK 6
ReadPreambleCL=3 tRPRE 0.9 1.1 0.9 1.1 0.9 1.1 tCK 6
ReadPreambleCL=2 tRPRE 0.5 1.1 0.5 1.1 0.5 1.1 tCK
DQSreadpostamble tRPST 0.4 0.6 0.4 0.6 0.4 0.6 tCK
ACTIVEtoPRECHARGE
CommandPeriod
tRAS 40 70,000 42 70,000 45
70,000
ns
ACTIVEtoACTIVECommand
Period
tRC 55 – 60 – 75 – ns
AUTOREFRESHtoACTIVE/AUTO
REFRESHCommandPeriod
tRFC 80 – 80 – 80 – ns 11
ACTIVEtoREADorWRITEDelay tRCD 15 – 18 – 22.5 – ns
PRECHARGECommandPeriod tRP 15 – 18 – 22.5 – ns
ACTIVEBankAtoACTIVEBankB
Delay
tRRD 10 –12 – 15 – ns
WRITERecoveryTime tWR 15 – 15 – 15 – ns
AutoPrechargeWriteRecovery+
PrechargeTime
tDAL (tWR/tCK)+(tRP/tCK) tCK 9
InternalWritetoReadCommand
Delay
tWTR 2–1–1– tCK
SelfRefreshExittonextvalid
CommandDelay
tXSR 120 –120 –120 –ns 7
ExitPowerDowntonextvalid
CommandDelay
tXP 2–1–1– tCK 8
CKEmin.PulseWidth(Highand
Low)
tCKE 1–1–1– tCK
AveragePeriodicRefreshInterval tREFI 7.81 7.81 7.81 – us
RefreshPeriod8Ktimes(x16)
4Ktimes(x32)
tREF – 64 – 64 – 64 ms
tREF – 32 –32 –32 ms 12
AC CHARACTERISTICS (ACoperatingconditionsunlessotherwisenoted)(Sheet2of2)
14 Integrated Silicon Solution, Inc.
Rev. 00B
06/23/09
IS43LR16160D, IS43LR32800D
Notes:
1.tHP(min)isthelesserofmin(tCL,tCH)actuallyappliedtothedeviceCKandCK inputs, collectively
2.DQandDMinputslewratesmustnotdeviatefromDQSbymorethan10percent.
3.IftheDQ/DM/DQSslewrateislessthan0.5V/ns,timingmustbederated:50psmstbeaddedtotDSandtDHforeach
100mV/nsreductioninslewrate.Ifslewrateexceeds4V/ns,functionalityisuncertain.
4.Fastcommand/addressinputslewrate1V/nS.Slowcommand/addressinputslewrate0.5V/ns.
5.tHZandtLZtransitionsoccurinthesameaccesstimewindowsasdatavalidtransitions.
6.tHZ(MAX)willprevailovertDQSCK(MAX)+tRPST(MAX)condition.
7.Clockmustbetoggledaminimumoftwotimesduringthisperiod.
8.Clockmustbetoggledaminimumofonetimeduringthisperiod.
9.tDAL=(tWR/tCK)+(tRP/tCK):foreachterm,ifnotalreadyaninteger,roundtothenexthigherinteger.
10.Outputsmeasuredwithequivalentload:
11.Amaximumof8RefreshCommandscanbepostedtotheDRAM.ThemaximumabsoluteinternalbetweenanyRefresh
Commandandthenextcommandis8xtr e f i .
12.The8Mx32optionrequiresall4K(4,096)rowsberefreshedwithin32ms,orequivalently,8Krefreshcyclesper64ms
(8K/64ms)
I/O
20 pF
I/O
10 pF
Full-drive strength
Ha lf-drive strength
I/O
5 pF
Quarter-drive strength
50
50
50
I/O
2.5pF
50
One-eighth-drive strength
Integrated Silicon Solution, Inc. 15
Rev. 00B
06/23/09
IS43LR16160D, IS43LR32800D
OUTPUT SLEW RATE CHARACTERISTICS
PARAMETER MIN MAX UNIT NOTES
Pull-upandPull-DownSlewRateforFullStrengthDriver 0.7 2.5 V/ns 1,2
Pull-upandPull-DownSlewRateforHalfStrengthDriver 0.3 1.0 V/ns 1,2
OutputSlewrateMatchingratio(Pull-uptoPull-down) 0.7 1.4 — 3
NOTES:
1.Measuredwithatestloadof20pFconnectedtoVSSQ.
2.OutputslewrateforrisingedgeismeasuredbetweenVILD(DC)toVIHD(AC)andforfallingedgebetweenVIHD(DC)to
VILD(AC).
3.Theratioofpull-upslewratetopull-downslewrateisspeciedforthesametemperatureandvoltage,overtheentiretem-
peratureandvoltagerange.Foragivenoutput,itrepresentsthemaximumdifferencebetweenpull-upandpull-downdrivers
due to process variation.
AC OVERSHOOT/UNDERSHOOT SPECIFICATION
PARAMETER SPECIFICATION
Maximumpeakamplitudeallowedforovershoot 0.5V
Maximumpeakamplitudeallowedforundershoot 0.5V
TheareabetweenovershootsignalandVDDmustbelessthanorequalto 3V-ns
TheareabetweenundershootsignalandGNDmustbelessthanorequalto 3V-ns
NOTES:
1.Thisspecicationisintendedfordeviceswithnoclampprotectionandisguaranteedbydesign.
-0.5
0
0.5
1.0
1.5
2.0
Max. Amplitude = 0.5 V Max. Area = 3 V-ns
VDD
VSS
Undershoot Area
Overshoot Area
2.5
Voltage (V)
Time (ns)
AC Overshoot and Undershoot Definition
16 Integrated Silicon Solution, Inc.
Rev. 00B
06/23/09
IS43LR16160D, IS43LR32800D
DRIVER CHARACTERISTICS
MobileDDRSDRAMoutputdrivercharacteristicsaredenedforfullandhalfdrivestrengthoperationasselectedin
theExtendedModeRegister.Thetablebelowshowsthedatainatabularformatsuitableforinputintosimulationtools.
Thefollowingguresshowthedriverstrengthcharacteristicsgraphically.
I-V CURVES FOR FULL DRIVE STRENGTH AND HALF DRIVE STRENGTH(1,2)
Voltage
[V]
FULL DRIVE STRENGTH HALF DRIVE STRENGTH
Pull-Down Current
[mA]
Pull-Up Current
[mA]
Pull-Down Current
[mA]
Pull-Up Current
[mA]
Min Max. Min. Max. Min. Max Min. Max.
0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00
0.10 2.80 18.53 -2.80 -18.53 1.27 8.42 -1.27 -8.42
0.20 5.60 26.80 -5.60 -26.80 2.55 12.30 -2.55 -12.30
0.30 8.40 32.80 -8.40 -32.80 3.82 14.95 -3.82 -14.95
0.40 11.20 37.05 -11.20 -37.05 5.09 16.84 -5.09 -16.84
0.50 14.00 40.00 -14.00 -40.00 6.36 18.20 -6.36 -18.20
0.60 16.80 42.50 -16.80 -42.50 7.64 19.30 -7.64 -19.30
0.70 19.60 44.57 -19.60 -44.57 8.91 20.30 -8.91 -20.30
0.80 22.40 46.50 -22.40 -46.50 10.16 21.20 -10.16 -21.20
0.85 23.80 47.48 -23.80 -47.48 10.80 21.60 -10.80 -21.60
0.9 23.80 48.50 -23.80 -48.50 10.80 22.00 -10.80 -22.00
0.95 23.80 49.40 -23.80 -49.40 10.80 22.45 -10.80 -22.45
1.00 23.80 50.05 -23.80 -50.05 10.80 22.73 -10.80 -22.73
1.10 23.80 51.35 -23.80 -51.35 10.80 23.21 -10.80 -23.21
1.20 23.80 52.65 -23.80 -52.65 10.80 23.67 -10.80 -23.67
1.30 23.80 53.95 -23.80 -53.95 10.80 24.14 -10.80 -24.14
1.40 23.80 55.25 -23.80 -55.25 10.80 24.61 -10.80 -24.61
1.50 23.80 56.55 -23.80 -56.55 10.80 25.08 -10.80 -25.08
1.60 23.80 57.85 -23.80 -57.85 10.80 25.54 -10.80 -25.54
1.70 23.80 59.15 -23.80 -59.15 10.80 26.01 -10.80 -26.01
1.80 —60.45 —-60.45 —26.48 —-26.48
1.90 — 61.75 —-61.75 —26.95 —-26.95
NOTES:
1.Basedonnominalimpedanceof25Ohms(FullDrive)and55Ohms(HalfDrive)atVDDQ/2
2.Thefullvariationindrivercurrentfromminimumtomaximumduetoprocess,temperatureandvoltagewillliewithintheouter
boundinglinesoftheI-Vcurve.
Integrated Silicon Solution, Inc. 17
Rev. 00B
06/23/09
IS43LR16160D, IS43LR32800D
I-V Curves For Full Drive Strength
I-V Curves For Half Drive Strength
Full Drive Strength I-V Curves
-75.0
-50.0
-25.0
0.0
25.0
50.0
75.0
0.0 0.5 1.0 1.5
PD Max
PD Min
PU Min
PU Max
Half Drive Strength I-V Curves
-30.0
-20.0
-10.0
0.0
10.0
20.0
30.0
0.0 0.5 1.0 1.5
PD Max
PD Min
PU Min
PU Max
18 Integrated Silicon Solution, Inc.
Rev. 00B
06/23/09
IS43LR16160D, IS43LR32800D
FUNCTIONAL DESCRIPTION
TheMobileDDRSDRAMisahighspeedCMOS,dynamicrandom-accessmemoryinternallyconguredasaquad-
bankDRAM.The256Mbdevicescontains:268,435,456bits.
TheMobileDDRSDRAMusesdoubledataratearchitecturetoachievehighspeedoperation.Thedoubledatarate
architecture is essentially a 2n prefetch architecture with an interface designed to transfer two data words per clock
cycleattheI/Opins.AsinglereadorwriteaccessfortheMobileDDRSDRAMeffectivelyconsistsofasingle2n-bit
wide,oneclockcycledatatransferattheinternalDRAMcoreandtwocorrespondingn-bitwide,one-half-clock-cycle
datatransfersattheI/Opins.
ReadandwriteaccessestotheMobileDDRSDRAMareburstoriented;accessesstartataselectedlocationand
continueforaprogrammednumberoflocationsinaprogrammedsequence.Accessesbeginwiththeregistrationof
anACTIVEcommand,whichisthenfollowedbyaREADorWRITEcommand.Theaddressbitsregisteredcoincident
withtheACTIVEcommandareusedtoselectthebankandtherowtobeaccessed.Theaddressbitsregistered
coincidentwiththeREADorWRITEcommandareusedtoselectthebankandthestartingcolumnlocationforthe
burst access.
Priortonormaloperation,theMobileDDRSDRAMmustbeinitialized.Thefollowingsectionprovidesdetailed
information covering device initialization, register definition, command description and device operation.
INITIALIZATION
MobileDDRSDRAMsmustbepoweredupandinitializedinapredenedmanner.Operationsproceduresotherthan
those specified may result in undefined operation. If there is any interruption to the device power, the initialization
routineshouldbefollowed.Thestepstobefollowedfordeviceinitializationarelistedbelow.TheInitializationFlow
diagramandtheInitializationFlowsequenceareshowninthefollowinggures.
TheModeRegisterandExtendedModeRegisterdonothavedefaultvalues.Iftheyarenotprogrammedduringthe
initializationsequence,itmayleadtounspeciedoperation.Theclockstopfeatureisnotavailableuntilthedevicehas
been properly initialized from Step 1 through 11.
Integrated Silicon Solution, Inc. 19
Rev. 00B
06/23/09
IS43LR16160D, IS43LR32800D
•Step1:Providepower,thedevicecorepower(VDD)andthedeviceI/Opower(VDDQ)mustbebrought
upsimultaneouslytopreventdevicelatch-up.Althoughnotrequired,itisrecommendedthatVDDand
VDDQarefromthesamepowersource.AlsoassertandholdClockEnable(CKE)toaLVCMOSlogic
high level
•Step2:OncethesystemhasestablishedconsistentdevicepowerandCKEisdrivenhigh,itissafeto
apply stable clock
•Step3:Theremustbeatleast200μsofvalidclocksbeforeanycommandmaybegiventotheDRAM.
DuringthistimeNOPorDESELECTcommandsmustbeissuedonthecommandbus.
•Step4:IssueaPRECHARGEALLcommand.
•Step5:ProvideNOPsorDESELECTcommandsforatleasttRPtime.
•Step6:IssueanAUTOREFRESHcommandfollowedbyNOPsorDESELECTcommandforatleast
tRFCtime.IssuethesecondAUTOREFRESHcommandfollowedbyNOPsorDESELECTcommandfor
atleasttRFCtime.Noteaspartoftheinitializationsequencetheremustbetwoautorefreshcommands
issued.ThetypicalowistoissuethematStep6,buttheymayalsobeissuedbetweensteps10and11.
•Step7:UsingtheMRScommand,loadthebasemoderegister.Setthedesiredoperatingmodes.
•Step8:ProvideNOPsorDESELECTcommandsforatleasttMRDtime.
•Step9:UsingtheMRScommand,programtheextendedmoderegisterforthedesiredoperatingmodes.
Notetheorderofthebaseandextendedmoderegisterprogrammingisnotimportant.
•Step10:ProvideNOPorDESELCTcommandsforatleasttMRDtime.
•Step11:TheDRAMhasbeenproperlyinitializedandisreadyforanyvalidcommand.
Initialization Flow Diagram
1VDD and VDDQ Ramp: CKE must be held high
2 Apply stable clocks
3Wait at least 200 µs with NOP or DESELECT on command
bus
4PRECHARGE ALL
5 Assert NOP or DESELCT for tRP time
6Issue two AUTOREFRESH commands each followed by
NOP or DESELECT commands for tRFC time
7Configure Mode Register
8 Assert NOP or DESELECT for tMRD time
9Configure Extended Mode Register
10 Assert NOP or DESELECT for tMRD time
11 LPDDR SDRAM is ready for any valid command
20 Integrated Silicon Solution, Inc.
Rev. 00B
06/23/09
IS43LR16160D, IS43LR32800D
Initialization Waveform Sequence
Integrated Silicon Solution, Inc. 21
Rev. 00B
06/23/09
IS43LR16160D, IS43LR32800D
MODE REGISTER (MR) DEFINITION
TheModeRegisterisusedtodenethespecicmodeofoperationoftheMobileDDRSDRAM.Thisdenition
includesthedenitionofaburstlength,abursttype,andaCASlatency.TheModeRegisterisprogrammedvia
theMODEREGISTERSETcommand(withBA0=0andBA1=0)andwillretainthestoredinformationuntilitis
reprogrammed,thedevicegoesintoDeepPower-Downmode,orthedevicelosespower.ModeRegisterbitsA0-A2
specifytheburstlength,A3thetypeofburst(sequentialorinterleave),A4-A6theCASlatency.Alogic0shouldbe
programmed to all the undefined addresses bits to ensure future compatibility.
TheModeRegistermustbeloadedwhenallbanksareidleandnoburstsareinprogress,andthecontrollermustwait
thespeciedtimetMRDbeforeinitiatinganysubsequentoperation.Violatingeitheroftheserequirementswillresultin
unspecified operation.
Reservedstatesshouldnotbeused,asunknownoperationorincompatibilitywithfutureversionsmayresult.
Notes:
1. MSBdependsonMobileDDRSDRAMdensity.
2. A logic 0 should be programmed to all unused / undefined address bits to ensure future compatibility.
MODE REGISTER DEFINITION
BA1 BA0 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
A2 A1 A0 Burst Length
0 0 0 Reserved
0 0 1 2
0 1 0 4
0 1 1 8
1 0 0 Reserved
1 0 1 Reserved
1 1 0 Reserved
1 1 1 Reserved
AddressBus(Ax)
ModeReg.(Ex)
A3 Burst Type
0 Sequential
1 Interleave
A6 A5 A4 CAS Latency
0 0 0 Reserved
0 0 1 Reserved
0 1 0 2 (optional)
0 1 1 3
1 0 0 Reserved
1 0 1 Reserved
1 1 0 Reserved
1 1 1 Reserved
Reserved(2)
BA1 BA0 Mode Register Denition
0 0 Program Mode Register
0 1 Reserved
1 0 Program Extended mode Register
1 1 Reserved
22 Integrated Silicon Solution, Inc.
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IS43LR16160D, IS43LR32800D
Burst Length
ReadandwriteaccessestotheMobileDDRSDRAMareburstoriented,withtheburstlengthbeingsetandtheburst
orderasinBurstDenition.Theburstlengthdeterminesthemaximumnumberofcolumnlocationsthatcanbeac-
cessedforagivenREADorWRITEcommand.Burstlengthsof2,4,or8locationsareavailableforboththesequen-
tial and the interleaved burst types.
Burst Definition
Burst
Length
Starting Column
Address
ORDER OF ACCESSES WITHIN A BURST
(HEXADECIMAL NOTATION)
A3 A2 A1 A0 Sequential Interleaved
20 0-1 0-1
1 1-0 1-0
4
0 0 0 - 1 - 2 - 3 0 - 1 - 2 - 3
0 1 1 - 2 - 3 - 0 1 - 0 - 3 - 2
1 0 2 - 3 - 0 - 1 2 - 3 - 0 - 1
1 1 3 - 0 - 1 - 2 3 - 2 - 1 - 0
8
0 0 0 0-1-2-3-4-5-6-7 0-1-2-3-4-5-6-7
0 0 1 1-2-3-4-5-6-7-0 1-0-3-2-5-4-7-6
0 1 0 2-3-4-5-6-7-0-1 2-3-0-1-6-7-4-5
0 1 1 3-4-5-6-7-0-1-2 3-2-1-0-7-6-5-4
1 0 0 4-5-6-7-0-1-2-3 4-5-6-7-0-1-2-3
1 0 1 5-6-7-0-1-2-3-4 5-4-7-6-1-0-3-2
1 1 0 6-7-0-1-2-3-4-5 6-7-4-5-2-3-0-1
1 1 1 7-0-1-2-3-4-5-6 7-6-5-4-3-2-1-0
Notes:
1. Foraburstlengthoftwo,A1-Anselectsthetwodataelementblock;A0selectstherstaccesswithintheblock.
2. Foraburstlengthoffour,A2-Anselectsthefourdataelementblock;A0-A1selectstherstaccesswithintheblock.
3. Foraburstlengthofeight,A3-Anselectstheeightdataelementblock;A0-A2selectstherstaccesswithintheblock.
4. Wheneveraboundaryoftheblockisreachedwithinagivensequence,thefollowingaccesswrapswithintheblock.
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WhenaREADorWRITEcommandisissued,ablockofcolumnsequaltotheburstlengthiseffectivelyselected.All
accesses for that burst take place within the block, meaning that the burst will wrap within the block if a boundary is
reached.TheblockisuniquelyselectedbyA1-Anwhentheburstlengthissettotwo,byA2-Anwhentheburstlength
issetto4,andbyA3-Anwhentheburstlengthissetto8(whereAnisthemostsignicantcolumnaddressbitfora
givenconguration).Theremaining(leastsignicant)addressbit(s)is(are)usedtoselectthestartinglocationwithin
theblock.Theprogrammedburstlengthappliestobothreadandwritebursts.
Burst Type
Accesseswithinagivenburstmaybeprogrammedtobeeithersequentialorinterleaved;thisisreferredtoasthe
bursttypeandisselectedviabitA3.Theorderingofaccesseswithinaburstisdeterminedbytheburstlength,the
burst type and the starting column address.
Read Latency
TheREADlatency,orCASlatency,isthedelaybetweentheregistrationofaREADcommandandtheavailabilityof
therstpieceofoutputdata.IfaREADcommandisregisteredataclockedgenandthelatencyis3clocks,therst
dataelementwillbevalidatn+2tCK+tAC.IfaREADcommandisregisteredataclockedgenandthelatencyis2
clocks,therstdataelementwillbevalidatn+tCK+tAC.
EXTENDED MODE REGISTER (EMR) DEFINITION
TheExtendedModeRegistercontrolsfunctionsbeyondthosecontrolledbytheModeRegister;theseadditional
functionsincludeoutputdrivestrengthselection,TemperatureCompensatedSelfRefresh(TCSR)andPartialArray
SelfRefresh(PASR),asshowninExtendedModeRegisterDenition.BothTCSRandPASRareeffectiveisinSelf
Refreshmodeonly.TheExtendedModeRegisterisprogrammedviatheMODEREGISTERSETcommand(with
BA1=1andBA0=0)andwillretainthestoredinformationuntilitisreprogrammed,thedeviceisputinDeepPower-
Downmode,orthedevicelosespower.TheExtendedModeRegistermustbeloadedwhenallbanksareidleand
noburstsareinprogress,andthecontrollermustwaitthespeciedtimetMRDbeforeinitiatinganysubsequent
operation.Violatingeitheroftheserequirementswillresultinunspeciedoperation.AddressbitsA0-A2specifyPASR,
A3-A4theTCSR,A5-A6theDriveStrength.Alogic0shouldbeprogrammedtoalltheundenedaddressesbitsto
ensurefuturecompatibility.Reservedstatesshouldnotbeused,asunknownoperationorincompatibilitywithfuture
versions may result.
Partial Array Self Refresh (PASR)
WithPASR,theselfrefreshmayberestrictedtoavariableportionofthetotalarray.Thewholearray(default),1/2
array,1/4array,1/8array,or1/16arraycouldbeselected.Dataoutsidethedenedareawillbelost.AddressbitsA0
toA2areusedtosetPASR.
Temperature Compensated Self Refresh (TCSR)
ThisfunctionisusedintheMobileDDRSDRAMtosetrefreshratesbasedoncasetemperature.Thedevicehas
InternalTemperatureCompensatedSelfRefreshfeature,whichautomaticallyadjuststherefreshratebasedonthe
devicetemperaturewithoutanyregisterupdateneeded.Itignores(don’tcare)theinputstoaddressbitsA3andA4
duringEMRSprogramming.
Output Driver Strength (DS)
Thedrivestrengthcanbesettofull(default),1/2,1/4,or1/8strengthviaaddressbitsA5andA6.Thepartialdrive
strength options are intended for lighter loads or point-to-point environments.
24 Integrated Silicon Solution, Inc.
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IS43LR16160D, IS43LR32800D
BA1 BA0 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
A2 A1 A0 PASR
0 0 0 All banks
0 0 1 Half array (BA1 = 0)
0 1 0 Quarter array (BA1 = BA0 = 0)
0 1 1 Reserved
1 0 0 Reserved
1 0 1 1/8 array
(BA1 = BA0 = Row Addr MSB = 0)
1 1 0 1/16 array
(BA1 = BA0 = Row Addr 2 MSB = 0)
1 1 1 Reserved
AddressBus(Ax)
Ext.ModeReg.(Ex)
Extended Mode Register Definition
Internal TCSR
On-chiptemperaturesensorisusedinplaceof
TSCR.Settingthesebitswillhavenoeffect.
A6 A5 Drive Strength
0 0 Full Drive
0 1 Half Drive
1 0 Quarter Strength Driver
1 1 1/8 Strength Driver
NOTES:
1.MSBdependsonMobileDDRSDRAMdensity.
2. A logic 0 should be programmed to all unused / undefined address bits to ensure future compatibility.
Reserved(2)
BA1 BA0 Mode Register Denition
0 0 Program Mode Register
0 1 Reserved
1 0 Program Extended mode Register
1 1 Reserved
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COMMANDS TRUTH TABLES
Allcommands(addressandcontrolsignals)areregisteredonthepositiveedgeofclock(crossingofCKgoinghigh
andCKgoinglow).TruthTableshowsbasictimingparametersforallcommands.
TruthTablesforCommandsprovideaquickreferenceofavailablecommands.Table"CurrentState"providesthe
currentstate/nextstateinformation.Thisisfollowedbyadetaileddescriptionofeachcommand.
NAME (FUNCTION) CS RAS CAS WE BA A10/AP Address Notes
DESELECT(NOP) H X X X X X X 2
NOOPERATION(NOP) L H H H X X X 2
ACTIVE(selectbankandactivaterow) L L H H Valid Row Row
READ(selectbankandcolumnandstartread
burst)
L H L H Valid L Col
READwithAP(readburstwithAutoPrecharge) L H L H Valid H Col 3
WRITE(selectbankandcolumnandstartwrite
burst)
L H L L Valid L Col
WRITEwithAP(writeburstwithAuto
Precharge)
L H L L Valid H Col 3
BURSTTERMINATEorenterDEEPPOWER
DOWN
L H H L X X X 4,5
PRECHARGE(deactivaterowinselected
bank)
L L H L Valid L X 6
PRECHARGEALL(deactivaterowsinall
banks)
L L H L X H X 6
AUTOREFRESHorenterSELFREFRESH L L L H X X X 7,8,9
MODEREGISTERSET L L L L Valid Op-code 10
Notes:
1. Allstatesandsequencesnotshownareillegalorreserved.
2. DESELECTandNOParefunctionallyinterchangeable.
3. Autoprechargeisnon-persistent.A10HighenablesAutoPrecharge,whileA10LowdisablesAutoprecharge.
4. BurstTerminateappliestoonlyReadburstswithAutoPrechargedisabled.Thiscommandisundenedandshouldnotbe
usedforReadwithAutoPrechargeenabled,andforWritebursts.
5. ThiscommandisBURSTTERMINATEifCKEisHighandDEEPPOWERDOWNentryifCKEisLow.
6. IfA10isLow,bankaddressdetermineswhichbankistobeprecharged.IfA10isHigh,allbanksareprechargedandBA0-
BA1aredon’tcare.
7. ThiscommandisAUTOREFRESHifCKEisHigh,andSELFREFRESHifCKEislow.
8. AlladdressinputsandI/Oare‘don'tcare’exceptforCKE.Internalrefreshcounterscontrolbankandrowaddressing.
9. AllbanksmustbeprechargedbeforeissuinganAUTO-REFRESHorSELFREFRESHcommand.
10.BA0andBA1valueselectbetweenMRSandEMRS.
11.CKEisHIGHforallcommandsshownexceptSELFREFRESHandDEEPPOWER-DOWN.
TRUTH TABLE - DM Operations
FUNCTION DM DQ NOTES
WriteEnable L Valid 1
Write Inhibit H X 1
Note:Usedtomaskwritedata,providedcoincidentwiththecorrespondingdata.
TRUTH TABLES - COMMANDS
26 Integrated Silicon Solution, Inc.
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IS43LR16160D, IS43LR32800D
TRUTH TABLE - CKE
CKE n-1 CKE n Current State COMMAND n ACTION n NOTES
L L PowerDown X MaintainPowerDown
L L SelfRefresh X MaintainSelfRefresh
L L DeepPowerDown X MaintainDeepPowerDown
L H PowerDown NOPorDESELECT ExitPowerDown 5,6,9
L H SelfRefresh NOPorDESELECT ExitSelfRefresh 5,7,10
L H DeepPowerDown NOPorDESELECT ExitDeepPowerDown 5,8
H L AllBanksIdle NOPorDESELECT PrechargePowerDownEntry 5
H L Bank(s)Active NOPorDESELECT ActivePowerDownEntry 5
H L AllBanksIdle AUTOREFRESH SelfRefreshentry
H L AllBanksIdle BURSTTERMINATE EnterDeepPowerDown
H H SeetheotherTruthTables
Notes:
1. CKEnisthelogicstateofCKEatclockedgen;CKEn-1wasthestateofCKEatthepreviousclockedge.
2. CurrentstateisthestateofMobileDDRimmediatelypriortoclockedgen.
3. COMMANDnisthecommandregisteredatclockedgen,andACTIONnistheresultofCOMMANDn.
4. Allstatesandsequencesnotshownareillegalorreserved.
5. DESELECTandNOParefunctionallyinterchangeable.
6. PowerDownexittime(tXP)shouldelapsebeforeacommandotherthanNOPorDESELECTisissued.
7. SELFREFRESHexittime(tXSR)shouldelapsebeforeacommandotherthanNOPorDESELECTisissued.
8. TheDeepPower-DownexitproceduremustbefollowedasdiscussedintheDeepPower-DownsectionoftheFunctional
Description.
9. TheclockmusttoggleatleastonceduringthetXPperiod.
10.TheclockmusttoggleatleastonceduringthetXSRtime.
Basic Timing Parameters for Commands
NOTE: Input = A0 - An, BA0, BA1, CKE, CS, RAS, CAS, WE;
An = Address bus MSB
= Don't Care
tCL
tCH
tIS tIH
tCK
CK
CK
Input ValidValidValid
Integrated Silicon Solution, Inc. 27
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CURRENT
STATE
CS RAS CAS WE COMMAND / ACTION NOTES
Any H X X X DESELECT(NOP/continuepreviousoperation)
L H H H NoOperation(NOP/continuepreviousoperation)
Idle
L L H H ACTIVE(selectandactivaterow)
L L L H AUTOREFRESH 10
L L L L MODEREGISTERSET 10
RowActive
L H L H READ(selectcolumn&startreadburst)
L H L L WRITE(selectcolumn&startwriteburst)
L L H L PRECHARGE(deactivaterowinbankorbanks) 4
Read
(AutoPrecharge
Disabled)
L H L H READ(selectcolumn&startnewreadburst) 5,6
L H L L WRITE(selectcolumn&startwriteburst) 5,6,13
L L H L PRECHARGE(truncatereadburst,startprecharge)
L H H L BURSTTERMINATE 11
Write
(AutoPrecharge
Disabled)
L H L H READ(selectcolumn&startreadburst) 5,6,12
L H L L WRITE(selectcolumn&startnewwriteburst) 5,6
L L H L PRECHARGE(truncatewriteburst,startprecharge) 12
TRUTH TABLE - CURRENT STATE BANK n - COMMAND TO BANK n
Notes:
1. ThetableapplieswhenbothCKEn-1andCKEnareHIGH,andaftertXSRortXPhasbeenmetifthepreviousstatewasSelf
RefreshorPowerDown.
2. DESELECTandNOParefunctionallyinterchangeable.
3. Allstatesandsequencesnotshownareillegalorreserved.
4. Thiscommandmayormaynotbebankspecic.Ifallbanksarebeingprecharged,theymustbeinavalidstateforprecharg-
ing.
5. AcommandotherthanNOPshouldnotbeissuedtothesamebankwhileaREADorWRITEburstwithAutoPrechargeis
enabled.
6. ThenewReadorWritecommandcouldbeAutoPrechargeenabledorAutoPrechargedisabled.
7. CurrentStateDenitions:
a. Idle:Thebankhasbeenprecharged,andtRPhasbeenmet.
b. RowActive:Arowinthebankhasbeenactivated,andtRCDhasbeenmet.Nodatabursts/accessesandnoregister
accesses are in progress.
c. Read:AREADbursthasbeeninitiated,withAutoPrechargedisabled,andhasnotyetterminatedorbeenterminated.
d. Write:aWRITEbursthasbeeninitiated,withAutoPrechargedisabled,andhasnotyetterminatedorbeenterminated.
8. Thefollowingstatesmustnotbeinterruptedbyacommandissuedtothesamebank.DESELECTorNOPcommandsor
allowable commands to the other bank should be issued on any clock edge occurring during these states. Allowable com-
mandstotheotherbankaredeterminedbyitscurrentstateandTable8,andaccordingtoTable9.
a. Precharging:startswiththeregistrationofaPRECHARGEcommandandendswhentRPismet.OncetRPismet,the
bank will be in the idle state.
b. RowActivating:startswithregistrationofanACTIVEcommandandendswhentRCDismet.OncetRCDismet,thebank
willbeinthe‘rowactive’state.
c. ReadwithAPEnabled:startswiththeregistrationoftheREADcommandwithAutoPrechargeenabledandendswhen
tRPhasbeenmet.OncetRPhasbeenmet,thebankwillbeintheidlestate.
d. WritewithAPEnabled:startswithregistrationofaWRITEcommandwithAutoPrechargeenabledandendswhentRP
hasbeenmet.OncetRPismet,thebankwillbeintheidlestate.
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9. Thefollowingstatesmustnotbeinterruptedbyanyexecutablecommand;DESELECTorNOPcommandsmustbeappliedto
each positive clock edge during these states.
a. Refreshing:startswithregistrationofanAUTOREFRESHcommandandendswhentRFCismet.OncetRFCismet,the
devicewillbeinan‘allbanksidle’state.
b. AccessingModeRegister:startswithregistrationofaMODEREGISTERSETcommandandendswhentMRDhasbeen
met.OncetMRDismet,thedevicewillbeinan‘allbanksidle’state.
c. PrechargingAll:startswiththeregistrationofaPRECHARGEALLcommandandendswhentRPismet.OncetRPismet,
the bank will be in the idle state.
10.Notbank-specic;requiresthatallbanksareidleandnoburstsareinprogress.
11.Notbank-specic.BURSTTERMINATEaffectsthemostrecentreadburst,regardlessofbank.
12.RequiresappropriateDMmasking.
13.AWRITEcommandmaybeappliedafterthecompletionoftheREADburst;otherwise,aBURSTTERMINATEmustbeused
toendtheREADpriortoassertingaWRITEcommand.
Integrated Silicon Solution, Inc. 29
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TRUTH TABLE - CURRENT STATE BANK n - COMMAND TO BANK m
CURRENT STATE CS RAS CAS WE COMMAND / ACTION NOTES
Any H X X X DESELECT(NOP/continuepreviousoperation)
L H H H NoOperation(NOP/continuepreviousoperation)
Idle X X X X Any command allowed to bank m
RowActivating,
Active, or
Precharging
L L H H ACTIVE(selectandactivaterow)
L H L H READ(selectcolumn&startreadburst) 8
L H L L WRITE(selectcolumn&startwriteburst) 8
L L H L PRECHARGE
Read
(AutoPrecharge
disabled)
L L H H ACTIVE(selectandactivaterow)
L H L H READ(selectcolumn&startnewreadburst) 8
L H L L WRITE(selectcolumn&startwriteburst) 8,10
L L H L PRECHARGE
Write
(AutoPrecharge
disabled)
L L H H ACTIVE(selectandactivaterow)
L H L H READ(selectcolumn&startreadburst) 8,9
L H L L WRITE(selectcolumn&startnewwriteburst) 8
L L H L PRECHARGE
Readwith
AutoPrecharge
L L H H ACTIVE(selectandactivaterow)
L H L H READ(selectcolumn&startnewreadburst) 5,8
L H L L WRITE(selectcolumn&startwriteburst) 5,8,10
L L H L PRECHARGE
Write with
AutoPrecharge
L L H H ACTIVE(selectandactivaterow)
L H L H READ(selectcolumn&startreadburst) 5,8
L H L L WRITE(selectcolumn&startnewwriteburst) 5,8
L L H L PRECHARGE
Notes:
1. ThetableapplieswhenbothCKEn-1andCKEnareHIGH,andaftertXSRortXPhasbeenmetifthepreviousstatewasSelf
RefreshorPowerDown.
2. DESELECTandNOParefunctionallyinterchangeable.
3. Allstatesandsequencesnotshownareillegalorreserved.
4. CurrentStateDenitions:
a. Idle:thebankhasbeenprecharged,andtRPhasbeenmet.
b. RowActive:arowinthebankhasbeenactivated,andtRCDhasbeenmet.Nodatabursts/accessesandnoregisterac-
cesses are in progress.
c. Read:aREADbursthasbeeninitiated,withAutoPrechargedisabled,andhasnotyetterminatedorbeenterminated.
d. Write:aWRITEbursthasbeeninitiated,withAutoPrechargedisabled,andhasnotyetterminatedorbeenterminated.
5. ReadwithAPenabledandWritewithAPenabled:theReadwithAutoPrechargeenabledorWritewithAutoPrecharge
enabledstatescanbebrokenintotwoparts:theaccessperiodandtheprechargeperiod.ForReadwithAP,theprecharge
periodisdenedasifthesameburstwasexecutedwithAutoPrechargedisabledandthenfollowedwiththeearliestpossible
PRECHARGEcommandthatstillaccessesallthedataintheburst.ForWritewithAP,theprechargeperiodbeginswhentWR
ends,withtWRmeasuredasifAutoPrechargewasdisabled.Theaccessperiodstartswithregistrationofthecommandand
endswheretheprechargeperiod(ortRP)begins.DuringtheprechargeperiodoftheReadwithAPenabledorWritewithAP
enabledstates,ACTIVE,PRECHARGE,READ,andWRITEcommandstotheotherbankmaybeapplied;duringtheaccess
period,onlyACTIVEandPRECHARGEcommandstotheotherbanksmaybeapplied.Ineithercase,allotherrelatedlimita-
tionsapply(e.g.contentionbetweenREADdataandWRITEdatamustbeavoided).
6.AUTOREFRESH,SELFREFRESH,andMODEREGISTERSETcommandsmayonlybeissuedwhenallbankareidle.
7.ABURSTTERMINATEcommandcannotbeissuedtoanotherbank;itappliestothebankrepresentedbythecurrentstateonly.
8.READsorWRITEslistedintheCommandcolumnincludeREADsandWRITEswithAutoPrechargeenabledandREADsand
WRITEswithAutoPrechargedisabled.
9.RequiresappropriateDMmasking.
10.AWRITEcommandmaybeappliedafterthecompletionofdataoutput,otherwiseaBURSTTERMINATEcommandmustbe
issuedtoendtheREADpriortoassertingaWRITEcommand.
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OPERATION
DESELECT
TheDESELECTfunction(CS=High)preventsnewcommandsfrombeingexecutedbytheMobileDDRSDRAM.The
MobileDDRSDRAMiseffectivelydeselected.Operationsalreadyinprogressarenotaffected.
NO OPERATION
TheNOOPERATION(NOP)commandisusedtoperformaNOPtoaMobileDDRSDRAMthatisselected(CS
=Low).Thispreventsunwantedcommandsfrombeingregisteredduringidleorwaitstates.Operationsalreadyin
progress are not affected.
MODE REGISTER SET
TheModeRegisterandtheExtendedModeRegisterareloadedviatheaddressinputs.See"ModeRegister"andthe
"ExtendedModeRegister"descriptionsforfurtherdetails.
TheMODEREGISTERSETcommandcanonlybeissuedwhenallbanksareidleandnoburstsareinprogress,and
asubsequentexecutablecommandcannotbeissueduntiltMRD(see"ModeRegisterSetCommandTiming")ismet.
NOP Command
= Don't Care
WE
CAS
CS
CKE(High)
A0-An
BA0,BA1
RAS
CK
CK
Mode Register Set command
= Don't Care
CS
CKE(High)
BA0,BA1Code
WE
CAS
RAS
CK
CK
A0-AnCode
Mode Register Set Command Timing
NOTE: Code = Mode Register / Extended Mode Register selection
(BA0, BA1) and op-code (A0 - An)
= Don't Care
CK
CK
Command MRS NOP Valid
tMRD
Address Code Valid
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ACTIVE
BeforeanyREADorWRITEcommandscanbeissuedtoabankintheMobileDDRSDRAM,arowinthatbankmust
beopened.ThisisaccomplishedbytheACTIVEcommand:BA0andBA1selectthebank,andtheaddressinputs
selecttherowtobeactivated.Morethanonebankcanbeactiveatanytime.
Oncearowisopen,aREADorWRITEcommandcouldbeissuedtothatrow,subjecttothetRCDspecication.
AsubsequentACTIVEcommandtoanotherrowinthesamebankcanonlybeissuedafterthepreviousrowhasbeen
closed.TheminimumtimeintervalbetweentwosuccessiveACTIVEcommandsonthesamebankisdenedbytRC.
AsubsequentACTIVEcommandtoanotherbankcanbeissuedwhiletherstbankisbeingaccessed,whichresults
inareductionoftotalrowaccessoverhead.TheminimumtimeintervalbetweentwosuccessiveACTIVEcommands
ondifferentbanksisdenedbytRRD.BankActivationCommandCycleshowsthetRCDandtRRDdenition.
TherowremainsactiveuntilaPRECHARGEcommand(orREADorWRITEcommandwithAutoPrecharge)isissued
to the bank.
APRECHARGEcommand(orREADorWRITEcommandwithAutoPrecharge)mustbeissuedbeforeopeninga
different row in the same bank.
ACTIVE command
= Don't Care
BA = Bank Address
RA = Row Address
WE
CAS
RAS
CS
CKE(High)
CK
CK
BA0,BA1BA
A0-AnRA
Bank Activation Command Cycle
tRRD tRCD= Don't Care
CK
CK
CommandACTNOPACTNOP RD/WR NOPNOP
A0-AnRowRowCol
BA0, BA1BA xBA y BA y
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READ
TheREADcommandisusedtoinitiateaburstreadaccessto
anactiverow,withaburstlengthassetintheModeRegister.
BA0andBA1selectthebank,andtheaddressinputsselect
thestartingcolumnlocation.ThevalueofA10determines
whetherornotAutoPrechargeisused.IfAutoPrechargeis
selected, the row being accessed will be precharged at the
endofthereadburst;ifAutoPrechargeisnotselected,the
rowwillremainopenforsubsequentaccesses.
ThebasicReadtimingparametersforDQsareshownin
FigureBasicReadTimingParameterstheyapplytoallRead
operations.
DuringReadbursts,DQSisdrivenbytheMobileDDR
SDRAMalongwiththeoutputdata.TheinitialLowstate
oftheDQSisknownasthereadpreamble;theLowstate
coincident with last data-out element is known as the read
postamble.Therstdata-outelementisedgealignedwith
therstrisingedgeofDQSandthesuccessivedata-out
elementsareedgealignedtosuccessiveedgesofDQS.This
isshowninFigureReadBurstShowingCASLatencywitha
CAS latency of 2 and 3.
Uponcompletionofareadburst,assumingnootherREAD
commandhasbeeninitiated,theDQswillgotoHigh-Z.
READ Command
WE
CKE(High)
RAS
CAS
A0-An
= Don't Care
BA = Bank Address
CA = Column Address
AP = Auto Precharge
CS
CK
CK
CA
A10 AP
Disable AP
Enable AP
BA0,BA1 BA
Basic Read Timing Parameters
= Don't Care
CK
CK
tCK tCH tCL
DQS
DQ DO nDO n+1DO n+2DO n+3
tDQSCK
tRPRE
tRPST
tAC
tLZ
tHZ
tDQSQmax
tQH tQH
tDQSCK
DQS
DQ DO nDO n+1DO n+2DO n+3
tDQSCK
tRPRE
tRPST
tAC
tLZ
tHZ
tDQSQmax
tQH tQH
tDQSCK
tACmin
tACmax
tCK
Notes:
1. DOn=DataOutfromcolumnn
2. AllDQarevalidtACaftertheCKedge.
AllDQarevalidtDQSQaftertheDQSedge,regardlessoftAC
Integrated Silicon Solution, Inc. 33
Rev. 00B
06/23/09
IS43LR16160D, IS43LR32800D
Read Burst Showing CAS Latency
Command
CK
CK
= Don't Care
NOPREAD NOPNOPNOPNOP
AddressBA,Col n
DQS
CL=2
DQ DO n
DQS
CL=3
DQ DO n
Notes:
1. DOn=DataOutfromcolumnn
2. BA,Coln=BankA,Columnn
3. BurstLength=4;3subsequentelementsofDataOutappearintheprogrammedorderfollowingDOn
4. ShownwithnominaltAC,tDQSCKandtDQSQ
READ to READ
DatafromareadburstmaybeconcatenatedortruncatedbyasubsequentREADcommand.Therstdatafromthe
new burst follows either the last element of a completed burst or the last desired element of a longer burst that is
beingtruncated.ThenewREADcommandshouldbeissuedXcyclesaftertherstREADcommand,whereXequals
thenumberofdesireddata-outelementpairs(pairsarerequiredbythe2nprefetcharchitecture).
AREADcommandcanbeinitiatedonanyclockcyclefollowingapreviousREADcommand.Full-speedrandomread
accesseswithinapageorpagescanbeperformedasshowninFigureRandomReadBursts.
READ BURST TERMINATE
DatafromanyREADburstmaybetruncatedwithaBURSTTERMINATEcommand.TheBURSTTERMINATElatency
isequaltotheread(CAS)latency,i.e.,theBURSTTERMINATEcommandshouldbeissuedXcyclesaftertheREAD
commandwhereXequalsthedesireddata-outelementpairs.
READ to WRITE
DatafromREADburstmustbecompletedortruncatedbeforeasubsequentWRITEcommandcanbeissued.If
truncationisnecessary,theBURSTTERMINATEcommandmustbeused,asshowninFigureReadtoWriteforthe
caseofnominaltDQSS.
READ to PRECHARGE
AReadburstmaybefollowedbyortruncatedwithaPRECHARGEcommandtothesamebank(providedAuto
Prechargewasnotactivated).ThePRECHARGEcommandshouldbeissuedXcyclesaftertheREADcommand,
whereXequalthenumberofdesireddata-outelementpairs.
FollowingthePRECHARGEcommand,asubsequentcommandtothesamebankcannotbeissueduntiltRPismet.
Notethatpartoftherowprechargetimeishiddenduringtheaccessofthelastdata-outelements.
InthecaseofaReadbeingexecutedtocompletion,aPRECHARGEcommandissuedattheoptimumtime(as
describedabove)providesthesameoperationthatwouldresultfromReadburstwithAutoPrechargeenabled.The
disadvantageofthePRECHARGEcommandisthatitrequiresthatthecommandandaddressbusesbeavailableat
theappropriatetimetoissuethecommand.TheadvantageofthePRECHARGEcommandisthatitcanbeusedto
truncate bursts.
34 Integrated Silicon Solution, Inc.
Rev. 00B
06/23/09
IS43LR16160D, IS43LR32800D
Consecutive Read Bursts
Notes:
1. DOn(orb)=DataOutfromcolumnn(orcolumnb).
2. BurstLength=4or8(if4,theburstsareconcatenated;if8,thesecondburstinterruptstherst).
3. Readburstsaretoanactiverowinanybank.
4. ShownwithnominaltAC,tDQSCKandtDQSQ.
Address
CK
CK
DQS
DQ DO n DO b
DQ DO n DO b
= Don't Care
DQS
Command NOPREAD READ NOPNOPNOP
BA,Col nBA,Col b
CL=3
CL=2
Non-Consecutive Read Bursts
Notes:
1. DOn(orb)=DataOutfromcolumnn(orcolumnb).
2. BAColn(b)=BankA,Columnn(b).
3. BurstLength=4;3subsequentelementsofDataOutappearintheprogrammedorderfollowingDOn(b).
4. ShownwithnominaltAC,tDQSCKandtDQSQ.
CK
CK
DQS
DQ DO n DO b
= Don't Care
DQ DO n
DQS
Command READ READNOP NOPNOPNOP
AddressBA,Col nBA,Col b
CL=3
CL=2
Integrated Silicon Solution, Inc. 35
Rev. 00B
06/23/09
IS43LR16160D, IS43LR32800D
Random Read Bursts
Notes:
1. DOn,etc.=DataOutfromcolumnn,etc.
n',x',etc.=DataOutelements,accordingtotheprogrammedburstorder.
2. BA,Coln=BankA,Columnn.
3. BurstLength=2,4or8incasesshown(ifburstof4or8,theburstisinterrupted).
4. Readsaretoactiverowsinanybanks.
Address
CK
CK
BA,Col bBA,Col g
DQS
= Don't Care
DQS
Command READ READ NOPNOPREAD READ
BA,Col nBA,Col x
DQ DO nDO n' DO xDO x' DO bDO b'
DQ DO nDO n' DO xDO x' DO bDO b' DO gDO g'
CL=3
CL=2
Terminating a Read Burst
Notes:
1. DOn=DataOutfromcolumnn.
2. BA,Coln=BankA,Columnn.
3. Casesshownareburstsof4or8terminatedafter2dataelements.
4. ShownwithnominaltAC,tDQSCKandtDQSQ.
CK
CK
DQS
= Don't Care
DQS
DQ
Command READ BSTNOPNOPNOPNOP
AddressBA,Col n
CL=3
CL=2
36 Integrated Silicon Solution, Inc.
Rev. 00B
06/23/09
IS43LR16160D, IS43LR32800D
Read To Write
Notes:
1. DOn=DataOutfromcolumnn;DIb=DataIntocolumnb.
2. Burstlength=4or8inthecasesshown;iftheburstlengthis2,theBSTcommandcanbeomitted.
3. ShownwithnominaltAC,tDQSCKandtDQSQ.
CK
CK
tDQSS
DQS
= Don't Care
Command BSTNOPWRITENOPNOPREAD
Command READ NOPWRITENOPNOPBST
DM
DM
DQ DO n
DQ DO n
DQS
AddressBA,Col nBA,Col b
AddressBA,Col nBA,Col b
CL=3
CL=2
Integrated Silicon Solution, Inc. 37
Rev. 00B
06/23/09
IS43LR16160D, IS43LR32800D
Read To Precharge
Notes:
1. DOn=DataOutfromcolumnn.
2. Casesshownareeitheruninterruptedburstof4,orinterruptedburstsof8or16.
3. ShownwithnominaltAC,tDQSCKandtDQSQ.
4. Prechargemaybeappliedat(BL/2)tCKaftertheREADcommand.
5. NotethatPrechargemaynotbeissuedbeforetRASnsaftertheACTIVEcommandforapplicablebanks.
6. TheACTIVEcommandmaybeappliediftRChasbeenmet.
CK
CK
DQS
DQ DO n
= Don't Care
DQ DO n
DQS
tRP
Command READ NOPNOP PRE NOPACT
AddressBA,Col nBA, Row
Bank
(a or all)
CL=3
CL=2
Burst Terminate
TheBURSTTERMINATEcommandisusedtotruncatereadbursts(withAutoPrechargedisabled).Themostrecently
registeredREADcommandpriortotheBURSTTERMINATEcommandwillbetruncated.NotethattheBURST
TERMINATEcommandisnotbankspecic.
Thiscommandshouldnotbeusedtoterminatewritebursts.
= Don't Care
CAS
CS
CKE(High)
A0-An
BA0,BA1
WE
RAS
CK
CK
Burst Terminate Command
38 Integrated Silicon Solution, Inc.
Rev. 00B
06/23/09
IS43LR16160D, IS43LR32800D
WRITE
TheWRITEcommandisusedtoinitiateaburstwriteaccess
toanactiverow,withaburstlengthassetintheMode
Register.BA0andBA1selectthebank,andtheaddress
inputsselectthestartingcolumnlocation.Thevalueof
A10determineswhetherornotAutoPrechargeisused.If
AutoPrechargeisselected,therowbeingaccessedwillbe
prechargedattheendofthewriteburst;ifAutoPrecharge
isnotselected,therowwillremainopenforsubsequent
accesses.
BasicWritetimingparametersforDQsareshowninFigure
BasicWriteTimingParameters;theyapplytoallWrite
operations.
Input data appearing on the data bus, is written to the
memoryarraysubjecttotheDMinputlogiclevelappearing
coincidentwiththedata.IfagivenDMsignalisregistered
Low,thecorrespondingdatawillbewrittentothememory;
iftheDMsignalisregisteredHigh,thecorrespondingdata
inputswillbeignored,andawritewillnotbeexecutedtothat
byte / column location.
WRITE command
BA0,BA1BA
CS
CKE(High)
RAS
CAS
A0-An
= Don't Care
BA = Bank Address
CA = Column Address
AP = Auto Precharge
WE
CK
CK
CA
A10AP
Disable AP
Enable AP
Basic Write Timing Parameters
Notes:
1. DIn=DataInforcolumnn.
2. 3subsequentelementsofDataInareappliedintheprogrammedorderfollowingDIn.
3. tDQSS:eachrisingedgeofDQSmustfallwithinthe±25%windowofthecorrespondingpositiveclockedge.
= Don't Care
Case 1:
tDQSS = min
Case 2:
tDQSS = max
t
DH
t
DS
DQ, DM DI n
t
WPRES
DQS
t
WPRE
t
DQSS
t
DQSH
t
DSH
t
DQSL
t
DSH
t
WPST
t
DH
t
DS
DI n
DQS
t
WPRES
t
WPRE
t
DQSS
t
DQSH
t
DSS
t
DQSL
t
DSS
t
WPST
CK
CK
t
CK
t
CH
t
CL
DQ, DM
Integrated Silicon Solution, Inc. 39
Rev. 00B
06/23/09
IS43LR16160D, IS43LR32800D
DuringWritebursts,therstvaliddata-inelementwillberegisteredontherstrisingedgeofDQSfollowingthe
WRITEcommand,andthesubsequentdataelementswillberegisteredonsuccessiveedgesofDQS.TheLowstate
ofDQSbetweentheWRITEcommandandtherstrisingedgeiscalledthewritepreamble,andtheLowstateon
DQSfollowingthelastdata-inelementiscalledthewritepostamble.ThetimebetweentheWRITEcommandandthe
rstcorrespondingrisingedgeofDQS(tDQSS)isspeciedwitharelativelywiderange-from75%to125%ofaclock
cycle.ThegurebelowshowsthetwoextremesoftDQSSforaburstof4.Uponcompletionofaburst,assumingno
othercommandshavebeeninitiated,theDQswillremainhigh-Zandanyadditionalinputdatawillbeignored.
Write Burst (min. and max. tDQSS)
Notes:
1. DIb=DataIntocolumnb.
2. 3subsequentelementsofDataInareappliedintheprogrammedorderfollowingDIb.
3. Anon-interruptedburstof4isshown.
4. A10isLOWwiththeWRITEcommand(AutoPrechargeisdisabled).
WRITE to WRITE
DataforanyWRITEburstmaybeconcatenatedwithortruncatedwithasubsequentWRITEcommand.Ineithercase,
acontinuousowofinputdata,canbemaintained.ThenewWRITEcommandcanbeissuedonanypositiveedgeof
theclockfollowingthepreviousWRITEcommand.
Therstdata-inelementfromthenewburstisappliedaftereitherthelastelementofacompletedburstorthelast
desireddataelementofalongerburstwhichisbeingtruncated.ThenewWRITEcommandshouldbeissuedXcycles
aftertherstWRITEcommand,whereXequalsthenumberofdesireddata-inelementpairs.
Full-speedrandomwriteaccesseswithinapageorpagescanbeperformedasshowninFigure29.
WRITE to READ
DataforanyWriteburstmaybefollowedbyasubsequentREADcommand.TofollowaWritewithouttruncatingthe
writeburst,tWTRshouldbemetasshowninNon-interruptingWritetoRead.
DataforanyWriteburstmaybetruncatedbyasubsequentREADcommandasshowninFigureInterruptingWriteto
Read.Notethattheonlydata-inpairsthatareregisteredpriortothetWTRperiodarewrittentotheinternalarray,and
anysubsequentdata-inmustbemaskedwithDM.
DQ
DQS
tDQSSmax
DM
AddressBA,Col b
DM
DQS
tDQSSmin
= Don't Care
CK
CK
Command WRITE NOP NOPNOPNOPNOP
DQ
40 Integrated Silicon Solution, Inc.
Rev. 00B
06/23/09
IS43LR16160D, IS43LR32800D
WRITE to PRECHARGE:
DataforanyWRITEburstmaybefollowedbyasubsequentPRECHARGEcommandtothesamebank(provided
AutoPrechargewasnotactivated).TofollowaWRITEwithouttruncatingtheWRITEburst,tWRshouldbemet.Data
foranyWRITEburstmaybetruncatedbyasubsequentPRECHARGEcommand.
Notethatonlydata-inpairsthatareregisteredpriortothetWRperiodarewrittentotheinternalarray,andany
subsequentdata-inshouldbemaskedwithDM.FollowingthePRECHARGEcommand,asubsequentcommandto
thesamebankcannotbeissueduntiltRPismet.
Concatenated Write Bursts
Notes:
1. DIb(n)=DataIntocolumnb(columnn).
2. 3subsequentelementsofDataInareappliedintheprogrammedorderfollowingDIb.
3subsequentelementsofDataInareappliedintheprogrammedorderfollowingDIn.
3. Non-interruptedburstsof4areshown.
4. EachWRITEcommandmaybetoanyactivebank.
Command
= Don't Care
DM
DM
tDQSSmin
DQS
CK
CK
DQS
tDQSSmax
WRITEWRITENOP NOPNOPNOP
AddressBA,Col bBA,Col n
DQ Di b Di n
DQ Di bDi n
Integrated Silicon Solution, Inc. 41
Rev. 00B
06/23/09
IS43LR16160D, IS43LR32800D
Non-Consecutive Write Bursts
Notes:
1. DIb(n)=DataIntocolumnb(orcolumnn).
2. 3subsequentelementsofDataInareappliedintheprogrammedorderfollowingDIb.
3subsequentelementsofDataInareappliedintheprogrammedorderfollowingDIn.
3. Non-interruptedburstsof4areshown.
4. EachWRITEcommandmaybetoanyactivebankandmaybetothesameordifferentdevices.
= Don't Care
CK
CK
DQS
tDQSSmax
DM
Address
CommandWRITEWRITENOPNOP NOPNOP
BA,Col bBA,Col n
DQ
Random Write Cycles
Notes:
1. DIbetc.=DataIntocolumnb,etc.;
b',etc.=thenextDataInfollowingDIb,etc.accordingtotheprogrammedburstorder.
2. Programmedburstlength=2,4,8or16incasesshown.Ifburstof4,8or16,burstwouldbetruncated.
3. EachWRITEcommandmaybetoanyactivebankandmaybetothesameordifferentdevices.
= Don't Care
CK
CK
DQS
tDQSSmax
DM
CommandWRITEWRITEWRITEWRITE WRITENOP
Address BA,Col bBA,Col aBA,Col x BA,Col nBA,Col g
DQ Di b Di nDi xDi aDi a'Di n'Di b' Di x'
42 Integrated Silicon Solution, Inc.
Rev. 00B
06/23/09
IS43LR16160D, IS43LR32800D
Non-Interrupting Write to Read
Notes:
1. DIb=DataIntocolumnb.
3subsequentelementsofDataInareappliedintheprogrammedorderfollowingDIb.
2. Anon-interruptedburstof4isshown.
3. tWTRisreferencedfromthepositiveclockedgeafterthelastDataInpair.
4. A10isLOWwiththeWRITEcommand(AutoPrechargeisdisabled).
5. TheREADandWRITEcommandsaretothesamedevicebutnotnecessarilytothesamebank.
= Don't Care
Address
CK
CK
Command
DQS
DQ
DM
BA,Col bBA,Col n
WRITENOPNOPNOP NOPREAD NOP
t
DQSSmax
CL=3
t
WTR
Di b
Interrupting Write to Read
Notes:
1. DIb=DataIntocolumnb.DOn=DataOutfromcolumnn.
2. Aninterruptedburstof4isshown,2dataelementsarewritten.
3subsequentelementsofDataInareappliedintheprogrammedorderfollowingDIb.
3. tWTRisreferencedfromthepositiveclockedgeafterthelastDataInpair.
4. A10isLOWwiththeWRITEcommand(AutoPrechargeisdisabled).
5. TheREADandWRITEcommandsaretothesamedevicebutnotnecessarilytothesamebank.
= Don't Care
CK
CK
Command
Address
DQ
DM
DQS
WRITE NOPNOPNOPREAD NOPNOP
BA,Col bBA,Col n
Di bDO n
t
DQSSmax
t
WTR
CL=3
Integrated Silicon Solution, Inc. 43
Rev. 00B
06/23/09
IS43LR16160D, IS43LR32800D
Non-Interrupting Write to Precharge
Notes:
1. DIb=DataIntocolumnb.
3subsequentelementsofDataInareappliedintheprogrammedorderfollowingDIb.
2. Anon-interruptedburstof4isshown.
3. tWRisreferencedfromthepositiveclockedgeafterthelastDataInpair.
4. A10isLOWwiththeWRITEcommand(AutoPrechargeisdisabled).
= Don't Care
CK
CK
tDQSSmaxtWR
DM
DQS
CommandWRITE NOP NOPNOPNOPPRE
AddressBA,Col bBA a
(or all)
DQ Di b
Interrupting Write to Precharge
Notes:
1. DIb=DataIntocolumnb.
2. Aninterruptedburstof4,8or16isshown,2dataelementsarewritten.
3. tWRisreferencedfromthepositiveclockedgeafterthelastdesiredDataInpair.
4. A10isLOWwiththeWRITEcommand(AutoPrechargeisdisabled).
5. *1=canbeDon'tCareforprogrammedburstlengthof4.
6. *2=forprogrammedburstlengthof4,DQSbecomesDon'tCareatthispoint.
= Don't Care
CK
CK
tDQSSmaxtWR
DQS*2
CommandWRITE NOP NOPNOPNOPPRE
AddressBA,Col bBA a
(or all)
DQ Di b
DM *1 *1 *1 *1
44 Integrated Silicon Solution, Inc.
Rev. 00B
06/23/09
IS43LR16160D, IS43LR32800D
PRECHARGE
ThePRECHARGEcommandisusedtodeactivatetheopenrowinaparticularbankortheopenrowinallbanks.
Thebank(s)willbeavailableforasubsequentrowaccessaspeciedtime(tRP)afterthePRECHARGEcommandis
issued.
Input A10 determines whether one or all banks are to be precharged. In case where only one bank is to be
precharged,inputsBA0,BA1selectthebank.OtherwiseBA0,BA1aretreatedas“Don’tCare”.
Onceabankhasbeenprecharged,itisintheidlestateandmustbeactivatedpriortoanyREADorWRITEcommand
beingissued.APRECHARGEcommandwillbetreatedasaNOPifthereisnoopenrowinthatbank,orifthe
previously open row is already in the process of precharging.
AUTO PRECHARGE
AutoPrechargeisafeaturewhichperformsthesameindividualbankprechargefunctionasdescribedabove,but
withoutrequiringanexplicitcommand.ThisisaccomplishedbyusingA10(A10=High),toenableAutoPrechargein
conjunctionwithaspecicREADorWRITEcommand.Aprechargeofthebank/rowthatisaddressedwiththeREAD
orWRITEcommandisautomaticallyperformeduponcompletionofthereadorwriteburst.AutoPrechargeisnon
persistentinthatitiseitherenabledordisabledforeachindividualREADorWRITEcommand.
AutoPrechargeensuresthataprechargeisinitiatedattheearliestvalidstagewithinaburst.Theusermustnotissue
anothercommandtothesamebankuntiltheprechargingtime(tRP)iscompleted.Thisisdeterminedasifanexplicit
PRECHARGEcommandwasissuedattheearliestpossibletime,asdescribedforeachbursttypeintheOperation
section of this specification.
BURST TERMINATE
TheBURSTTERMINATEcommandisusedtotruncatereadbursts(withAutoPrechargedisabled).
ThemostrecentlyregisteredREADcommandpriortotheBURSTTERMINATEcommandwillbetruncated.Notethat
theBURSTTERMINATEcommandisnotbankspecic.Thiscommandshouldnotbeusedtoterminatewritebursts.
PRECHARGE command
CS
CKE(High)
= Don't Care
BA = Bank Address
(if A10 = L, otherwise Don't Care)
RAS
CAS
WE
A
0-A9, An
CK
CK
A10
One Bank
All Banks
BA0,BA1BA
Burst Terminate Command
= Don't Care
CAS
CS
CKE(High)
A0-An
BA0,BA1
WE
RAS
CK
CK
Integrated Silicon Solution, Inc. 45
Rev. 00B
06/23/09
IS43LR16160D, IS43LR32800D
REFRESH REQUIREMENTS
MobileDDRSDRAMdevicesrequirearefreshofallrowsinarollingtimeinterval.Eachrefreshisgeneratedinone
oftwoways:byanexplicitAUTOREFRESHcommand,orbyaninternallytimedeventinSELFREFRESHmode.
Dividingthenumberofdevicerowsintotherollingtimeinterval(tr e f )denestheaveragerefreshinterval(tREFI),
which is a guideline to controllers for distributed refresh timing.
AUTO REFRESH
AUTOREFRESHcommandisusedduringnormaloperationoftheMobileDDRSDRAM.Thiscommandisnon
persistent,soitmustbeissuedeachtimearefreshisrequired.
Therefreshaddressingisgeneratedbytheinternalrefreshcontroller.TheMobileDDRSDRAMrequiresAUTO
REFRESHcommandsatanaverageperiodicintervaloftREFI.
SELF REFRESH
TheSELFREFRESHcommandcanbeusedtoretaindataintheMobileDDRSDRAM,eveniftherestofthesystem
ispowereddown.WhenintheSelfRefreshmode,theMobileDDRSDRAMretainsdatawithoutexternalclocking.
TheMobileDDRSDRAMdevicehasabuilt-intimertoaccommodateSelfRefreshoperation.TheSELFREFRESH
commandisinitiatedlikeanAUTOREFRESHcommandexceptCKEisLOW.InputsignalsexceptCKEare“Don’t
Care”duringSelfRefresh.TheusermayhalttheexternalclockoneclockaftertheSELFREFRESHcommandis
registered.
Oncethecommandisregistered,CKEmustbeheldlowtokeepthedeviceinSelfRefreshmode.Theclockis
internallydisabledduringSelfRefreshoperationtosavepower.Theminimumtimethatthedevicemustremainin
SelfRefreshmodeistRFC.TheprocedureforexitingSelfRefreshrequiresasequenceofcommands.First,the
clockmustbestablepriortoCKEgoingbackHigh.OnceSelfRefreshExitisregistered,adelayofatleasttXSmust
be satisfied before a valid command can be issued to the device to allow for completion of any internal refresh in
progress.
TheuseofSelfRefreshmodeintroducesthepossibilitythataninternallytimedrefresheventcanbemissedwhen
CKEisraisedforexitfromSelfRefreshmode.UponexitfromSelfRefreshanextraAUTOREFRESHcommandis
recommended.IntheSelfRefreshmode,twoadditionalpower-savingoptionsexist:TemperatureCompensatedSelf
Refresh(TCSR)andPartialArraySelfRefresh(PASR);theyaredescribedintheExtendedModeRegistersection.
AUTO REFRESH command
= Don't Care
CS
CKE(High)
A0-An
BA0,BA1
CAS
WE
RAS
CK
CK
SELF REFRESH command
= Don't Care
CS
CKE
A0-An
BA0,BA1
CAS
WE
RAS
CK
CK
46 Integrated Silicon Solution, Inc.
Rev. 00B
06/23/09
IS43LR16160D, IS43LR32800D
Auto Refresh Cycles Back-to-Back
Note:BaA,Rown=BankA,Rown.
Ba A, Row n = Bank A, Row n
tRP tRFCtRFC
= Don't Care
A10 (AP)
CK
CK
DQ High-Z
CommandNOP ARFPRENOP NOPARF NOPNOPACT
AddressBa A,
Row n
Row n
Pre All
Self Refresh Entry and Exit
tRP
= Don't Care
CKE
Command NOPARFNOPNOP NOPPRE ARFACTNOP
DQ High-Z
> tRFC tXSRtRFC
Enter
Self Refresh
Mode
Exit from
Self Refresh
Mode
Any Command
(Auto Refresh
Recommended)
AddressBa A,
R
ow n
A10 (AP) Pre AllRow n
CK
CK
Integrated Silicon Solution, Inc. 47
Rev. 00B
06/23/09
IS43LR16160D, IS43LR32800D
POWER-DOWN
Power-downisenteredwhenCKEisregisteredLow(noaccessescanbeinprogress).Ifpower-downoccurswhenall
banksareidle,thismodeisreferredtoasprechargepower-down;ifpower-downoccurswhenthereisarowactivein
any bank, this mode is referred to as active power-down.
Enteringpower-downdeactivatestheinputandoutputbuffers,excludingCK,CKandCKE.Inpower-downmode,CKE
Lowmustbemaintained,andallotherinputsignalsare“Don’tCare”.Theminimumpower-downdurationisspecied
bytCKE.However,power-downdurationislimitedbytherefreshrequirementsofthedevice.
Thepower-downstateissynchronouslyexitedwhenCKEisregisteredHigh(alongwithaNOPorDESELECT
command).AvalidcommandmaybeappliedtXPafterexitfrompower-down.
Power-Down Entry and Exit
Note:PrechargePower-Downmodeshown:allbanksareidleandtRPismetwhenPower-DownEntrycommandisissued.
= Don't Care
Any
Command
Power Down
Entry
Exit from
Power Down
tCKEtXP
CK
CK
CKE
CommandNOPNOPNOPValidPRENOPNOP
AddressValid
DQ High-Z
A10 (AP) Valid
Pre All
tRP
48 Integrated Silicon Solution, Inc.
Rev. 00B
06/23/09
IS43LR16160D, IS43LR32800D
DEEP POWER-DOWN
TheDeepPower-Down(DPD)modeenablesverylowstandbycurrents.Allinternalvoltagegeneratorsinsidethe
MobileDDRSDRAMarestoppedandallmemorydataislostinthismode.AlltheinformationintheModeRegister
andtheExtendedModeRegisterislost.
DeepPower-DownisenteredusingtheBURSTTERMINATEcommandexceptthatCKEisregisteredLow.Allbanks
mustbeinidlestatewithnoactivityonthedatabuspriortoenteringtheDPDmode.Whileinthisstate,CKEmustbe
heldinaconstantLowstate.
ToexittheDPDmode,CKEistakenhighaftertheclockisstableandNOPcommandsmustbemaintainedforatleast
200μs.After200μsacompletere-initializationisrequiredfollowingsteps4through11asdenedfortheinitialization
sequence.
Deep Power-Down Entry and Exit
Notes:
1. ClockmustbestablebeforeexitingDeepPower-Downmode.Thatis,theclockmustbecyclingwithinspecicationsbyTa0.
2. DevicemustbeintheallbanksidlestatepriortoenteringDeepPower-Downmode.
3. 200μsisrequiredbeforeanycommandcanbeapplieduponexitingDeepPower-Downmode.
4. UponexitingDeepPower-DownmodeaPRECHARGEALLcommandmustbeissued,followedbytwoAUTOREFRESH
commandsandaloadmoderegistersequence.
= Don't Care
CKE
Command
DQ
Enter DPD Mode
Address
CK
CK
DPDNOPNOPValid
Valid
DQS
DM
Exit DPD Mode
T0 T1 Ta0Ta1 Ta2
T = 200 µs
tRP
Integrated Silicon Solution, Inc. 49
Rev. 00B
06/23/09
IS43LR16160D, IS43LR32800D
CLOCK STOP
Stopping a clock during idle periods is an effective method of reducing power consumption.
TheMobileDDRSDRAMsupportsclockstopunderthefollowingconditions:
• Thelastcommand(ACTIVE,READ,WRITE,PRECHARGE,AUTOREFRESHorMODEREGISTERSET)hasex-
ecutedtocompletion,includinganydata-outduringreadbursts;thenumberofclockpulsesperaccesscommand
dependsonthedevice’sACtimingparametersandtheclockfrequency;
• Therelatedtimingconditions(tRCD,tWR,tRP,tRFC,tMRD)hasbeenmet;
• CKEisheldHigh
Whenallconditionshavebeenmet,thedeviceiseitherin“idlestate”or“rowactivestate”andclockstopmodemay
beenteredwithCKheldLowandCKheldHigh.
Clockstopmodeisexitedbyrestartingtheclock.AtleastoneNOPcommandhastobeissuedbeforethenextaccess
commandmaybeapplied.Additionalclockpulsesmightberequireddependingonthesystemcharacteristics.
• Initiallythedeviceisinclockstopmode
• TheclockisrestartedwiththerisingedgeofT0andaNOPonthecommandinputs
• WithT1avalidaccesscommandislatched;thiscommandisfollowedbyNOPcommandsinordertoallowforclock
stop as soon as this access command is completed
• TnisthelastclockpulserequiredbytheaccesscommandlatchedwithT1
• TheclockcanbestoppedafterTn
Clock Stop Mode Entry and Exit
Command
Timing Condition
NOP NOPCMD NOPNOP
= Don't Care
CK
CK
CKE
Enter
Clock
Stop
Mode
Exit
Clock
Stop
Mode
Clock
Stopped
Valid
Command
Valid
Address
DQ, DQS(High-Z)
T0 T1 T2 Tn
50 Integrated Silicon Solution, Inc.
Rev. 00B
06/23/09
IS43LR16160D, IS43LR32800D
16Mx16 ORDERING INFORMATION - VD D = 1.8V
Commercial Range: 0°C to 70°C
Frequency Speed (ns) Order Part No. Package
200MHz 5 IS43LR16160D-5BL 60-ballTF-BGA,Lead-free
166MHz 6 IS43LR16160D-6BL 60-ballTF-BGA,Lead-free
133MHz 7.5 IS43LR16160D-75BL 60-ballTF-BGA,Lead-free
8Mx32 ORDERING INFORMATION - VD D = 1.8V
Commercial Range: 0°C to 70°C
Frequency Speed (ns) Order Part No. Package
200MHz 5 IS43LR32800D-5BL 90-ballTF-BGA,Lead-free
166MHz 6 IS43LR32800D-6BL 90-ballTF-BGA,Lead-free
133MHz 7.5 IS43LR32800D-75BL 90-ballTF-BGA,Lead-free
Industrial Range: -40°C to +85°C
Frequency Speed (ns) Order Part No. Package
200MHz 5 IS43LR16160D-5BLI 60-ballTF-BGA,Lead-free
166MHz 6 IS43LR16160D-6BLI 60-ballTF-BGA,Lead-free
133MHz 7.5 IS43LR16160D-75BLI 60-ballTF-BGA,Lead-free
PleasecontactProductManagerforleadedproductsupport.
Industrial Range: -40°C to +85°C
Frequency Speed (ns) Order Part No. Package
200MHz 5 IS43LR32800D-5BLI 90-ballTF-BGA,Lead-free
166MHz 6 IS43LR32800D-6BLI 90-ballTF-BGA,Lead-free
133MHz 7.5 IS43LR32800D-75BLI 90-ballTF-BGA,Lead-free
PleasecontactProductManagerforleadedproductsupport.
Integrated Silicon Solution, Inc. 51
Rev. 00B
06/23/09
IS43LR16160D, IS43LR32800D
52 Integrated Silicon Solution, Inc.
Rev. 00B
06/23/09
IS43LR16160D, IS43LR32800D
0.45
0.80
D1
2. Reference document : JEDEC MO-207
1. CONTROLLING DIMENSION : MM .
NOTE :
Package Outline 08/14/2008