U62256
November 01, 2001 1 1
F 32768x8 bit static CMOS RAM
F Access times 70 ns, 100 ns
F Common data inputs and
data outputs
F Three-state outputs
F Typ. operat i ng supply current
70 ns: 50 mA
100 ns: 40 mA
F TTL/CMOS-compatible
F Automatical reduct ion of power
dissipation in long Read Cycles
F Power supply voltage 5 V + 10 %
F Operating temperature ranges
0 to 70 °C
-40 to 85 °C
F CECC 90000 Qual ity Standard
F ESD protection > 2000 V
(MIL STD 883C M3015. 7)
F Latch-up immunity >100 mA
F Package: SOP28 (330 mil)
Standard 32K x 8 SRAM
Features
The U62256 is a static RAM ma nu-
factured using a CMOS process
technology with the following ope-
rating modes:
- Read - Standby
- Write - Data Retention
The memory array is based on a
MIX MOS ce ll.
The circuit is activated by the fal-
ling edge of E. The address and
control inputs open simul taneously.
According to the information of W
and G, the data inputs, or outputs,
are active. In a Read cycle, the
data outputs are activated by the
falling edge of G, afterwards the
data word read will be available at
the outputs DQ0-DQ7. After the
address change, the data outputs
go High-Z until the new information
read is available. The data outputs
have not preferred state.
The Read cycle is finished by the
falling edge of W, or by the rising
edge of E, respectively.
Data retention is guaranteed down
to 2 V. With the exception of E, all
inputs consist of NOR gates, so
that no pull-up/pull-down resistors
are required.
Description
Pin Conf i gurat ion
1
A14 VCC
28
2
A12 W
27
4
A6 A8
25
5
A5 A9
24
3
A7 A13
26
6
A4 A11
23
7
A3 G
22
8
A2 A10
21
12
DQ1 DQ5
17
9
A1 E
20
10
A0 DQ7
19
11
DQ0 DQ6
18
13
DQ2 DQ4
16
14
VSS DQ3
15
Top View
Signal Name Signal Description
A0 - A14 Address Inputs
DQ0 - DQ7 Data In/Ou t
EChip Enable
GOutput Enable
WWrite En able
VCC Power Supply V ol tage
VSS Ground
Pin Descript ion
SOP
U62256
November 01, 2001
2
Operating Mode E W G DQ0 - DQ7
Standby/not selected H * * High-Z
Internal Read L H H High-Z
Read L H L Dat a Outputs Low- Z
Write L L * Data Inputs High-Z
Truth Ta bl e
Block Diagram
Characteristics
a St resses great er than those listed under „Absolute Maximum Ratings“ may cause permanent damage to the device. T his is a stress rating
only, and functional operation of the device at condition above those indicated in the operational sections of this specification i s not imp lied .
Exposure to absolute maximum rating conditions for extended periods may affect reliability
b Maxi mum voltage is 7 V
c Not more than 1 output should be shorted at the same time. Duration of the short circuit should not exceed 30 s.
All voltages are referenced to VSS = 0 V (ground).
All characteristics are valid in the power supply vol tage range and in the operating tempera ture range specifi ed.
Dynamic measurements are based on a rise and fall time of ≤ 5 ns, measured between 10 % and 90 % of VI, as well as
input levels of VIL = 0 V and VIH = 3 V. The ti ming reference le vel of al l input and outpu t signals is 1.5 V,
with the exce ption o f the tdis- times and ten-times, in whic h cases transition is measured ±200 mV from steady-stat e voltage.
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
VCC VSS W GE
Row Address
Inputs
Column Address
Inputs
Address
Change
Detector
Column Decoder Row Decoder
Se ns e Am plifi er/
Write Control Logic
Clock
Generator
Co mmo n Data I/O
Memory Cell
Array
512 Rows x
64 x 8 Columns
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
*H or L
Maxim um Rating s aSymbol Min. Max. Unit
Powe r Supply Vo ltage VCC -0.5 7 V
Input Vol tage VI-0.5 VCC + 0.5 bV
Out put Voltage VO-0.5 VCC + 0.5 bV
Power Dissipation PD-1W
Operating Temperature C-Type
K-Type Ta0
-40 70
85 °C
Storage Tem peratu re Tstg -65 125 °C
Out put Short-Circuit Current
at VCC = 5 V and VO = 0 V c| IOS | 200 mA
U62256
November 01, 2001 3 3
d -2 V at Pulse Width 30 ns
Recommended
Operating Condi tions Symbol Conditions Min. Max. Unit
Power Supply Voltage VCC 4.5 5.5 V
Input Low Volt age d VIL -0.3 0.8 V
Input High Voltage VIH 2.2 VCC + 0.3 V
Electrical Characteri stics Symbol Cond itions Min. Max. Unit
Supply Current - Operating Mode
Supply Current - Standby Mode
(CMOS level)
Supply Current - Standby Mode
(TTL level)
ICC(OP)
ICC(SB)
ICC(SB)1
VCC
VIL
VIH
tcW
tcW
VCC
VE
VCC
VE
= 5.5 V
= 0.8 V
=2.2 V
= 70 ns
= 100 ns
=5.5 V
= VCC - 0.2 V
= 5.5 V
= 2.2 V
70
65
50
10
mA
mA
µA
mA
Output High Voltage
Output Low Volt age
VOH
VOL
VCC
IOH
VCC
IOL
= 4.5 V
=-1.0 mA
=4.5 V
=3.2 mA
2.4
0.4
V
V
Input High Leakage Current
Input Low Leakage Curren t
IIH
IIL
VCC
VIH
VCC
VIL
= 5.5 V
= 5.5 V
= 5.5 V
= 0 V -2
2µA
µA
Output High Current
Output Low Current
IOH
IOL
VCC
VOH
VCC
VOL
=4.5 V
=2.4 V
=4.5 V
=0.4 V 3,2
-1 mA
mA
Output Leakage Current
High at Three-State Outputs
Low at Three-S tate Output s
IOHZ
IOLZ
VCC
VOH
VCC
VOL
=5.5 V
=5.5 V
=5.5 V
=0 V -2
2µA
µA
U62256
November 01, 2001
4
Switching Characteristics
Read Cycle Symbol 07 10 Unit
Alt. IEC Min. Max. Min. Max.
Read Cycle Time tRC tcR 70 100 ns
Address Access Time to Data Valid t AA ta(A) 70 100 ns
Chip Enable Access Time to Data Valid tACE ta(E) 70 100 ns
Output Enable A ccess Time to Data Valid tOE ta(G) 35 45 ns
E HIG H to O u tp ut in H i g h - Z tHZCE tdis(E) 25 35 ns
G HIGH to Output in High-Z tHZOE tdis(G) 25 35 ns
E LOW to Output in Low-Z tLZCE ten(E) 55ns
G LOW to Output in Low-Z tLZOE ten(G) 00ns
Output Hold Time from Address Change tOH tv(A) 55ns
Switching Characteri stics
Write Cycle Symbol 07 10 Unit
Alt. IEC Min. Max. Min. Max.
Write Cycle Time tWC tcW 70 100 ns
Write Pulse Width tWP tw(W) 55 70 ns
Write Pulse Width Setup Time tWP tsu(W) 55 70 ns
Address Setup Time tAS tsu(A) 00ns
Address Valid to End of W rite tAW tsu(A-WH) 65 80 ns
Chip Enable Setup T ime tCW tsu(E) 65 80 ns
Pulse Width Chip Enable to End of Write tCW tw(E) 65 80 ns
Da ta Setup Tim e tDS tsu(D) 30 35 ns
Data Hold Time tDH th(D) 00ns
Address Hold from End of Write tAH th(A) 00ns
W LOW to Output in High-Z tHZWE tdis(W) 25 35 ns
G HIGH to Output in High-Z tHZOE tdis(G) 25 35 ns
W HIGH to O u t p u t in L o w - Z tLZWE ten(W) 00ns
G LOW to Output in Low-Z tLZOE ten(G) 00ns
U62256
November 01, 2001 5 5
Data Retention Mode
E-Controlled
Data Retention
4.5 V
tDR trec
VCC
E
VCC(DR) ≥ 2 V
0 V
2.2 V
2.2 V
VCC(DR) - 0.2 V ≤ VE(DR) ≤ VCC(DR) + 0.3 V
Data Retention
Characteristics Symbol
Alt. IEC Conditions Min. Typ. Max. Unit
Data Retention Supply Voltage VCC(DR) 25.5V
Data Retention Supply Current ICC(DR) VCC(DR) = 3 V
VE = V
CC(DR)-0.2V
30 µA
Data Retention Setup Tim e tCDR tsu(DR) See Dat a Retention
W aveforms (above) 0ns
O perati ng Recovery Time tRtrec tcR ns
Te st Conf ig uratio n fo r Fu nc ti onal Check
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
VIH
VIL
VSS
VCC
5 V
960
30 pF1)
VO
Input level according to the
relevant test measu remen t
Simultaneous measurement
of all 8 output pins
E
W
G
1)In meas urem ent of tdis(E), tdis(W), tdis(G), t en(E), t en(W), ten(G) the capacitance is 5 pF.
510
U62256
November 01, 2001
6
Capacitance Conditions Symbol Min. Max. Unit
Input Capacitance VCC
VI
f
Ta
= 5.0 V
= VSS
= 1 MHz
= 25 °C
CI-7pF
Out put Capacitance CO-7pF
IC Code Numbers
Example
Type
Package Access Ti me
S = SOP 28 (330 mil) 07 = 70 ns
10 = 100 ns
Operating Temperature Ranges
C = 0 to 70 °C
K = -40 to 85 °C
SU62256 07K
All pins not under test must be connected with ground by capacitors.
The date of manufacture is given by the last 4 digits of the mark, the first 2 digits indicating the year, and the last 2
digits the calendar week.
U62256
November 01, 2001 7 7
tdis(G)
tdis(E)
tcR
Previ ous Data Va li d Output Data Val id
Ou tp ut Data Va li d
Address Valid
Address Valid
tsu(A)
High-Z
ten(E)
ten(G)
ta(G)
ta(E)
Read Cycle 1: Ai-controlled (during Read Cycle : E = G = VIL, W = VIH)
Read Cycle 2: G-, E-control l e d (during R ea d Cycle: W = VIH)
ta(A)
tcR
tv(A)
Ai
DQi
Output
Ai
E
G
DQi
Output
U62256
November 01, 2001
8
Wr ite Cycle1: W-controlled
th(D)
Ai
E
W
DQi
Input
G
DQi
Output
tcW
tsu(E) th(A)
tw(W)
tsu(A) tsu(D)
tdis(W) ten(W)
Address Valid
Input Data V a lid
High-Z
tsu(A-WH)
Write Cycle 2: E-controlled
Input Data Valid
tsu(A)
th(D)
Ai
E
W
DQi
Input
G
DQi
Output
tcW
tw(E)
th(A)
tsu(W)
tsu(D)
tdis(W)
t
en(E)
High-Z
Ad dres s Va li d
tdis(G)
L- to H- le vel undefined H- to L-le ve l
The informati on describes the type of component and shall not be considered as assured characteristics.Terms of
delivery and rights to chang e design reserved .
U62256
Zent rum Mikroelekt ronik Dresden AG
Grenzstr aße 28 • D-01109 Dr esden • P. O. B. 80 01 34 • D-01101 Dresden • Germany
Phone: +49 351 8822 306 • Fax: +49 351 8822 337 • Emai l: sales@zmd.de • h ttp:/ /w w w.z m d . d e
November 01, 2001
LIFE SUP P O RT PO LI C Y
ZMD products are not designed, intended, or authorized for use as components in systems intended for surgical
implant into the body, or other applications intended t o support or sustain life, or for any other appli cation in which the
failure of the ZM D product could create a situation where personal injury or d eath may occur.
Components used in life-support devices or systems must be expressly authorized by ZMD for such purpose.
LIMITED WARRANTY
The informati on in this document has been carefully checked and is believed to be reliable. However Zentrum Mik ro-
elektronik Dresden AG (ZMD) makes no guarantee or warranty concerning the accuracy of said information and s hall
not be responsible for any loss or damage of whatever nature resulting from t he use of, or reliance upon it. The infor-
mation in this document describes th e type of component and sh all not be considered as assured charac teristics.
ZMD does not guarantee that the use of any information contained herein will not infringe upon the patent, trade-
mark, copyright, mask work right or other rights of third parties, and no patent or licence is implied hereby. This docu-
ment does not in any way extent ZMD’s warranty on any product beyond that set forth in its standard terms and
conditions of sale.
ZMD reserves terms of delivery and reserves the right to make changes in the products or specifications, or both,
presented in this publication at any time and without notice.
