3-Channel, Integrated Ultralow Power Solution
with Dual Buck Regulators and Load Switch
Data Sheet
ADP5310
FEATURES
Wide input voltage range: 2.7 V to 15.0 V
700 nA quiescent current when EN1 = SYNC/MODE = low
±1.5% output accuracy over full temperature range in PWM mode
600 kHz (or 1.2 MHz) switching frequency with optional
synchronization input from 400 kHz to 1.4 MHz
Channel 1: 800 mA buck regulator
Automatic PSM/PWM or forced PWM mode via factory fuse
100% duty cycle operation mode
Adjustable/fixed output options via factory fuse
Power-good flag
Channel 2: ultralow power buck regulator
Selectable hysteresis or PWM operation mode
Output current up to 50 mA in hysteresis mode, 300 mA in
PWM mode with 100% duty cycle operation mode
Low noise at 0.8 V reference in PWM mode
Adjustable/fixed output voltage options via factory fuse
Channel 3: high-side load switch
Low RDS(ON) of 494 mΩ at VOUT3 = 2.5 V
Quick output discharge (QOD) option
UVLO, OCP, and TSD protection
16-lead TSSOP_EP package
−40°C to +125°C operational junction temperature
APPLICATIONS
Energy (gas and water) metering
Portable and battery-powered equipment
Medical applications
Keep-alive power supplies
TYPICAL APPLICATION CIRCUIT
SW1
PGND1
FB1
R1
R2
C3
10µF
MLCC
L1
4.7µH V
OUT1
SW2
PGND2
FB2
C4
10µF
MLCC
L2
4.7µH V
OUT2
VOUT3 V
OUT3
ADP5310
EN1
FROM MCU PWRGD
TO MCU
FROM MCU
PVIN1
PVIN2
NC
EN3
SYNC/
MODE
CHANNEL 1
BUCK
REGULATOR
(800mA)
CHANNEL 3
LOAD
SWITCH
CHANNEL 2
ULTRALOW
POWER
BUCK
REGULATOR
(50mA/300mA)
C1
10µF
MLCC
– +– +
2 × LiMnO2
V
IN
=
2.7V TO 15V
AGNDVREG
C6
1µF
C5
220nF
MLCC
13008-001
Figure 1.
GENERAL DESCRIPTION
The ADP5310 combines dual buck regulators and one load switch
in a 16-lead TSSOP_EP package that meets demanding perfor-
mance and board space requirements. The device enables direct
connection to a wide input voltage range of 2.7 V to 15.0 V, allowing
the use of multiple alkaline/NiMH or lithium cells and other
power sources.
The buck regulator in Channel 1 uses a current mode, constant
frequency pulse-width modulation (PWM) control scheme for
excellent stability and transient performance, which provides up
to 800 mA of output current. The automatic PWM/pulse skipping
mode (PSM) control scheme achieves excellent efficiency in light
output current. A power-good signal indicates that the output
of Channel 1 is within 92% of its nominal value.
An ultralow power buck regulator is integrated in Channel 2 with
the SYNC/MODE pin to control its operation mode. When
SYNC/MODE is set to low, the buck regulator operates in hysteresis
mode, which draws only 700 nA of quiescent current to regulate
the output under zero load and provides up to 50 mA of output
current. Hysteresis mode helps achieve excellent efficiency at less
than 1 mW and can work as a keep-alive power supply in a battery-
powered system. When the SYNC/MODE pin is set to high, the
buck regulator switches to a traditional constant frequency PWM
control scheme to provide low output ripple for noise sensitive
applications, and the buck regulator provides up to 300 mA of
output current in PWM mode.
Channel 3 integrates a high-side load switch that operates from
1.65 V to 5.5 V with its input connected to the output of Channel 2.
The load switch provides power domain isolation and extends
battery operation time.
Other key safety features of the ADP5310 include overcurrent
protection (OCP), thermal shutdown (TSD), and input under-
voltage lockout (UVLO). The ADP5310 is rated for the −40°C
to +125°C junction temperature range.
Rev. A Document Feedback
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responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
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Technical Support www.analog.com
ADP5310 Data Sheet
Rev. A | Page 2 of 28
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
Typical Application Circuit ............................................................. 1
General Description ......................................................................... 1
Revision History ............................................................................... 2
Detailed Functional Block Diagram .............................................. 3
Specifications ..................................................................................... 4
Buck Regulators and Load Switch Specifications ..................... 5
Absolute Maximum Ratings ............................................................ 7
Thermal Resistance ...................................................................... 7
ESD Caution .................................................................................. 7
Pin Configuration and Function Descriptions ............................. 8
Typical Performance Characteristics ............................................. 9
Theory of Operation ...................................................................... 18
Buck Regulator Operation Modes ............................................ 18
Adjustable and Fixed Output Voltages .................................... 19
Undervoltage Lockout (UVLO) ............................................... 19
Enable and Shutdown Features ................................................. 19
Internal Linear Regulator (VREG) ........................................... 19
Oscillator and Synchronization ................................................ 19
Current Limit .............................................................................. 19
Short-Circuit Protection ............................................................ 19
Soft Start ...................................................................................... 19
Startup with Precharged Output .............................................. 19
100% Duty Operation ................................................................ 19
Active Discharge ......................................................................... 20
Power-Good Function ............................................................... 20
Load Switch ................................................................................. 20
Thermal Shutdown .................................................................... 20
Applications Information .............................................................. 21
External Component Selection ................................................ 21
Selecting the Inductor ................................................................ 21
Output Capacitor........................................................................ 21
Input Capacitor ........................................................................... 21
Adjustable Output Voltage Programming .............................. 22
Efficiency ..................................................................................... 22
Recommended Buck External Components .......................... 22
Capacitor Selection .................................................................... 24
Circuit Board Layout Recommendations ............................... 24
Typical Application Circuits .......................................................... 25
Factory Programmable Options ................................................... 26
Outline Dimensions ....................................................................... 28
Ordering Guide .......................................................................... 28
REVISION HISTORY
11/2016—Rev. 0 to Rev. A
Changes to Ordering Guide .......................................................... 28
4/2015—Revision 0: Initial Version
Moved Circuit Board Layout Recommendations Section
and Figure 57................................................................................... 24
Data Sheet ADP5310
Rev. A | Page 3 of 28
DETAILED FUNCTIONAL BLOCK DIAGRAM
VREG
SYNC/MODE
1.2V
LDO
2.55V
2.4V
UVLO
PVIN2
PVIN1
BAND GAP
BIAS
AND
CONTROL
LOGIC S/H
OSC
1.2V
0.4V
CH1
CH2
1.2MHz
OSC
CH1
CH2
CH2
SYNC
P_ILIMIT
1.2A
IMIN N_ILIMIT
PWM
0.808V
0.8V
PSM
SW1
FB1
PVIN1
CONTROL
LOGIC
DRIVER
VIN
DRIVER
VIN
–0.5A ( P WM)
0A (PSM)
RDS(ON) × kr
VIN
300mA/kr
RDS(ON) × kr
VIN
EN1 0.4V
SOFT
START
0.8V
V TO I
PWRGD 0.736V
0.696V
FB1
CHANNEL 1
PGND1
P_ILIMIT
0.6A
IMIN N_ILIMIT
PWM
0.808V
0.8V
PSM
SW2
FB2
VOUT3
PVIN2
CONTROL
LOGIC
DRIVER
VIN
DRIVER
VIN
–0.5A ( P WM)
0A (PSM)
RDS(ON) × kr
VIN
300mA/kr
RDS(ON) × kr
VIN
SOFT
START
0.8V
V TO I
CHANNEL 2
CHANNEL 3
PGND2
EN3
1.2V
0.4V
DRIVER
ADP5310
13008-002
1.2V
SLOPE
COMPENSATION
SLOPE
COMPENSATION
Figure 2.
ADP5310 Data Sheet
Rev. A | Page 4 of 28
SPECIFICATIONS
VIN = 6 V, VREG = 3.9 V, TJ = −40°C to +125°C for minimum and maximum specifications, and TA = 25°C for typical specifications, unless
otherwise noted.
Table 1.
Parameter Symbol Min Typ Max Unit Test Conditions/Comments
INPUT SUPPLY VOLTAGE RANGE VIN 2.7 15.0 V PVIN1 and PVIN2 pins
QUIESCENT CURRENT PVIN1 and PVIN2 pins
Operating Quiescent Current
Standby Operation IQ1 700 1850 nA −40°C ≤ TJ ≤ +85°C, EN1 =
SYNC/MODE = low
700 3800 nA −40°C ≤ TJ ≤ +125°C, EN1 =
SYNC/MODE = low
PWM Operation
I
Q3
1.4
1.65
EN1 = SYNC/MODE = high
UNDERVOLTAGE LOCKOUT UVLO PVIN2 pin
UVLO Threshold
Rising
V
UVLO_RISING
2.55
2.75
Falling VUVLO_FALLING 2.15 2.40 V
Hysteresis VHYS 150 mV
OSCILLATOR CIRCUIT
For Channel 1 and Channel 2,
PWM mode
Switching Frequency fSW 1050 1200 1350 kHz
525 600 675 kHz
Feedback (FB) Threshold of
Frequency Fold
VOSC_FOLD 0.3 V
SYNCHRONIZATION THRESHOLD
SYNC Clock Range SYNCCLOCK 400 800 kHz fSW = 600 kHz
SYNC
CLOCK
800
1400
f
SW
= 1.2 MHz
SYNC High Level Threshold SYNCHIGH 1.2 V
SYNC Low Level Threshold SYNCLOW 0.4 V
SYNC Pulse On Time Range SYNCON 80 1/fSW − 150 ns
EN1 and EN3
Input High Level Threshold VIH 1.2 V
Input Low Level Threshold VIL 0.4 V
Input Leakage Current ILEAKAGE 300 nA
INTERNAL POWER GOOD
Internal Power-Good Threshold VPWRGD(RISE) 88 92 96 %
Internal Power-Good Hysteresis VPWRGD(HYS) 5 %
Internal Power-Good Rising Delay tPWRGD_RISE 16 Clock
cycles
Internal Power-Good Falling Delay tPWRGD_FALL 1 µs
Leakage Current for PWRGD Pin IPWRGD_LEAKAGE 10 40 nA
Output Low Voltage for PWRGD Pin VPWRGD_LOW 50 100 mV IPWRGD = 100 µA
INTERNAL REGULATOR
VREG Output Voltage VREG 3.6 3.9 4.2 V
THERMAL SHUTDOWN
Threshold TSHDN 135 °C
Hysteresis THYS 15 °C
Data Sheet ADP5310
Rev. A | Page 5 of 28
BUCK REGULATORS AND LOAD SWITCH SPECIFICATIONS
VIN = 6 V, VREG = 3.9 V, TJ = −40°C to +125°C for minimum and maximum specifications, and TA = 25°C for typical specifications, unless
otherwise noted.
Table 2.
Parameter Symbol Min Typ Max Unit Test Conditions/Comments
CHANNEL 1 SYNC BUCK REGULATOR
Supply Voltage Range VIN1 2.7 15.0 V PVIN1 pin
Rating Output Current IOUT 800 mA
FB1 Pin in PWM Mode
Fixed Output Options VOUT1_FIX 1.2 5.0 V Factory trim, 3 bits (adjustable,
1.2 V, 1.5 V, 1.8 V, 2.5 V, 2.85 V,
3.3 V, 5.0 V)
Fixed Output Accuracy VFB1_FIX −1.5 +1.5 %
Adjustable Output Voltage Range VOUT1_ADJ 0.8 PVIN1 V Adjustable voltage option
Adjustable Feedback Voltage VFB1 0.800 V Adjustable voltage option
Adjustable Feedback Voltage
Accuracy
VFB1_ADJ −0.55 +0.55 % TJ = 25°C
−1.2 +1.0 % 0°C ≤ TJ ≤ 85°C
−1.5 +1.5 % −40°C ≤ TJ ≤ +125°C
FB1 Pin in PSM Mode
Threshold Accuracy from Active
Mode to Skip Mode
VFB1_PSM −1.5 +1.5 %
Hysteresis of Threshold Accuracy
from Active Mode to Skip Mode
V
FB1_PSM(PSM)
1
%
Feedback Bias Current IFB1 0.1 µA Adjustable voltage option
SW1 Pin
High-Side Power FET On
Resistance
RDS(ON)1H 472 690 mΩ Pin to pin measurement
Low-Side Power FET On
Resistance
RDS(ON)1L 438 725 mΩ Pin to pin measurement
Current-Limit Threshold ITH(ILIM1) 1000 1260 1450 mA
Minimum On Time tMIN_ON1 38 70 ns
Soft Start Time tSS1 350 µs Factory trim, 1 bit (350 µs, 2800 µs)
C
OUT
Discharge Switch On Resistance
R
DIS1
287
Ω
CHANNEL 2 SYNC BUCK REGULATOR
Supply Voltage Range
V
IN2
2.7
15.0
V
PVIN2 pin
Rating Output Current
Hysteresis Mode IOUT_HYS 50 mA
PWM Mode IOUT_PWM 300 mA
Mode Transition
Transition Delay from Hysteresis
Mode to PWM Mode
THYS_TO_PWM 8 Clock
cycles
SYNC/MODE goes logic high
from logic low
FB2 Pin in PWM Mode
Fixed Output Options VOUT2_FIX 1.2 5.0 V Factory trim, 8 bits (adjustable,
1.2 V to 3.6 V in 50 mV steps, and
3.6 V to 5.0 V in 100 mV steps)
Fixed Output Accuracy
V
FB2_FIX
−1.5
+1.5
%
Adjustable Output Voltage Range VOUT2_ADJ 0.8 PVIN2 V Adjustable voltage option (note
that Channel 3 has no use in this
setting)
Adjustable Feedback Voltage VFB2 0.800 V Adjustable voltage option
ADP5310 Data Sheet
Rev. A | Page 6 of 28
Parameter
Symbol
Min
Typ
Max
Unit
Test Conditions/Comments
Adjustable Feedback Voltage
Accuracy
VFB2_ADJ −0.55 +0.55 % TJ = 25°C
−1.2 +1.0 % 0°C ≤ TJ ≤ 85°C
−1.5
+1.5
%
−40°C ≤ T
J
≤ +125°C
Feedback Bias Current IFB2_ADJ 15 200 nA Adjustable voltage option
Feedback Resistor to GND IFB2_FIX 57 MΩ Fixed voltage option
FB2 Pin in Hysteresis Mode
Threshold Accuracy from Active
Mode to Standby Mode
VFB2_HYS −1.5 +1.5 %
Hysteresis of Threshold Accuracy
from Active Mode to Standby
Mode
V
FB2_HYS(HYS)
1
%
SW2 Pin
High-Side Power FET
On Resistance
RDS(ON)2H 868 1250 mΩ Pin to pin measurement
Low-Side Power FET
On Resistance
RDS(ON)2L 893 1360 mΩ Pin to pin measurement
Current-Limit Threshold in PWM
Mode
ITH(ILIM2) 450 600 730 mA SYNC/MODE = high
Peak Inductor Current in
Hysteresis Mode
IL2 300 mA SYNC/MODE = low
Minimum On Time tMIN_ON2 36 70 ns
Soft Start Time tSS2 350 µs Factory trim, 1 bit (350 µs,
2800 µs)
COUT Discharge Switch On Resistance RDIS2 282 Ω
CHANNEL 3 LOAD SWTICH
Supply Voltage Range VIN3 1.65 5.5 V FB2 pin
FB2 to VOUT3 On Resistance RDS(ON)3 382 550 mΩ VOUT3 = 5.0 V, ILOAD3 = 50 mA
430 615 mΩ VOUT3 = 3.3 V, ILOAD3 = 50 mA
494 700 mΩ VOUT3 = 2.5 V, ILOAD3 = 50 mA
VOUT3 TIME
Turn On Rise Time tRISE3 12 16 µs VOUT3 = 2.5 V, CLOAD3 = 1 µF, factory
trim, 2 bits (3 µs, 12 µs, 48 µs,
192 µs)
COUT Discharge Switch On Resistance RDIS3 286 Ω
Data Sheet ADP5310
Rev. A | Page 7 of 28
ABSOLUTE MAXIMUM RATINGS
Table 3.
Parameter Rating
PVIN1, PVIN2 to PGNDx −0.3 V to +17 V
SW1, SW2 to PGNDx
−0.3 V to PVIN + 0.3 V
VREG to PGNDx −0.3 V to +6 V
EN1, EN3, SYNC/MODE, PWRGD to
AGND
−0.3 V to +17 V
FB1, FB2 to AGND −0.3 V to +6 V
VOUT3 to PGNDx −0.3 V to +6 V
PGND1, PGND2 to AGND −0.3 V to +0.3 V
Storage Temperate Range −65°C to +150°C
Operational Junction Temperature
Range
−40°C to +125°C
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
THERMAL RESISTANCE
θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages.
Table 4. Thermal Resistance
Package Type θJA θJC Unit
16-Lead TSSOP_EP 39.14 2.59 °C/W
ESD CAUTION
ADP5310 Data Sheet
Rev. A | Page 8 of 28
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
PVIN2
NC
SW2
VOUT3
FB2
PGND2
PVIN1
PGND1
EN1
FB1
VREG
EN3 AGND
SYNC/MODE
PWRGD
SW1
ADP5310
TOP VIEW
(No t t o Scale)
NOTES
1. NC = NO CONNECT .
2. SOLDER THE EXPOSED PAD TO A LARGE EXTERNAL
COPP E R GROUND P LANE UNDERNE ATH THE IC FO R
THERMAL DISSIPATION.
13008-003
Figure 3. Pin Configuration
Table 5. Pin Function Descriptions
Pin No. Mnemonic Description
1 PVIN1 Power Input of Channel 1. This pin must be connected to PVIN2.
2 PVIN2 Power Input of Channel 2 and Internal Linear Regulator.
3
NC
No Connect. This pin is not internally connected. Leave this pin floating.
4 SW2 Switching Node Output of Channel 2.
5 PGND2 Power Ground of Channel 2.
6 FB2 Feedback Sensing Input of Channel 2.
7 VOUT3 Power Output of Channel 3.
8 EN3 Enable Input of Channel 3.
9 AGND Analog Ground.
10 VREG Output of the Internal Linear Regulator. Connect a 1.0 µF ceramic capacitor between this pin and ground.
11 SYNC/MODE Synchronization Input Pin (SYNC). To synchronize the switching frequency of the device to an external clock,
connect this pin to an external clock with a frequency from 400 kHz to 1.4 MHz.
PWM or Hysteresis Mode Selection Pin of Channel 2 (MODE). When this pin is logic high, the regulator operates
in PWM mode. When this pin is logic low, the regulator operates in hysteresis mode.
12 PWRGD Power-Good Signal Output. This open-drain output is the power-good signal of Channel 1.
13 FB1 Feedback Sensing Input of Channel 1.
14 EN1 Enable Input of Channel 1.
15 PGND1 Power Ground of Channel 1.
16
SW1
Switching Node Output of Channel 1.
EPAD Exposed Pad. Solder the exposed pad to a large external copper ground plane underneath the IC for thermal
dissipation.
Data Sheet ADP5310
Rev. A | Page 9 of 28
TYPICAL PERFORMANCE CHARACTERISTICS
VIN = 6 V, V OUT1 = 4 V, V OUT2 = 3 V, L1 = 4.7 µH, L2 = 6.8 µH, CIN = COUT = 10 μF, fSW = 1.2 MHz, TA = 25°C, unless otherwise noted.
90
0
10
20
30
40
50
60
70
80
0.1 110 100 1000
EF FICI E NCY ( %)
LO AD CURRE NT (mA)
V
IN
= 5V
V
IN
= 7.2V
V
IN
= 9V
V
IN
= 12V
V
IN
= 15V
13008-004
Figure 4. Channel 1 Auto PSM/PWM Efficiency vs. Load Current, VOUT1 = 1.2 V
90
100
10
20
30
40
50
60
70
80
0.1 110 100 1000
EF FICI E NCY ( %)
LOAD CURRENT ( mA)
VIN = 5V
VIN = 7.2V
VIN = 9V
VIN = 12V
VIN = 15V
13008-005
Figure 5. Channel 1 Auto PSM/PWM Efficiency vs. Load Current, VOUT1 = 2.5 V
90
100
20
30
40
50
60
70
80
0.1 110 100 1000
EF FICI E NCY ( %)
LOAD CURRENT ( mA)
V
IN
= 7.2V
V
IN
= 9V
V
IN
= 12V
V
IN
= 15V
13008-006
Figure 6. Channel 1 Auto PSM/PWM Efficiency vs. Load Current, VOUT1 = 5 V
90
100
10
0
20
30
40
50
60
70
80
0.1 110 100 1000
EF FICI E NCY ( %)
LOAD CURRENT ( mA)
V
IN
= 5V
V
IN
= 7.2V
V
IN
= 9V
V
IN
= 12V
V
IN
= 15V
13008-007
Figure 7. Channel 1 Auto PSM/PWM Efficiency vs. Load Current, VOUT1 = 1.8 V
90
100
10
20
30
40
50
60
70
80
0.1 110 100 1000
EF FICI E NCY ( %)
LOAD CURRENT ( mA)
V
IN
= 5V
V
IN
= 7.2V
V
IN
= 9V
V
IN
= 12V
V
IN
= 15V
13008-008
Figure 8. Channel 1 Auto PSM/PWM Efficiency vs. Load Current, VOUT1 = 3.3 V
0200 400 600 800100 300 500 700
90
0
10
20
30
40
50
60
70
80
EF FICI E NCY ( %)
LO AD CURRE NT (mA)
VIN = 5V
VIN = 7.2V
VIN = 9V
VIN = 12V
13008-009
Figure 9. Channel 1 PWM Efficiency vs. Load Current, VOUT1 = 1.2 V
ADP5310 Data Sheet
Rev. A | Page 10 of 28
90
100
10
0
20
30
40
50
60
70
80
0200 400 600 800100 300 500 700
EF FICI E NCY ( %)
LOAD CURRENT ( mA)
VIN = 5V
VIN = 7.2V
VIN = 9V
VIN = 12V
VIN = 15V
13008-010
Figure 10. Channel 1 PWM Efficiency vs. Load Current, VOUT1 = 1.8 V
90
100
10
0
20
30
40
50
60
70
80
0200 400 600 800100 300 500 700
EF FICI E NCY ( %)
LOAD CURRENT ( mA)
V
IN
= 5V
V
IN
= 7.2V
V
IN
= 9V
V
IN
= 12V
V
IN
= 15V
13008-011
Figure 11. Channel 1 PWM Efficiency vs. Load Current, VOUT1 = 3.3 V
80
10
15
20
25
30
35
40
45
50
55
60
65
70
75
0.001 0.01 0.1 110 100
EF FICI E NCY ( %)
LOAD CURRENT ( mA)
V
IN
= 5V
V
IN
= 7.2V
V
IN
= 9V
V
IN
= 12V
13008-012
Figure 12. Channel 2 Hysteresis Efficiency vs. Load Current, VOUT2 = 1.2 V
90
100
10
0
20
30
40
50
60
70
80
0200 400 600 800100 300 500 700
EF FICI E NCY ( %)
LOAD CURRENT ( mA)
VIN = 5V
VIN = 7.2V
VIN = 9V
VIN = 12V
VIN = 15V
13008-013
Figure 13. Channel 1 PWM Efficiency vs. Load Current, VOUT1 = 2.5 V
90
100
10
0
20
30
40
50
60
70
80
0200 400 600 800100 300 500 700
EF FICI E NCY ( %)
LOAD CURRENT ( mA)
V
IN
= 7.2V
V
IN
= 9V
V
IN
= 12V
V
IN
= 15V
13008-014
Figure 14. Channel 1 PWM Efficiency vs. Load Current, VOUT1 = 5 V
80
85
10
15
20
25
30
35
40
45
50
55
60
65
70
75
0.001 0.01 0.1 110 100
EF FICI E NCY ( %)
LOAD CURRENT ( mA)
V
IN
= 5V
V
IN
= 7.2V
V
IN
= 9V
V
IN
= 12V
V
IN
= 15V
13008-015
Figure 15. Channel 2 Hysteresis Efficiency vs. Load Current, VOUT2 = 1.8 V
Data Sheet ADP5310
Rev. A | Page 11 of 28
80
85
90
95
15
20
25
30
35
40
45
50
55
60
65
70
75
0.001 0.01 0.1 110 100
EF FICI E NCY ( %)
LOAD CURRENT ( mA)
VIN = 5V
VIN = 7.2V
VIN = 9V
VIN = 12V
VIN = 15V
13008-016
Figure 16. Channel 2 Hysteresis Efficiency vs. Load Current, VOUT2 = 2.5 V
80
85
90
95
30
35
40
45
50
55
60
65
70
75
0.001 0.01 0.1 110 100
EF FICI E NCY ( %)
LOAD CURRENT ( mA)
VIN = 7.2V
VIN = 9V
VIN = 12V
VIN = 15V
13008-017
Figure 17. Channel 2 Hysteresis Efficiency vs. Load Current, VOUT2 = 5 V
90
0
10
20
30
40
50
60
70
80
050 100 150 200 250 300
EF FICI E NCY ( %)
LO AD CURRE NT (mA)
V
IN
= 5V
V
IN
= 7.2V
V
IN
= 9V
V
IN
= 12V
V
IN
= 15V
13008-018
Figure 18. Channel 2 PWM Efficiency vs. Load Current, VOUT2 = 1.8 V
80
85
90
95
30
25
20
35
40
45
50
55
60
65
70
75
0.001 0.01 0.1 110 100
EF FICI E NCY ( %)
LOAD CURRENT ( mA)
VIN = 5V
VIN = 7.2V
VIN = 9V
VIN = 12V
VIN = 15V
13008-019
Figure 19. Channel 2 Hysteresis Efficiency vs. Load Current, VOUT2 = 3.3 V
0
10
20
30
40
50
60
70
80
050 100 150 200 250 300
EF FICI E NCY ( %)
LOAD CURRENT ( mA)
VIN = 5V
VIN = 7.2V
VIN = 9V
VIN = 12V
VIN = 15V
13008-020
Figure 20. Channel 2 PWM Efficiency vs. Load Current, VOUT2 = 1.2 V
050 100 150 200 250 300
90
100
10
0
20
30
40
50
60
70
80
EF FICI E NCY ( %)
LOAD CURRENT ( mA)
V
IN
= 5V
V
IN
= 7.2V
V
IN
= 9V
V
IN
= 12V
V
IN
= 15V
13008-021
Figure 21. Channel 2 PWM Efficiency vs. Load Current, VOUT2 = 2.5 V
ADP5310 Data Sheet
Rev. A | Page 12 of 28
100
0
10
20
30
40
50
60
70
80
90
050 100 150 200 250 300
EF FICI E NCY ( %)
LO AD CURRE NT (mA)
V
IN
= 5V
V
IN
= 7.2V
V
IN
= 9V
V
IN
= 12V
V
IN
= 15V
13008-022
Figure 22. Channel 2 PWM Efficiency vs. Load Current, VOUT2 = 3.3 V
2500
0
500
1000
1500
2000
357911 13 15
QUIESCENT CURRENT, HYSTERESIS MO DE (nA)
V
IN
(V)
–40°C
+25°C
+85°C
+125°C
13008-023
Figure 23. Quiescent Current, Hysteresis Mode vs. VIN, EN1 = SYNC/MODE = Low
806
794
796
798
800
802
804
–40 025 85 125
FEE DBACK V OLTAGE ( mV )
TEMPERATURE (°C)
ACTIVE MODE TO SKIP MODE
SKIP MODE TO ACTIVE MODE
13008-024
Figure 24. Channel 1 Feedback Voltage of PSM Mode vs. Temperature
100
0
10
20
30
40
50
60
70
80
90
050 100 150 200 250 300
EF FICI E NCY ( %)
LO AD CURRE NT (mA)
V
IN
= 6V
V
IN
= 7.2V
V
IN
= 9V
V
IN
= 12V
V
IN
= 15V
13008-025
Figure 25. Channel 2 PWM Efficiency vs. Load Current, VOUT2 = 5 V
1.8
1.0
1.1
1.2
1.3
1.4
1.5
1.6
1.7
2 4 6 8 10 12 14 16
QUI E S CE NT CURRENT , PW M M ODE (mA)
V
IN
(V)
–40°C
+25°C
+125°C
13008-026
Figure 26. Quiescent Current, PWM Mode, EN1 = SYNC/MODE = High
802
796
797
798
799
800
801
–40 025 85 125
FE EDBACK V OLTAGE ( mV )
TEMPERATURE (°C)
FB2
FB1
13008-027
Figure 27. Channel 2 Feedback Voltage of PWM Mode vs. Temperature
Data Sheet ADP5310
Rev. A | Page 13 of 28
812
794
796
800
804
808
798
802
806
810
–40 025 85 125
FE EDBACK V OLTAGE ( mV )
TEMPERATURE (°C)
ACTI V E M ODE T O ST ANDBY M ODE
STANDBY M ODE T O ACTIVE M ODE
13008-028
Figure 28. Channel 2 Feedback Voltage of Hysteresis Mode vs. Temperature
900
100
200
300
400
500
600
700
800
2 4 6 8 10 12 14 16
LOW -SI DE R
DS(ON)1L
(mΩ)
V
IN
(V)
–40°C
+25°C
+125°C
13008-029
Figure 29. Channel 1 Low-Side RDS(ON)1L vs. VIN
1600
200
400
600
800
1000
1200
1400
2 4 6 8 10 12 14 16
LOW -SI DE R
DS(ON)2L
(mΩ)
V
IN
(V)
–40°C
+25°C
+125°C
13008-030
Figure 30. Channel 2 Low-Side RDS(ON)2L vs. VIN
900
200
300
400
500
600
700
800
246810 12 14 16
HIG H-SIDE R
DS(ON)1H
(mΩ)
V
IN
(V)
–40°C
+25°C
+125°C
13008-031
Figure 31. Channel 1 High-Side RDS(ON)1H vs. VIN
1600
200
400
600
800
1000
1200
1400
2 4 6 8 10 12 14 16
HIG H-SIDE R
DS(ON)2H
(mΩ)
V
IN
(V)
–40°C
+25°C
+125°C
13008-032
Figure 32. Channel 2 High-Side RDS(ON)2H vs. VIN
900
100
200
300
400
500
600
700
800
1.5 2.5 3.5 4.5 5.5
LO AD S WITCH RDS(ON)3 (mΩ)
VIN (V)
–40°C
+25°C
+125°C
13008-033
Figure 33. Channel 3 Load Switch RDS(ON)3 vs. VIN
ADP5310 Data Sheet
Rev. A | Page 14 of 28
1300
1000
1050
1100
1250
1150
1200
–40 025 85 125
PEAK CURRENT LIMI T (A)
TEMPERATURE (°C)
13008-034
Figure 34. Channel 1 Peak Current Limit vs. Temperature
620
480
500
520
600
580
540
560
–40 025 85 125
PEAK CURRENT LIMI T (A)
TEMPERATURE (°C)
13008-035
Figure 35. Channel 2 Peak Current Limit vs. Temperature
2.68
2.28
2.32
2.40
2.48
2.60
2.36
2.44
2.56
2.52
2.64
–40 025 85 125
UVL O THRES HOLD ( V )
TEMPERATURE (°C)
RISING
FALLING
13008-036
Figure 36. UVLO Threshold, Rising and Falling, vs. Temperature
1300
1000
1050
1100
1150
1200
1250
4 6 8 10 12 14 16
PEAK CURRENT LIMI T (A)
V
IN
(V)
–40°C
+25°C
+125°C
13008-037
Figure 37. Channel 1 Peak Current Limit vs. VIN
640
460
480
500
520
540
580
620
560
600
4 6 8 10 12 14 16
PEAK CURRENT LIMI T (A)
V
IN
(V)
–40°C
+25°C
+125°C
13008-038
Figure 38. Channel 2 Peak Current Limit vs. VIN
1300
1050
1075
1100
1125
1150
1175
1225
1275
1200
1250
42 6 8 10 12 14 16
SW ITCHI NG FRE QUENCY ( kHz )
V
IN
(V)
–40°C
+25°C
+125°C
13008-039
Figure 39. Switching Frequency vs. VIN
Data Sheet ADP5310
Rev. A | Page 15 of 28
CH1 10.0mV BWCH2 5.00mV BW
CH3 10.0V CH4 5.00V M 1. 00µ s A CH3 4.80V
T 30.20%
1
2
4
3
TVOUT1 (AC)
SW1
VOUT2 (AC)
SW2
13008-040
Figure 40. Steady Waveform of PWM Mode
1
2
3
4
T
CH1 2.00V CH2 2.00V BW
CH3 2.00V BWCH4 2.00V BW
M 200µs A CH2 3.32V
T 50.00%
VOUT1
VOUT2
VOUT3
VIN
13008-041
Figure 41. Soft Start Waveform
1
3
4
T
CH1 5.00V BW
CH3 50.0mV BWCH4 200mA Ω BW
M 1. 00ms A CH1 7.20V
T 20.20%
VOUT2 (AC)
IL2
VIN
13008-042
Figure 42. Channel 2 Line Transient in Hysteresis Mode
1
3
4
T
CH1 5.00V
BW
CH3 50.0mV
BW
CH4 200mA Ω
BW
M 10. 0µ s A CH1 2.40V
T 20.80%
V
OUT2
(AC)
I
L2
SW2
13008-043
Figure 43. Channel 2 Output Ripple of Hysteresis Mode
1
2
3
T
CH1 5.00V
CH3 5.00V BW
CH2 5.00V M 1.00µs A CH3 3.00V
T 50.40%
SYNC/MODE
SW1
SW2
13008-044
Figure 44. Synchronization to 1 MHz
1
3
4
T
CH1 5.00V BW
CH3 10.0mV BWCH4 200mA Ω BW
M 1. 00ms A CH1 7.20V
T 20.20%
VOUT2 (AC)
IL2
VIN
13008-045
Figure 45. Channel 2 Line Transient in PWM Mode
ADP5310 Data Sheet
Rev. A | Page 16 of 28
1
2
4
T
CH1 5.00V BWCH2 20.0mV BW
CH4 500mA Ω BW
M 1. 00ms A CH1 7.20V
T 20.20%
VOUT1 (AC)
IL1
VIN
13008-046
Figure 46. Channel 1 Line Transient in PWM Mode
1
4
T
CH1 200mV BWCH4 500mA Ω
M 200µs A CH4 400mA
T 20.40%
VOUT1 (AC)
IOUT1 (AC)
13008-047
Figure 47. Channel 1 Load Transient (0.2 A to 0.6 A Load Step)
2
3
T
CH1 1.00V BW
CH3 5.00V CH2 1.00V BWM 400µs A CH1 3.40V
T 19.80%
SW1
VIN
VOUT1
13008-048
Figure 48. Channel 1 100% Duty Operation in PWM Mode
2
4
T
CH2 50.0mV
BW
CH4 20.0mA Ω
BW
M 100µs A CH4 –41.6mA
T 70.40%
I
OUT2
V
OUT2
(AC)
13008-049
Figure 49. Channel 2 Hysteresis Mode Load Transient (10 mA to 30 mA Load Step)
13008-050
CH2 10.0mV
BW
CH4 100mA Ω
BW
M 100µs A CH4 92.0mA
T 70.40%
2
4
T
V
OUT2
(AC)
I
OUT2
Figure 50. Channel 2 PWM Mode Load Transient (75 mA to 225 mA Load Step)
13008-051
1
3
T
CH1 1.00V
CH3 2.00V CH2 1.00V BWM 400µs A CH1 4.36V
T 39.40%
VOUT2
SW2
VIN
Figure 51. Channel 2 100% Duty Operation in PWM Mode
Data Sheet ADP5310
Rev. A | Page 17 of 28
13008-052
1
2
3
T
CH1 1.00V
CH3 2.00V CH2 1.00V BWM 400µs A CH1 4.36V
T 39.40%
VOUT2
SW2
VIN
Figure 52. Channel 2 100% Duty Operation in Hysteresis Mode
13008-053
1
2
4
T
CH1 2.00V
BW
CH2 5.00V
CH4 200mA Ω
BW
M 20. 0µ s A CH1 2.12V
T 30.40%
V
OUT2
(AC)
I
L2
SW2
Figure 53. Output Short
13008-054
CH1 5.00V CH2 5.00V
CH3 100mV CH4 500mA Ω BW
M 4. 00µ s A CH1 1.80V
T 20.40%
1
2
4
3
T
SYNC/MODE
IL2
VOUT2 (AC)
SW2
Figure 54. Mode Transition from Hysteresis Mode to PWM Mode
13008-055
1
2
4
T
CH1 2.00V
BW
CH2 5.00V
CH4 200mA Ω
BW
M 20. 0µ s A CH1 2.12V
T 50.20%
V
OUT2
I
L2
SW2
Figure 55. Output Short Recovery
ADP5310 Data Sheet
Rev. A | Page 18 of 28
THEORY OF OPERATION
The ADP5310 is an ultralow power management unit that
combines dual buck regulators and one load switch in a 16-lead
TSSOP_EP package to meet demanding performance and board
space requirements. The device enables direct connection to the
wide input voltage range of 2.7 V to 15 V, allowing the use of
multiple alkaline/NiMH or lithium cells and other power sources.
BUCK REGULATOR OPERATION MODES
PWM Mode
In PWM mode, the buck regulators in the ADP5310 operate at a
fixed frequency that is set by an internal oscillator. At the start
of each oscillator cycle, the high-side MOSFET switch turns on and
sends a positive voltage across the inductor. The inductor current
increases until the current sense signal exceeds the peak current
threshold of the inductor that turns off the high-side MOSFET
switch and turns on the low-side MOSFET. This places a negative
voltage across the inductor, causing the inductor current to reduce.
The low-side MOSFET stays on for the remainder of the cycle.
PSM Mode
The ADP5310 smoothly transitions to the variable frequency
PSM mode of operation when the load current decreases below
the pulse skipping threshold current, IMIN. For the peak current
of the inductor based on the input and output voltages, the design
of the IMIN value is based on the recommended inductor values.
Deviating from the recommended inductor value for a particular
output voltage results in shifting the PSM to PWM threshold
and may result in the device entering discontinuous mode (DCM).
As long as the required peak inductor current is above IMIN, the
regulator remains in PWM mode. As the load decreases, the PSM
circuitry prevents the peak inductor current from dropping below
the PSM peak current value. This circuitry causes the regulator
to supply more current to the output than the load requires,
resulting in the output voltage increasing and the output of the
internal compensation node of the error amplifier, VCOMP,
decreasing.
When the FB1 pin voltage rises above 1% of the nominal output
voltage and the VCOMP node voltage is below a predetermined
PSM threshold voltage level, the regulator enters skip mode.
While in skip mode, the high-side and low-side switches and a
majority of the circuitry are disabled to allow a low skip mode
quiescent current as well as high efficiency performance.
During skip mode, the output voltage decreases as the output
capacitor discharges into the load. Fixed frequency operation starts
when the FB1 voltage reaches the nominal output voltage. When
the load requirement increases past the IMIN peak current level,
the VCOMP node rises and the PWM control loop sets the duty
cycle. While the device is entering and exiting skip mode, the
PSM voltage ripple is larger than 1% because of the delay in the
comparators.
Hysteresis Mode
In hysteresis mode, the buck regulator in the ADP5310 charges
the output voltage slightly higher than its nominal output
voltage with PWM pulses by regulating the constant peak
inductor current. When the output voltage increases until the
output sense signal exceeds the hysteresis upper threshold, the
regulator enters standby mode. In standby mode, the high-side
and low-side MOSFET and a majority of the circuitry are
disabled to allow a low quiescent current as well as high
efficiency performance.
During standby mode, the output capacitor supplies the energy
into the load and the output voltage decreases until it falls below
the hysteresis comparator lower threshold. The buck regulator
wakes up and generates the PWM pulses to charge the output
again.
Because the output voltage occasionally enters standby mode
and then recovers, the output voltage ripple in hysteresis mode
is larger than the ripple in PWM mode.
Mode Selection
The buck regulator in Channel 1 uses the default automatic
PSM/PWM mode for excellent light load efficiency. Current
mode, constant frequency PWM mode can be programmed by
the factory fuse for excellent stability and transient performance.
The buck regulator in Channel 2 includes the SYNC/MODE pin,
allowing configuration in hysteresis mode or PWM mode.
When a logic high level is applied to the SYNC/MODE pin, the
buck regulator in Channel 2 is forced to operate in PWM mode.
In PWM mode, the regulator can supply up to 300 mA of output
current. The regulator can provide lower output ripple and
lower 1/f output noise in PWM mode, which benefits noise
sensitive applications.
When a logic low level is applied to the SYNC/MODE pin, the
buck regulator in Channel 2 is forced to operate in hysteresis
mode. In hysteresis mode, the regulator draws only 700 nA of
quiescent current to regulate the output under zero load, which
allows Channel 2 to act as a keep-alive power supply in a
battery-powered system. In hysteresis mode, the regulator
supplies up to 50 mA of output current with a relatively large
output ripple compared to PWM mode.
The user can alternate between hysteresis mode and PWM
mode during operation. The flexible configuration capability
during operation of the device enables efficient power
management to meet high efficiency and low output ripple
requirements when the system switches between active mode
and standby mode.
Data Sheet ADP5310
Rev. A | Page 19 of 28
ADJUSTABLE AND FIXED OUTPUT VOLTAGES
The buck regulator in Channel 1 provides adjustable and fixed
output voltage settings via the factory fuse. For the adjustable
output settings, use an external resistor divider to set the
desired output voltage via the feedback reference voltage (0.8 V
for Channel 1).
The buck regulator in Channel 2 provides adjustable and fixed
output voltage settings via the factory fuse as well. Because the
input source of the load switch in Channel 3 shares the FB2 pin,
the load switch in Channel 3 is unusable when Channel 2 is
configured in adjustable output mode via the factory fuse.
UNDERVOLTAGE LOCKOUT (UVLO)
The UVLO circuitry monitors the input voltage level of the
ADP5310 in the PVIN2 pin. When the input voltage falls below
2.40 V (typical), all channels turn off. After the input voltage
rises above 2.55 V (typical), the soft start period is initiated, and
the corresponding channel is enabled when the ENx pin is high.
ENABLE AND SHUTDOWN FEATURES
The ADP5310 uses the enable pins (EN1 and EN3) at logic
levels to enable and disable Channel 1 and Channel 3. The
associated channel begins operation with soft start when the
enable pin is toggled from logic low to logic high. Pulling an
enable pin low forces the associated channel into a shutdown
condition.
The buck regulator in Channel 2 is always alive as long as the
PVIN2 voltage is above the UVLO threshold.
INTERNAL LINEAR REGULATOR (VREG)
The internal linear VREG regulator in the ADP5310 provides a
stable 3.9 V power supply for the bias voltage of the MOSFET
drivers and internal control circuits. Connect a 1.0 µF ceramic
capacitor between VREG and ground.
OSCILLATOR AND SYNCHRONIZATION
The ADP5310 ensures that both buck regulators operate at the
same switching frequency when both buck regulators are in
PWM mode.
The ADP5310 offers 600 kHz or 1.2 MHz switching frequency
options in PWM operation mode via the factory fuse. The
default switching frequency is 1.2 MHz.
The switching frequency of the ADP5310 can be synchronized to
an external clock with a frequency range from 400 kHz to 1.4 MHz.
The ADP5310 automatically detects the presence of an external
clock applied to the SYNC/MODE pin, and the switching
frequency transitions to the frequency of the external clock.
When the external clock signal stops, the device automatically
switches back to the internal clock and continues to operate.
CURRENT LIMIT
The buck regulators in the ADP5310 have protection circuitry
that limit the direction and the amount of current to a certain
level that flows through the high-side MOSFET and the low-
side MOSFET in cycle-by-cycle mode. The positive current
limit on the high-side MOSFET limits the amount of current
that can flow from the input to the output. The negative current
limit on the low-side MOSFET prevents the inductor current
from reversing direction and flowing out of the load.
SHORT-CIRCUIT PROTECTION
The buck regulators in the ADP5310 include frequency foldback to
prevent current runaway on a hard short. When the output voltage
at the feedback pin falls below 0.3 V, indicating the possibility of
a hard short at the output, the switching frequency (in PWM
mode) is reduced to ¼ of the internal oscillator frequency. The
reduction in the switching frequency allows more time for the
inductor to discharge, preventing a runaway of output current.
SOFT START
The ADP5310 has an internal soft start function that ramps up
the output voltage in a controlled manner upon startup, thereby
limiting the inrush current. This prevents possible input voltage
drops when a battery or a high impedance power source is
connected to the input of the device. The default soft start time
is 350 µs for the regulators in Channel 1 and Channel 2.
Different soft start times can be programmed for each channel
by the factory fuse.
STARTUP WITH PRECHARGED OUTPUT
The buck regulators in the ADP5310 include a precharged
start-up feature to protect the low-side FETs from damage
during startup. If the output voltage is precharged before the
regulator is turned on, the regulator prevents reverse inductor
current, which discharges the output capacitor until the internal
soft start reference voltage exceeds the precharged voltage on
the feedback pin.
100% DUTY OPERATION
With a drop in input voltage or with an increase in load current,
the buck regulator in the ADP5310 may reach a limit where,
even with the high-side MOSFET on 100% of the time, the
ADP5310 works in 100% duty operation and the output is lower
than the preset value. At this limit, the buck regulator transitions to
a mode where the high-side MOSFET switch stays on 100% of
the time. When the input conditions charge again and the
required duty cycle falls, the buck immediately restarts PWM
regulation without allowing overshoot on the output voltage.
ADP5310 Data Sheet
Rev. A | Page 20 of 28
ACTIVE DISCHARGE
All channels in the ADP5310 integrate an optional, factory
programmable, discharge switch from the switching node (or
from the VOUT3 pin in the load switch) to ground. This switch
turns on when its associated regulator is disabled, which helps
discharge the output capacitor quickly. The typical value of the
discharge switch is 282 Ω to 287 Ω for each channel.
By default, the discharge function is not enabled. The option to
enable this active discharge function can be programmed for each
channel by the factory fuse.
POWER-GOOD FUNCTION
The ADP5310 includes an open-drain, power-good output
(PWRGD pin) that becomes active high when the buck
regulator in Channel 1 is operating normally.
A logic high on the PWRGD pin indicates that the regulated
output voltage of the buck regulator in Channel 1 is above 92%
(typical) of its nominal output for a delay time greater than
approximately 16 switching cycles (typical). When the regulated
output voltage of the buck regulator in Channel 1 falls below
87% (typical) of its nominal output, the PWRGD pin goes low.
LOAD SWITCH
The ADP5310 integrates a high-side load switch that operates
from 1.65 V to 5.5 V. The supply of the load switch is connected
to the FB2 pin of Channel 2 internally, which provides the
power domain isolation for the output of Channel 2 and helps
extend battery operation time. The Channel 3 load switch has a
low on resistance of 494 mΩ (typical) at VOUT3 = 2.5 V.
The inrush control circuitry (soft start) is included in the load
switch as well. The default soft start time is 12 µs. Different soft
start times can be programmed by the factory fuse.
Note that the load switch in Channel 3 is not usable when
Channel 2 is configured as the adjustable output mode via the
factory fuse.
THERMAL SHUTDOWN
If the ADP5310 junction temperature exceeds 135°C, the thermal
shutdown circuit turns off the IC except for the internal linear
regulator. Extreme junction temperatures can be the result of
high current operation, poor circuit board design, or high ambient
temperature. A 15°C hysteresis is included so that the ADP5310
does not return to operation after thermal shutdown, until the
on-chip temperature falls below 120°C. When the device exits
thermal shutdown, a soft start is initiated for each enabled channel.
Data Sheet ADP5310
Rev. A | Page 21 of 28
APPLICATIONS INFORMATION
This section describes the external components selection for the
ADP5310. The typical application circuit is shown in Figure 56.
13008-056
SW1
PGND1
FB1
PWRGD
R1 R3
R2
C3
10µF
MLCC
L1
4.7µH VOUT1
PWRGD
SW2
PGND2
FB2
C4
10µF
MLCC
L2
4.7µH
VOUT2
ADP5310
EN1
FRO M MCU
FRO M MCU
PVIN1
PVIN PVIN2
NC
EN3
SYNC/MODE
C1
10µF
MLCC
VOUT3 VOUT3
C5
220nF
MLCC
AGNDVREG
C2
1µF
Figure 56. Typical Application Circuit
EXTERNAL COMPONENT SELECTION
Table 6, Table 7, and Table 8 list external component selections for
the ADP5310 application circuit. The selection of components is
dependent on the input voltage, output voltage, and load current
requirements. Additionally, trade-offs among performance
parameters, such as efficiency and transient response, are made
by varying the choice of external components.
SELECTING THE INDUCTOR
The high frequency switching of the ADP5310 allows the use of
small surface-mount power inductors. The inductor value affects
the transition from PWM to PSM, efficiency, output ripple, and
current limit values. Use the following equation to calculate the
ideal inductance, which is derived from the inductor current
slope compensation, for a given output voltage and switching
frequency:
SW
OUT
fk V
L×
×
=2.1
where:
L is the inductor value in μH.
VOUT is the output voltage for Channel 1 and Channel 2 of the
buck regulator.
k is 1.06 (Channel 1) or 0.478 (Channel 2).
fSW is the switching frequency in MHz (1.2 MHz typical).
The ripple current is calculated as follows:
−×
×
=∆
IN
OUT
SW
OUT
L
V
V
Lf
V
I1
The dc resistance (DCR) value of the selected inductor affects
efficiency. A minimum requirement of the dc current rating of the
inductor is for it to be equal to the maximum load current plus
half of the inductor current ripple, as shown in the following
equation:
∆
+=
2
)(
L
MAXLOAD
PK
I
II
OUTPUT CAPACITOR
Output capacitance is required to minimize the voltage overshoot,
voltage undershoot, and the ripple voltage present on the output.
Capacitors with low equivalent series resistance (ESR) values
produce the lowest output ripple; Furthermore, use capacitors
such as the X5R and X7R dielectric. Do not use Y5V and Z5U
capacitors. Y5V and Z5U capacitors are unsuitable choices
because of their large capacitance variation over temperature and
their dc bias voltage changes. Because ESR is important, select
the capacitor using the following equation:
L
RIPPLE
COUT
I
V
ESR ∆
≤
where:
ESRCOUT is the ESR of the chosen capacitor.
VRIPPLE is the peak-to-peak output voltage ripple.
Use the following equation to determine the output capacitance:
RIPPLE
SW
L
OUT Vf
I
C××
∆
≥
8
Increasing the output capacitor value has no effect on stability
and may reduce output ripple and enhance load transient response.
When choosing the output capacitor value, it is important to
account for the loss of capacitance due to output voltage dc bias.
INPUT CAPACITOR
An input capacitor is required to reduce input voltage ripple and
source impedance. Place the input capacitor as close as possible
to the PVINx pin. A low ESR X7R or X5R type capacitor is highly
recommended to minimize the input voltage ripple. Use
the following equation to determine the rms input current:
IN
OUT
IN
OUT
MAXLOAD
RMS
V
VVV
II )(
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−
≥
ADP5310 Data Sheet
Rev. A | Page 22 of 28
ADJUSTABLE OUTPUT VOLTAGE PROGRAMMING
The ADP5310 features an adjustable output voltage range from
0.8 V to 5.0 V. The output voltage is set by the ratio of two external
resistors. The device servos the output to maintain the voltage at
the FBx pin at 0.8 V, referenced to ground; the current in R1 is
then equal to 0.8 V/R2 plus the FB pin bias current. The bias
current of the FBx pin, 15 nA at 25°C, flows through R2 into the
FBx pin.
The output voltage is calculated using the equation
VOUT = 0.8 V(1 + R1/R2) + (IFB_ADJ)(R1)
To minimize errors in the output voltage caused by the bias
current of the FBx pin, maintain a value of R2 that is less than
200 kΩ. For example, when R1 and R2 each equal 200 kΩ, the
output voltage is 1.6 V. The output voltage error introduced by
the FBx pin bias current is 3 mV, or 0.187%, assuming a typical
FBx pin bias current of 15 nA at 25°C.
Note that in shutdown mode, the output is turned off and the
divider current is zero.
EFFICIENCY
Efficiency is the ratio of output power to input power. The high
efficiency of the ADP5310 has two distinct advantages. First,
only a small amount of power is lost in the dc-to-dc converter
package, which in turn, reduces thermal constraints. Second,
the high efficiency delivers the maximum output power for the
given input power, thereby extending battery life in portable
applications.
Power Switch Conduction Losses
Power switch dc conduction losses are caused by the flow of
output current through the P-channel power switch and the
N-channel synchronous rectifier, which have internal resis-
tances (RDS(ON)) associated with them. The amount of power
loss is approximated by
PSW_COND = (RDS(ON)_P × D + RDS(ON)_N × (1 − D)) × IOUT2
where:
IN
OUT
V
V
D=
The internal resistance of the power switches increases with tem-
perature and increases when the input voltage is less than 5.5 V.
Inductor Losses
Inductor conduction losses are caused by the flow of current
through the inductor, which has an internal DCR associated
with it. Larger size inductors have smaller DCR, which can
decrease inductor conduction losses. Inductor core losses relate
to the magnetic permeability of the core material. Because the
ADP5310 has high switching frequency dc-to-dc regulators,
shielded ferrite core material is recommended because of its low
EMI.
To estimate the total amount of power lost in the inductor (PL),
use the following equation:
PL = DCR × IOUT2 + Core Losses
Driver Losses
Driver losses are associated with the current drawn by the
driver to turn on and turn off the power devices at the switching
frequency. Each time a power device gate is turned on and turned
off, the driver transfers a charge from the input supply to the
gate, and then from the gate to ground.
Estimate driver losses using the following equation:
PDRIVER = (CGATE_P + CGATE_N) × VIN2 × fSW
where:
CGATE_P is the gate capacitance of the internal high-side switch.
CGATE_N is the gate capacitance of the internal low-side switch.
fSW is the switching frequency.
The typical value for both gate capacitances, CGATE_P and CGATE_N,
is 150 pF.
Transition Losses
Transition losses occur because the P-channel switch cannot
turn on or turn off instantaneously. In the middle of an SWx
node transition, the power switch provides all of the inductor
current. The source-to-drain voltage of the power switch is half
of the input voltage, resulting in power loss. Transition losses
increase with both load current and input voltage and occur
twice for each switching cycle.
Use the following equation to estimate transition losses:
PTRAN = VIN/2 × IOUT × (tR + tF) × fSW
where:
tR is the rise time of the SWx node.
tF is the fall time of the SWx node.
The typical value for the rise and fall times, tR and tF, is 2 ns.
RECOMMENDED BUCK EXTERNAL COMPONENTS
The recommended external components for use with the
ADP5310 are listed in Table 6, Tabl e 7, and Table 8.
Data Sheet ADP5310
Rev. A | Page 23 of 28
Table 6. Channel 1 Inductors
Vendor Model Frequency
Output
Voltage (V)
Ideal Value
(μH)
Standard Value
(μH)
Dimensions
(mm)
ISAT 1
(A)
DCR
(mΩ)
Coilcraft XFL4020-102ME 1.2 MHz 1.2 1.1 1 4 × 4 × 2 4.5 12
Coilcraft XFL4020-152ME 1.2 MHz 1.8 1.7 1.5 4 × 4 × 2 4.1 16
Coilcraft XFL4020-222ME 1.2 MHz 2.5 2.4 2.2 4 × 4 × 2 3.1 24
Coilcraft XFL4020-332ME 1.2 MHz 3.3 3.1 3.3 4 × 4 × 2 2.7 38
Coilcraft XFL4020-472ME 1.2 MHz 5 4.7 4.7 4 × 4 × 2 2.0 57
Coilcraft
XFL4020-222ME
600 kHz
1.2
2.3
2.2
4 × 4 × 2
3.1
24
Coilcraft XFL4020-332ME 600 kHz 1.8 3.4 3.3 4 × 4 × 2 2.7 38
Coilcraft XFL4020-472ME 600 kHz 2.5 4.7 4.7 4 × 4 × 2 2.0 57
Coilcraft XAL4030-682ME 600 kHz 3.3 6.2 6.8 4 × 4 × 3 1.9 74
Coilcraft XAL4040-103ME 600 kHz 5 9.4 10 4 × 4 × 4 1.5 92
1 ISAT is the dc current at which the inductance drops 30% (typical) from its value without current.
Table 7. Channel 2 Inductors
Vendor Model Frequency
Output Voltage
(V)
Ideal Value
(μH)
Standard Value
(μH)
Dimensions
(mm) ISAT 1 (A)
DCR
(mΩ)
Coilcraft
XFL4020-222ME
1.2 MHz
1.2
2.5
2.2
4 × 4 × 2
4.1
24
Coilcraft XFL4020-332ME 1.2 MHz 1.8 3.8 3.3 4 × 4 × 2 3.1 38
Coilcraft XFL4020-472ME 1.2 MHz 2.5 5.2 4.7 4 × 4 × 2 2.0 57
Coilcraft XAL4030-682ME 1.2 MHz 3.0 6.3 6.8 4 × 4 × 3 1.9 74
Coilcraft XAL4030-682ME 1.2 MHz 3.3 6.9 6.8 4 × 4 × 3 1.9 74
Coilcraft
XAL4040-103ME
1.2 MHz
5
10.5
10
4 × 4 × 4
1.5
92
Coilcraft XFL4020-472ME 600 kHz 1.2 5.0 4.7 4 × 4 × 2 2.0 57
Coilcraft XAL4030-682ME 600 kHz 1.8 7.5 6.8 4 × 4 × 3 1.9 74
Coilcraft XAL4040-103ME 600 kHz 2.5 10.5 10 4 × 4 × 4 1.5 92
Coilcraft XAL4040-103ME 600 kHz 3.0 12.6 10 4 × 4 × 4 1.5 92
Coilcraft XAL4040-153ME 600 kHz 3.3 13.8 15 4 × 4 × 4 1.3 120
Coilcraft
LPS6235-223ML
600 kHz
5
20.9
22
6 × 6 × 3.5
1.6
145
1 ISAT is the dc current at which the inductance drops 30% (typical) from its value without current.
Table 8. 10 μF Capacitors
Vendor Model Case Size Voltage Rating (V) Location Input Voltage (V) Output Voltage (V)
Murata GRM32ER7YA106KA12 1210 35 Input 12 < VIN < 15 Not applicable
Murata
GRM32DR61E106KA12
1210
25
Input
8 < V
IN
< 12
Not applicable
Murata GRM31CR61C106KA88 1206 16 Input VIN < 8 Not applicable
Murata GRM32ER7YA106KA12 1210 35 Output Not applicable 9 < VOUT < VIN
Murata GRM32DR61E106KA12 1210 25 Output Not applicable 7 < VOUT < 9
Murata GRM31CR61C106KA88 1206 16 Output Not applicable 2.5 < VOUT < 7
Murata GRM21BR61C106KE15 0805 16 Output Not applicable VOUT < 2.5
ADP5310 Data Sheet
Rev. A | Page 24 of 28
CAPACITOR SELECTION
Output Capacitor
The ADP5310 is designed for operation with small, space-saving
ceramic capacitors, but functions with most common capacitors
provided that the ESR value is carefully considered. The ESR of
the output capacitor affects the stability of the control loop. A
minimum output capacitance of 6.2 µF with an ESR of 10 mΩ
or less is recommended to ensure the stability of the ADP5310.
Input Bypass Capacitor
Connect a 10 µF capacitor from PVINx to PGND to reduce the
circuit sensitivity to the printed circuit board (PCB) layout,
especially when long input traces or high source impedance are
encountered. If greater than 10 µF of output capacitance is
required, increase the input capacitor to match the output
capacitance to improve the transient response.
Input and Output Capacitor Properties
Use any good quality ceramic capacitors with the ADP5310;
however they must meet the minimum capacitance and
maximum ESR requirements. Ceramic capacitors are manu-
factured with a variety of dielectrics, each with different behavior
over temperature and applied voltage. Capacitors must have a
dielectric adequate to ensure the minimum capacitance over the
necessary temperature range and dc bias conditions. X5R or X7R
dielectric capacitors with a voltage rating of 6.3 V to 25 V are
recommended for best performance. Y5V and Z5U dielectrics
are not recommended because of their poor temperature and dc
bias characteristics.
Use the following equation to determine the worst-case
capacitance, accounting for capacitor variation over
temperature, component tolerance, and voltage:
CEFF = CBIAS × (1 − TEMPCO) × (1 − TOL)
where:
CBIAS is the effective capacitance at the operating voltage.
TEMPCO is the worst-case capacitor temperature coefficient (TC).
TOL is the worst-case component tolerance.
In this example, the worst-case TC over −40°C to +85°C is
assumed to be 15% for an X5R dielectric. The tolerance of the
capacitor (TOL) is assumed to be 10%, and CBIAS is 8.53 μF at 12 V
for the 10 μF, 35 V capacitor in a 1210 package.
Substituting these values in Equation 1 yields
CEFF = 8.53 μF × (1 − 0.15) × (1 − 0.1) = 6.53 μF
Therefore, the capacitor chosen in this example meets the
minimum capacitance requirement of the ADP5310 over
temperature and tolerance at the chosen output voltage.
To guarantee the performance of the ADP5310, it is imperative
that the effects of dc bias, temperature, and tolerances of the
capacitors are evaluated for each application.
CIRCUIT BOARD LAYOUT RECOMMENDATIONS
13008-057
15.75
VOUT1
VOUT3
VOUT2
8.94
100kΩ
0402
1.0µF
6.3V/X5R
0402
9 AGND
12 PWRGD
13 FB1
14 EN1
15 PGND1
16 SW1
11 SYNC/MODE
10 VREG
4.7µH
4mm × 4mm
4.7µH
4mm × 4mm
10µF
25V/X5R
1206
10µF
25V/X5R
1206
100kΩ
0402
ADP5310
1.0µF
6.3V/X5R
0603
10µF
25V/X5R
1206
VIN
PVIN2
SW2
PGND2
FB2
PVIN1
EN3
VOUT3
NC
2
4
5
6
1
8
7
3
Figure 57. Typical PCB Layout for the ADP5310
Data Sheet ADP5310
Rev. A | Page 25 of 28
TYPICAL APPLICATION CIRCUITS
Figure 58 and Figure 59 show how the ADP5310 can be applied in energy metering and medical applications controlled by a
microcontroller or a processor.
13008-058
SW1
PGND1
FB1 R1 R2
10µF
4.7µH
SW2
PGND2
FB2
10µF
4.7µH
VOUT3
ADP5310
EN1
FROM MCU PWRGD
TO MCU
FROM MCU
PVIN1
PVIN2
NC
EN3
SYNC/
MODE
CHANNEL 1
BUCK
REGULATOR
(800mA)
PA
MCU
(AL WAYS O N)
ADF70xx
(Rx/Tx)
CHANNEL 3
LOAD
SWITCH
CHANNEL 2
ULTRALOW
POWER
BUCK
REGULATOR
(50mA/300mA)
10µF
– +– +
2 × LiMnO2
MAX = 15V
MI N = 2.7V
AGNDVREG
1µF
1µF
2.2V~2.8V
AT 15mA
2.2V~2.8V
AT 2µ A
3.6V~4.6V
AT 400mA
INPUT/
OUTPUT
V
OUT
CONTROL
(BY DAC OR
GPIO SWITCH)
Figure 58. Typical Application of a Smart Meter
13008-059
SW1
PGND1
FB1 R1 R2
10µF
1.0µH
SW2
PGND2
FB2
10µF
6.8µH
VOUT3
ADP5310
EN1
FRO M DSP PWRGD
TO DSP
FRO M DSP
PVIN1
PVIN2
NC
EN3
SYNC/
MODE
CHANNEL 1
BUCK
REGULATOR
(800mA)
ADP160
ADI DSP
HIBERNATE
ALWAYS O N
VDD_INT
VDD_DMC
LPDDR
CMOS
SENSOR
PERIPHERAL
(AL WAYS O N)
PERIPHERAL
(O FF HI BE RNATE)
VDD_EXT
VDD_OTP
VDD_HADC
VDD_USB
VDD_RTC
CHANNEL 3
LOAD
SWITCH
CHANNEL 2
ULTRALOW
POWER
BUCK
REGULATOR
(50mA/300mA)
22µF
– +– +
MAX = 15V
MI N = 2.7V
AGND
VREG
1µF
1µF
3.3V
1.8V
3.3V
3.3V
3.3V
1.1V
V
OUT
CONT ROL
(BY DAC O R
SWITCH)
MODE:
HIG H = FORCE D P WM
LOW = FO RCED HYSTERESIS
Figure 59. Battery Powered Typical Application with a DSP from Analog Devices, Inc.
ADP5310 Data Sheet
Rev. A | Page 26 of 28
FACTORY PROGRAMMABLE OPTIONS
To order a device with options other than the default options, contact your local Analog Devices sales or distribution representative.
Table 9. Output Voltage Options for Channel 1 (Fixed Output Options: 1.2 V to 5.0 V)
Option Description
Option 0
0.8 V adjustable output (default)
Option 1 1.2 V fixed output
Option 2 1.5 V fixed output
Option 3 1.8 V fixed output
Option 4 2.5 V fixed output
Option 5 2.85 V fixed output
Option 6 3.3 V fixed output
Option 7 5.0 V fixed output
Table 10. Output Voltage Options for Channel 2 (Fixed Output Options: 1.20 V to 3.60 V in 50 mV Increments, and 3.60 V to 5.00 V in
100 mV Increments)
Option Description
Option 0 0.8 V adjustable output (note that the Channel 3 load switch is not usable in this configuration)
Option 1
1.20 V fixed output
Option 2 1.25 V fixed output
… …
Option 35 2.90 V fixed output
Option 36 2.95 V fixed output
Option 37 3.00 V fixed output (default)
Option 38 3.05 V fixed output
… …
Option 48 3.55 V fixed output
Option 49 3.60 V fixed output
Option 50 3.70 V fixed output
Option 51
3.80 V fixed output
… …
Option 62 4.90 V fixed output
Option 63 5.00 V fixed output
Table 11. Switching Frequency
Option Description
Option 0 1.2 MHz (default)
Option 1 600 kHz
Table 12. Operation Mode for Channel 1
Option Description
Option 0 Forced PWM mode
Option 1 Automatic PWM/PSM mode (default)
Table 13. Output Discharge Functionality Options for Channel 1
Option Description
Option 0
Output discharge function disabled for the buck regulator in Channel 1 (default)
Option 1 Output discharge function enabled for the buck regulator in Channel 1
Data Sheet ADP5310
Rev. A | Page 27 of 28
Table 14. Output Discharge Functionality Options for Channel 2
Option Description
Option 0 Output discharge function disabled for the buck regulator in Channel 2 (default)
Option 1 Output discharge function enabled for the buck regulator in Channel 2
Table 15. Output Discharge Functionality Options for Channel 3
Option Description
Option 0 Output discharge function disabled for the load switch in Channel 3 (default)
Option 1 Output discharge function enabled for the load switch in Channel 3
Table 16. Soft Start Time for Channel 1
Option Description
Option 0 350 µs (default)
Option 1 2800 µs
Table 17. Soft Start Time for Channel 2
Option Description
Option 0 350 µs (default)
Option 1
2800 µs
Table 18. Turn-On Rise (Soft Start) Time for Channel 3
Option Description
Option 0 3 µs
Option 1 12 µs (default)
Option 2
48 µs
Option 3 192 µs
ADP5310 Data Sheet
Rev. A | Page 28 of 28
OUTLINE DIMENSIONS
COMPLIANT TO JEDEC S TANDARDS M O-153-ABT
16 9
8
1
5.10
5.00
4.90
4.50
4.40
4.30
6.40
BSC
TOP VIEW BOTTOM VIEW
0.65 BSC
0.15
0.05
COPLANARITY
0.10
1.20 M AX 1.05
1.00
0.80
0.30
0.19
0.20
0.09
3.05
3.00 SQ
2.95
8°
0°
0.75
0.60
0.45
02-17-2012-A
FO R P ROPER CONNECT ION OF
THE EXPOSED PAD, REFER TO
THE P IN CONFIGURATION AND
FUNCTIO N DE S CRIPT IONS
SECTION OF THIS DATA SHEET.
EXPOSED
PAD
SEATING
PLANE
Figure 60. 16-Lead Thin Shrink Small Outline With Exposed Pad [TSSOP_EP]
(RE-16-2)
Dimensions shown in millimeters
ORDERING GUIDE
Model1
Temperature
Range Output Voltage
Package
Description
Package
Option
ADP5310AREZN-255R7
−40°C to +125°C
Channel 1 = adjustable, Channel 2 = 2.55 V
16-Lead TSSOP_EP
RE-16-2
ADP5310AREZN-2.8R7 −40°C to +125°C Channel 1 = adjustable, Channel 2 = 2.8 V 16-Lead TSSOP_EP RE-16-2
ADP5310AREZN-3.3R7 −40°C to +125°C Channel 1 = adjustable, Channel 2 = 3.3 V 16-Lead TSSOP_EP RE-16-2
ADP5310AREZN-R7 −40°C to +125°C Channel 1 = adjustable with automatic PWM/PSM mode,
Channel 2 = adjustable
16-Lead TSSOP_EP RE-16-2
ADP5310READJ-EVALZ Evaluation Board
1 Z = RoHS Compliant Part.
©2015–2016 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D13008-0-11/16(A)