M25P40 4 Mbit, low voltage, serial Flash memory with 75 MHz SPI bus interface Features 4 Mbit of Flash memory 2.3 V to 3.6 V single supply voltage SPI bus compatible serial interface 75 MHz clock rate (maximum) Page Program (up to 256 bytes) in 0.8 ms (typical) Sector Erase (512 Kbit) in 0.6 s (typical) Bulk Erase (4 Mbit) in 4.5 s (typical) Deep Power-down mode 1 A (typical) Hardware Write Protection: protected area size defined by three non-volatile bits (BP0, BP1 and BP2) Electronic signatures - JEDEC standard two-byte signature (2013h) - Unique ID code (UID) with 16 bytes readonly, available upon customer request - RES instruction, one-byte, signature (12h), for backward compatibility SO8 (MN) 150 mils width SO8W (MW) 208 mils width QFN8L (MS) MLP8 6 x 5 mm Packages - ECOPACK(R) (RoHS compliant) VFQPN8 (MP) (MLP8 6 x 5 mm) October 2008 Rev 16 1/59 www.Numonyx.com 1 Contents M25P40 Contents 1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2 Signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.1 Serial Data output (Q) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.2 Serial Data input (D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.3 Serial Clock (C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.4 Chip Select (S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.5 Hold (HOLD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.6 Write Protect (W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.7 VCC supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.8 VSS ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3 SPI modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 4 Operating features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 4.1 Page Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 4.2 Sector Erase and Bulk Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 4.3 Polling during a Write, Program or Erase cycle . . . . . . . . . . . . . . . . . . . . 12 4.4 Active Power, Standby Power and Deep Power-down modes . . . . . . . . . 12 4.5 Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4.6 Protection modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4.7 Hold condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 5 Memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 6 Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2/59 6.1 Write Enable (WREN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 6.2 Write Disable (WRDI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 6.3 Read Identification (RDID) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 6.4 Read Status Register (RDSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 6.4.1 WIP bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 6.4.2 WEL bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 6.4.3 BP2, BP1, BP0 bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 M25P40 Contents 6.4.4 SRWD bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 6.5 Write Status Register (WRSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 6.6 Read Data Bytes (READ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 6.7 Read Data Bytes at Higher Speed (FAST_READ) . . . . . . . . . . . . . . . . . . 27 6.8 Page Program (PP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 6.9 Sector Erase (SE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 6.10 Bulk Erase (BE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 6.11 Deep Power-down (DP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 6.12 Release from Deep Power-down and Read Electronic Signature (RES) . 33 7 Power-up and Power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 8 Initial delivery state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 9 Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 10 DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 11 Package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 12 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 13 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 3/59 List of tables M25P40 List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Table 28. 4/59 Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Protected area sizes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Read Identification (RDID) data-out sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Status Register format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Protection modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Power-up timing and VWI threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Operating conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Data retention and endurance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 DC characteristics (device grade 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 DC characteristics (device grade 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Instruction times, process technology T9HX (device grade 6) . . . . . . . . . . . . . . . . . . . . . . 40 Instruction times, process technology T7Y (device grade 6) . . . . . . . . . . . . . . . . . . . . . . . 41 Instruction times (device grade 3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 AC measurement conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 AC characteristics (25 MHz operation, device grade 3, VCC min = 2.7 V) . . . . . . . . . . . . . 43 AC characteristics (50 MHz operation, device grade 6, VCC min = 2.7 V) . . . . . . . . . . . . . 44 AC characteristics (*40 MHz operation, device grade 6, VCC min = 2.3 V) . . . . . . . . . . . . 45 AC characteristics, grade 6 (T9HX technology), 75 MHz operation, VCC min = 2.7 V . . . 46 SO8 narrow - 8 lead plastic Small Outline, 150 mils body width, package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 SO8 wide - 8 lead plastic small outline, 208 mils body width, package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 QFN8L (MLP8) 8-lead dual flat package no lead, 6 x 5 mm package mechanical data. . . 51 VFQFPN8 (MLP8) 8-lead Very thin Fine pitch Quad Flat Package No lead, 6 x 5 mm, package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 M25P40 List of figures List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Figure 29. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 SO and MLP8 connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Bus Master and memory devices on the SPI bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 SPI modes supported . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Hold condition activation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Write Enable (WREN) instruction sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Write Disable (WRDI) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Read Identification (RDID) instruction sequence and data-out sequence . . . . . . . . . . . . . 22 Read Status Register (RDSR) instruction sequence and data-out sequence . . . . . . . . . . 23 Write Status Register (WRSR) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Read Data Bytes (READ) instruction sequence and data-out sequence . . . . . . . . . . . . . . 26 Read Data Bytes at Higher Speed (FAST_READ) instruction sequence and data-out sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Page Program (PP) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Sector Erase (SE) instruction sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Bulk Erase (BE) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Deep Power-down (DP) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Release from Deep Power-down and Read Electronic Signature (RES) instruction sequence and data-out sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Release from Deep Power-down (RES) instruction sequence . . . . . . . . . . . . . . . . . . . . . . 34 Power-up timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 AC measurement I/O waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Serial input timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Write Protect setup and hold timing during WRSR when SRWD = 1 . . . . . . . . . . . . . . . . . 47 Hold timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Output timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 SO8 narrow - 8 lead plastic Small Outline, 150 mils body width, package outline. . . . . . . 49 SO8W - 8 lead plastic small outline, 208 mils body width, package outline. . . . . . . . . . . . 50 QFN8L (MLP8) 8-lead, dual flat package no lead, 6 x 5 mm, package outline . . . . . . . . . 51 VFQFPN8 (MLP8) 8-lead Very thin Fine pitch Quad Flat Package No lead, 6 x 5 mm, package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 5/59 Description 1 M25P40 Description The M25P40 is a 4 Mbit (512 K x 8) Serial Flash memory, with advanced write protection mechanisms, accessed by a high speed SPI-compatible bus. The M25P40 features high performance instructions allowing clock frequency up to 75 MHz.(1) The memory can be programmed 1 to 256 bytes at a time, using the Page Program instruction. The memory is organized as 8 sectors, each containing 256 pages. Each page is 256 bytes wide. Thus, the whole memory can be viewed as consisting of 2048 pages, or 524,288 bytes. The whole memory can be erased using the Bulk Erase instruction, or a sector at a time, using the Sector Erase instruction. In order to meet environmental requirements, Numonyx offers the M25P40 in ECOPACK(R) packages. ECOPACK(R) packages are Lead-free and RoHS compliant. ECOPACK is an Numonyx trademark. ECOPACK specifications are available at: www.Numonyx.com. Important: This datasheet details the functionality of the M25P40 devices, based on the previous T7Y process or based on the current T9HX process (available since August 2008). The new device in T9HX is completely backward compatible with the old one in T7Y and it additionaly features: - improved max frequency (Fast Read) to 75 MHz in the standard Vcc range 2.7 V to 3.6 V, while the max frequency (Fast Read) in the extended Vcc range 2.3 V to 2.7 V is 40 MHz - UID/CFD protection feature Figure 1. Logic diagram VCC D Q C S M25P40 W HOLD VSS AI04090 1. 75 MHz operation is available only on the VCC range 2.7 V - 3.6 V and for process technology T9HX devices, identified by process identification digit "4" in the device marking and process letter "B" in the part number. 6/59 M25P40 Description Table 1. Signal names Signal name Function Direction C Serial Clock Input D Serial Data input Input Q Serial Data output Output S Chip Select Input W Write Protect Input HOLD Hold Input VCC Supply voltage VSS Ground Figure 2. SO and MLP8 connections M25P40 S Q W VSS 1 2 3 4 8 7 6 5 VCC HOLD C D AI04091B 1. There is an exposed central pad on the underside of the MLP8 packages. This is pulled, internally, to VSS, and must not be allowed to be connected to any other voltage or signal line on the PCB. 2. See Section 11: Package mechanical for package dimensions, and how to identify pin-1. 7/59 Signal description 2 Signal description 2.1 Serial Data output (Q) M25P40 This output signal is used to transfer data serially out of the device. Data is shifted out on the falling edge of Serial Clock (C). 2.2 Serial Data input (D) This input signal is used to transfer data serially into the device. It receives instructions, addresses, and the data to be programmed. Values are latched on the rising edge of Serial Clock (C). 2.3 Serial Clock (C) This input signal provides the timing of the serial interface. Instructions, addresses, or data present at Serial Data input (D) are latched on the rising edge of Serial Clock (C). Data on Serial Data output (Q) changes after the falling edge of Serial Clock (C). 2.4 Chip Select (S) When this input signal is High, the device is deselected and Serial Data output (Q) is at high impedance. Unless an internal Program, Erase or Write Status Register cycle is in progress, the device will be in the Standby Power mode (this is not the Deep Power-down mode). Driving Chip Select (S) Low selects the device, placing it in the Active Power mode. After Power-up, a falling edge on Chip Select (S) is required prior to the start of any instruction. 2.5 Hold (HOLD) The Hold (HOLD) signal is used to pause any serial communications with the device without deselecting the device. During the Hold condition, the Serial Data output (Q) is high impedance, and Serial Data input (D) and Serial Clock (C) are Don't Care. To start the Hold condition, the device must be selected, with Chip Select (S) driven Low. 2.6 Write Protect (W) The main purpose of this input signal is to freeze the size of the area of memory that is protected against program or erase instructions (as specified by the values in the BP2, BP1 and BP0 bits of the Status Register). 8/59 M25P40 2.7 Signal description VCC supply voltage VCC is the supply voltage. 2.8 VSS ground VSS is the reference for the VCC supply voltage. 9/59 SPI modes 3 M25P40 SPI modes These devices can be driven by a microcontroller with its SPI peripheral running in either of the two following modes: CPOL=0, CPHA=0 CPOL=1, CPHA=1 For these two modes, input data is latched in on the rising edge of Serial Clock (C), and output data is available from the falling edge of Serial Clock (C). The difference between the two modes, as shown in Figure 4, is the clock polarity when the bus master is in Stand-by mode and not transferring data: C remains at 0 for (CPOL=0, CPHA=0) C remains at 1 for (CPOL=1, CPHA=1) Figure 3. Bus Master and memory devices on the SPI bus VSS VCC R SDO SPI Interface with (CPOL, CPHA) = (0, 0) or (1, 1) SDI SCK VCC C Q D SPI Bus Master SPI Memory Device R CS3 VCC C Q D VSS C Q D VCC VSS SPI Memory Device R VSS SPI Memory Device R CS2 CS1 S W HOLD S W HOLD S W HOLD AI12836b 1. The Write Protect (W) and Hold (HOLD) signals should be driven, High or Low as appropriate. Figure 3 shows an example of three devices connected to an MCU, on an SPI bus. Only one device is selected at a time, so only one device drives the Serial Data output (Q) line at a time, the other devices are high impedance. Resistors R (represented in Figure 3) ensure that the M25P40 is not selected if the Bus Master leaves the S line in the high impedance state. As the Bus Master may enter a state where all inputs/outputs are in high impedance at the same time (for example, when the Bus Master is reset), the clock line (C) must be connected to an external pull-down resistor so that, when all inputs/outputs become high impedance, the S line is pulled High while the C line is pulled Low (thus ensuring that S and C do not become High at the same time, and so, that the tSHCH requirement is met). The typical value of R is 100 k, assuming that the time constant R*Cp (Cp = parasitic capacitance of the bus line) is shorter than the time during which the Bus Master leaves the SPI bus in high impedance. 10/59 M25P40 SPI modes Example: Cp = 50 pF, that is R*Cp = 5 s <=> the application must ensure that the Bus Master never leaves the SPI bus in the high impedance state for a time period shorter than 5 s. Figure 4. SPI modes supported CPOL CPHA 0 0 C 1 1 C D Q MSB MSB AI01438B 11/59 Operating features 4 Operating features 4.1 Page Programming M25P40 To program one data byte, two instructions are required: Write Enable (WREN), which is one byte, and a Page Program (PP) sequence, which consists of four bytes plus data. This is followed by the internal Program cycle (of duration tPP). To spread this overhead, the Page Program (PP) instruction allows up to 256 bytes to be programmed at a time (changing bits from 1 to 0), provided that they lie in consecutive addresses on the same page of memory. For optimized timings, it is recommended to use the Page Program (PP) instruction to program all consecutive targeted bytes in a single sequence versus using several Page Program (PP) sequences with each containing only a few bytes (see Page Program (PP), Instruction times, process technology T9HX (device grade 6) and Table 17: Instruction times (device grade 3)). 4.2 Sector Erase and Bulk Erase The Page Program (PP) instruction allows bits to be reset from 1 to 0. Before this can be applied, the bytes of memory need to have been erased to all 1s (FFh). This can be achieved either a sector at a time, using the Sector Erase (SE) instruction, or throughout the entire memory, using the Bulk Erase (BE) instruction. This starts an internal Erase cycle (of duration tSE or tBE). The Erase instruction must be preceded by a Write Enable (WREN) instruction. 4.3 Polling during a Write, Program or Erase cycle A further improvement in the time to Write Status Register (WRSR), Program (PP) or Erase (SE or BE) can be achieved by not waiting for the worst case delay (tW, tPP, tSE, or tBE). The Write In Progress (WIP) bit is provided in the Status Register so that the application program can monitor its value, polling it to establish when the previous Write cycle, Program cycle or Erase cycle is complete. 4.4 Active Power, Standby Power and Deep Power-down modes When Chip Select (S) is Low, the device is selected, and in the Active Power mode. When Chip Select (S) is High, the device is deselected, but could remain in the Active Power mode until all internal cycles have completed (Program, Erase, Write Status Register). The device then goes in to the Standby Power mode. The device consumption drops to ICC1. The Deep Power-down mode is entered when the specific instruction (the Deep Powerdown (DP) instruction) is executed. The device consumption drops further to ICC2. The device remains in this mode until another specific instruction (the Release from Deep Power-down and Read Electronic Signature (RES) instruction) is executed. 12/59 M25P40 Operating features All other instructions are ignored while the device is in the Deep Power-down mode. This can be used as an extra software protection mechanism, when the device is not in active use, to protect the device from inadvertent Write, Program or Erase instructions. 4.5 Status Register The Status Register contains a number of status and control bits that can be read or set (as appropriate) by specific instructions. For a detailed description of the Status Register bits, see Section 6.4: Read Status Register (RDSR). 4.6 Protection modes The environments where non-volatile memory devices are used can be very noisy. No SPI device can operate correctly in the presence of excessive noise. To help combat this, the M25P40 features the following data protection mechanisms: Power On Reset and an internal timer (tPUW) can provide protection against inadvertent changes while the power supply is outside the operating specification. Program, Erase and Write Status Register instructions are checked that they consist of a number of clock pulses that is a multiple of eight, before they are accepted for execution. All instructions that modify data must be preceded by a Write Enable (WREN) instruction to set the Write Enable Latch (WEL) bit. This bit is returned to its reset state by the following events: - Power-up - Write Disable (WRDI) instruction completion - Write Status Register (WRSR) instruction completion - Page Program (PP) instruction completion - Sector Erase (SE) instruction completion - Bulk Erase (BE) instruction completion The Block Protect (BP2, BP1, BP0) bits allow part of the memory to be configured as read-only. This is the Software Protected Mode (SPM). The Write Protect (W) signal allows the Block Protect (BP2, BP1, BP0) bits and Status Register Write Disable (SRWD) bit to be protected. This is the Hardware Protected Mode (HPM). In addition to the low power consumption feature, the Deep Power-down mode offers extra software protection from inadvertent Write, Program and Erase instructions, as all instructions are ignored except one particular instruction (the Release from Deep Power-down instruction). 13/59 Operating features M25P40 Table 2. Protected area sizes Status Register content BP2 BP1 bit bit Memory content BP0 bit Protected area Unprotected area 0 0 0 none All sectors(1) (eight sectors: 0 to 7) 0 0 1 Upper eighth (Sector 7) Lower seven-eighths (seven sectors: 0 to 6) 0 1 0 Upper quarter (two sectors: 6 and 7) Lower three-quarters (six sectors: 0 to 5) 0 1 1 Upper half (four sectors: 4 to 7) Lower half (four sectors: 0 to 3) 1 0 0 All sectors (eight sectors: 0 to 7) none 1 0 1 All sectors (eight sectors: 0 to 7) none 1 1 0 All sectors (eight sectors: 0 to 7) none 1 1 1 All sectors (eight sectors: 0 to 7) none 1. The device is ready to accept a Bulk Erase instruction if, and only if, all Block Protect (BP2, BP1, BP0) are 0. 4.7 Hold condition The Hold (HOLD) signal is used to pause any serial communications with the device without resetting the clocking sequence. However, taking this signal Low does not terminate any Write Status Register, Program or Erase cycle that is currently in progress. To enter the Hold condition, the device must be selected, with Chip Select (S) Low. The Hold condition starts on the falling edge of the Hold (HOLD) signal, provided that this coincides with Serial Clock (C) being Low (as shown in Figure 5). The Hold condition ends on the rising edge of the Hold (HOLD) signal, provided that this coincides with Serial Clock (C) being Low. If the falling edge does not coincide with Serial Clock (C) being Low, the Hold condition starts after Serial Clock (C) next goes Low. Similarly, if the rising edge does not coincide with Serial Clock (C) being Low, the Hold condition ends after Serial Clock (C) next goes Low. (This is shown in Figure 5). During the Hold condition, the Serial Data output (Q) is high impedance, and Serial Data input (D) and Serial Clock (C) are Don't Care. Normally, the device is kept selected, with Chip Select (S) driven Low, for the whole duration of the Hold condition. This is to ensure that the state of the internal logic remains unchanged from the moment of entering the Hold condition. If Chip Select (S) goes High while the device is in the Hold condition, this has the effect of resetting the internal logic of the device. To restart communication with the device, it is necessary to drive Hold (HOLD) High, and then to drive Chip Select (S) Low. This prevents the device from going back to the Hold condition. 14/59 M25P40 Operating features Figure 5. Hold condition activation C HOLD Hold Condition (standard use) Hold Condition (non-standard use) AI02029D 15/59 Memory organization 5 M25P40 Memory organization The memory is organized as: 524,288 bytes (8 bits each) 8 sectors (512 Kbits, 65536 bytes each) 2048 pages (256 bytes each). Each page can be individually programmed (bits are programmed from 1 to 0). The device is Sector or Bulk Erasable (bits are erased from 0 to 1) but not Page Erasable. Table 3. Memory organization Sector 16/59 Address range 7 70000h 7FFFFh 6 60000h 6FFFFh 5 50000h 5FFFFh 4 40000h 4FFFFh 3 30000h 3FFFFh 2 20000h 2FFFFh 1 10000h 1FFFFh 0 00000h 0FFFFh M25P40 Memory organization Figure 6. Block diagram HOLD W High Voltage Generator Control Logic S C D I/O Shift Register Q Address Register and Counter Status Register 256 Byte Data Buffer 7FFFFh Y Decoder Size of the read-only memory area 00000h 000FFh 256 Bytes (Page Size) X Decoder AI04986 17/59 Instructions 6 M25P40 Instructions All instructions, addresses and data are shifted in and out of the device, most significant bit first. Serial Data input (D) is sampled on the first rising edge of Serial Clock (C) after Chip Select (S) is driven Low. Then, the one-byte instruction code must be shifted in to the device, most significant bit first, on Serial Data input (D), each bit being latched on the rising edges of Serial Clock (C). The instruction set is listed in Table 4. Every instruction sequence starts with a one-byte instruction code. Depending on the instruction, this might be followed by address bytes, or by data bytes, or by both or none. Chip Select (S) must be driven High after the last bit of the instruction sequence has been shifted in. In the case of a Read Data Bytes (READ), Read Data Bytes at Higher Speed (Fast_Read), Read Identification (RDID), Read Status Register (RDSR) or Release from Deep Powerdown, and Read Electronic Signature (RES) instruction, the shifted-in instruction sequence is followed by a data-out sequence. Chip Select (S) can be driven High after any bit of the data-out sequence is being shifted out. In the case of a Page Program (PP), Sector Erase (SE), Bulk Erase (BE), Write Status Register (WRSR), Write Enable (WREN), Write Disable (WRDI) or Deep Power-down (DP) instruction, Chip Select (S) must be driven High exactly at a byte boundary, otherwise the instruction is rejected, and is not executed. That is, Chip Select (S) must driven High when the number of clock pulses after Chip Select (S) being driven Low is an exact multiple of eight. All attempts to access the memory array during a Write Status Register cycle, Program cycle or Erase cycle are ignored, and the internal Write Status Register cycle, Program cycle or Erase cycle continues unaffected. 18/59 M25P40 Instructions Table 4. Instruction set Instruction One-byte instruction code Description Address Dummy bytes bytes Data bytes WREN Write Enable 0000 0110 06h 0 0 0 WRDI Write Disable 0000 0100 04h 0 0 0 RDID(1) Read Identification 1001 1111 9Fh 0 0 1 to 3 RDSR Read Status Register 0000 0101 05h 0 0 1 to WRSR Write Status Register 0000 0001 01h 0 0 1 READ Read Data Bytes 0000 0011 03h 3 0 1 to Read Data Bytes at Higher Speed 0000 1011 0Bh 3 1 1 to PP Page Program 0000 0010 02h 3 0 1 to 256 SE Sector Erase 1101 1000 D8h 3 0 0 BE Bulk Erase 1100 0111 C7h 0 0 0 DP Deep Power-down 1011 1001 B9h 0 0 0 Release from Deep Powerdown, and Read Electronic Signature 0 3 1 to 1010 1011 ABh 0 0 0 FAST_READ RES Release from Deep Powerdown 1. The Read Identification (RDID) instruction is available only in products with Process Technology code X and 4 (see Application Note AN1995). 6.1 Write Enable (WREN) The Write Enable (WREN) instruction (Figure 7) sets the Write Enable Latch (WEL) bit. The Write Enable Latch (WEL) bit must be set prior to every Page Program (PP), Sector Erase (SE), Bulk Erase (BE) and Write Status Register (WRSR) instruction. The Write Enable (WREN) instruction is entered by driving Chip Select (S) Low, sending the instruction code, and then driving Chip Select (S) High. Figure 7. Write Enable (WREN) instruction sequence S 0 1 2 3 4 5 6 7 C Instruction D High Impedance Q AI02281E 19/59 Instructions 6.2 M25P40 Write Disable (WRDI) The Write Disable (WRDI) instruction (Figure 8) resets the Write Enable Latch (WEL) bit. The Write Disable (WRDI) instruction is entered by driving Chip Select (S) Low, sending the instruction code, and then driving Chip Select (S) High. The Write Enable Latch (WEL) bit is reset under the following conditions: Power-up Write Disable (WRDI) instruction completion Write Status Register (WRSR) instruction completion Page Program (PP) instruction completion Sector Erase (SE) instruction completion Bulk Erase (BE) instruction completion Figure 8. Write Disable (WRDI) instruction sequence S 0 1 2 3 4 5 6 7 C Instruction D High Impedance Q AI03750D 20/59 M25P40 6.3 Instructions Read Identification (RDID) The Read Identification (RDID) instruction allows to read the device identification data: Manufacturer identification (1 byte) Device identification (2 bytes) A Unique ID code (UID) (17 bytes, of which 16 available upon customer request).(2) The manufacturer identification is assigned by JEDEC, and has the value 20h for Numonyx. The device identification is assigned by the device manufacturer, and indicates the memory type in the first byte (20h), and the memory capacity of the device in the second byte (13h). The UID contains the length of the following data in the first byte (set to 10h), and 16 bytes of the optional Customized Factory Data (CFD) content. The CFD bytes are read-only and can be programmed with customers data upon their demand. If the customers do not make requests, the devices are shipped with all the CFD bytes programmed to zero (00h). Any Read Identification (RDID) instruction while an Erase or Program cycle is in progress, is not decoded, and has no effect on the cycle that is in progress. The device is first selected by driving Chip Select (S) Low. Then, the 8-bit instruction code for the instruction is shifted in. After this, the 24-bit device identification, stored in the memory, the 8-bit CFD length followed by 16 bytes of CFD content will be shifted out on Serial Data output (Q). Each bit is shifted out during the falling edge of Serial Clock (C). The instruction sequence is shown in Figure 9. The Read Identification (RDID) instruction is terminated by driving Chip Select (S) High at any time during data output. When Chip Select (S) is driven High, the device is put in the Stand-by Power mode. Once in the Stand-by Power mode, the device waits to be selected, so that it can receive, decode and execute instructions. Table 5. Read Identification (RDID) data-out sequence Device identification UID Manufacturer identification 20h Memory type Memory capacity CFD length CFD content 20h 13h 10h 16 bytes 2. The UID feature is available only for process technology T9HX devices, identified by with process identification digit "4" in the device marking and process letter "B" in the part number. 21/59 Instructions M25P40 Figure 9. Read Identification (RDID) instruction sequence and data-out sequence S 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 28 29 30 31 C Instruction D Manufacturer Identification Device Identification High Impedance Q 15 14 13 3 2 1 0 MSB MSB AI06809b 6.4 Read Status Register (RDSR) The Read Status Register (RDSR) instruction allows the Status Register to be read. The Status Register may be read at any time, even while a Program, Erase or Write Status Register cycle is in progress. When one of these cycles is in progress, it is recommended to check the Write In Progress (WIP) bit before sending a new instruction to the device. It is also possible to read the Status Register continuously, as shown in Figure 10. Table 6. Status Register format b7 SRWD b0 0 0 BP2 BP1 BP0 WEL WIP Status Register Write Protect Block Protect bits Write Enable Latch bit Write In Progress bit The status and control bits of the Status Register are as follows: 6.4.1 WIP bit The Write In Progress (WIP) bit indicates whether the memory is busy with a Write Status Register, Program or Erase cycle. When set to 1, such a cycle is in progress, when reset to 0 no such cycle is in progress. 6.4.2 WEL bit The Write Enable Latch (WEL) bit indicates the status of the internal Write Enable Latch. When set to 1 the internal Write Enable Latch is set, when set to 0 the internal Write Enable Latch is reset and no Write Status Register, Program or Erase instruction is accepted. 22/59 M25P40 6.4.3 Instructions BP2, BP1, BP0 bits The Block Protect (BP2, BP1, BP0) bits are non-volatile. They define the size of the area to be software protected against Program and Erase instructions. These bits are written with the Write Status Register (WRSR) instruction. When one or more of the Block Protect (BP2, BP1, BP0) bits is set to 1, the relevant memory area (as defined in Table 2) becomes protected against Page Program (PP) and Sector Erase (SE) instructions. The Block Protect (BP2, BP1, BP0) bits can be written provided that the Hardware Protected mode has not been set. The Bulk Erase (BE) instruction is executed if, and only if, all Block Protect (BP2, BP1, BP0) bits are 0. 6.4.4 SRWD bit The Status Register Write Disable (SRWD) bit is operated in conjunction with the Write Protect (W) signal. The Status Register Write Disable (SRWD) bit and Write Protect (W) signal allow the device to be put in the Hardware Protected mode (when the Status Register Write Disable (SRWD) bit is set to 1, and Write Protect (W) is driven Low). In this mode, the non-volatile bits of the Status Register (SRWD, BP2, BP1, BP0) become read-only bits and the Write Status Register (WRSR) instruction is no longer accepted for execution. Figure 10. Read Status Register (RDSR) instruction sequence and data-out sequence S 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 C Instruction D Status Register Out Status Register Out High Impedance Q 7 MSB 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 MSB AI02031E 23/59 Instructions 6.5 M25P40 Write Status Register (WRSR) The Write Status Register (WRSR) instruction allows new values to be written to the Status Register. Before it can be accepted, a Write Enable (WREN) instruction must previously have been executed. After the Write Enable (WREN) instruction has been decoded and executed, the device sets the Write Enable Latch (WEL). The Write Status Register (WRSR) instruction is entered by driving Chip Select (S) Low, followed by the instruction code and the data byte on Serial Data input (D). The instruction sequence is shown in Figure 11. The Write Status Register (WRSR) instruction has no effect on b6, b5, b1 and b0 of the Status Register. b6 and b5 are always read as 0. Chip Select (S) must be driven High after the eighth bit of the data byte has been latched in. If not, the Write Status Register (WRSR) instruction is not executed. As soon as Chip Select (S) is driven High, the self-timed Write Status Register cycle (whose duration is tW) is initiated. While the Write Status Register cycle is in progress, the Status Register may still be read to check the value of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the self-timed Write Status Register cycle, and is 0 when it is completed. When the cycle is completed, the Write Enable Latch (WEL) is reset. The Write Status Register (WRSR) instruction allows the user to change the values of the Block Protect (BP2, BP1, BP0) bits, to define the size of the area that is to be treated as read-only, as defined in Table 2. The Write Status Register (WRSR) instruction also allows the user to set or reset the Status Register Write Disable (SRWD) bit in accordance with the Write Protect (W) signal. The Status Register Write Disable (SRWD) bit and Write Protect (W) signal allow the device to be put in the Hardware Protected Mode (HPM). The Write Status Register (WRSR) instruction is not executed once the Hardware Protected Mode (HPM) is entered. Figure 11. Write Status Register (WRSR) instruction sequence S 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 C Instruction Status Register In 7 D High Impedance 6 5 4 3 2 1 0 MSB Q AI02282D 24/59 M25P40 Instructions Table 7. Protection modes W SRWD signal bit 1 0 0 0 1 1 0 1 Mode Write Protection of the Status Register Memory content Protected area (1) Unprotected area(1) Status Register is Writable (if the WREN Software instruction has set the Protected WEL bit) (SPM) The values in the SRWD, BP2, BP1 and BP0 bits can be changed Protected against Page Program, Sector Erase and Bulk Erase Ready to accept Page Program and Sector Erase instructions Status Register is Hardware Hardware write protected Protected The values in the SRWD, (HPM) BP2, BP1 and BP0 bits cannot be changed Protected against Page Program, Sector Erase and Bulk Erase Ready to accept Page Program and Sector Erase instructions 1. As defined by the values in the Block Protect (BP2, BP1, BP0) bits of the Status Register, as shown in Table 2. The protection features of the device are summarized in Table 7. When the Status Register Write Disable (SRWD) bit of the Status Register is 0 (its initial delivery state), it is possible to write to the Status Register provided that the Write Enable Latch (WEL) bit has previously been set by a Write Enable (WREN) instruction, regardless of the whether Write Protect (W) is driven High or Low. When the Status Register Write Disable (SRWD) bit of the Status Register is set to 1, two cases need to be considered, depending on the state of Write Protect (W): If Write Protect (W) is driven High, it is possible to write to the Status Register provided that the Write Enable Latch (WEL) bit has previously been set by a Write Enable (WREN) instruction. If Write Protect (W) is driven Low, it is not possible to write to the Status Register even if the Write Enable Latch (WEL) bit has previously been set by a Write Enable (WREN) instruction. (Attempts to write to the Status Register are rejected, and are not accepted for execution). As a consequence, all the data bytes in the memory area that are software protected (SPM) by the Block Protect (BP2, BP1, BP0) bits of the Status Register, are also hardware protected against data modification. Regardless of the order of the two events, the Hardware Protected Mode (HPM) can be entered: by setting the Status Register Write Disable (SRWD) bit after driving Write Protect (W) Low or by driving Write Protect (W) Low after setting the Status Register Write Disable (SRWD) bit. The only way to exit the Hardware Protected Mode (HPM) once entered is to pull Write Protect (W) High. If Write Protect (W) is permanently tied High, the Hardware Protected Mode (HPM) can never be activated, and only the Software Protected Mode (SPM), using the Block Protect (BP2, BP1, BP0) bits of the Status Register, can be used. 25/59 Instructions 6.6 M25P40 Read Data Bytes (READ) The device is first selected by driving Chip Select (S) Low. The instruction code for the Read Data Bytes (READ) instruction is followed by a 3-byte address (A23-A0), each bit being latched-in during the rising edge of Serial Clock (C). Then the memory contents, at that address, is shifted out on Serial Data output (Q), each bit being shifted out, at a maximum frequency fR, during the falling edge of Serial Clock (C). The instruction sequence is shown in Figure 12. The first byte addressed can be at any location. The address is automatically incremented to the next higher address after each byte of data is shifted out. The whole memory can, therefore, be read with a single Read Data Bytes (READ) instruction. When the highest address is reached, the address counter rolls over to 000000h, allowing the read sequence to be continued indefinitely. The Read Data Bytes (READ) instruction is terminated by driving Chip Select (S) High. Chip Select (S) can be driven High at any time during data output. Any Read Data Bytes (READ) instruction, while an Erase, Program or Write cycle is in progress, is rejected without having any effects on the cycle that is in progress. Figure 12. Read Data Bytes (READ) instruction sequence and data-out sequence S 0 1 2 3 4 5 6 7 8 9 10 28 29 30 31 32 33 34 35 36 37 38 39 C Instruction 24-Bit Address 23 22 21 D 3 2 1 0 MSB Data Out 1 High Impedance Q 7 6 5 4 3 2 Data Out 2 1 0 7 MSB AI03748D 1. Address bits A23 to A19 are Don't Care. 26/59 M25P40 6.7 Instructions Read Data Bytes at Higher Speed (FAST_READ) The device is first selected by driving Chip Select (S) Low. The instruction code for the Read Data Bytes at Higher Speed (FAST_READ) instruction is followed by a 3-byte address (A23A0) and a dummy byte, each bit being latched-in during the rising edge of Serial Clock (C). Then the memory contents, at that address, is shifted out on Serial Data output (Q), each bit being shifted out, at a maximum frequency fC, during the falling edge of Serial Clock (C). The instruction sequence is shown in Figure 13. The first byte addressed can be at any location. The address is automatically incremented to the next higher address after each byte of data is shifted out. The whole memory can, therefore, be read with a single Read Data Bytes at Higher Speed (FAST_READ) instruction. When the highest address is reached, the address counter rolls over to 000000h, allowing the read sequence to be continued indefinitely. The Read Data Bytes at Higher Speed (FAST_READ) instruction is terminated by driving Chip Select (S) High. Chip Select (S) can be driven High at any time during data output. Any Read Data Bytes at Higher Speed (FAST_READ) instruction, while an Erase, Program or Write cycle is in progress, is rejected without having any effects on the cycle that is in progress. Figure 13. Read Data Bytes at Higher Speed (FAST_READ) instruction sequence and data-out sequence S 0 1 2 3 4 5 6 7 8 9 10 28 29 30 31 C Instruction 24 BIT ADDRESS 23 22 21 D 3 2 1 0 High Impedance Q S 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 C Dummy Byte D 7 6 5 4 3 2 1 0 DATA OUT 2 DATA OUT 1 7 Q MSB 6 5 4 3 2 1 0 7 MSB 6 5 4 3 2 1 0 7 MSB AI04006 1. Address bits A23 to A19 are Don't Care. 27/59 Instructions 6.8 M25P40 Page Program (PP) The Page Program (PP) instruction allows bytes to be programmed in the memory (changing bits from 1 to 0). Before it can be accepted, a Write Enable (WREN) instruction must previously have been executed. After the Write Enable (WREN) instruction has been decoded, the device sets the Write Enable Latch (WEL). The Page Program (PP) instruction is entered by driving Chip Select (S) Low, followed by the instruction code, three address bytes and at least one data byte on Serial Data input (D). If the 8 least significant address bits (A7-A0) are not all zero, all transmitted data that goes beyond the end of the current page are programmed from the start address of the same page (from the address whose 8 least significant bits (A7-A0) are all zero). Chip Select (S) must be driven Low for the entire duration of the sequence. The instruction sequence is shown in Figure 14. If more than 256 bytes are sent to the device, previously latched data are discarded and the last 256 data bytes are guaranteed to be programmed correctly within the same page. If less than 256 Data bytes are sent to device, they are correctly programmed at the requested addresses without having any effects on the other bytes of the same page. For optimized timings, it is recommended to use the Page Program (PP) instruction to program all consecutive targeted bytes in a single sequence versus using several Page Program (PP) sequences with each containing only a few bytes (see Instruction times, process technology T9HX (device grade 6) and Table 17: Instruction times (device grade 3)). Chip Select (S) must be driven High after the eighth bit of the last data byte has been latched in, otherwise the Page Program (PP) instruction is not executed. As soon as Chip Select (S) is driven High, the self-timed Page Program cycle (whose duration is tPP) is initiated. While the Page Program cycle is in progress, the Status Register may be read to check the value of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the self-timed Page Program cycle, and is 0 when it is completed. At some unspecified time before the cycle is completed, the Write Enable Latch (WEL) bit is reset. A Page Program (PP) instruction applied to a page which is protected by the Block Protect (BP2, BP1, BP0) bits (see Table 3 and Table 2) is not executed. 28/59 M25P40 Instructions Figure 14. Page Program (PP) instruction sequence S 0 1 2 3 4 5 6 7 8 28 29 30 31 32 33 34 35 36 37 38 39 9 10 C Instruction 24-Bit Address 23 22 21 D 3 2 Data Byte 1 1 0 7 6 5 4 3 2 1 0 MSB MSB 2078 2079 2077 2076 2075 2074 2073 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 2072 S 1 0 C Data Byte 2 D 7 6 MSB 5 4 3 2 Data Byte 3 1 0 7 MSB 6 5 4 3 2 Data Byte 256 1 0 7 6 5 4 3 2 MSB AI04082B 1. Address bits A23 to A19 are Don't Care. 29/59 Instructions 6.9 M25P40 Sector Erase (SE) The Sector Erase (SE) instruction sets to 1 (FFh) all bits inside the chosen sector. Before it can be accepted, a Write Enable (WREN) instruction must previously have been executed. After the Write Enable (WREN) instruction has been decoded, the device sets the Write Enable Latch (WEL). The Sector Erase (SE) instruction is entered by driving Chip Select (S) Low, followed by the instruction code, and three address bytes on Serial Data input (D). Any address inside the Sector (see Table 3) is a valid address for the Sector Erase (SE) instruction. Chip Select (S) must be driven Low for the entire duration of the sequence. The instruction sequence is shown in Figure 15. Chip Select (S) must be driven High after the eighth bit of the last address byte has been latched in, otherwise the Sector Erase (SE) instruction is not executed. As soon as Chip Select (S) is driven High, the self-timed Sector Erase cycle (whose duration is tSE) is initiated. While the Sector Erase cycle is in progress, the Status Register may be read to check the value of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the self-timed Sector Erase cycle, and is 0 when it is completed. At some unspecified time before the cycle is completed, the Write Enable Latch (WEL) bit is reset. A Sector Erase (SE) instruction applied to a page which is protected by the Block Protect (BP2, BP1, BP0) bits (see Table 3 and Table 2) is not executed. Figure 15. Sector Erase (SE) instruction sequence S 0 1 2 3 4 5 6 7 8 9 29 30 31 C Instruction D 24 Bit Address 23 22 2 1 0 MSB AI03751D 1. Address bits A23 to A19 are Don't Care. 30/59 M25P40 6.10 Instructions Bulk Erase (BE) The Bulk Erase (BE) instruction sets all bits to 1 (FFh). Before it can be accepted, a Write Enable (WREN) instruction must previously have been executed. After the Write Enable (WREN) instruction has been decoded, the device sets the Write Enable Latch (WEL). The Bulk Erase (BE) instruction is entered by driving Chip Select (S) Low, followed by the instruction code on Serial Data input (D). Chip Select (S) must be driven Low for the entire duration of the sequence. The instruction sequence is shown in Figure 16. Chip Select (S) must be driven High after the eighth bit of the instruction code has been latched in, otherwise the Bulk Erase instruction is not executed. As soon as Chip Select (S) is driven High, the self-timed Bulk Erase cycle (whose duration is tBE) is initiated. While the Bulk Erase cycle is in progress, the Status Register may be read to check the value of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the self-timed Bulk Erase cycle, and is 0 when it is completed. At some unspecified time before the cycle is completed, the Write Enable Latch (WEL) bit is reset. The Bulk Erase (BE) instruction is executed only if all Block Protect (BP2, BP1, BP0) bits are 0. The Bulk Erase (BE) instruction is ignored if one, or more, sectors are protected. Figure 16. Bulk Erase (BE) instruction sequence S 0 1 2 3 4 5 6 7 C Instruction D AI03752D 31/59 Instructions 6.11 M25P40 Deep Power-down (DP) Executing the Deep Power-down (DP) instruction is the only way to put the device in the lowest consumption mode (the Deep Power-down mode). It can also be used as an extra software protection mechanism, while the device is not in active use, since in this mode, the device ignores all Write, Program and Erase instructions. Driving Chip Select (S) High deselects the device, and puts the device in the Standby Power mode (if there is no internal cycle currently in progress). But this mode is not the Deep Power-down mode. The Deep Power-down mode can only be entered by executing the Deep Power-down (DP) instruction, subsequently reducing the standby current (from ICC1 to ICC2, as specified in Table 13). Once the device has entered the Deep Power-down mode, all instructions are ignored except the Release from Deep Power-down and Read Electronic Signature (RES) instruction. This releases the device from this mode. The Release from Deep Power-down and Read Electronic Signature (RES) instruction and the Read Identification (RDID) instruction also allow the Electronic Signature of the device to be output on Serial Data output (Q). The Deep Power-down mode automatically stops at Power-down, and the device always Powers-up in the Standby Power mode. The Deep Power-down (DP) instruction is entered by driving Chip Select (S) Low, followed by the instruction code on Serial Data input (D). Chip Select (S) must be driven Low for the entire duration of the sequence. The instruction sequence is shown in Figure 17. Chip Select (S) must be driven High after the eighth bit of the instruction code has been latched in, otherwise the Deep Power-down (DP) instruction is not executed. As soon as Chip Select (S) is driven High, it requires a delay of tDP before the supply current is reduced to ICC2 and the Deep Power-down mode is entered. Any Deep Power-down (DP) instruction, while an Erase, Program or Write cycle is in progress, is rejected without having any effects on the cycle that is in progress. Figure 17. Deep Power-down (DP) instruction sequence S 0 1 2 3 4 5 6 7 tDP C Instruction D Stand-by Mode Deep Power-down Mode AI03753D 32/59 M25P40 6.12 Instructions Release from Deep Power-down and Read Electronic Signature (RES) Once the device has entered the Deep Power-down mode, all instructions are ignored except the Release from Deep Power-down and Read Electronic Signature (RES) instruction. Executing this instruction takes the device out of the Deep Power-down mode. The instruction can also be used to read, on Serial Data output (Q), the 8-bit Electronic Signature, whose value for the M25P40 is 12h. Except while an Erase, Program or Write Status Register cycle is in progress, the Release from Deep Power-down and Read Electronic Signature (RES) instruction always provides access to the 8-bit Electronic Signature of the device, and can be applied even if the Deep Power-down mode has not been entered. Any Release from Deep Power-down and Read Electronic Signature (RES) instruction while an Erase, Program or Write Status Register cycle is in progress, is not decoded, and has no effect on the cycle that is in progress. The device is first selected by driving Chip Select (S) Low. The instruction code is followed by 3 dummy bytes, each bit being latched-in on Serial Data input (D) during the rising edge of Serial Clock (C). Then, the 8-bit Electronic Signature, stored in the memory, is shifted out on Serial Data output (Q), each bit being shifted out during the falling edge of Serial Clock (C). The instruction sequence is shown in Figure 18. The Release from Deep Power-down and Read Electronic Signature (RES) instruction is terminated by driving Chip Select (S) High after the Electronic Signature has been read at least once. Sending additional clock cycles on Serial Clock (C), while Chip Select (S) is driven Low, cause the Electronic Signature to be output repeatedly. When Chip Select (S) is driven High, the device is put in the Standby Power mode. If the device was not previously in the Deep Power-down mode, the transition to the Standby Power mode is immediate. If the device was previously in the Deep Power-down mode, though, the transition to the Standby Power mode is delayed by tRES2, and Chip Select (S) must remain High for at least tRES2(max), as specified in Table 19. Once in the Standby Power mode, the device waits to be selected, so that it can receive, decode and execute instructions. Driving Chip Select (S) High after the 8-bit instruction byte has been received by the device, but before the whole of the 8-bit Electronic Signature has been transmitted for the first time (as shown in Figure 19), still ensures that the device is put into Standby Power mode. If the device was not previously in the Deep Power-down mode, the transition to the Standby Power mode is immediate. If the device was previously in the Deep Power-down mode, though, the transition to the Standby Power mode is delayed by tRES1, and Chip Select (S) must remain High for at least tRES1(max), as specified in Table 19. Once in the Standby Power mode, the device waits to be selected, so that it can receive, decode and execute instructions. 33/59 Instructions M25P40 Figure 18. Release from Deep Power-down and Read Electronic Signature (RES) instruction sequence and data-out sequence S 0 1 2 3 4 5 6 7 8 28 29 30 31 32 33 34 35 36 37 38 9 10 C Instruction tRES2 3 Dummy Bytes 23 22 21 D 3 2 1 0 MSB Electronic Signature Out High Impedance 7 Q 6 5 4 3 2 1 0 MSB Deep Power-down Mode Stand-by Mode AI04047C 1. The value of the 8-bit Electronic Signature, for the M25P40, is 12h. Figure 19. Release from Deep Power-down (RES) instruction sequence S 0 1 2 3 4 5 6 7 tRES1 C Instruction D High Impedance Q Deep Power-down Mode Stand-by Mode AI04078B 34/59 M25P40 7 Power-up and Power-down Power-up and Power-down At Power-up and Power-down, the device must not be selected (that is Chip Select (S) must follow the voltage applied on VCC) until VCC reaches the correct value: VCC(min) at Power-up, and then for a further delay of tVSL VSS at Power-down A safe configuration is provided in Section 3: SPI modes. To avoid data corruption and inadvertent write operations during power-up, a Power On Reset (POR) circuit is included. The logic inside the device is held reset while VCC is less than the Power On Reset (POR) threshold voltage, VWI - all operations are disabled, and the device does not respond to any instruction. Moreover, the device ignores all Write Enable (WREN), Page Program (PP), Sector Erase (SE), Bulk Erase (BE) and Write Status Register (WRSR) instructions until a time delay of tPUW has elapsed after the moment that VCC rises above the VWI threshold. However, the correct operation of the device is not guaranteed if, by this time, VCC is still below VCC(min). No Write Status Register, Program or Erase instructions should be sent until the later of: tPUW after VCC passed the VWI threshold tVSL after VCC passed the VCC(min) level These values are specified in Table 9. If the delay, tVSL, has elapsed, after VCC has risen above VCC(min), the device can be selected for READ instructions even if the tPUW delay is not yet fully elapsed. At Power-up, the device is in the following state: The device is in the Standby Power mode (not the Deep Power-down mode). The Write Enable Latch (WEL) bit is reset. The Write In Progress (WIP) bit is reset. Normal precautions must be taken for supply rail decoupling, to stabilize the VCC supply. Each device in a system should have the VCC rail decoupled by a suitable capacitor close to the package pins. (Generally, this capacitor is of the order of 100 nF). At Power-down, when VCC drops from the operating voltage, to below the Power On Reset (POR) threshold voltage, VWI, all operations are disabled and the device does not respond to any instruction. (The designer needs to be aware that if a Power-down occurs while a Write, Program or Erase cycle is in progress, some data corruption can result.) 35/59 Power-up and Power-down M25P40 Figure 20. Power-up timing VCC VCC(max) Program, Erase and Write Commands are Rejected by the Device Chip Selection Not Allowed VCC(min) tVSL Reset State of the Device Read Access allowed Device fully accessible VWI tPUW time AI04009C Table 8. Power-up timing and VWI threshold Symbol tVSL(1) tPUW (1) VWI(1) Parameter Max. Unit VCC (min) to S low 10 Time delay to Write instruction 1 10 ms Write Inhibit voltage (device grade 6) 1 2.1 V Write Inhibit voltage (device grade 3) 2.1 2.1 V 1. These parameters are characterized only. 36/59 Min. s M25P40 8 Initial delivery state Initial delivery state The device is delivered with the memory array erased: all bits are set to 1 (each byte contains FFh). The Status Register contains 00h (all Status Register bits are 0). 9 Maximum rating Stressing the device above the rating listed in the Absolute maximum ratings table may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Refer also to the Numonyx SURE Program and other relevant quality documents. Table 9. Absolute maximum ratings Symbol TSTG TLEAD Parameter Storage temperature Max. Unit -65 150 C (1) C -0.6 VCC + 0.6 V -0.6 4.0 V -2000 2000 V Lead temperature during soldering VIO Input and output voltage (with respect to Ground) (2) VCC Supply voltage VESD Min. see (3) Electrostatic Discharge voltage (Human Body model) 1. Compliant with JEDEC Std J-STD-020C (for small body, Sn-Pb or Pb assembly), the ST ECOPACK(R) 7191395 specification, and the European directive on Restrictions on Hazardous Substances (RoHS) 2002/95/EU. 2. The minimum voltage may reach the value of -2 V for no more than 20 ns during transitions; The maximum voltage may reach the value of VCC+2 V for no more than 20 ns during transitions.. 3. JEDEC Std JESD22-A114A (C1 = 100 pF, R1 = 1500 , R2 = 500 ). 37/59 DC and AC parameters 10 M25P40 DC and AC parameters This section summarizes the operating and measurement conditions, and the DC and AC characteristics of the device. The parameters in the DC and AC characteristic tables that follow are derived from tests performed under the Measurement Conditions summarized in the relevant tables. Designers should check that the operating conditions in their circuit match the measurement conditions when relying on the quoted parameters. Table 10. Operating conditions Symbol VCC TA Table 11. Parameter Min. Max. Unit Supply voltage 2.3 3.6 V Ambient operating temperature (device grade 6) -40 85 Ambient operating temperature (device grade 3) -40 125 Data retention and endurance Parameter Condition Min. Erase/Program cycles Device grade 6 100,000 Device grade 3 10,000 Data Retention at 55C Table 12. Symbol Max. Unit cycles per sector 20 years Capacitance(1) Parameter COUT Output capacitance (Q) CIN Input capacitance (other pins) Test condition Max. Unit VOUT = 0 V 8 pF VIN = 0 V 6 pF 1. Sampled only, not 100% tested, at TA=25 C and a frequency of 25 MHz. 38/59 C Min. M25P40 DC and AC parameters Table 13. Symbol DC characteristics (device grade 6) Parameter Test condition (in addition to those in Table 10) Min. Max. Unit ILI Input leakage current 2 A ILO Output leakage current 2 A ICC1 Standby current S = VCC, V IN = VSS or VCC 50 A ICC2 Deep Power-down current S = VCC, V IN = VSS or VCC 10 A C = 0.1VCC / 0.9.VCC at 40 MHz and 75 MHz, Q = open 8 mA C = 0.1VCC / 0.9.VCC at 25 MHz, Q = open 4 mA ICC3 Operating current (READ) ICC4 Operating current (PP) S = VCC 15 mA ICC5 Operating current (WRSR) S = VCC 15 mA ICC6 Operating current (SE) S = VCC 15 mA ICC7 Operating current (BE) S = VCC 15 mA VIL Input low voltage -0.5 0.3VCC V VIH Input high voltage 0.7VCC VCC+0.4 V VOL Output low voltage IOL = 1.6 mA 0.4 V VOH Output high voltage IOH = -100 A VCC-0.2 V 39/59 DC and AC parameters Table 14. M25P40 DC characteristics (device grade 3) Symbol Test condition (in addition to those in Table 10) Parameter Min(1) Max(1) Unit ILI Input leakage current 2 A ILO Output leakage current 2 A ICC1 Standby current S = VCC, VIN = VSS or VCC 100 A ICC2 Deep Power-down current S = VCC, VIN = VSS or VCC 50 A C = 0.1VCC / 0.9.VCC at 25 MHz, Q = open 8 mA C = 0.1VCC / 0.9.VCC at 20 MHz, Q = open 4 mA ICC3 Operating current (READ) ICC4 Operating current (PP) S = VCC 15 mA ICC5 Operating current (WRSR) S = VCC 15 mA ICC6 Operating current (SE) S = VCC 15 mA ICC7 Operating current (BE) S = VCC 15 mA VIL Input low voltage - 0.5 0.3VCC V VIH Input high voltage 0.7VCC VCC+0.4 V VOL Output low voltage IOL = 1.6 mA 0.4 V VOH Output high voltage IOH = -100 A VCC-0.2 V 1. This is preliminary data. Table 15. Instruction times, process technology T9HX(1) (device grade 6) Test conditions specified in Table 10 and Table 18 Symbol tW tPP (2) Alt. Parameter Typ. Max. Unit Write Status Register cycle time 1.3 15 ms Page Program cycle time (256 bytes) 0.8 int (n/8) x 0.025 (2) 5 ms Page Program cycle time (n bytes) Min. tSE Sector Erase cycle time 0.6 3 s tBE Bulk Erase cycle time 4.5 10 s 1. Technology T9HX devices are identified by process identification digit "4" in the device marking and process letter "B" in the part number. 2. When using the Page Program (PP) instruction to program consecutive bytes, optimized timings are obtained with one sequence including all the bytes versus several sequences of only a few bytes. (1 n 256) 40/59 M25P40 DC and AC parameters Table 16. Instruction times, process technology T7Y(1) (device grade 6) Test conditions specified in Table 10 and Table 18 Symbol Alt. Parameter Min. Typ. Max. Unit 5 15 ms 0.4+n*1/ 256(2) 5 ms 1 3 s 4.5 10 s Write Status Register cycle time tW Page Program cycle time (256 bytes) tPP 1.4 (2) Page Program cycle time (n bytes) tSE Sector Erase cycle time tBE Bulk Erase cycle time 1. Technology T7Y devices are identified by process identification digit "X" in the device marking. 2. When using the Page Program (PP) instruction to program consecutive bytes, optimized timings are obtained with one sequence including all the bytes versus several sequences of only a few bytes. (1 n 256) Table 17. Instruction times (device grade 3) Test conditions specified in Table 10 and Table 18 Symbol Alt. Parameter Min. Typ.(1) (2) Max.(2) Unit 8 15 ms 0.4+ n*1.1/256 5 ms 1 3 s 4.5 10 s Write Status Register cycle time tW Page Program cycle time (256 bytes) tPP(3) 1.5 Page Program cycle time (n bytes) tSE Sector Erase cycle time tBE Bulk Erase cycle time 1. At 85 C 2. Preliminary data. 3. When using the Page Program (PP) instruction to program consecutive bytes, optimized timings are obtained with one sequence including all the bytes versus several sequences of only a few bytes. (1 n 256) Table 18. Symbol CL AC measurement conditions Parameter Min. Load capacitance Max. 30 Input rise and fall times Unit pF 5 ns Input pulse voltages 0.2VCC to 0.8VCC V Input timing reference voltages 0.3VCC to 0.7VCC V VCC / 2 V Output timing reference voltages 1. Output Hi-Z is defined as the point where data out is no longer driven. 41/59 DC and AC parameters M25P40 Figure 21. AC measurement I/O waveform Input Levels 0.8VCC 0.2VCC Input and Output Timing Reference Levels 0.7VCC 0.5VCC 0.3VCC AI07455 42/59 M25P40 DC and AC parameters Table 19. AC characteristics (25 MHz operation, device grade 3, VCC min = 2.7 V) Test conditions specified in Table 10 and Table 18 Symbol Alt. Parameter Min. fC fC Clock frequency for the following instructions: FAST_READ, PP, SE, BE, DP, RES, WREN, WRDI, RDSR, WRSR Clock frequency for READ instructions fR Typ. Max. Unit D.C. 25 MHz D.C. 20 MHz tCH(1) tCL(1) tCLCH(2) tCHCL(2) tCLH Clock High time 18 ns tCLL Clock Low time 18 ns 0.1 V/ns 0.1 V/ns tSLCH tCSS S Active Setup time (relative to C) 10 ns S Not Active Hold time (relative to C) 10 ns Clock Rise time (3) (3) Clock Fall time tCHSL (peak to peak) (peak to peak) tDVCH tDSU Data In Setup time 5 ns tCHDX tDH Data In Hold time 5 ns tCHSH S Active Hold time (relative to C) 10 ns tSHCH S Not Active Setup time (relative to C) 10 ns 100 ns tSHSL tCSH S Deselect time tSHQZ(2) tDIS Output Disable time 15 ns tCLQV tV Clock Low to Output Valid 15 ns tCLQX tHO Output Hold time 0 ns tHLCH HOLD Setup time (relative to C) 10 ns tCHHH HOLD Hold time (relative to C) 10 ns tHHCH HOLD Setup time (relative to C) 10 ns tCHHL HOLD Hold time (relative to C) 10 ns tHHQX(2) tHLQZ(2) tWHSL(4) tSHWL(4) tDP(2) tLZ HOLD to Output Low-Z 15 ns tHZ HOLD to Output High-Z 20 ns Write Protect Setup time 20 ns Write Protect Hold time 100 ns S High to Deep Power-down mode tRES1(2) S High to Standby Power mode without Electronic Signature Read tRES2(2) S High to Standby Power mode with Electronic Signature Read 3 s 3 or 30(5) s 1.8 or 30(5) s 1. tCH + tCL must be greater than or equal to 1/ fC 2. Value guaranteed by characterization, not 100% tested in production. 3. Expressed as a slew-rate. 4. Only applicable as a constraint for a WRSR instruction when SRWD is set at 1. 5. It is 30 s in devices produced with the "X" process technology (grade 3 devices are only produced using the "X" process technology). Details of how to find the process letter on the device marking are given in the Application note AN1995. 43/59 DC and AC parameters Table 20. M25P40 AC characteristics (50 MHz operation, device grade 6, VCC min = 2.7 V) Test conditions specified in Table 10 and Table 18 Symbol Alt. Parameter Min. fC fC Clock frequency for the following instructions: FAST_READ, PP, SE, BE, DP, RES, WREN, RDID, WRDI, RDSR, WRSR Clock frequency for READ instructions fR Max. Unit D.C. 50 MHz D.C. 25 MHz tCH(1) tCLH Clock High time 9 ns tCL(1) tCLL Clock Low time 9 ns 0.1 V/ns 0.1 V/ns S Active Setup time (relative to C) 5 ns S Not Active Hold time (relative to C) 5 ns tCLCH(2) Clock Rise tCHCL(2) tSLCH time (3) Clock Fall time tCSS tCHSL (3) (peak to peak) (peak to peak) tDVCH tDSU Data In Setup time 2 ns tCHDX tDH Data In Hold time 5 ns tCHSH S Active Hold time (relative to C) 5 ns tSHCH S Not Active Setup time (relative to C) 5 ns 100 ns tSHSL tCSH S Deselect time tSHQZ(2) tDIS Output Disable time 8 ns tCLQV tV Clock Low to Output Valid 8 ns tCLQX tHO Output Hold time 0 ns tHLCH HOLD Setup time (relative to C) 5 ns tCHHH HOLD Hold time (relative to C) 5 ns tHHCH HOLD Setup time (relative to C) 5 ns tCHHL HOLD Hold time (relative to C) 5 ns tHHQX(2) tLZ HOLD to Output Low-Z 8 ns tHLQZ(2) tHZ HOLD to Output High-Z 8 ns tWHSL(4) Write Protect Setup time 20 ns tSHWL(4) Write Protect Hold time 100 ns tDP(2) S High to Deep Power-down mode 3 s tRES1(2) S High to Standby Power mode without Electronic Signature Read 30 s tRES2(2) S High to Standby Power mode with Electronic Signature Read 30 s 1. tCH + tCL must be greater than or equal to 1/ fC 2. Value guaranteed by characterization, not 100% tested in production. 3. Expressed as a slew-rate. 4. Only applicable as a constraint for a WRSR instruction when SRWD is set at 1. 44/59 Typ. M25P40 DC and AC parameters Table 21. AC characteristics (*40 MHz operation, device grade 6, VCC min = 2.3 V) Extended VCC range available only in products with Process Technology code X and 4 Test conditions specified in Table 10 and Table 18 Symbol Alt. Parameter Min. fC fC Clock frequency for the following instructions: FAST_READ, PP, SE, BE, DP, RES, WREN, RDID, WRDI, RDSR, WRSR Clock frequency for READ instructions fR Typ. (1) Max. Unit D.C. 40 MHz D.C. 25 MHz tCH(2) tCL(1) tCLCH(3) tCHCL(2) tCLH Clock High time 11 ns tCLL Clock Low time 11 ns 0.1 V/ns 0.1 V/ns tSLCH tCSS S Active Setup time (relative to C) 5 ns S Not Active Hold time (relative to C) 5 ns Clock Rise time Clock Fall time tCHSL (4) (3) (peak to peak) (peak to peak) tDVCH tDSU Data In Setup time 2 ns tCHDX tDH Data In Hold time 5 ns tCHSH S Active Hold time (relative to C) 5 ns tSHCH S Not Active Setup time (relative to C) 5 ns 100 ns tSHSL tCSH S Deselect time tSHQZ(2) tDIS Output Disable time 8 ns tCLQV tV Clock Low to Output Valid 8 ns tCLQX tHO Output Hold time 0 ns tHLCH HOLD Setup time (relative to C) 5 ns tCHHH HOLD Hold time (relative to C) 5 ns tHHCH HOLD Setup time (relative to C) 5 ns tCHHL HOLD Hold time (relative to C) 5 ns tHHQX(2) tHLQZ(2) tWHSL(5) tSHWL(4) tDP(2) tLZ HOLD to Output Low-Z 8 ns tHZ HOLD to Output High-Z 8 ns Write Protect Setup time 20 ns Write Protect Hold time 100 ns S High to Deep Power-down mode 3 s tRES1(2) S High to Standby Power mode without Electronic Signature Read 30 s tRES2(2) S High to Standby Power mode with Electronic Signature Read 30 s 1. Details of how to find the date of marking are given in Application Note, AN1995. 2. tCH + tCL must be greater than or equal to 1/ fC 3. Value guaranteed by characterization, not 100% tested in production. 4. Expressed as a slew-rate. 5. Only applicable as a constraint for a WRSR instruction when SRWD is set at 1. Note: *40 MHz = max frequency device operation in extended Vcc range 2.3 to 2.7 V. 45/59 DC and AC parameters Table 22. M25P40 AC characteristics, grade 6 (T9HX technology), 75 MHz operation, VCC min = 2.7 V Applies only to products made with T9HX technology, identified with process digit `4' and process letter "B" in the part number (1) (2) Test conditions specified in Table 10 and Table 12 Symbol Alt. fC fC fR Parameter Min Max Unit Clock frequency for the following instructions: FAST_READ, PP, SE, BE, DP, RES, WREN, WRDI, RDID, RDSR, WRSR D.C. 75 MHz Clock frequency for READ instructions D.C. 33 MHz tCH(4) tCLH Clock High time 6 ns tCL(3) tCLL Clock Low time 6 ns 0.1 V/ns 0.1 V/ns 5 ns 5 ns tCLCH(5) Clock Rise time tCHCL(5) Clock Fall time(6) (peak to peak) tSLCH (6) (peak to peak) tCSS S Active Setup time (relative to C) tCHSL S Not Active Hold time (relative to C) tDVCH tDSU Data In Setup time 2 ns tCHDX tDH Data In Hold time 5 ns tCHSH S Active Hold time (relative to C) 5 ns tSHCH S Not Active Setup time (relative to C) 5 ns 100 ns tSHSL tCSH S Deselect time tSHQZ(5) tDIS Output Disable time tCLQV tCLQX tV Clock Low to Output Valid under 30 pF/10 pF tHO Output Hold time 8 ns 8/6 ns 0 ns tHLCH HOLD Setup time (relative to C) 5 ns tCHHH HOLD Hold time (relative to C) 5 ns tHHCH HOLD Setup time (relative to C) 5 ns tCHHL HOLD Hold time (relative to C) 5 ns tHHQX(5) tLZ HOLD to Output Low-Z 8 ns tHLQZ(5) tHZ HOLD to Output High-Z 8 ns tWHSL(7) Write Protect Setup time 20 ns tSHWL(7) Write Protect Hold time 100 ns tDP(5) 46/59 Typ(3) S High to Deep Power-down mode 3 s tRES1(5) S High to Standby mode without Read Electronic Signature 30 s tRES2(5) S High to Standby mode with Read Electronic Signature 30 s M25P40 DC and AC parameters 1. Details of how to find the technology process in the marking are given in AN1995, see also Section 12: Part numbering. 2. 75 MHz operation is available only on the VCC range 2.7 V - 3.6 V; the maximum frequency in the extended Vcc range 2.3 V to 2.7 V is 40 MHz. 3. Typical values given for TA = 25 C. 4. tCH + tCL must be greater than or equal to 1/ fC. 5. Value guaranteed by characterization, not 100% tested in production. 6. Expressed as a slew-rate. 7. Only applicable as a constraint for a WRSR instruction when SRWD is set at `1'. Figure 22. Serial input timing tSHSL S tCHSL tSLCH tCHSH tSHCH C tDVCH tCHCL tCHDX D Q MSB IN tCLCH LSB IN High Impedance Figure 23. Write Protect setup and hold timing during WRSR when SRWD = 1 W tSHWL tWHSL S C D High Impedance Q AI07439 47/59 DC and AC parameters M25P40 Figure 24. Hold timing S tHLCH tCHHL tHHCH C tCHHH tHLQZ tHHQX Q D HOLD AI02032 Figure 25. Output timing S tCH C tCLQV tCLQX tCLQV tCL tSHQZ tCLQX LSB OUT Q tQLQH tQHQL D ADDR. LSB IN AI01449e 48/59 M25P40 11 Package mechanical Package mechanical 40 MHz is the maximum frequency for the devices operation in the extended Vcc range 2.3 V to 2.7 V. Figure 26. SO8 narrow - 8 lead plastic Small Outline, 150 mils body width, package outline h x 45 A2 A c ccc b e 0.25 mm GAUGE PLANE D k 8 E1 E 1 L A1 L1 SO-A 1. Drawing is not to scale. 2. The `1' that appears in the top view of the package shows the position of pin 1. Table 23. SO8 narrow - 8 lead plastic Small Outline, 150 mils body width, package mechanical data millimeters inches Symbol Typ Min A Max Typ Min 1.75 Max 0.069 A1 0.10 A2 1.25 b 0.28 0.48 0.011 0.019 c 0.17 0.23 0.007 0.009 ccc 0.25 0.004 0.010 0.049 0.10 0.004 D 4.90 4.80 5.00 0.193 0.189 0.197 E 6.00 5.80 6.20 0.236 0.228 0.244 E1 3.90 3.80 4.00 0.154 0.150 0.157 e 1.27 - - 0.050 - - h 0.25 0.50 0.010 0.020 k 0 8 0 8 L 0.40 1.27 0.016 0.050 L1 1.04 0.041 49/59 Package mechanical M25P40 Figure 27. SO8W - 8 lead plastic small outline, 208 mils body width, package outline A2 A c b CP e D N E E1 1 A1 k L 6L_ME 1. Drawing is not to scale. Table 24. SO8 wide - 8 lead plastic small outline, 208 mils body width, package mechanical data millimeters inches Symbol Typ Min A Typ Min 2.50 Max 0.098 A1 0.00 0.25 0.000 0.010 A2 1.51 2.00 0.059 0.079 b 0.40 0.35 0.51 0.016 0.014 0.020 c 0.20 0.10 0.35 0.008 0.004 0.014 CP 0.10 0.004 D 6.05 0.238 E 5.02 6.22 0.198 0.245 E1 7.62 8.89 0.300 0.350 - - - - k 0 10 0 10 L 0.50 0.80 0.020 0.031 N 8 e 50/59 Max 1.27 0.050 8 M25P40 Package mechanical Figure 28. QFN8L (MLP8) 8-lead, dual flat package no lead, 6 x 5 mm, package outline E E2 0PIN 1 ID OPTION L D D2 b e A E2/2 A3 A1 0.08 5X_ME 1. Drawing is not to scale. Table 25. QFN8L (MLP8) 8-lead dual flat package no lead, 6 x 5 mm package mechanical data millimeters inches Symbol Typ Min Max Typ Min Max A 0.90 0.80 1.00 0.035 0.031 0.039 A1 0.02 0.00 0.05 0.001 0.000 0.002 A3 0.20 b 0.40 0.014 0.019 D 6.00 D2 3.00 0.110 0.126 E 5.00 E2 3.00 0.110 0.126 e 1.27 L 0.60 0.020 0.030 0.008 0.35 0.48 0.016 0.236 2.80 3.20 0.118 0.197 2.80 3.20 0.118 0.050 0.50 0.75 0.024 51/59 Package mechanical M25P40 Figure 29. VFQFPN8 (MLP8) 8-lead Very thin Fine pitch Quad Flat Package No lead, 6 x 5 mm, package outline A D aaa C A R1 D1 E1 E2 e bbb E M C A B B 2x b aaa C B 0.10 C B D2 0.10 C A L A2 ddd A C A1 A3 70-ME 1. Drawing is not to scale. 2. The circle in the top view of the package indicates the position of pin 1. Table 26. VFQFPN8 (MLP8) 8-lead Very thin Fine pitch Quad Flat Package No lead, 6 x 5 mm, package mechanical data millimeters inches Symbol A Typ Min Max Typ Min Max 0.85 0.80 1.00 0.0335 0.0315 0.0394 0.00 0.05 0.0000 0.0020 0.0138 0.0189 0.1260 0.1417 A1 52/59 A2 0.65 0.0256 A3 0.20 0.0079 b 0.40 D 6.00 0.2362 D1 5.75 0.2264 D2 3.40 E 5.00 0.1969 E1 4.75 0.1870 E2 4.00 3.80 4.30 0.1575 0.1496 0.1693 e 1.27 - - 0.0500 - - R1 0.10 0.00 0.0039 0.0000 L 0.60 0.50 0.0236 0.0197 0.35 3.20 0.48 3.60 0.75 0.0157 0.1339 0.0295 Q 12 12 aaa 0.15 0.0059 bbb 0.10 0.0039 ddd 0.05 0.0020 M25P40 12 Part numbering Part numbering Table 27. Ordering information scheme Example: M25P40 - V MN 6 T P B Device Type M25P = Serial Flash memory for Code Storage Device Function 40 = 4 Mbit (512 K x 8) Security features(1) - = no extra security S = CFD programmed with UID Operating Voltage V = VCC = 2.3 V to 3.6 V Package MN = SO8 (150 mil width) MP = VFQFPN8 6 x 5 mm (MLP8) MW = SO8W (208 mils width) MS = QFN8L (MLP8)(2), 6 x 5 mm Device grade 6 = Industrial temperature range, -40 to 85 C. Device tested with standard test flow 3(3) = Device tested with High Reliability Certified Flow(4) . Automotive temperature range (-40 to 125 C) Option blank = Standard Packing T = Tape and Reel Packing Plating technology P or G = ECOPACK(R) (RoHS compliant) Process(5) /X = T7Y B = T9HX 1. Secure options are available upon customer request. 2. Exposed pad of 3 x 3 mm. 3. Device grade 3 available in an SO8 ECOPACK(R) (RoHS compliant) package. 4. Numonyx strongly recommends the use of the Automotive Grade devices for use in an automotive environment. The High Reliability Certified Flow (HRCF) is described in the quality note QNEE9801. Please ask your nearest Numonyx sales office for a copy. 53/59 Part numbering M25P40 5. The process letter (/X) is specified in the ordering information of grade 3 devices only. For grade 6 devices, the process letter does not appear in the Ordering Information, it only appears on the device package (marking) and on the shipment box. Please contact your nearest Numonyx Sales Office. For more information on how to identify products by the Process Identification Letter, please refer to AN1995: Serial Flash Memory Device Marking. For a list of available options (speed, package, etc.) or for further information on any aspect of this device, please contact your nearest Numonyx Sales Office. The category of second-Level Interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. 54/59 M25P40 13 Revision history Revision history Table 28. Document revision history Date Revision 12-Apr-2001 1.0 Document written. 25-May-2001 1.1 Serial Paged Flash Memory renamed as Serial Flash Memory. 1.2 Changes to text: Signal Description/Chip Select; Hold Condition/1st para; Protection modes; Release from Power-down and Read Electronic Signature (RES); Power-up. Repositioning of several tables and illustrations without changing their contents. Power-up timing illustration; SO8W package removed. Changes to tables: Abs Max Ratings/VIO ; DC Characteristics/VIL. 1.3 FAST_READ instruction added. Document revised with new timings, VWI, ICC3 and clock slew rate. Descriptions of Polling, Hold Condition, Page Programming, Release for Deep Power-down made more precise. Value of tW(max) modified. 1.4 Clarification of descriptions of entering Standby Power mode from Deep Power-down mode, and of terminating an instruction sequence or dataout sequence. VFQFPN8 package (MLP8) added. Document promoted to Preliminary Data. 13-Dec-2002 1.5 Typical Page Program time improved. Deep Power-down current changed. Write Protect setup and hold times specified, for applications that switch Write Protect to exit the Hardware Protection mode immediately before a WRSR, and to enter the Hardware Protection mode again immediately after. 12-Jun-2003 1.6 Document promoted from Preliminary Data to full Datasheet. 24-Nov-2003 2.0 Table of contents, warning about exposed paddle on MLP8, and Pb-free options added. 40 MHz AC Characteristics table included as well as 25 MHz. ICC3(max), tSE(typ) and tBE (typ) values improved. Change of naming for VDFPN8 package. 12-Mar-2004 3.0 Automotive range added. Soldering temperature information clarified for RoHS compliant devices. 05-Aug-2004 4.0 Device grade information clarified. Data-retention measurement temperature corrected. Details of how to find the date of marking added. 03-Jan-2005 5.0 Small text changes. Notes 2 and 3 removed from Table 27: Ordering information scheme. End timing line of tSHQZ modified in Figure 25: Output timing. 01-Aug-2005 6.0 Updated Page Program (PP) instructions in Page Programming, Page Program (PP), Instruction times, process technology T9HX (device grade 6) and Instruction times (device grade 3). 11-Sep-2001 16-Jan-2002 12-Sep-2002 Changes 55/59 Revision history Table 28. M25P40 Document revision history (continued) Date 24-Oct-2005 22-Dec-2005 14-Apr-2006 05-Jun-2006 18-Dec-2006 25-Jan-2007 15-May-2007 56/59 Revision Changes 7.0 50 MHz operation added (see Table 20: AC characteristics (50 MHz operation, device grade 6, VCC min = 2.7 V)). All packages are ECOPACK(R). Blank option removed from under Plating technology in Table 27: Ordering information scheme. MLP package renamed as VFQFPN, silhouette and package mechanical drawing updated (see on page 1 and Figure 29: VFQFPN8 (MLP8) 8-lead Very thin Fine pitch Quad Flat Package No lead, 6 x 5 mm, package outline. 8.0 Note 2 added below Figure 26 and note 3 added below Figure 29 tRES1 and tRES2 modified in Table 20: AC characteristics (50 MHz operation, device grade 6, VCC min = 2.7 V). Read Identification (RDID) added. Titles of Figure 29 and Table 26 corrected. 9 The data contained in Table 11, Table 17 and Table 19 is no longer preliminary data. Figure 3: Bus Master and memory devices on the SPI bus modified and Note 2 added. 40 MHz frequency condition modified for ICC3 in Table 14: DC characteristics (device grade 3). Table 17: Instruction times (device grade 3) shows preliminary data. Condition changed for the Data Retention parameter in Table 11: Data retention and endurance. VWI parameter for device grade 3 added to Table 8: Power-up timing and VWI threshold. SO8 package specifications updated (see Figure 26 and Table 23). /X Process added to Table 27: Ordering information scheme. 10 tRES1 and tRES2 parameter timings changed for devices produced with the "X" process technology in Table 19 and Table 19. SO8 Narrow package specifications updated (see Figure 26 and Table 23). 11 Hardware Write Protection feature added on page 1. Small text changes. Section 2.7: VCC supply voltage and Section 2.8: VSS ground added. Figure 3: Bus Master and memory devices on the SPI bus modified, note 2 removed and replaced by explanatory paragraph. WIP bit behavior specified at Power-up in Section 7: Power-up and Power-down. TLEAD added to Table 9: Absolute maximum ratings and VIO max modified. VFQFPN8 package specifications updated (see Table 26 and Figure 29). 12 VCC voltage range from W17 2007 is extended to 2.3 V to 3.6 V. Table 21: AC characteristics (33 MHz operation, device grade 6, VCCmin =2.3 V) added. AC characteristics at 40 MHz removed. 13 40 MHz operation added (see Table 21: AC characteristics (*40 MHz operation, device grade 6, VCC min = 2.3 V). Removed the note below Table 10. Removed "AC characteristics (33 MHz operation, device grade 6, VCCmin =2.3 V)" Table. M25P40 Revision history Table 28. Document revision history (continued) Date Revision Changes 26-Jun-2007 14 Modified the note below Table 12. Changed test condition for ICC3 in Table 13. Changed clock frequency, from 20 to 25 MHz, in Table 20 and Table 21. 10-Dec-2007 15 Added Numonyx Branding. 16 Changed frequency up to 75 MHz (only in the standard Vcc range). Added new packages. Added UID/CFD protection. Extended Vcc range to 2.3 V. 15-Oct-2008 57/59 M25P40 Please Read Carefully: INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH NUMONYXTM PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN NUMONYX'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, NUMONYX ASSUMES NO LIABILITY WHATSOEVER, AND NUMONYX DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF NUMONYX PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. 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Contact your local Numonyx sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an order number and are referenced in this document, or other Numonyx literature may be obtained by visiting Numonyx's website at http://www.numonyx.com. Numonyx StrataFlash is a trademark or registered trademark of Numonyx or its subsidiaries in the United States and other countries. *Other names and brands may be claimed as the property of others. Copyright (c) 2008, Numonyx, B.V., All Rights Reserved. 58/58