Data Sheet AD9574
Rev. B | Page 27 of 35
REFERENCE CLOCK INPUTS
The REF0 and REF1 input channels provide for two operating
modes based on the scanned state of PPR0. Note that the
resulting mode applies to both the REF0 and REF1 channels.
That is, independent input mode selection is not an option.
In single-ended 3.3 V CMOS buffer mode, the user may
connect a 3.3 V clock source directly to the positive reference
input pin (REF0_P, for example). Note that in single-ended
mode, it is best to connect a 0.1 nF capacitor from the negative
input pin (REF0_N, for example) to GND.
In differential mode, the user may connect a differential clock
driver to the two reference input pins (REF0_P and REF0_N,
for example). Note that differential operation requires ac
coupling, that is, a series connected 0.1 nF capacitor from each
output of an external differential clock driver to the corresponding
reference input pin. This mode also supports a single-ended
1.8 V CMOS clock source by connecting the source to either of
the reference input pins (REF0_P or REF0_N, for example).
Connect the unused input pin to GND via a 0.1 nF capacitor.
MONITOR CLOCK INPUT
The MCLK_x pins are the monitor clock inputs and are intended
to accept a stable frequency reference source. The MCLK_x pins
are configurable as either single-ended 3.3 V CMOS or differen-
tial. The monitor clock accepts a fixed frequency of 0.008 MHz,
10 MHz, 19.44 MHz, 25 MHz, or 38.88 MHz. Note that the
monitor clock input frequency and receiver configuration
depend on the scanned state of PPR6 (see the PPR6—Monitor
Clock (MCLK_x) Input Configuration section for details).
A stable monitor clock frequency source supports the operation
of the reference monitor (see the Reference Monitor section).
Because the reference monitor relies on the precision and
stability of the monitor clock input signal, the user must ensure
the frequency accuracy of the monitor clock source.
REFERENCE SWITCHING
The AD9574 provides for manual reference switching
capability. Although the on-board reference monitor provides
the user with information regarding the status of the input
references, the device does not provide for automatic reference
switchover as a result of status changes. Rather, the REF_SEL pin
provides the user with manual reference switchover control. A
Logic 0 on the REF_SEL pin informs the internal reference
switching logic to make REF0 the active reference, whereas a
Logic 1 makes REF1 the active reference.
The switch to a new active reference does not occur
instantaneously with a corresponding change of state on the
REF_SEL pin. Instead, the reference switching logic notes the
request for a reference switch and waits for the opportune moment
to make the physical switch. This functionality ensures a minimal
frequency disturbance on the output clocks associated with the
integrated PLL (the OUT2 through OUT6 channels).
The reference switching logic provides information about which
reference channel (REF0 or REF1) is the currently active
reference via the REF_ACT output pin. The REF_ACT pin is
Logic 0 when REF0 is the active reference and Logic 1 when
REF1 is the active reference. Furthermore, the reference
switching logic indicates when the device is in the process of
performing a reference switchover via the REF_SW pin (that is,
REF_SW is Logic 1 when a reference switch is in progress). The
REF_SW pin assumes a Logic 1 state when REF_SEL changes
states and returns to a Logic 0 state when the device completes
the reference switchover process. See the Reference Switching
section for additional information.
Changing the state of the REF_SEL pin triggers the internal
state machine to perform the reference switching process.
Confirm (via the REF_ACT pin) that the device has switched to
the desired reference before a subsequent change of the
REF_SEL pin. Changing the state of the REF_SEL pin before the
internal state machine completes the reference switching
process may cause undesired results.
Because the reference switching logic waits for an optimal
switchover point rather than switching immediately, there is the
rare possibility that either or both references happen to fail
(resulting in a loss of reference (LOR) fault condition) just after
the user requests a reference switchover (via the REF_SEL pin),
but before the switching logic identifies the optimal switchover
point. In such an instance, the LOR condition associated with
either reference causes the internal state machine to stall and
the device fails to switch references, thereby retaining the
currently active reference. If the currently active reference fails,
the device loses lock, thereby necessitating a device reset. If the
requested reference fails, the device retains the currently active
reference, but switches to the requested reference if it becomes
available. Note that as long as a reference remains in an LOR
condition, the state machine remains stalled. Only a device reset
makes the state machine disregard the initial request to switch
references.
The REF_SEL pin determines which reference is the active
reference any time device power is cycled or the user asserts the
RESET pin.
REFERENCE MONITOR
An on-board reference frequency monitor provides the user
with a means to validate the frequency accuracy of the active
reference channel (REF0 or REF1) in real time. The REFMON pin
enables or disables the reference monitoring function (Logic 1
or Logic 0, respectively).
Apply a static and valid Logic 0 or Logic 1 level to the
REFMON pin. Do not allow the REFMON pin to float. Do not
toggle the REFMON pin during device operation.
When enabled, the reference monitor continuously tests the
frequency of the active reference by comparing it to the
frequency of the MCLK_x signal. The result of this comparison
appears on the REF_FHI and REF_FLO pins per Table 29.