TPS62081
1µH
10µF
2.3V .. 6V
VIN
22µF
180k
VOUT
POWER GOOD
1.8V
SW
VOS
VIN
EN
GND
MODE
PG
FB
TPS62080, TPS62080A
TPS62081, TPS62082
www.ti.com
SLVSAE8B –SEPTEMBER 2011–REVISED MARCH 2012
1.2A High Efficient Step Down Converter with Snooze Mode
Check for Samples: TPS62080,TPS62080A,TPS62081,TPS62082
1FEATURES DESCRIPTION
The TPS6208x devices are a family of high frequency
• DCS-ControlTM Architecture for Fast Transient synchronous step down converters. With an input
Regulation voltage range of 2.3V to 6.0V, common battery
• Snooze Mode for 6.5µA Ultra Low Quiescent technologies are supported. Alternatively, the device
Current can be used for low voltage system power rails.
• 2.3V to 6.0V Input Voltage Range The TPS6208x focuses on high efficient step down
• Supports High Output Capacitance up to conversion over a wide output current range. At
100µF medium to heavy loads, the converter operates in
PWM mode and automatically enters Power Save
• 100% Duty Cycle for Lowest Dropout Mode operation at light load currents to maintain high
• Power Save Mode for Light Load Efficiency efficiency over the entire load current range. To
• Output Discharge Function maintain high efficiency at very low load or no load
currents, a Snooze Mode with an ultra low quiescent
• Short Circuit Protection current is implemented, that is enabled by the Mode
• Power Good Output pin. This function increases the run-time of battery
• Thermal Shutdown driven applications and keeps the standby current at
its lowest level to meet green energy standards
• Available in 2x2mm 8-Pin SON Package and targeting for a low stand-by current.
VSSOP Package To address the requirements of system power rails,
APPLICATIONS the internal compensation circuit allows a large
selection of external output capacitor values ranging
• Battery Powered Portable Devices from 10µF up to 100uF effective capacitance. With its
• Point of Load Regulators DCS-ControlTM architecture excellent load transient
• System Power Rail Voltage Conversion performance and output voltage regulation accuracy
is achieved. The device is available in 2x2mm SON
package and VSSOP package with Thermal PAD.
Figure 1. Typical Application of TPS62081 (1.8V Fixed Output)
1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
UNLESS OTHERWISE NOTED this document contains Copyright © 2011–2012, Texas Instruments Incorporated
PRODUCTION DATA information current as of publication date.
Products conform to specifications per the terms of Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
TPS62080, TPS62080A
TPS62081, TPS62082
SLVSAE8B –SEPTEMBER 2011–REVISED MARCH 2012
www.ti.com
Table 1. ORDERING INFORMATION
TAOUTPUT VOLTAGE(1) PACKAGE MARKING PACKAGE PART NUMBER(2)
Adjustable QVR 8-Pin SON TPS62080DSG
1.8 V QVS 8-Pin SON TPS62081DSG
–40°C to 85°C 3.3 V QVT 8-Pin SON TPS62082DSG
Adjustable SBN 8-Pin SON TPS62080ADSG
Adjustable 8-Pin VSSOP TPS62080ADGN(3)
(1) Contact the factory to check availability of other fixed output voltage versions.
(2) For detailed ordering information please check the PACKAGE OPTION ADDENDUM section at the end of this datasheet.
(3) Product Preview
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted)(1)
VALUE UNIT
Voltage range at VIN, PG, VOS(2) –0.3 to 7 V
Voltage range at SW(2)(3) –1 to 7 V
Voltage range at FB(2) –0.3 to 3.6 V
Voltage range at EN, MODE(2) –0.3 to (VIN + 0.3V) V
ESD rating, Human Body Model 2 kV
ESD rating, Charged Device Model 500 V
Continuous total power dissipation See Dissipation Rating Table
Operating junction temperature range, TJ–40 to 150 °C
Operating ambient temperature range, TA–40 to 85 °C
Storage temperature range, Tstg –65 to 150 °C
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute–maximum–rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to network ground terminal.
(3) During operation, device switching
THERMAL INFORMATION TPS62080
THERMAL METRIC(1) UNITS
DSG (8 PINS)
θJA Junction-to-ambient thermal resistance 65.1
θJCtop Junction-to-case (top) thermal resistance 100.7
θJB Junction-to-board thermal resistance 135.7 °C/W
ψJT Junction-to-top characterization parameter 2.3
ψJB Junction-to-board characterization parameter 45.1
θJCbot Junction-to-case (bottom) thermal resistance 8.6
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
RECOMMENDED OPERATING CONDITIONS(1)
MIN TYP MAX UNIT
VIN Input voltage range, VIN 2.3 6.0 V
VOUT Output voltage range 0.5 4.0 V
ISNOOZE Maximum load current in Snooze Mode 2 mA
TAOperating ambient temperature –40 85 °C
TJOperating junction temperature –40 125 °C
(1) Refer to the APPLICATION INFORMATION section for further information.
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SLVSAE8B –SEPTEMBER 2011–REVISED MARCH 2012
ELECTRICAL CHARACTERISTICS
Over recommended free-air temperature range, TA= -40°C to 85°C, typical values are at TA= 25°C (unless otherwise noted),
VIN=3.6V, MODE = LOW.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY
VIN Input voltage range 2.3 6.0 V
Quiescent current into VIN IOUT = 0mA, Device not switching 30 uA
IQQuiescent current into VIN (SNOOZE IOUT = 0mA, Device not switching, MODE=HIGH 6.5 uA
MODE)
ISD Shutdown current into VIN EN = LOW 1 µA
Under voltage lock out Input voltage falling 1.8 2.0 V
VUVLO Under voltage lock out hysteresis Rising above VUVLO 120 mV
TJSD Thermal shut down Temperature rising 150 °C
Thermal shutdown hysteresis Temperature falling below TJSD 20 °C
LOGIC INTERFACE (ENABLE, MODE)
VIH High level input voltage 2.3V ≤VIN ≤6.0V 1 V
VIL Low level input voltage 2.3V ≤VIN ≤6.0V 0.4 V
ILKG Input leakage current 0.01 0.5 µA
POWER GOOD
VPG Power good threshold VOUT falling referenced to VOUT nominal –15 –10 –5 %
Power good hysteresis 5 %
VIL Low level voltage Isink = 500 µA 0.3 V
IPG,LKG PG Leakage current VPG = 5.0 V 0.01 0.1 µA
OUTPUT
Output voltage range 0.5 4.0 V
TPS62080, TPS62080A
Output voltage accuracy IOUT = 0 mA; VIN ≥2.3V –2.5 2.5 %
TPS62081
VOUT Output voltage accuracy IOUT = 0 mA; VIN ≥3.6V –2.5 2.5 %
TPS62082
Snooze Mode output voltage accuracy MODE = HIGH; VIN ≥2.3V and VIN ≥VOUT + 1V –5 5 %
Feedback regulation voltage
VFB VIN ≥2.3V and VIN ≥VOUT + 1V 0.438 0.45 0.462 V
TPS62080, TPS62080A
Feedback input bias current
IFB VFB = 0.45 V 10 100 nA
TPS62080, TPS62080A EN = LOW, VOUT = 1.8 V 1 kΩ
RDIS Output discharge resistor TPS62080A , EN = LOW, VOUT = 1.2 V, 25 40 65 Ω
Line Regulation 0 %/V
Load Regulation TPS62081, TPS62082 -0.25 %/A
High side FET on-resistance ISW = 500 mA 120 mΩ
RDS(on) Low side FET on-resistance ISW = 500 mA 90 mΩ
ILIM High side FET switch current limit Rising inductor current 1.6 2.8 4 A
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1
2
3
4
8
7
6
5
EN
GND
MODE
FB
VIN
PG
SW
VOS
THERMAL PAD
TPS62080, TPS62080A
TPS62081, TPS62082
SLVSAE8B –SEPTEMBER 2011–REVISED MARCH 2012
www.ti.com
DEVICE INFORMATION
QFN
8 PIN 2X2 mm
PIN FUNCTIONS
PIN I/O DESCRIPTION
NAME NO.
VIN 8 PWR Power Supply Voltage Input.
EN 1 IN Device Enable Logic Input.
Logic HIGH enables the device, logic LOW disables the device and turns it into shutdown.
MODE 3 IN Snooze Mode Enable Logic Input.
Logic HIGH enables the Snooze Mode, logic LOW disables the Snooze Mode
GND 2 PWR Power and Signal Ground.
VOS 5 IN Output Voltage Sense Pin for the internal control loop. Must be connected to output.
SW 7 PWR Switch Pin connected to the internal MOSFET switches and inductor terminal.
Connect the inductor of the output filter here.
FB 4 IN Feedback Pin for the internal control loop.
Connect this pin to the external feedback divider for the adjustable output version. For the fixed output voltage
versions this pin must be left floating or connected to GND.
PG 6 OUT Power Good open drain output.
This pin is pulled to low if the output voltage is below regulation limits. Can be left floating if not used.
Thermal Pad Connect it to GND.
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Gate
Driver
Control
Logic Low Side
N-MOS
High Side
N-MOS
Thermal
Shutdown
Softstart
Under
Voltage
Shutdown
direct control
&
compensation
VIN
SW
GND
PG
EN
VOS
REF
Active
Output
Discharge
Power
Good
Snooze Mode
MODE
FB
ramp
minimum
on-timer
DSC-CONTROLTM
error
amplifier
comparator
Thermal
Shutdown
Softstart
Under
Voltage
Shutdown
direct control
&
compensation
PG
EN
VOS
REF
Power
Good
MODE
FB
ramp
minimum
on-timer
DSC-CONTROLTM
Gate
Driver
Control
Logic Low Side
N-MOS
High Side
N-MOS
VIN
SW
GND
Snooze Mode
comparator
error
amplifier
Active
Output
Discharge
TPS62080, TPS62080A
TPS62081, TPS62082
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SLVSAE8B –SEPTEMBER 2011–REVISED MARCH 2012
FUNCTIONAL BLOCK DIAGRAMS
Figure 2. Functional Block Diagram (Adjustable Output Voltage Version)
Figure 3. Functional Block Diagram (Fixed Output Voltage Version)
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TPS6208x
L1
C1
R1
R2
VIN
POWER GOOD
SW
VOS
VIN
EN
GND
MODE
PG
FB
C2
R3
VOUT
C3
TPS62080, TPS62080A
TPS62081, TPS62082
SLVSAE8B –SEPTEMBER 2011–REVISED MARCH 2012
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TYPICAL CHARACTERISTICS
PARAMETER MEASUREMENT INFORMATION
Table 2. List of Components
REFERENCE DESCRIPTION MANUFACTURER
C1 10uF, Ceramic Capacitor, 6.3V, X5R, size 0603 Std
22uF, Ceramic Capacitor, 6.3V, X5R, size 0805,
C2 Murata
GRM21BR60J226ME39L
47uF, Tantalum Capacitor, 8V, 35mΩ, size 3528,
C3 Kemet
T520B476M008ATE035
L1 1.0µH, Power Inductor, 2.2A, size 3x3x1.2mm, XFL3012-102MEB Coilcraft
Depending on the output voltage of TPS62080, 1%; Not be
R1 populated for TPS62081, TPS62082;
R2 39.2k, Chip Resistor, 1/16W, 1%, size 0603 Std
R3 178k, Chip Resistor, 1/16W, 1%, size 0603 Std
TABLE OF GRAPHS
Figure
TPS62080, Load Current, VOUT = 0.9V Figure 4
TPS62080, Load Current, VOUT = 1.2V Figure 5
Efficiency TPS62080, Load Current, VOUT = 2.5V Figure 6
TPS62081, Load Current, VOUT = 1.8V Figure 7
TPS62082, Load Current, VOUT = 3.3V Figure 8
TPS62080, Input Voltage, VOUT = 0.9V Figure 9
TPS62080, Input Voltage, VOUT = 2.5V Figure 10
TPS62081, Input Voltage, VOUT = 1.8V Figure 11
TPS62082, Input Voltage, VOUT = 3.3V Figure 12
Output Voltage
Accuracy TPS62080, Load Current, VOUT = 0.9V Figure 13
TPS62080, Load Current, VOUT = 2.5V Figure 14
TPS62081, Load Current, VOUT = 1.8V Figure 15
TPS62082, Load Current, VOUT = 3.3V Figure 16
Input Voltage, Normal Mode Figure 17
Quiescent Current Input Voltage, Snooze Mode Figure 18
Input Voltage, High Side FET Figure 19
RDS(on) Input Voltage, Low Side FET Figure 20
TPS62080, Load Current, VOUT = 0.9V, Figure 21
Switching Frequency TPS62080, Load Current, VOUT = 2.5V, Figure 22
TPS62080, VIN = 3.3V, VOUT = 1.2V, Load Current = 500mA, PWM Mode Figure 23
Typical Operation TPS62080, VIN = 3.3V, VOUT = 1.2V, Load Current = 10mA, PFM Mode Figure 24
TPS62080, VIN = 3.3V, VOUT = 1.2V, Load Current = 2mA, Snooze Mode Figure 25
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0
10
20
30
40
50
60
70
80
90
100
10u 100u 1m 10m 100m 1 3
Output Current (A)
Efficiency (%)
VIN = 2.8 V
VIN = 3.6 V
VIN = 4.2 V
VIN = 2.8 V, Snooze Mode
VIN = 3.6 V, Snooze Mode
VIN = 4.2 V, Snooze Mode
TPS62080
VOUT = 0.9 V
G001
0
10
20
30
40
50
60
70
80
90
100
10u 100u 1m 10m 100m 1 3
Output Current (A)
Efficiency (%)
VIN = 2.8 V
VIN = 3.6 V
VIN = 4.2 V
VIN = 2.8 V, Snooze Mode
VIN = 3.6 V, Snooze Mode
VIN = 4.2 V, Snooze Mode
TPS62080
VOUT = 1.2 V
G002
0
10
20
30
40
50
60
70
80
90
100
10u 100u 1m 10m 100m 1 3
Output Current (A)
Efficiency (%)
VIN = 3.6 V
VIN = 4.2 V
VIN = 5.0 V
VIN = 3.6 V, Snooze Mode
VIN = 4.2 V, Snooze Mode
VIN = 5.0 V, Snooze Mode
TPS62080
VOUT = 2.5 V
G003
0
10
20
30
40
50
60
70
80
90
100
10u 100u 1m 10m 100m 1 3
Output Current (A)
Efficiency (%)
VIN = 2.8 V
VIN = 3.6 V
VIN = 4.2 V
VIN = 2.8 V, Snooze Mode
VIN = 3.6 V, Snooze Mode
VIN = 4.2 V, Snooze Mode
TPS62081
VOUT = 1.8 V
G005
TPS62080, TPS62080A
TPS62081, TPS62082
www.ti.com
SLVSAE8B –SEPTEMBER 2011–REVISED MARCH 2012
Figure
Load Transient TPS62080, VIN = 3.3V, VOUT = 1.2V, Load Current = 50mA to 1A Figure 26
Line Transient TPS62080, VIN = 3.3V to 4.2V, VOUT = 1.2V, Load = 2.2ΩFigure 27
TPS62080, VIN = 3.3V, VOUT = 1.2V, Load = 2.2ΩFigure 28
Startup TPS62080, VIN = 3.3V, VOUT = 1.2V, No Load Figure 29
Shutdown with TPS62080, VIN = 3.3V, VOUT = 1.2V, No Load Figure 30
Output Discharge
EFFICIENCY EFFICIENCY
vs vs
LOAD CURRENT LOAD CURRENT
Figure 4. Figure 5.
EFFICIENCY EFFICIENCY
vs vs
LOAD CURRENT LOAD CURRENT
Figure 6. Figure 7.
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0
10
20
30
40
50
60
70
80
90
100
10u 100u 1m 10m 100m 1 3
Output Current (A)
Efficiency (%)
VIN = 3.6 V
VIN = 4.2 V
VIN = 5.0 V
VIN = 3.6 V, Snooze Mode
VIN = 4.2 V, Snooze Mode
VIN = 5.0 V, Snooze Mode
TPS62082
VOUT = 3.3 V
G004
0.880
0.885
0.890
0.895
0.900
0.905
0.910
2.3 2.8 3.3 3.8 4.3 4.8 5.3 5.8
Input Voltage (V)
Output Voltage (V)
IOUT = 1A, TA = 25°C
IOUT = 1A, TA = −40°C
IOUT = 1A, TA = 85°C
IOUT = 10mA, TA = 25°C
IOUT = 10mA, TA = −40°C
IOUT = 10mA, TA = 85°C
TPS62080
VOUT = 0.9 V
G006
2.44
2.46
2.48
2.50
2.52
2.54
2.56
2.5 3 3.5 4 4.5 5 5.5 6
Input Voltage (V)
Output Voltage (V)
IOUT = 1A, TA = 25°C
IOUT = 1A, TA = −40°C
IOUT = 1A, TA = 85°C
IOUT = 10mA, TA = 25°C
IOUT = 10mA, TA = −40°C
IOUT = 10mA, TA = 85°C
TPS62080
VOUT = 2.5 V
G007
1.70
1.72
1.74
1.76
1.78
1.80
1.82
1.84
1.86
2.3 2.8 3.3 3.8 4.3 4.8 5.3 5.8
Input Voltage (V)
Output Voltage (V)
IOUT = 1A, TA = 25°C
IOUT = 1A, TA = −40°C
IOUT = 1A, TA = 85°C
IOUT = 10mA, TA = 25°C
IOUT = 10mA, TA = −40°C
IOUT = 10mA, TA = 85°C
TPS62081
VOUT = 1.8 V
G008
3.18
3.20
3.22
3.24
3.26
3.28
3.30
3.32
3.34
3.36
3.3 3.8 4.3 4.8 5.3 5.8
Input Voltage (V)
Output Voltage (V)
IOUT = 1A, TA = 25°C
IOUT = 1A, TA = −40°C
IOUT = 1A, TA = 85°C
IOUT = 10mA, TA = 25°C
IOUT = 10mA, TA = −40°C
IOUT = 10mA, TA = 85°C
TPS62082
VOUT = 3.3 V
G009
0.890
0.892
0.894
0.896
0.898
0.900
0.902
0.904
0.906
0.908
0.910
10u 100u 1m 10m 100m 1 3
Output Current (A)
Output Voltage (V)
TA = 25°C
TA = −40°C
TA = 85°C
TPS62080
VIN = 3.6 V
G010
TPS62080, TPS62080A
TPS62081, TPS62082
SLVSAE8B –SEPTEMBER 2011–REVISED MARCH 2012
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EFFICIENCY OUTPUT VOLTAGE
vs vs
LOAD CURRENT INPUT VOLTAGE
Figure 8. Figure 9.
OUTPUT VOLTAGE OUTPUT VOLTAGE
vs vs
INPUT VOLTAGE INPUT VOLTAGE
Figure 10. Figure 11.
OUTPUT VOLTAGE OUTPUT VOLTAGE
vs vs
INPUT VOLTAGE LOAD CURRENT
Figure 12. Figure 13.
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2.46
2.48
2.50
2.52
2.54
10u 100u 1m 10m 100m 1 3
Output Current (A)
Output Voltage (V)
TA = 25°C
TA = −40°C
TA = 85°C
TPS62080
VIN = 3.6 V
G011
1.76
1.78
1.80
1.82
1.84
10u 100u 1m 10m 100m 1 3
Output Current (A)
Output Voltage (V)
TA = 25°C
TA = −40°C
TA = 85°C
TPS62081
VIN = 3.6 V
G012
3.24
3.26
3.28
3.30
3.32
3.34
10u 100u 1m 10m 100m 1 3
Output Current (A)
Output Voltage (V)
TA = 25°C
TA = −40°C
TA = 85°C
TPS62082
VIN = 3.6 V
G013
15u
20u
25u
30u
35u
40u
2.3 2.8 3.3 3.8 4.3 4.8 5.3 5.8
Input Voltage (V)
Quiescent Current (A)
TA = 25°C
TA = −40°C
TA = 85°C
IOUT = 0 A, Mode = Low
G016
2u
3.5u
5u
6.5u
8u
9.5u
2.3 2.8 3.3 3.8 4.3 4.8 5.3 5.8
Input Voltage (V)
Quiescent Current (A)
TA = 25°C
TA = −40°C
TA = 85°C
IOUT = 0 A, Snooze Mode
G017
50
90
130
170
210
250
2.3 2.8 3.3 3.8 4.3 4.8 5.3 5.8
Input Voltage (V)
FET On−Resistance (mΩ)
TA = 25°C
TA = −40°C
TA = 85°C
G018
TPS62080, TPS62080A
TPS62081, TPS62082
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SLVSAE8B –SEPTEMBER 2011–REVISED MARCH 2012
OUTPUT VOLTAGE OUTPUT VOLTAGE
vs vs
LOAD CURRENT LOAD CURRENT
Figure 14. Figure 15.
OUTPUT VOLTAGE QUIESCENT CURRENT
vs vs
LOAD CURRENT INPUT VOLTAGE
Figure 16. Figure 17.
QUIESCENT CURRENT HIGH SIDE FET RDS(on)
vs vs
INPUT VOLTAGE INPUT VOLTAGE
Figure 18. Figure 19.
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20
60
100
140
180
220
2.3 2.8 3.3 3.8 4.3 4.8 5.3 5.8
Input Voltage (V)
FET On−Resistance (mΩ)
TA = 25°C
TA = −40°C
TA = 85°C
G019
0
500k
1M
1.5M
2M
2.5M
3M
0 400m 800m 1.2 1.6
Output Current (A)
Switching Frequency (Hz)
VIN = 2.3V
VIN = 3.3V
VIN = 4.2V
VIN = 5.0V
TPS62080
VOUT = 0.9V
G014
0
500k
1M
1.5M
2M
2.5M
3M
3.5M
4M
4.5M
0 400m 800m 1.2 1.6
Output Current (A)
Switching Frequency (Hz)
VIN = 2.5V
VIN = 3.3V
VIN = 4.2V
VIN = 5.0V
TPS62080
VOUT = 2.5V
G015
SW
2V/div
t - 200ns/div
V
20mV/div
OUT
L
0.5A/div
COIL
TPS62080, TPS62080A
TPS62081, TPS62082
SLVSAE8B –SEPTEMBER 2011–REVISED MARCH 2012
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LOW SIDE FET RDS(on) SWITCHING FREQUENCY
vs vs
INPUT VOLTAGE LOAD CURRENT
Figure 20. Figure 21.
SWITCHING FREQUENCY
vs
LOAD CURRENT TYPICAL APPLICATION (PWM MODE)
Figure 22. Figure 23.
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SW
2V/div
t - 2 s/divµ
V
20mV/div
OUT
L
0.2A/div
COIL
SW
2V/div
t - 50 s/divµ
V
50mV/div
OUT
L
0.2A/div
COIL
LOAD
1A/div
t - 50 s/divµ
V
20mV/div
OUT
L
1A/div
COIL
1A
50mA
t - 100 s/divµ
V
50mV/div
OUT
3.3V
4.2V
V
1V/div
IN
TPS62080, TPS62080A
TPS62081, TPS62082
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SLVSAE8B –SEPTEMBER 2011–REVISED MARCH 2012
TYPICAL APPLICATION (PFM MODE) TYPICAL APPLICATION (SNOOZE MODE)
Figure 24. Figure 25.
LOAD TRANSIENT LINE TRANSIENT
Figure 26. Figure 27.
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EN
5V/div
t - 20 s/divµ
V
1V/div
OUT
L
0.5A/div
COIL
PG
1V/div
EN
5V/div
t - 20 s/divµ
V
1V/div
OUT
L
0.2A/div
COIL
PG
1V/div
EN
5V/div
t - 20ms/div
V
0.5V/div
OUT
TPS62080, TPS62080A
TPS62081, TPS62082
SLVSAE8B –SEPTEMBER 2011–REVISED MARCH 2012
www.ti.com
START UP START UP (WITHOUT LOAD)
Figure 28. Figure 29.
SHUT DOWN
Figure 30.
12 Submit Documentation Feedback Copyright © 2011–2012, Texas Instruments Incorporated
Product Folder Link(s): TPS62080 TPS62080A TPS62081 TPS62082
TPS62080, TPS62080A
TPS62081, TPS62082
www.ti.com
SLVSAE8B –SEPTEMBER 2011–REVISED MARCH 2012
DETAILED DESCRIPTION
DEVICE OPERATION
The TPS6208x synchronous switched mode converters are based on DCS™ Control (Direct Control with
Seamless transition into Power Save Mode). This is an advanced regulation topology that combines the
advantages of hysteretic and voltage mode control.
The DCS™ Control topology operates in PWM (Pulse Width Modulation) mode for medium to heavy load
conditions and in Power Save Mode at light load currents. In PWM the converter operates with its nominal
switching frequency of 2MHz having a controlled frequency variation over the input voltage range. As the load
current decreases the converter enters Power Save Mode, reducing the switching frequency and minimizing the
IC quiescent current to achieve high efficiency over the entire load current range. DCS™ Control supports both
operation modes (PWM and PFM) using a single building block having a seamless transition from PWM to Power
Save Mode without effects on the output voltage. Fixed output voltage versions provide smallest solution size
combined with lowest quiescent current. The TPS6208x offers both excellent DC voltage and superior load
transient regulation, combined with very low output voltage ripple, minimizing interference with RF circuits.
The device is equipped with the Snooze Mode functionality, which is enabled with the Mode pin. The Snooze
Mode supports high efficiency conversion at lowest output currents below 2mA. If no load current is drawn, the
ultra low quiescent current of 6.5uA is sufficient to maintain the output voltage. This extends battery run time by
reducing the quiescent current during lowest or no load conditions in battery driven applications. For mains-
operated voltage supplies, the Snooze Mode reduces the system's stand-by energy consumption. During
shutdown (EN = LOW), the device reduces energy consumption to less than 1uA.
POWER SAVE MODE
As the load current decreases the TPS6208x will enter the Power Save Mode operation. During Power Save
Mode the converter operates with reduced switching frequency in PFM mode and with a minimum quiescent
current maintaining high efficiency. The power save mode occurs when the inductor current becomes
discontinuous. It is based on a fixed on time architecture. The typical on time is given by ton=210ns·(VOUT / VIN).
The switching frequency over the whole load current range is shown in Figure 21 and Figure 22.
SNOOZE MODE
The TPS6208x offers a Snooze Mode function. If the Snooze Mode is enabled by an external logic signal setting
the MODE pin to HIGH, the device's quiescent current consumption is reduced to typically 6.5µA. As a result, the
high efficiency range is extended towards the range of lowest output currents below 2mA, see the typical
characteristics efficiency figures.
If the device is operating in Snooze Mode, a dedicated, low power consuming block monitors the output voltage.
All other control blocks are snoozing during that time. If the output voltage falls below the programmed output
voltage by 3.5% (typ), the control blocks wake up, regulates the output voltage and allow themselves to snooze
again until the output voltage drops again. The Snooze Mode operation provides a clear efficiency improvement
at lowest output currents. If the load current increases, the advantage of efficiency in Snooze mode will be
deprived. Since the dynamic load regulation operates best if the Snooze Mode is disabled, it is recommended to
turn off the Snooze Mode by external logic signal if the load current exceeds 2mA, like a micro controller to
operate the MODE pin.
100% DUTY CYCLE LOW DROPOUT OPERATION
The device offers low input to output voltage difference by entering 100% duty cycle mode. In this mode the high
side MOSFET switch is constantly turned on and the low side MOSFET is switched off. This is particularly useful
in battery powered applications to achieve longest operation time by taking full advantage of the whole battery
voltage range. The minimum input voltage to maintain switching regulation, depending on the load current and
output voltage can be calculated as:
(1)
With:
VIN,MIN = Minimum input voltage
IOUT,MAX = Maximum output current
Copyright © 2011–2012, Texas Instruments Incorporated Submit Documentation Feedback 13
Product Folder Link(s): TPS62080 TPS62080A TPS62081 TPS62082
TPS62080, TPS62080A
TPS62081, TPS62082
SLVSAE8B –SEPTEMBER 2011–REVISED MARCH 2012
www.ti.com
RDS(on) = High side FET on-resistance
RL= Inductor ohmic resistance
ENABLING / DISABLING THE DEVICE
The device is enabled by setting the EN input to a logic HIGH. Accordingly, a logic LOW disables the device. If
the device is enabled, the internal power stage will start switching and regulate the output voltage to the
programmed threshold. The EN input must be terminated with a resistance less than 1MΩpulled to VIN or GND.
OUTPUT DISCHARGE
The output gets discharged by the SW pin with a typical discharge resistor of RDIS whenever the device shuts
down. This is the case when the device gets disabled by enable, thermal shutdown trigger, and undervoltage
lockout trigger.
SOFT START
After enabling the device, an internal soft-start circuitry monotonically ramps up the output voltage and reaches
the nominal output voltage during a soft start time (100µs, typical). This avoids excessive inrush current and
creates a smooth output voltage rise slope. It also prevents excessive voltage drops of primary cells and
rechargeable batteries with high internal impedance.
If the output voltage is not reached within the soft start time, such as in the case of heavy load, the converter will
enter regular operation. Consequently, the inductor current limit will operate as described below. The TPS6208x
is able to start into a pre-biased output capacitor. The converter starts with the applied bias voltage and ramps
the output voltage to its nominal value.
POWER GOOD
The TPS6208x has a power good output going low when the output voltage is below its nominal value. The
power good keeps high impedance once the output is above 95% of the regulated voltage, and is driven to low
once the output voltage falls below typically 90% of the regulated voltage. The PG pin is a open drain output and
is specified to sink typically up to 0.5mA. The power good output requires a pull up resistor that is recommended
connecting to the device output. When the device is off due to disable, UVLO or thermal shutdown, the PG pin is
at high impedance.
The PG signal can be used for sequencing of multiple rails by connecting to the EN pin of other converters.
Leave the PG pin unconnected when not used.
UNDER VOLTAGE LOCKOUT
To avoid mis-operation of the device at low input voltages, an under voltage lockout is implemented, that shuts
down the device at voltages lower than VUVLO with a VHYS_UVLO hysteresis.
THERMAL SHUTDOWN
The device goes into thermal shutdown once the junction temperature exceeds typically TJSD. Once the device
temperature falls below the threshold the device returns to normal operation automatically.
INDUCTOR CURRENT LIMIT
The Inductor Current Limit prevents the device from high inductor current and drawing excessive current from the
battery or input voltage rail. Excessive current might occur with a shorted/saturated inductor or a heavy
load/shorted output circuit condition.
The incorporated inductor peak current limit measures the current during the high side and low side power
MOSFET on-phase in PWM mode. Once the high side switch current limit is tripped, the high side MOSFET is
turned off and the low side MOSFET is turned on to reduce the inductor current. Until the inductor current drops
down to low side switch current limit, the low side MOSFET is turned off and the high side switch is turned on
again. This operation repeats until the inductor current does not reach the high side switch current limit. Due to
the internal propagation delay, the real current limit value can exceed the static current limit in the electrical
characteristics table.
14 Submit Documentation Feedback Copyright © 2011–2012, Texas Instruments Incorporated
Product Folder Link(s): TPS62080 TPS62080A TPS62081 TPS62082
SW
IN
OUT
OUTL
L
MAX,OUTMAX,L
fL
V
V
1
VI
2
I
II
´
-
´=D
D
+=
TPS62080, TPS62080A
TPS62081, TPS62082
www.ti.com
SLVSAE8B –SEPTEMBER 2011–REVISED MARCH 2012
APPLICATION INFORMATION
Output Filter Design
The inductor and the output capacitor together provide a low pass frequency filter. To simplify this process
Table 3 outlines possible inductor and capacitor value combinations for the most application.
Table 3. Matrix of Output Capacitor / Inductor Combinations
COUT [µF](1)
L [µH](1) 10 22 47 100 150
0.47
1+ +(2)(3) + +
2.2 + + + +
4.7
(1) Capacitance tolerance and bias voltage de-rating is anticipated. The effective capacitance can vary
by+20% and -50%. Inductor tolerance and current de-rating is anticipated. The effective inductance
can vary by +20% and -30%.
(2) Plus mark indicates recommended filter combinations.
(3) Filter combination in typical application.
Inductor Selection
Main parameter for the inductor selection is the inductor value and then the saturation current of the inductor. To
calculate the maximum inductor current under static load conditions, Equation 4 is given.
(2)
Where
IOUT,MAX = Maximum output current
ΔIL= Inductor current ripple
fSW = Switching frequency
L = Inductor value
It's recommended to choose the saturation current for the inductor 20%~30% higher than the IL,MAX, out of
Equation 4. A higher inductor value is also useful to lower ripple current, but will increase the transient response
time as well. The following inductors are recommended to be used in designs.
Table 4. List of Recommended Inductors
INDUCTANCE CURRENT RATING DIMENSIONS DC RESISTANCE TYPE MANUFACTURER
[µH] [mA] L x W x H [mm3] [mΩtyp]
1.0 2500 3 x 3 x 1.2 35 XFL3012-102ME Coilcraft
1.0 1650 3 x 3 x 1.2 40 LQH3NPN1R0NJ0 Murata
2.2 2500 4 x 3.7 x 1.65 49 LQH44PN2R2MP0 Murata
2.2 1600 3 x 3 x 1.2 81 XFL3012-222ME Coilcraft
Capacitor Selection
The input capacitor is the low impedance energy source for the converter which helps to provide stable
operation. A low ESR multilayer ceramic capacitor is recommended for best filtering and should be placed
between VIN and PGND as close as possible to that pins. For most applications 10μF will be sufficient, a larger
value reduces input current ripple.
Copyright © 2011–2012, Texas Instruments Incorporated Submit Documentation Feedback 15
Product Folder Link(s): TPS62080 TPS62080A TPS62081 TPS62082
TPS62080
1mH
10µF
2.3V .. 6V
R1
R2
VIN
POWER GOOD
SW
VOS
VIN
EN
GND
MODE
PG
FB
22µF
180k
VOUT
÷
ø
ö
ç
è
æ+´=
÷
ø
ö
ç
è
æ+´= 2R
1R
1V45.0
2R
1R
1VV FBOUT
TPS62080, TPS62080A
TPS62081, TPS62082
SLVSAE8B –SEPTEMBER 2011–REVISED MARCH 2012
www.ti.com
The architecture of the TPS6208X allows to use tiny ceramic-type output capacitors with low equivalent series
resistance (ESR). These capacitors provide low output voltage ripple and are recommended. To keep its
resistance up to high frequencies and to get narrow capacitance variation with temperature, it's recommended to
use X7R or X5R dielectric. The TPS6208x is designed to operate with an output capacitance of 10µF to 100µF,
as outlined in Table 3.
Table 5. List of Recommended Capacitors
CAPACITANCE DIMENSIONS
TYPE MANUFACTURER
[µF] L x W x H [mm3]
10 GRM188R60J106M 0603: 1.6 x 0.8 x 0.8 Murata
22 GRM188R60G226M 0603: 1.6 x 0.8 x 0.8 Murata
22 GRM21BR60J226M 0805: 2.0 x 1.2 x 1.25 Murata
Setting the Output Voltage
The TPS608x devices are available as fixed and adjustable output voltage versions. The fixed versions are
internally programmed to a fixed output voltage, whereas the adjustable output voltage version needs to be
programmed via an external voltage divider to set the desired output voltage.
Adjustable output voltage version
For the adjustable output voltage version, an external resistor divider is used. By selecting R1and R2, the output
voltage is programmed to the desired value.
Figure 31. Typical Application Circuit for Adjustable Output Voltage Option
When the output voltage is regulated, the typical voltage at the FB pin is VFB for the adjustable devices. The
following equation can be used to calculate R1and R2.
(3)
For best accuracy, R2 should be kept smaller than 40kΩto ensure that the current flowing through R2 is at least
100 times larger than IFB. Changing the sum towards a lower value increases the robustness against noise
injection. Changing the sum towards higher values reduces the quiescent current and supports the Snooze Mode
function for achieving highest efficiency at low load currents. For lowest quiescent current during the Snooze
Mode, it is recommended to use a fixed output voltage version like TPS62081 and TPS62082.
PCB Layout
The PCB layout is an important step to maintain the high performance of the TPS6208x devices.
The input/output capacitors and the inductor should be placed as close as possible to the IC. This keeps the
traces short. Routing these traces direct and wide results in low trace resistance and low parasitic inductance. A
common power GND should be used. The low side of the input and output capacitors must be connected
properly to the power GND to avoid a GND potential shift.
The sense traces connected to FB and VOS pins are signal traces. Special care should be taken to avoid noise
being induced. By a direct routing, parasitic inductance can be kept small. GND layers might be used for
shielding. Keep these traces away from SW nodes.
16 Submit Documentation Feedback Copyright © 2011–2012, Texas Instruments Incorporated
Product Folder Link(s): TPS62080 TPS62080A TPS62081 TPS62082
L
C
IN
C
OUT
R
2
R
1
V
IN
V
OUT
GND
1
TPS62082
1µH
10µF
3.6V .. 6V
VIN
22µF
180k
VOUT
POWER GOOD
3.3V
SW
VOS
VIN
EN
GND
MODE
PG
FB
TPS62080, TPS62080A
TPS62081, TPS62082
www.ti.com
SLVSAE8B –SEPTEMBER 2011–REVISED MARCH 2012
Figure 32. PCB Layout Suggestion
THERMAL INFORMATION
Implementation of integrated circuits in low-profile and fine-pitch surface-mount packages typically requires
special attention to power dissipation. Many system-dependent issues such as thermal coupling, airflow, added
heat sinks and convection surfaces, and the presence of other heat-generating components affect the power-
dissipation limits of a given component.
Three basic approaches for enhancing thermal performance are listed below:
• Improving the power dissipation capability of the PCB design
• Improving the thermal coupling of the component to the PCB by soldering the ThermalPAD™
• Introducing airflow in the system
For more details on how to use the thermal parameters, see the application notes: Thermal Characteristics
Application Notes SZZA017 and SPRA953.
APPLICATION EXAMPLES
Figure 33. 3.3V Fixed Output Voltage Application (TPS62082)
Copyright © 2011–2012, Texas Instruments Incorporated Submit Documentation Feedback 17
Product Folder Link(s): TPS62080 TPS62080A TPS62081 TPS62082
TPS62080
1mH
10µF
2.3V .. 6V
65.3k
39.2k
VIN
POWER GOOD
SW
VOS
VIN
EN
GND
MODE
PG
FB
22µF
180k
VOUT
1.2V
TPS62080
1mH
10µF
3.0V .. 6V
178.6k
39.2k
VIN
POWER GOOD
SW
VOS
VIN
EN
GND
MODE
PG
FB
22µF
180k
VOUT
2.5V
TPS62080, TPS62080A
TPS62081, TPS62082
SLVSAE8B –SEPTEMBER 2011–REVISED MARCH 2012
www.ti.com
Figure 34. 1.2V Output Voltage Application (TPS62080)
Figure 35. 2.5V Output Voltage Application (TPS62080)
18 Submit Documentation Feedback Copyright © 2011–2012, Texas Instruments Incorporated
Product Folder Link(s): TPS62080 TPS62080A TPS62081 TPS62082
TPS62080, TPS62080A
TPS62081, TPS62082
www.ti.com
SLVSAE8B –SEPTEMBER 2011–REVISED MARCH 2012
REVISION HISTORY
Changes from Original (September 2011) to Revision A Page
• Added TPS62080A device .................................................................................................................................................... 1
• Added TPS62080ADSG (Product Preview) and TPS62080ADGN (Product Preview) to ORDERING INFORMATION ...... 2
• Added TPS62080A output discharge resistor ....................................................................................................................... 3
Changes from Revision A (February 2012) to Revision B Page
• Changed TPS62080ADSG from Product Preview to Production Data in ORDERING INFORMATION .............................. 2
Copyright © 2011–2012, Texas Instruments Incorporated Submit Documentation Feedback 19
Product Folder Link(s): TPS62080 TPS62080A TPS62081 TPS62082
PACKAGE OPTION ADDENDUM
www.ti.com 31-Mar-2012
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
TPS62080ADGNR PREVIEW MSOP-
PowerPAD DGN 8 2500 TBD Call TI Call TI
TPS62080ADGNT PREVIEW MSOP-
PowerPAD DGN 8 250 TBD Call TI Call TI
TPS62080ADSGR ACTIVE WSON DSG 8 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS62080ADSGT ACTIVE WSON DSG 8 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS62080DSGR ACTIVE WSON DSG 8 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS62080DSGT ACTIVE WSON DSG 8 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS62081DSGR ACTIVE WSON DSG 8 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS62081DSGT ACTIVE WSON DSG 8 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS62082DSGR ACTIVE WSON DSG 8 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS62082DSGT ACTIVE WSON DSG 8 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
PACKAGE OPTION ADDENDUM
www.ti.com 31-Mar-2012
Addendum-Page 2
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
TPS62080ADSGR WSON DSG 8 3000 179.0 8.4 2.2 2.2 1.2 4.0 8.0 Q2
TPS62080ADSGT WSON DSG 8 250 179.0 8.4 2.2 2.2 1.2 4.0 8.0 Q2
TPS62080DSGR WSON DSG 8 3000 179.0 8.4 2.2 2.2 1.2 4.0 8.0 Q2
TPS62080DSGT WSON DSG 8 250 179.0 8.4 2.2 2.2 1.2 4.0 8.0 Q2
TPS62081DSGR WSON DSG 8 3000 179.0 8.4 2.2 2.2 1.2 4.0 8.0 Q2
TPS62081DSGT WSON DSG 8 250 179.0 8.4 2.2 2.2 1.2 4.0 8.0 Q2
TPS62082DSGR WSON DSG 8 3000 179.0 8.4 2.2 2.2 1.2 4.0 8.0 Q2
TPS62082DSGT WSON DSG 8 250 179.0 8.4 2.2 2.2 1.2 4.0 8.0 Q2
PACKAGE MATERIALS INFORMATION
www.ti.com 30-Mar-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TPS62080ADSGR WSON DSG 8 3000 195.0 200.0 45.0
TPS62080ADSGT WSON DSG 8 250 195.0 200.0 45.0
TPS62080DSGR WSON DSG 8 3000 195.0 200.0 45.0
TPS62080DSGT WSON DSG 8 250 195.0 200.0 45.0
TPS62081DSGR WSON DSG 8 3000 195.0 200.0 45.0
TPS62081DSGT WSON DSG 8 250 195.0 200.0 45.0
TPS62082DSGR WSON DSG 8 3000 195.0 200.0 45.0
TPS62082DSGT WSON DSG 8 250 195.0 200.0 45.0
PACKAGE MATERIALS INFORMATION
www.ti.com 30-Mar-2012
Pack Materials-Page 2
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