1. General description
The 74HC4067; 74HCT406 7 is a hig h-sp eed Si-gate CMOS device and is pin co mpatible
with the HEF4067B. The device is specified in compliance with JEDEC standard no. 7A.
The 74HC4067; 74HCT4067 is a 16-channel analog multiplexer/demultiplexer with four
address inputs (S0 to S3), an active-LOW enable input (E), sixteen independent
inputs/outputs (Y0 to Y15) and a common input/output (Z).
The 74HC4067; 74HCT4067 contains sixteen bidirectional analog switches, each with
one side connected to an independent input/output (Y0 to Y15) and the other side
connected to a common input/output (Z).
With pin E = LOW, one of the sixteen switches is selected by pins S0 to S3 (low
impedance ON-state). All unselected switches are in the high-impedance OFF-state.
With pin E = HIGH, all switches are in the high-impedance OFF-state, independe nt of pins
S0 to S3.
The analog inputs/outputs (Y0 to Y15, and Z) can swing between VCC as a positive limit
and GND as a negative limit. VCC to GND may not exceed 10 V.
2. Features and benefits
Low ON resistance:
80 (typical) at VCC = 4.5 V
70 (typical) at VCC = 6.0 V
60 (typical) at VCC = 9.0 V
Typical ‘break before make’ built-in
3. Applications
Analog multiplexing and demultiplexing
Digital multiplexing and demultiplexing
Signal gating
74HC4067; 74HCT4067
16-channel analog multiplexer/demultiplexer
Rev. 5 — 13 December 2011 Product data sheet
74HC_HCT4067 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 5 — 13 December 2011 2 of 30
NXP Semiconductors 74HC4067; 74HCT4067
16-channel analog multiplexer/demultiplexer
4. Ordering information
Table 1. Ordering information
Type number Package
Temperature range Name Description Version
74HC4067
74HC4067N 40 C to +125 C DIP24 plastic dual in-line package; 24 leads (600 mil);
reverse bending SOT101-1
74HC4067D 40 C to +125 C SO24 plastic small outline package; 24 leads;
body width 7.5 mm SOT137-1
74HC4067DB 40 C to +125 C SSOP24 plastic shrink small outlin e package; 24 leads;
body width 5.3 mm SOT340-1
74HC4067PW 40 C to +125 C TSSOP24 plastic thin shrink small outline package; 24 leads;
body width 4.4 mm SOT355-1
74HC4067BQ 40 C to +125 C DHVQFN24 plastic dual in-line compatible thermal enhanced very
thin quad flat package; no leads; 24 terminals;
body 3.5 5.5 0.85 mm
SOT815-1
74HCT4067
74HCT4067N 40 C to +125 C DIP24 plastic dual in-line package; 24 leads (600 mil);
reverse bending SOT101-1
74HCT4067D 40 C to +125 C SO24 plastic small outline package; 24 leads;
body width 7.5 mm SOT137-1
74HCT4067DB 40 C to +125 C SSOP24 plastic shrink small outlin e package; 24 leads;
body width 5.3 mm SOT340-1
74HCT4067PW 40 C to +125 C TSSOP24 plastic thin shrink small outline package; 24 leads;
body width 4.4 mm SOT355-1
74HCT4067BQ 40 C to +125 C DHVQFN24 plastic dual in-line compatible thermal enhanced very
thin quad flat package; no leads; 24 terminals;
body 3.5 5.5 0.85 mm
SOT815-1
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Product data sheet Rev. 5 — 1 3 December 2011 3 of 30
NXP Semiconductors 74HC4067; 74HCT4067
16-channel analog multiplexer/demultiplexer
5. Functional diagram
Fig 1. Logic symbol Fig 2. IEC logic symbol
001aag725
9Y0
8
10 Y1S0
11
S1
14
S2
13
S3
15
E
7Y2
6Y3
5Y4
4Y5
Z
1
3Y6
2Y7
23 Y8
22 Y9
21 Y10
20 Y11
19 Y12
18 Y13
17 Y14
16 Y15
0
MUX/DMUX
3
9
G16
8
7
6
15
4
3
2
0
1
2
3
4
5
6
723
22
21
20
19
18
17
16
8
9
10
11
12
13
14
15
001aag726
16 ×0
15
10
11
14
13
15
Fig 3. Schematic diagra m (one sw itch)
001aag729
Yn
Z
GND
from
logic
V
CC
V
CC
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Product data sheet Rev. 5 — 1 3 December 2011 4 of 30
NXP Semiconductors 74HC4067; 74HCT4067
16-channel analog multiplexer/demultiplexer
Fig 4. Functional dia g ra m
001aag727
1-OF-16
DECODER
10
9Y0
S0
8Y1
7Y2
6Y3
5Y4
4Y5
3Y6
2Y7
23 Y8
22 Y9
21 Y10
20 Y11
19 Y12
18 Y13
17 Y14
16 Y15
1Z
11
S1
14
S2
13
S3
15
E
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Product data sheet Rev. 5 — 1 3 December 2011 5 of 30
NXP Semiconductors 74HC4067; 74HCT4067
16-channel analog multiplexer/demultiplexer
Fig 5. Logic diagram
001aag728
Y0
Y1
S0
S1
S2
S3
E
Y2
Y3
Y4
Y5
Y6
Y7
Y8
Y9
Y10
Y11
Y12
Y13
Y14
Y15
Z
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Product data sheet Rev. 5 — 1 3 December 2011 6 of 30
NXP Semiconductors 74HC4067; 74HCT4067
16-channel analog multiplexer/demultiplexer
6. Pinning information
6.1 Pinning
6.2 Pin description
(1) This is not a supply pin. The substrate is attached to
this pad using conductive die attach material. There
is no electrical or mechanical requirement to solder
this pad. However, if it is soldered, the solder land
should remain floating or be connected to VCC.
Fig 6. Pin configu ration for DIP24, SO24, SSOP24 and
TSSOP24 Fig 7. Pin configuration for DHVQFN24
74HC4067
74HCT4067
ZV
CC
Y7 Y8
Y6 Y9
Y5 Y10
Y4 Y11
Y3 Y12
Y2 Y13
Y1 Y14
Y0 Y15
S0 E
S1 S2
GND S3
001aag730
1
2
3
4
5
6
7
8
9
10
11
12
14
13
16
15
18
17
20
19
22
21
24
23
001aag731
74HC4067
74HCT4067
Transparent top view
S2
S0
S1
E
Y0 Y15
Y1 Y14
Y2 Y13
Y3 Y12
Y4 Y11
Y5 Y10
Y6 Y9
Y7 Y8
GND
S3
Z
VCC
11 14
10 15
9 16
8 17
7 18
6 19
5 20
4 21
3 22
2 23
12
13
1
24
terminal 1
index area
VCC(1)
Table 2. Pin description
Symbol Pin Description
Z 1 common input or output
Y7, Y6, Y5, Y4, Y3, Y2, Y1, Y0, Y15,
Y14, Y13, Y12, Y11, Y10, Y9, Y8 2, 3, 4, 5, 6, 7, 8, 9, 16, 17, 18, 19, 20, 21, 22, 23 independent input or output
S0, S1, S3, S2 10, 11, 13, 14 address input 0
GND 12 ground (0 V)
E15 enable input (active LOW)
VCC 24 supply voltage
74HC_HCT4067 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 5 — 1 3 December 2011 7 of 30
NXP Semiconductors 74HC4067; 74HCT4067
16-channel analog multiplexer/demultiplexer
7. Functional description
[1] H = HIGH voltage level;
L = LOW voltage level;
X = don’t care.
8. Limiting values
Table 3. Function table[1]
Inputs Channel ON
ES3 S2 S1 S0
LLLLLY0 to Z
LLLLHY1 to Z
LLLHLY2 to Z
LLLHHY3 to Z
L L H L L Y4 to Z
LLHLHY5 to Z
L L H H L Y6 to Z
LLHHHY7 to Z
LHLLLY8 to Z
L H L L H Y9 to Z
LHLHLY10 to Z
L H L H H Y11 to Z
LHHLLY12 to Z
LHHLHY13 to Z
LHHHLY14 to Z
LHHHHY15 to Z
HXXXX-
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions Min Max Unit
VCC supply voltage [1] 0.5 +11.0 V
IIK input clamping current VI<0.5 V or VI>V
CC +0.5V - 20 mA
ISK switch clamping current VSW <0.5 V or VSW >V
CC +0.5V - 20 mA
ISW switch current VSW =0.5 V to VCC +0.5V - 25 mA
ICC supply current - 50 mA
IGND ground current - 50 mA
Tstg storage temperature 65 +150 C
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Product data sheet Rev. 5 — 1 3 December 2011 8 of 30
NXP Semiconductors 74HC4067; 74HCT4067
16-channel analog multiplexer/demultiplexer
[1] To avoid drawing VCC current out of terminal Z, when switch current flows in terminals Yn, the voltage drop across the bidirectional
switch must not exceed 0.4 V. If the switch current flows into terminal Z, no VCC current will flow out of terminals Yn. In this case there is
no limit for the voltage drop across the switch, but the voltages at Yn and Z may not exceed VCC or GND.
[2] For DIP24 package: Ptot derates linearly with 12 mW/K above 70 C.
[3] For SO24 package: Ptot derates linearly with 8 mW/K above 70 C.
[4] For SSOP24 and TSSOP24 packages: Ptot derates linearly with 5.5 mW/K above 60 C.
[5] For DHVQFN24 package: Ptot derates linearly with 4.5 mW/K above 60 C.
9. Recommended operating conditions
Ptot total power dissipation Tamb = 40 C to +125 C
DIP24 package [2] -750mW
SO24 package [3] -500mW
SSOP24 package [4] -500mW
TSSOP24 package [4] -500mW
DHVQFN24 package [5] -500mW
P power dissipation per switch - 100 mW
Table 4. Limiting values …continued
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions Min Max Unit
Table 5. Recommended op erating conditions
Symbol Parameter Conditions Min Typ Max Unit
74HC4067
VCC supply voltage 2.0 5.0 10.0 V
VIinput voltage GND - VCC V
VSW switch voltage GND - VCC V
t/V input transition rise and fall rate VCC = 2.0 V - - 625 ns
VCC = 4.5 V - 1.67 139 ns
VCC =6.0V - - 83 ns
VCC = 10.0 V - - 31 ns
Tamb ambient temperature 40 +25 +125 C
74HCT4067
VCC supply voltage 4.5 5.0 5.5 V
VIinput voltage GND - VCC V
VSW switch voltage GND - VCC V
t/V input transition rise and fall rate VCC = 4.5 V - 1.67 139 ns
Tamb ambient temperature 40 +25 +125 C
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Product data sheet Rev. 5 — 1 3 December 2011 9 of 30
NXP Semiconductors 74HC4067; 74HCT4067
16-channel analog multiplexer/demultiplexer
10. Static characteristics
[1] At supply voltages (VCC GND) approaching 2 V, the analog switch ON resistance becomes extremely non-linear. Therefore it is
recommended that these devices be used to transmit digital signals only, when using these supply voltages.
Table 6. R ON resistance per switch for types 74H C4067 and 74HCT4067
VI = VIH or VIL; for test circuit see Figure 8.
Vis is the input voltage at a Yn or Z terminal, whichever is assigned as an input.
Vos is the output voltage at a Yn or Z terminal, whichever is assigned as an output.
For 74HC4067: VCC
GND = 2.0 V, 4.5 V, 6.0 V and 9.0 V.
For 74HCT4067: VCC
GND = 4.5 V.
Symbol Parameter Conditions 25 C40 C to +125 CUnit
Typ Max Max
(85 C) Max
(125 C)
RON(peak) ON resistance (peak) Vis = VCC to GND
VCC = 2.0 V; ISW = 100 A[1] ----
VCC = 4.5 V; ISW = 1000 A 110 180 225 270
VCC = 6.0 V; ISW = 1000 A 95 160 200 240
VCC = 9.0 V; ISW = 1000 A 75 130 165 195
RON(rail) ON resistance (rail) Vis = GND or VCC
VCC = 2.0 V; ISW = 100 A[1] 150---
VCC = 4.5 V; ISW = 1000 A 90 160 200 240
VCC = 6.0 V; ISW = 1000 A 80 140 175 210
VCC = 9.0 V; ISW = 1000 A 70 120 150 180
RON ON resistance mismatch
between channels Vis = VCC to GND
VCC = 2.0 V [1] ----
VCC = 4.5V 9---
VCC = 6.0V 8---
VCC = 9.0V 6---
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Product data sheet Rev. 5 — 1 3 December 2011 10 of 30
NXP Semiconductors 74HC4067; 74HCT4067
16-channel analog multiplexer/demultiplexer
Vis = 0 V to (VCC GND) Vis = 0 V to (VCC GND)
(1) VCC = 4.5 V
(2) VCC = 6.0 V
(3) VCC = 9.0 V
Fig 8. Test circuit for measuring RON Fig 9. Typical RON as a function of input voltage Vis
001aag733
V
IL
Z
V
CC
Yn
E
ISW
Vis
GND
V
SW
RON VSW
ISW
----------
=
Table 7. Static characteristics 74HC4067
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Vis is the input voltage at a Yn or Z terminal, whichever is assigned as an input.
Vos is the output voltage at a Yn or Z terminal, whichever is assigned as an output.
Symbol Parameter Conditions Min Typ Max Unit
Tamb = 25 C
VIH HIGH-level input voltage VCC = 2.0 V 1.5 1.2 - V
VCC = 4.5 V 3.15 2.4 - V
VCC = 6.0 V 4.2 3.2 - V
VCC = 9.0 V 6.3 4.7 - V
VIL LOW-level input voltage VCC = 2.0 V - 0.8 0.5 V
VCC = 4.5 V - 2.1 1.35 V
VCC = 6.0 V - 2.8 1.80 V
VCC = 9.0 V - 4.3 2.70 V
IIinput leakage current VI = VCC or GND
VCC = 6.0 V - - 0.1 A
VCC = 10.0 V - - 0.2 A
IS(OFF) OFF-state leakage current VCC = 10.0 V; VI = VIH or VIL;
VSW=VCC GND; see Figure 10
per channel - - 0.1 A
all channels - - 0.8 A
IS(ON) ON-state leakage current VCC = 10.0 V; VI = VIH or VIL;
VSW=VCC GND; see Figure 11 --0.8 A
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Product data sheet Rev. 5 — 1 3 December 2011 11 of 30
NXP Semiconductors 74HC4067; 74HCT4067
16-channel analog multiplexer/demultiplexer
ICC supply current VI = VCC or GND; Vis = GND or VCC;
Vos =V
CC or GND
VCC = 6.0 V - - 8.0 A
VCC = 10.0 V - - 16.0 A
CIinput capacitance - 3.5 - pF
Tamb = 40 C to +85 C
VIH HIGH-level input voltage VCC = 2.0 V 1.5 - - V
VCC = 4.5 V 3.15 - - V
VCC = 6.0 V 4.2 - - V
VCC = 9.0 V 6.3 - - V
VIL LOW-level input voltage VCC = 2.0 V - - 0.50 V
VCC = 4.5 V - - 1.35 V
VCC = 6.0 V - - 1.80 V
VCC = 9.0 V - - 2.70 V
IIinput leakage current VI = VCC or GND
VCC = 6.0 V - - 1.0 A
VCC = 10.0 V - - 2.0 A
IS(OFF) OFF-state leakage current VCC = 10.0 V; VI = VIH or VIL;
VSW=VCC GND; see Figure 10
per channel - - 1.0 A
all channels - - 8.0 A
IS(ON) ON-state leakage current VCC = 10.0 V; VI = VIH or VIL;
VSW=VCC GND; see Figure 11 --8.0 A
ICC supply current VI = VCC or GND; Vis = GND or VCC;
Vos =V
CC or GND
VCC = 6.0 V - - 80.0 A
VCC = 10.0 V - - 160 A
Tamb = 40 C to +125 C
VIH HIGH-level input voltage VCC = 2.0 V 1.5 - - V
VCC = 4.5 V 3.15 - - V
VCC = 6.0 V 4.2 - - V
VCC = 9.0 V 6.3 - - V
VIL LOW-level input voltage VCC = 2.0 V - - 0.50 V
VCC = 4.5 V - - 1.35 V
VCC = 6.0 V - - 1.80 V
VCC = 9.0 V - - 2.70 V
IIinput leakage current VI = VCC or GND
VCC = 6.0 V - - 1.0 A
VCC = 10.0 V - - 2.0 A
Table 7. Static characteristics 74HC4067 …continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Vis is the input voltage at a Yn or Z terminal, whichever is assigned as an input.
Vos is the output voltage at a Yn or Z terminal, whichever is assigned as an output.
Symbol Parameter Conditions Min Typ Max Unit
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Product data sheet Rev. 5 — 1 3 December 2011 12 of 30
NXP Semiconductors 74HC4067; 74HCT4067
16-channel analog multiplexer/demultiplexer
IS(OFF) OFF-state leakage current VCC = 10.0 V; VI = VIH or VIL;
VSW=VCC GND; see Figure 10
per channel - - 1.0 A
all channels - - 8.0 A
IS(ON) ON-state leakage current VCC = 10.0 V; VI = VIH or VIL;
VSW=VCC GND; see Figure 11 --8.0 A
ICC supply current VI = VCC or GND; Vis = GND or VCC;
Vos =V
CC or GND
VCC = 6.0 V - - 160 A
VCC = 10.0 V - - 320 A
Table 7. Static characteristics 74HC4067 …continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Vis is the input voltage at a Yn or Z terminal, whichever is assigned as an input.
Vos is the output voltage at a Yn or Z terminal, whichever is assigned as an output.
Symbol Parameter Conditions Min Typ Max Unit
Table 8. Static characteristics 74HCT4067
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Vis is the input voltage at a Yn or Z terminal, whichever is assigned as an input.
Vos is the output voltage at a Yn or Z terminal, whichever is assigned as an output.
Symbol Parameter Conditions Min Typ Max Unit
Tamb = 25 C
VIH HIGH-level input voltage VCC = 4.5 V to 5.5 V 2.0 1.6 - V
VIL LOW-level input voltage VCC = 4.5 V to 5.5 V - 1.2 0.8 V
IIinput leakage current VI = VCC or GND; VCC = 5.5 V - - 0.1 A
IS(OFF) OFF-state leakage current VCC = 5.5 V; VI = VIH or VIL;
VSW=VCC GND; see Figure 10
per channel - - 0.1 A
all channels - - 0.8 A
IS(ON) ON-state leakage current VCC = 5.5 V; VI = VIH or VIL;
VSW=VCC GND; see Figure 11 --0.8 A
ICC supply current VI = VCC or GND; Vis = GND or VCC;
Vos =V
CC or GND; VCC = 4.5 V to 5.5 V --8.0A
ICC additional supply current per input pin; VI = VCC 2.1 V; other inputs
at VCC or GND; VCC = 4.5 V to 5.5 V
pin E - 60 216 A
pin Sn - 50 180 A
CIinput capacitance - 3.5 - pF
Tamb = 40 C to +85 C
VIH HIGH-level input voltage VCC = 4.5 V to 5.5 V 2.0 - - V
VIL LOW-level input voltage VCC = 4.5 V to 5.5 V - - 0.8 V
IIinput leakage current VI = VCC or GND; VCC = 5.5 V - - 1.0 A
IS(OFF) OFF-state leakage current VCC = 5.5 V; VI = VIH or VIL;
VSW=VCC GND; see Figure 10
per channel - - 1.0 A
all channels - - 8.0 A
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Product data sheet Rev. 5 — 1 3 December 2011 13 of 30
NXP Semiconductors 74HC4067; 74HCT4067
16-channel analog multiplexer/demultiplexer
IS(ON) ON-state leakage current VCC = 5.5 V; VI = VIH or VIL;
VSW=VCC GND; see Figure 11 --8.0 A
ICC supply current VI = VCC or GND; Vis = GND or VCC;
Vos =V
CC or GND; VCC = 4.5 V to 5.5 V - - 80.0 A
ICC additional supply current per input pin; VI = VCC 2.1 V; other inputs
at VCC or GND; VCC = 4.5 V to 5.5 V
pin E - - 270 A
pin Sn - - 225 A
Tamb = 40 C to +125 C
VIH HIGH-level input voltage VCC = 4.5 V to 5.5 V 2.0 - - V
VIL LOW-level input voltage VCC = 4.5 V to 5.5 V - - 0.8 V
IIinput leakage current VI = VCC or GND; VCC = 5.5 V - - 1.0 A
IS(OFF) OFF-state leakage current VCC = 5.5 V; VI = VIH or VIL;
VSW=VCC GND; see Figure 10
per channel - - 1.0 A
all channels - - 8.0 A
IS(ON) ON-state leakage current VCC = 5.5 V; VI = VIH or VIL;
VSW=VCC GND; see Figure 11 --8.0 A
ICC supply current VI = VCC or GND; Vis = GND or VCC;
Vos =V
CC or GND; VCC = 4.5 V to 5.5 V - - 160 A
ICC additional supply current per input pin; VI = VCC 2.1 V; other inputs
at VCC or GND; VCC = 4.5 V to 5.5 V
pin E - - 294 A
pin Sn - - 245 A
Table 8. Static characteristics 74HCT4067 …continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Vis is the input voltage at a Yn or Z terminal, whichever is assigned as an input.
Vos is the output voltage at a Yn or Z terminal, whichever is assigned as an output.
Symbol Parameter Conditions Min Typ Max Unit
Vis = VCC and Vos = GND
Vis = GND and Vos = VCC
Vis = VCC and Vos = open
Vis = GND and Vos = open
Fig 10. Test circuit for measuring OF F-state leakage
current Fig 11. Test circuit for measuring ON-state leakage
current
I
SW
I
SW
001aag734
V
IH
Z
V
CC
Yn
E
Vos
Vis
GND
ISW
001aag735
VIL ZYn
E
Vos
Vis GND
VCC
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Product data sheet Rev. 5 — 1 3 December 2011 14 of 30
NXP Semiconductors 74HC4067; 74HCT4067
16-channel analog multiplexer/demultiplexer
11. Dynamic characteristics
Table 9. Dynamic characteristics 74HC4067
GND = 0 V; tr = tf = 6 ns; CL = 50 pF unless specified otherwise; for test circuit see Figure 14.
Vis is the input voltage at a Yn or Z terminal, whichever is assigned as an input.
Vos is the output voltage at a Yn or Z terminal, whichever is assigned as an output.
Symbol Parameter Conditions 25 C40 C to +125 CUnit
Typ Max Max
(85 C) Max
(125 C)
tpd propagation delay Yn to Z; see Figure 12 [1][2]
VCC = 2.0 V 25 75 95 110 ns
VCC = 4.5 V 9 15 19 22 ns
VCC = 6.0 V 7 13 16 19 ns
VCC = 9.0 V 5 9 11 14 ns
Z to Yn
VCC = 2.0 V 18 60 75 90 ns
VCC = 4.5 V 6 12 15 18 ns
VCC = 6.0 V 5 10 13 15 ns
VCC = 9.0 V 4 8 10 12 ns
toff turn-off time E to Yn; see Figure 13 [3]
VCC = 2.0 V 74 250 315 375 ns
VCC = 4.5 V 27 50 63 75 ns
VCC = 5.0 V; CL = 15 pF 27 - - - ns
VCC = 6.0 V 22 43 54 64 ns
VCC = 9.0 V 20 38 48 57 ns
Sn to Yn
VCC = 2.0 V 83 250 315 375 ns
VCC = 4.5 V 30 50 63 75 ns
VCC = 5.0 V; CL = 15 pF 29 - - - ns
VCC = 6.0 V 24 43 54 64 ns
VCC = 9.0 V 21 38 48 57 ns
E to Z
VCC = 2.0 V 85 275 345 415 ns
VCC = 4.5 V 31 55 69 83 ns
VCC = 6.0 V 25 47 59 71 ns
VCC = 9.0 V 24 42 53 63 ns
Sn to Z
VCC = 2.0 V 94 290 365 435 ns
VCC = 4.5 V 34 58 73 87 ns
VCC = 6.0 V 27 47 62 74 ns
VCC = 9.0 V 25 45 56 68 ns
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Product data sheet Rev. 5 — 1 3 December 2011 15 of 30
NXP Semiconductors 74HC4067; 74HCT4067
16-channel analog multiplexer/demultiplexer
[1] tpd is the same as tPHL and tPLH.
[2] Due to higher Z terminal capacitance (16 switches versus 1) the delay figures to the Z terminal are higher than those to the Y terminal.
[3] ton is the same as tPHZ and tPLZ.
[4] toff is the same as tPZH and tPZL.
[5] CPD is used to determine the dynamic power dissipation (PD in W).
PD = CPD VCC2fi+{(CL+C
sw) VCC2 fo} where:
fi = input frequency in MHz;
fo = output frequency in MHz;
{(CL+C
sw) VCC2 fo} = sum of outputs;
CL = output load capacitance in pF;
Csw = switch capacitance in pF;
VCC = supply voltage in V.
ton turn-on time E to Yn; see Figure 13 [4]
VCC = 2.0 V 80 275 345 415 ns
VCC = 4.5 V 29 55 69 83 ns
VCC = 5.0 V; CL = 15 pF 26 - - - ns
VCC = 6.0 V 23 47 59 71 ns
VCC = 9.0 V 17 42 53 63 ns
Sn to Yn
VCC = 2.0 V 88 300 375 450 ns
VCC = 4.5 V 32 60 75 90 ns
VCC = 5.0 V; CL = 15 pF 29 - - - ns
VCC = 6.0 V 26 51 64 77 ns
VCC = 9.0 V 18 45 56 68 ns
E to Z
VCC = 2.0 V 85 275 345 415 ns
VCC = 4.5 V 31 55 69 83 ns
VCC = 6.0 V 25 47 59 71 ns
VCC = 9.0 V 18 42 53 63 ns
Sn to Z
VCC = 2.0 V 94 300 375 450 ns
VCC = 4.5 V 34 60 75 90 ns
VCC = 6.0 V 27 51 64 77 ns
VCC = 9.0 V 19 45 56 68 ns
CPD power dissipation
capacitance per switch; VI = GND to VCC [5] 29 - - - pF
Table 9. Dynamic characteristics 74HC4067 …continued
GND = 0 V; tr = tf = 6 ns; CL = 50 pF unless specified otherwise; for test circuit see Figure 14.
Vis is the input voltage at a Yn or Z terminal, whichever is assigned as an input.
Vos is the output voltage at a Yn or Z terminal, whichever is assigned as an output.
Symbol Parameter Conditions 25 C40 C to +125 CUnit
Typ Max Max
(85 C) Max
(125 C)
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Product data sheet Rev. 5 — 1 3 December 2011 16 of 30
NXP Semiconductors 74HC4067; 74HCT4067
16-channel analog multiplexer/demultiplexer
[1] tpd is the same as tPHL and tPLH.
[2] Due to higher Z terminal capacitance (16 switches versus 1) the delay figures to the Z terminal are higher than those to the Y terminal.
[3] ton is the same as tPHZ and tPLZ.
[4] toff is the same as tPZH and tPZL.
[5] CPD is used to determine the dynamic power dissipation (PD in W).
PD = CPD VCC2fi+{(CL+C
sw) VCC2 fo} where:
fi = input frequency in MHz;
fo = output frequency in MHz;
{(CL+C
sw) VCC2 fo} = sum of outputs;
CL = output load capacitance in pF;
Csw = switch capacitance in pF;
VCC = supply voltage in V.
Table 10. Dynamic characteristics 74HCT4067
GND = 0 V; tr = tf = 6 ns; CL = 50 pF unless specified otherwise; for test circuit see Figure 14.
Vis is the input voltage at a Yn or Z terminal, whichever is assigned as an input.
Vos is the output voltage at a Yn or Z terminal, whichever is assigned as an output.
Symbol Parameter Conditions 25 C40 C to +125 CUnit
Typ Max Max
(85 C) Max
(125 C)
tpd propagation delay Yn to Z; see Figure 12 [1][2]
VCC = 4.5 V 9 15 19 22 ns
Z to Yn
VCC = 4.5 V 6 12 15 18 ns
toff turn-off time E to Yn; see Figure 13 [3]
VCC = 4.5 V 26 55 69 83 ns
VCC = 5.0 V; CL = 15 pF 26 - - - ns
Sn to Yn
VCC = 4.5 V 31 55 69 83 ns
VCC = 5.0 V; CL = 15 pF 30 - - - ns
E to Z
VCC = 4.5 V 30 60 75 90 ns
Sn to Z
VCC = 4.5 V 35 60 75 90 ns
ton turn-on time E to Yn; see Figure 13 [4]
VCC = 4.5 V 32 60 75 90 ns
VCC = 5.0 V; CL = 15 pF 32 - - - ns
Sn to Yn
VCC = 4.5 V 35 60 75 90 ns
VCC = 5.0 V; CL = 15 pF 33 - - - ns
E to Z
VCC = 4.5 V 38 65 81 98 ns
Sn to Z
VCC = 4.5 V 38 65 81 98 ns
CPD power dissipation
capacitance per switch; VI = GND to (VCC 1.5 V) [5] 29 - - - pF
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Product data sheet Rev. 5 — 1 3 December 2011 17 of 30
NXP Semiconductors 74HC4067; 74HCT4067
16-channel analog multiplexer/demultiplexer
12. Waveforms
Fig 12. Input (Vis) to output (Vos) propagation delays
001aad555
tPLH tPHL
50 %
50 %
Vis input
Vos output
Measurement points are shown in Table 11.
Fig 13. Turn-on and turn-off times
001aad556
t
PLZ
t
PHZ
switch OFF switch ON
switch ON
V
os
output
V
os
output
E, Sn inputs V
M
V
I
0 V
90 %
10 %
t
PZL
t
PZH
50 %
50 %
Table 11. Measurement points
Type VIVM
74HC4067 VCC 0.5VCC
74HCT4067 3.0 V 1.3 V
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Product data sheet Rev. 5 — 1 3 December 2011 18 of 30
NXP Semiconductors 74HC4067; 74HCT4067
16-channel analog multiplexer/demultiplexer
[1] For 74HCT4067: maximum input voltage VI = 3.0 V.
Test data is given in Table 12.
Definitions test circuit:
RT = Termination resistance should be equal to output impedance Zo of the pulse generator.
CL = Load capacitance including jig and probe capacitance.
RL = Load resistor.
S1 = Test selection switch.
Fig 14. Load circuitry for measuring switching time s
V
M
V
M
t
W
t
W
10 %
90 %
0 V
V
I
V
I
negative
pulse
positive
pulse
0 V
V
M
V
M
90 %
10 %
t
f
t
r
t
r
t
f
001aag732
V
CC
V
CC
open
GND
V
I
V
os
DUT
CL
RT
RLS1
PULSE
GENERATOR
V
is
Table 12. Test data
Test Input Output S1 position
Control E Address Sn Switch Yn (Z) tr, tfSwitch Z (Yn)
VI[1] VI[1] Vis CLRL
tPHL, tPLH GND GND or VCC GND to VCC 6ns 50pF - open
tPHZ, tPZH GND to VCC GND to VCC VCC 6ns 50pF, 15pF 1kGND
tPLZ, tPZL GND to VCC GND to VCC GND 6 ns 50 pF, 15 pF 1 kVCC
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Product data sheet Rev. 5 — 1 3 December 2011 19 of 30
NXP Semiconductors 74HC4067; 74HCT4067
16-channel analog multiplexer/demultiplexer
13. Additional dynamic characteristics
[1] Adjust input voltage Vis to 0 dBm level (0 dBm = 1 mW into 600 ).
[2] Adjust input voltage Vis to 0 dBm leve l at Vos for fi = 1 MHz (0 dBm = 1 mW into 50 ). After set-up, fi is increased to obtain a reading of
3dB at V
os.
Table 13. Additional dynamic characteristics
Recommended conditio ns and typical values; GND = 0 V; Tamb = 25
C.
Vis is the input voltage at a Yn or Z terminal, whichever is assigned as an input.
Vos is the output voltage at a Yn or Z terminal, whichever is assigned as an output.
Symbol Parameter Conditions Min Typ Max Unit
THD total harmonic distortion RL = 10 k; CL = 50 pF; see Figure 15
fi = 1 kHz
VCC = 4.5 V; Vis(p-p) = 4.0 V - 0.04 - %
VCC = 9.0 V; Vis(p-p) = 8.0 V - 0.02 - %
fi = 10 kHz
VCC = 4.5 V; Vis(p-p) = 4.0 V - 0.12 - %
VCC = 9.0 V; Vis(p-p) = 8.0 V - 0.06 - %
iso isolation (OFF-state) RL = 600 ; CL = 50 pF; see Figure 16 [1]
VCC = 4.5 V - 50 - dB
VCC = 9.0 V - 50 - dB
f(-3dB) 3 dB frequency response RL = 50 ;C
L = 10 pF; see Figure 17 [2]
VCC = 4.5 V - 90 - MHz
VCC = 9.0 V - 100 - MHz
Csw switch capacitance independent pins Y - 5 - pF
common pin Z - 45 - p F
Fig 15. Test circuit for measuring total harmonic distortion
10 μF
001aag736
V
IL
Z
GND
Yn
E
V
os
D
V
CC
2RL
2RLCL
V
is
fi
V
CC
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Product data sheet Rev. 5 — 1 3 December 2011 20 of 30
NXP Semiconductors 74HC4067; 74HCT4067
16-channel analog multiplexer/demultiplexer
a. Isolation (OFF-state)
b. Test circuit
VCC = 4.5 V; GND = 0 V; RL = 600 ; Rsource = 1 k.
Fig 16. Isolation (OFF-state) as a function of frequency
001aae332
fi (kHz)
10 105106
104
102103
−60
−40
−80
−20
0
αiso
(dB)
−100
0.1 μF
001aag737
V
IH
Z
GND
Yn
E
V
os
V
CC
2RL
2RLCL
V
is
fi
dB
V
CC
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Product data sheet Rev. 5 — 1 3 December 2011 21 of 30
NXP Semiconductors 74HC4067; 74HCT4067
16-channel analog multiplexer/demultiplexer
a. Typical 3 dB fre quency response
b. Test circuit
VCC = 4.5 V; GND = 0 V; RL = 50 ; Rsource = 1 k.
Fig 17. 3 dB frequency resp onse
001aag739
f
i
(kHz)
10 10
5
10
6
10
4
10
2
10
3
0
5
V
os
(dB)
−5
0.1 μF
001aag738
V
IL
Z
dB
Yn
E
V
os
V
CC
2RL
2RLCL
V
is
fi
GND
V
CC
74HC_HCT4067 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 5 — 1 3 December 2011 22 of 30
NXP Semiconductors 74HC4067; 74HCT4067
16-channel analog multiplexer/demultiplexer
14. Package outline
Fig 18. Package outline SOT101-1 (DIP24)
UNIT A
max. 1 2 b1cD E e M
H
L
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
mm
inches
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
SOT101-1 99-12-27
03-02-13
A
min. A
max. bw
ME
e1
1.7
1.3 0.53
0.38 0.32
0.23 32.0
31.4 14.1
13.7 3.9
3.4 0.252.54 15.24 15.80
15.24 17.15
15.90 2.25.1 0.51 4
0.066
0.051 0.021
0.015 0.013
0.009 1.26
1.24 0.56
0.54 0.15
0.13 0.010.1 0.6 0.62
0.60 0.68
0.63 0.0870.2 0.02 0.16
051G02 MO-015 SC-509-24
MH
c
(e )
1
ME
A
L
seating plane
A1
wM
b1
e
D
A2
Z
24
1
13
12
b
E
pin 1 index
0 5 10 mm
scale
Note
1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included.
Z
max.
(1)
(1)(1)
DIP24: plastic dual in-line package; 24 leads (600 mil) SOT101-1
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Product data sheet Rev. 5 — 1 3 December 2011 23 of 30
NXP Semiconductors 74HC4067; 74HCT4067
16-channel analog multiplexer/demultiplexer
Fig 19. Package outline SOT137-1 (SO24)
UNIT A
max. A1A2A3bpcD
(1) E(1) (1)
eH
ELL
pQZ
ywv θ
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
mm
inches
2.65 0.3
0.1 2.45
2.25 0.49
0.36 0.32
0.23 15.6
15.2 7.6
7.4 1.27 10.65
10.00 1.1
1.0 0.9
0.4 8
0
o
o
0.25 0.1
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
Note
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.
1.1
0.4
SOT137-1
X
12
24
wM
θ
A
A1
A2
bp
D
HE
Lp
Q
detail X
E
Z
c
L
vMA
13
(A )
3
A
y
0.25
075E05 MS-013
pin 1 index
0.1 0.012
0.004 0.096
0.089 0.019
0.014 0.013
0.009 0.61
0.60 0.30
0.29 0.05
1.4
0.055
0.419
0.394 0.043
0.039 0.035
0.016
0.01
0.25
0.01 0.004
0.043
0.016
0.01
e
1
0 5 10 mm
scale
SO24: plastic small outline package; 24 leads; body width 7.5 mm SOT137-1
99-12-27
03-02-19
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Product data sheet Rev. 5 — 1 3 December 2011 24 of 30
NXP Semiconductors 74HC4067; 74HCT4067
16-channel analog multiplexer/demultiplexer
Fig 20. Package outline SOT340-1 (SSOP24)
UNIT A1A2A3bpcD
(1) E(1) (1)
eH
ELL
pQZywv θ
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
mm 0.21
0.05 1.80
1.65 0.38
0.25 0.20
0.09 8.4
8.0 5.4
5.2 0.65 1.25
7.9
7.6 0.9
0.7 0.8
0.4 8
0
o
o
0.13 0.10.2
DIMENSIONS (mm are the original dimensions)
Note
1. Plastic or metal protrusions of 0.2 mm maximum per side are not included.
1.03
0.63
SOT340-1 MO-150 99-12-27
03-02-19
X
wM
θ
A
A1
A2
bp
D
HE
Lp
Q
detail X
E
Z
e
c
L
vMA
(A )
3
A
112
24 13
0.25
y
pin 1 index
0 2.5 5 mm
scale
SSOP24: plastic shrink small outline package; 24 leads; body width 5.3 mm SOT340-1
A
max.
2
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Product data sheet Rev. 5 — 1 3 December 2011 25 of 30
NXP Semiconductors 74HC4067; 74HCT4067
16-channel analog multiplexer/demultiplexer
Fig 21. Package outline SOT355-1 (TSSOP24)
UNIT A1A2A3bpcD
(1) E(2) (1)
eH
ELL
pQZywv θ
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
mm 0.15
0.05 0.95
0.80 0.30
0.19 0.2
0.1 7.9
7.7 4.5
4.3 0.65 6.6
6.2 0.4
0.3 8
0
o
o
0.13 0.10.21
DIMENSIONS (mm are the original dimensions)
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
0.75
0.50
SOT355-1 MO-153 99-12-27
03-02-19
0.25 0.5
0.2
wM
bp
Z
e
112
24 13
pin 1 index
θ
A
A1
A2
Lp
Q
detail X
L
(A )
3
HE
E
c
vMA
X
A
D
y
0 2.5 5 mm
scale
TSSOP24: plastic thin shrink small outline package; 24 leads; body width 4.4 mm SOT355-1
A
max.
1.1
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Product data sheet Rev. 5 — 1 3 December 2011 26 of 30
NXP Semiconductors 74HC4067; 74HCT4067
16-channel analog multiplexer/demultiplexer
Fig 22. Package outline SOT815-1 (DHVQFN24)
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
Note
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.
SOT815-1 - - - - - - - - - 03-04-29
SOT815-1
0 2.5 5 mm
scale
by
y1C
C
AC
CB
vM
wM
e1
e2
terminal 1
index area
terminal 1
index area
X
UNIT A(1)
max. A1bc eEhLe1ywv
mm 10.05
0.00 0.30
0.18 0.5 4.5
e2
1.50.2 2.25
1.95
Dh
4.25
3.95 0.05 0.05
y1
0.10.1
DIMENSIONS (mm are the original dimensions)
0.5
0.3
D(1)
5.6
5.4
E(1)
3.6
3.4
D
E
BA
e
DHVQFN24: plastic dual in-line compatible thermal enhanced very thin quad flat package;
no leads; 24 terminals; body 3.5 x 5.5 x 0.85 mm
AA1c
detail X
Eh
L
Dh
2
23
11
14
13
12
1
24
74HC_HCT4067 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 5 — 1 3 December 2011 27 of 30
NXP Semiconductors 74HC4067; 74HCT4067
16-channel analog multiplexer/demultiplexer
15. Revision history
Table 14. Revision history
Document ID Release date Data sheet status Change notice Supersedes
74HC_HCT4067 v.5 20111213 Product data sheet - 74HC_HCT4067 v.4
Modifications: •Legal pages updated.
74HC_HCT4067 v.4 20110518 Product data sheet - 74HC_HCT4067 v.3
74HC_HCT4067 v.3 20071015 Product data sheet - 74HC_HCT4067_CNV v.2
74HC_HCT4067_CNV v .2 19970901 Product specification - -
74HC_HCT4067 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 5 — 1 3 December 2011 28 of 30
NXP Semiconductors 74HC4067; 74HCT4067
16-channel analog multiplexer/demultiplexer
16. Legal information
16.1 Data sheet status
[1] Please consult the most recently issued document before initiating or completing a design.
[2] The term ‘short data sheet’ is explained in section “Definitions”.
[3] The product status of de vice(s) d escribed in th is docume nt may have changed since this docum ent was pub lished and may dif fer in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
16.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liab ility for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and tit le. A short data sh eet is intended
for quick reference only and shou ld not be rel ied u pon to cont ain det ailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall pre vail.
Product specificatio n — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to off er functions and qualities beyond those descri bed in the
Product data sheet.
16.3 Disclaimers
Limited warr a nty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequ ential damages (including - wit hout limitatio n - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability t owards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all informa tion supplied prior
to the publication hereof .
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suit able for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in perso nal injury, death or severe property or environmental
damage. NXP Semiconductors accepts no liab ility for inclusion and/or use of
NXP Semiconductors products in such equipment or applications and
therefore such inclusion and/or use is at the customer’s own risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty tha t such application s will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and ope ration of their applications
and products using NXP Semiconductors product s, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suit able and fit for the custome r’s applications and
products planned, as well as fo r the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for th e customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanent ly and irreversibly affect
the quality and reliability of the device.
Te rms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individua l agreement. In case an individual
agreement is concluded only the ter ms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly ob jects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
No offer to sell or license — Nothing i n this document may be interpreted or
construed as an of fer t o sell product s that is open for accept ance or t he grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
Export control — This document as well as the item(s) described herein
may be subject to export control regulatio ns. Export might require a prior
authorization from competent authorities.
Document status[1][2] Product status[3] Definition
Objective [short] data sheet Development This document contains data from the objective specification for product development.
Preliminary [short] dat a sheet Qualification This document contains data from the preliminary specification.
Product [short] dat a sheet Production This document contains the product specification.
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Product data sheet Rev. 5 — 1 3 December 2011 29 of 30
NXP Semiconductors 74HC4067; 74HCT4067
16-channel analog multiplexer/demultiplexer
Non-automotive qualified products — Unless this data sheet expressly
states that this specific NXP Semiconductors product is automotive qualified,
the product is not suitable for automotive use. It i s neit her qua lified nor tested
in accordance with automotive testing or application requirements. NXP
Semiconductors accepts no liability for inclusion and/or use of
non-automotive qualified products in automotive equipment or applications.
In the event that customer uses the product for design-in and use in
automotive applications to automot ive specifications and standard s, customer
(a) shall use the product without NXP Semiconductors’ warranty of the
product for such automotive applications, use and specifications, and (b)
whenever customer uses the product for automotive applications beyond
NXP Semiconductors’ specifications such use shall be solely at customer’s
own risk, and (c) customer fully indemnifies NXP Semiconductors for any
liability, damages or failed product claims resulting f rom customer design an d
use of the product for automotive applications beyond NXP Semiconductors’
standard warranty and NXP Semiconductors’ product specifications.
16.4 Trademarks
Notice: All referenced b rands, produc t names, service names and trademarks
are the property of their respect i ve ow ners.
17. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
NXP Semiconductors 74HC4067; 74HCT4067
16-channel analog multiplexer/demultiplexer
© NXP B.V. 2011. All rights reserved.
For more information, please visit: http://www.nxp.co m
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 13 December 2011
Document identifier: 74HC_HCT4067
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
18. Contents
1 General description. . . . . . . . . . . . . . . . . . . . . . 1
2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1
3 Applications. . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
4 Ordering information. . . . . . . . . . . . . . . . . . . . . 2
5 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 3
6 Pinning information. . . . . . . . . . . . . . . . . . . . . . 6
6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 6
7 Functional description . . . . . . . . . . . . . . . . . . . 7
8 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 7
9 Recommended operating conditions. . . . . . . . 8
10 Static characteristics. . . . . . . . . . . . . . . . . . . . . 9
11 Dynamic characteristics . . . . . . . . . . . . . . . . . 14
12 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
13 Additional dynamic char acteristics . . . . . . . . 19
14 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 22
15 Revision history. . . . . . . . . . . . . . . . . . . . . . . . 27
16 Legal information. . . . . . . . . . . . . . . . . . . . . . . 28
16.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 28
16.2 Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
16.3 Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 28
16.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 29
17 Contact information. . . . . . . . . . . . . . . . . . . . . 29
18 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30