CAT1161WI-25-G - ON Semiconductor

July, 2012 − Rev. 12

1Publication Order Number:

CAT1161/D

CAT1161, CAT1162

Supervisory Circuits with

I2C Serial CMOS EEPROM,

Precision Reset Controller

and Watchdog Timer (16K)

Description

The CAT1161/2 is a complete memory and supervisory solution for

microcontroller−based systems. A serial EEPROM memory (16K)

with hardware memory write protection, a system power supervisor

with brown out protection and a watchdog timer are integrated

together in low power CMOS technology. Memory interface is via an

I2C bus.

The 1.6−second watchdog circuit returns a system to a known good

state if a software or hardware glitch halts or “hangs” the system. The

CAT1161 watchdog monitors the SDA line, making an additional PC

board trace unnecessary. The lower cost CAT1162 does not have a

watchdog timer.

The power supply monitor and reset circuit protects memory and

system controllers during power up/down and against brownout

conditions. Five reset threshold voltages support 5 V, 3.3 V and 3 V

systems. If power supply voltages are out of tolerance reset signals

become active, preventing the system microcontroller, ASIC or

peripherals from operating. Reset signals become inactive typically

200 ms after the supply voltage exceeds the reset threshold level. With

both active high and low reset signals, interface to microcontrollers

and other ICs is simple. In addition, a reset pin can be used as a

debounced input for pushbutton manual reset capability.

The CAT1161/2 memory features a 16−byte page. In addition,

hardware data protection is provided by a write protect pin WP and by

a VCC sense circuit that prevents writes to memory whenever VCC falls

below the reset threshold or until VCC reaches the reset threshold

during power up.

Available packages include an 8−pin DIP and a surface mount,

8−pin SO package.

Features

•Watchdog Monitors SDA Signal (CAT1161)

•400 kHz I2C Bus Compatible

•2.7 V to 6 V Operation

•Low Power CMOS Technology

•16−Byte Page Write Buffer

•Built−in Inadvertent Write Protection

♦VCC Lock Out

♦Write Protection Pin, WP

•Active High or Low Reset

♦Precision Power Supply Voltage Monitor

♦5 V, 3.3 V and 3 V Systems

♦Five Threshold Voltage Options

•1,000,000 Program/Erase Cycles

•Manual Reset

•100 Year Data Retention

•8−Pin DIP or 8−Pin SOIC

•Commercial and Industrial Temperature Ranges

•These Devices are Pb−Free, Halogen Free/BFR Free

and are RoHS Compliant

ORDERING INFORMATION

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PDIP−8

CASE 646AA

SOIC−8

CASE 751BD

For Ordering Information details, see page 11.

RESET

GND

VCC

RESET

SCL

SDA

CAT1161

CAT1162

PIN CONFIGURATION

PIN FUNCTIONS

Pin Name Function

DC Do Not Connect

RESET Active Low Reset I/O

WP Write Protect

GND Ground

SDA Serial Data/Address

SCL Clock Input

RESET Active High Reset I/O

VCC Power Supply

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Table 1. RESET THRESHOLD OPTION

Part Dash

Number

Minimum

Threshold

Maximum

Threshold

−45 4.50 4.75

−42 4.25 4.50

−30 3.00 3.15

−28 2.85 3.00

−25 2.55 2.70

BLOCK DIAGRAM

16K

DOUT

ACK

SENSEAMPS

SHIFT REGISTERS

CONTROL

LOGIC

WORDADDRESS

BUFFERS

START/STOP

LOGIC

EEPROM

VCC

EXTERNAL LOAD

COLUMN

DECODERS

XDEC

DATA IN STORAGE

HIGHVOLTAGE/

TIMING CONTROL

GND

SDA

RESET Controller

Precision

Vcc Monitor

STATE COUNTERS

SLAVE

ADDRESS

COMPARATORS

SCL

RESET RESET

WATCHDOG

Only for

CAT1161

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SPECIFICATIONS

Table 2. ABSOLUTE MAXIMUM RATINGS

Parameters Ratings Units

Temperature Under Bias –55 to +125 °C

Storage Temperature –65 to +150 °C

Voltage on any Pin with Respect to Ground (Note 1) −2.0 to VCC + 2.0 V

VCC with Respect to Ground −2.0 to 7.0 V

Package Power Dissipation Capability (TA = 25°C) 1.0 W

Lead Soldering Temperature (10 sec) 300 °C

Output Short Circuit Current (Note 2) 100 mA

Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the

Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect

device reliability.

1. The minimum DC input voltage is –0.5 V. During transitions, inputs may undershoot to –2.0 V for periods of less than 20 ns. Maximum

DC voltage on output pins is VCC +0.5 V, which may overshoot to VCC +2.0 V for periods of less than 20 ns.

2. Output shorted for no more than one second. No more than one output shorted at a time.

Table 3. RELIABILITY CHARACTERISTICS

Symbol Parameter Reference Test Method Min Max Units

NEND (Note 3) Endurance MIL−STD−883, Test Method 1033 1,000,000 Cycles/Byte

TDR (Note 3) Data Retention MIL−STD−883, Test Method 1008 100 Years

VZAP (Note 3) ESD Susceptibility MIL−STD−883, Test Method 3015 2000 Volts

ILTH (Notes 3 & 4) Latch−Up JEDEC Standard 17 100 mA

3. This parameter is tested initially and after a design or process change that affects the parameter.

4. Latch−up protection is provided for stresses up to 100 mA on address and data pins from –1 V to VCC +1 V.

Table 4. D.C. OPERATING CHARACTERISTICS

VCC = 2.7 V to 6 V, unless otherwise specified.

Symbol Parameter Test Conditions Min Typ Max Units

ICC Power Supply Current fSCL = 100 kHz 3 mA

ISB Standby Current VCC = 3.3 V 40 mA

VCC = 5 V 50 mA

ILI Input Leakage Current VIN = GND or VCC 2mA

ILO Output Leakage Current VIN = GND or VCC 10 mA

VIL Input Low Voltage −1 VCC x 0.3 V

VIH Input High Voltage VCC x 0.7 VCC + 0.5 V

VOL1 Output Low Voltage (SDA) IOL = 3 mA, VCC = 3.0 V 0.4 V

Table 5. CAPACITANCE

TA = 25°C, f = 1.0 MHz, VCC = 5 V

Symbol Test Test Conditions Max Units

CI/O (Note 3) Input/Output Capacitance (SDA) VI/O = 0 V 8 pF

CIN (Note 3) Input Capacitance (SCL) VIN = 0 V 6 pF

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Table 6. AC CHARACTERISTICS

VCC = 2.7 V to 6.0 V unless otherwise specified. Output Load is TTL Gate and 100 pF.

Symbol Parameter Min Max Min Max Units

FSCL Clock Frequency 100 400 kHz

T1 (Note 1) Noise Suppression Time Constant at SCL, SDA Inputs 200 200 ns

tAA SCL Low to SDA Data Out and ACK Out 3.5 1 ms

tBUF (Note 1) Time the Bus must be Free Before a New Transmission Can

Start

4.7 1.2 ms

tHD; STA Start Condition Hold Time 4 0.6 ms

tLOW Clock Low Period 4.7 1.2 ms

tHIGH Clock High Period 4 0.6 ms

tSU; STA Start Condition Setup Time (for a Repeated Start Condition) 4.7 0.6 ms

tHD; DAT Data in Hold Time 0 0 ns

tSU; DAT Data in Setup Time 50 50 ns

tR (Note 1) SDA and SCL Rise Time 1 0.3 ms

tF (Note 1) SDA and SCL Fall Time 300 300 ns

tSU; STO Stop Condition Setup Time 4 0.6 ms

tDH Data Out Hold Time 100 100 ns

1. This parameter is tested initially and after a design or process change that affects the parameter.

Table 7. WRITE CYCLE LIMITS

Symbol Parameter Min Typ Max Units

tWR Write Cycle Time 10 ms

* The write cycle time is the time from a valid stop condition of a write sequence to the end of the internal program/erase cycle. During the write

cycle, the bus interface circuits are disabled, SDA is allowed to remain high, and the device does not respond to its slave address.

Table 8. RESET CIRCUIT CHARACTERISTICS

Symbol Parameter Min Typ Max Units

tGLITCH VCC Glitch Reject Pulse Width 100 ns

VRT Reset Threshold Hysteresis 15 mV

VOLRS Reset Output Low Voltage (IOLRS = 1 mA) 0.4 V

VOHRS Reset Output High Voltage VCC − 0.75 V

VTH Reset Threshold (VCC = 5 V), (CAT1161/2−45) 4.50 4.75 V

Reset Threshold (VCC = 5 V), (CAT1161/2−42) 4.25 4.50

Reset Threshold (VCC = 3.3 V), (CAT1161/2−30) 3.00 3.15

Reset Threshold (VCC = 3.3 V), (CAT1161/2−28) 2.85 3.00

Reset Threshold (VCC = 3 V), (CAT1161/2−25) 2.55 2.70

tPURST Power−Up Reset Timeout 130 270 ms

tWP Watchdog Period 1.6 s

tRPD VTH to RESET Output Delay 5ms

VRVALID RESET Output Valid 1 V

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PIN DESCRIPTION

WP: WRITE PROTECT

If the pin is tied to VCC the entire memory array becomes

Write Protected (READ only). When the pin is tied to GND

or left floating normal read/write operations are allowed to

the device.

RESET/RESET: RESET I/O

These are open drain pins and can be used as reset trigger

inputs. By forcing a reset condition on the pins the device

will initiate and maintain a reset condition. The RESET pin

must be connected through a pulldown resistor, and the

RESET pin must be connected through a pull−up resistor.

SDA: SERIAL DATA ADDRESS

The bidirectional serial data/address pin is used to transfer

all data into and out of the device. The SDA pin is an open

drain output and can be wire−ORed with other open drain or

open collector outputs.

If there is no transition on the SDA for more than

1.6 seconds, the watchdog timer times out.

SCL: Serial Clock

Serial clock input.

DEVICE OPERATION

Reset Controller Description

The CAT1161/2 precision RESET controller ensures

correct system operation during brownout and power

up/down conditions. It is configured with open drain

RESET outputs. During power−up, the RESET outputs

remain active until VCC reaches the VTH threshold and will

continue driving the outputs for approximately 200 ms

(tPURST) after reaching VTH. After the tPURST timeout

interval, the device will cease to drive the reset outputs. At

this point the reset outputs will be pulled up or down by their

respective pull up/down resistors. During power−down, the

RESET outputs will be active when VCC falls below VTH.

The RESET outputs will be valid so long as VCC is > 1.0 V

(VRVALID).

The RESET pins are I/Os; therefore, the CAT1161/2 can

act as a signal conditioning circuit for an externally applied

manual reset. The inputs are edge triggered; that is, the

RESET input in the CAT1161/2 will initiate a reset timeout

after detecting a low to high transition and the RESET input

will initiate a reset timeout after detecting a high to low

transition.

Watchdog Timer

The Watchdog Timer provides an independent protection

for microcontrollers. During a system failure, the CAT1161

will respond with a reset signal after a time−out interval of

1.6 seconds for a lack of activity. The CAT1161 is designed

with the Watchdog Timer feature on the SDA input. If the

microcontroller does not toggle the SDA input pin within 1.6

seconds, the Watchdog Timer times out. This will generate

a reset condition on reset outputs. The Watchdog Timer is

cleared by any transition on SDA.

As long as reset signal is asserted, the Watchdog Timer

will not count and will stay cleared.

The CAT1162 does not have a Watchdog.

Figure 1. RESET Output Timing

GLITCH

VCC

PURST

tRPD

RVALID

VTH

RESET

RPD

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Hardware Data Protection

The CAT1161/2 is designed with the following hardware

data protection features to provide a high degree of data

integrity.

1. The CAT1161/2 features a WP pin. When the WP

pin is tied high the entire memory array becomes

write protected (read only).

2. The VCC sense provides write protection when

VCC falls below the reset threshold value (VTH).

The VCC lock out inhibits writes to the serial

EEPROM whenever VCC falls below (power

down) VTH or until VCC reaches the reset threshold

(power up) VTH. Any attempt to access the

internal EEPROM is not recognized and an ACK

will not be sent on the SDA line when RESET or

RESET is active.

Reset Threshold Voltage

The CAT1161/2 is offered with five reset threshold

voltage ranges. They are 4.50 ÷ 4.75 V, 4.25 ÷ 4.50 V,

3.00 ÷3.15 V, 2.85 ÷ 3.00 V and 2.55 ÷ 2.70 V.

Figure 2. Bus Timing

tHIGH

SCL

SDA IN

SDA OUT

tLOW

tBUF

tSU:STO

tSU:DAT

tHD:DAT

tHD:STA

tSU:STA

tAA tDH

Figure 3. Write Cycle Timing

tWR

STOP

CONDITION

START

CONDITION

ADDRESS

ACK8TH BIT

BYTE n

SCL

SDA

Figure 4. Start/Stop Timing

START BIT

STOP BIT

SCL

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FUCTIONAL DESCRIPTION

The CAT1161/2 supports the I2C Bus data transmission

protocol. This Inter−Integrated Circuit Bus protocol defines

any device that sends data to the bus to be a transmitter and

any device receiving data to be a receiver. The transfer is

controlled by the Master device which generates the serial

clock and all START and STOP conditions for bus access.

Both the Master device and Slave device can operate as

either transmitter or receiver, but the Master device controls

which mode is activated.

I2C Bus Protocol

The features of the I2C bus protocol are defined as

follows:

1. Data transfer may be initiated only when the bus is

not busy.

2. During a data transfer, the data line must remain

stable whenever the clock line is high. Any

changes in the data line while the clock line is high

will be interpreted as a START or STOP condition.

START Condition

The START Condition precedes all commands to the

device, and is defined as a HIGH to LOW transition of SDA

when SCL is HIGH. The CAT1161/2 monitors the SDA and

SCL lines and will not respond until this condition is met.

STOP Condition

A LOW to HIGH transition of SDA when SCL is HIGH

determines the STOP condition. All operations must end

with a STOP condition.

Device Addressing

The Master begins a transmission by sending a START

condition. The Master sends the address of the particular

slave device it is requesting. The four most significant bits

of the 8−bit slave address are fixed as 1010.

The next three bits (Figure 6) define memory addressing.

For the CAT1161/2 the three bits define higher order bits.

The last bit of the slave address specifies whether a Read

or Write operation is to be performed. When this bit is set to

1, a Read operation is selected, and when set to 0, a Write

operation is selected.

After the Master sends a START condition and the slave

address byte, the CAT1161/2 monitors the bus and responds

with an acknowledge (on the SDA line) when its address

matches the transmitted slave address. The CAT1161/2 then

performs a Read or Write operation depending on the

R/W bit.

Figure 5. Acknowledge Timing

ACKNOWLEDGE

RTSTA

SCL FROM

MASTER 8

DATA OUTPUT

FROM TRANSMITTER

DATA OUTPUT

FROM RECEIVER

Figure 6. Slave Address Bits

1 0 1 0 a10 a9 a8 R/W

Note: a8, a9 and a10 correspond to the address of the memory array address word.

CAT1161/2

Acknowledge

After a successful data transfer, each receiving device is

required to generate an acknowledge. The acknowledging

device pulls down the SDA line during the ninth clock cycle,

signaling that it received the 8 bits of data.

The CAT1161/2 responds with an acknowledge after

receiving a START condition and its slave address. If the

device has been selected along with a write operation, it

responds with an acknowledge after receiving each 8−bit

byte.

When the CAT1161/2 begins a READ mode it transmits

8 bits of data, releases the SDA line and monitors the line for

an acknowledge. Once it receives this acknowledge, the

CAT1161/2 will continue to transmit data. If no

acknowledge is sent by the Master, the device terminates

data transmission and waits for a STOP condition.

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WRITE OPERATIONS

Byte Write

In the Byte Write mode, the Master device sends the

START condition and the slave address information (with

the R/W bit set to zero) to the Slave device. After the Slave

generates an acknowledge, the Master sends a 8−bit address

that is to be written into the address pointers of the

CAT1161/2. After receiving another acknowledge from the

Slave, the Master device transmits the data to be written into

the addressed memory location. The CAT1161/2

acknowledges once more and the Master generates the

STOP condition. At this time, the device begins an internal

programming cycle to non−volatile memory. While the

cycle is in progress, the device will not respond to any

request from the Master device.

Page Write

The CAT1161/2 writes up to 16 bytes of data in a single

write cycle, using the Page Write operation. The page write

operation is initiated in the same manner as the byte write

operation, however instead of terminating after the initial

byte is transmitted, the Master is allowed to send up to 15

additional bytes. After each byte has been transmitted, the

CAT1161/2 will respond with an acknowledge and

internally increment the lower order address bits by one. The

high order bits remain unchanged.

If the Master transmits more than 16 bytes before sending

the STOP condition, the address counter ‘wraps around,’

and previously transmitted data will be overwritten.

When all 16 bytes are received, and the STOP condition

has been sent by the Master, the internal programming cycle

begins. At this point, all received data is written to the

CAT1161/2 in a single write cycle.

Figure 7. Byte Write Timing

BYTE

ADDRESS

SLAVE

ADDRESS

DATA

BUS ACTIVITY:

MASTER

SDA LINE

Figure 8. Page Write Timing

BUS ACTIVITY:

MASTER

SDA LINE

DATA n+15

BYTE

ADDRESS (n)

DATA n

DATA n+1

SLAVE

ADDRESS

Acknowledge Polling

Disabling of the inputs can be used to take advantage of

the typical write cycle time. Once the stop condition is issued

to indicate the end of the host’s write operation, the

CAT1161/2 initiates the internal write cycle. ACK polling

can be initiated immediately. This involves issuing the start

condition followed by the slave address for a write

operation. If the CAT1161/2 is still busy with the write

operation, no ACK will be returned. If a write operation has

completed, an ACK will be returned and the host can then

proceed with the next read or write operation.

WRITE PROTECTION

The Write Protection feature allows the user to protect

against inadvertent memory array programming. If the WP

pin is tied to VCC, the entire memory array is protected and

becomes read only. The CAT1161/2 will accept both slave

and byte addresses, but the memory location accessed is

protected from programming by the device’s failure to send

an acknowledge after the first byte of data is received.

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READ OPERATIONS

The READ operation for the CAT1161/2 is initiated in the

same manner as the write operation with one exception, that

R/W bit is set to one. Three different READ operations are

possible: Immediate/Current Address READ,

Selective/Random READ and Sequential READ.

Immediate/Current Address Read

The CAT1161/2 address counter contains the address of

the last byte accessed, incremented by one. In other words,

if the last READ or WRITE access was to address N, the

READ immediately following would access data from

address N+1. For all devices, N=E=2047. The counter will

wrap around to Zero and continue to clock out valid data for

the 16K devices. After the CAT1161/2 receives its slave

address information (with the R/W bit set to one), it issues

an acknowledge, then transmits the 8−bit byte requested.

The master device does not send an acknowledge, but will

generate a STOP condition.

Figure 9. Immediate Address Read Timing

SCL

SDA8TH BIT

STOPNO ACKDATA OUT

SLAVE

ADDRESS

DATA N

BUS ACTIVITY:

MASTER

SDA LINE

Selective/Random Read

Selective/Random READ operations allow the Master

device to select at random any memory location for a READ

operation. The Master device first performs a ‘dummy’

write operation by sending the START condition, slave

address and byte addresses of the location it wishes to read.

After the CAT1161/2 acknowledges, the Master device

sends the START condition and the slave address again, this

time with the R/W bit set to one. The CAT1161/2 then

responds with its acknowledge and sends the 8−bit byte

requested. The master device does not send an acknowledge

but will generate a STOP condition.

Sequential Read

The Sequential READ operation can be initiated by either

the Immediate Address READ or Selective READ

operations. After the CAT1161/2 sends the inital 8−bit byte

requested, the Master will responds with an acknowledge

which tells the device it requires more data. The CAT1161/2

will continue to output an 8−bit byte for each acknowledge,

thus sending the STOP condition.

The data being transmitted from the CAT1161/2 is

outputted sequentially with data from address N followed by

data from address N+1. The READ operation address

counter increments all of the CAT1161/2 address bits so that

the entire memory array can be read during one operation.

If more than E (where E=2047 for the CAT1161/2) bytes are

read out, the counter will ‘wrap around’ and continue to

clock out data bytes.

Manual Reset Operation

The CAT116x RESET or RESET pin can also be used as

a manual reset input.

Only the “active” edge of the manual reset input is

internally sensed. The positive edge is sensed if RESET is

used as a manual reset input and the negative edge is sensed

if RESET is used as a manual reset input.

An internal counter starts a 200 ms count. During this

time, the complementary reset output will be kept in the

active state. If the manual reset input is forced active for

more than 200 ms, the complementary reset output will

switch back to the non active state after the 200 ms expired,

regardless for how long the manual reset input is forced

active.

The embedded EEPROM is disabled as long as a reset

condition is maintained on any RESET pin. If the external

forced RESET/RESET is longer than internal controlled

time−out period, tPURST, the memory will not respond with

an acknowledge for any access as long as the manual reset

input is active.

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Figure 10. Selective Read Timing

SLAVE

ADDRESS

BUS ACTIVITY:

MASTER

SDA LINE

BYTE

ADDRESS (n)

DATA n

SLAVE

ADDRESS

Figure 11. Sequential Read Timing

BUS ACTIVITY:

MASTER

SDA LINE

DATA n+xDATA n

DATA n+1

DATA n+2

SLAVE

ADDRESS

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ORDERING INFORMATION

Orderable Part Numbers − CAT1161/2 Series

(See Notes 1 − 4)

Device Reset Threshold

Voltage

Package−Pins Shipping

CAT1161LI−45−G4.50 V − 4.75 V

PDIP−8

3000 Tape & Reel

CAT1161LI−42−G4.25 V − 4.50 V

CAT1161LI−30−G3.00 V − 3.15 V

CAT1161LI−28−G2.85 V − 3.00 V

CAT1161LI−25−G2.55 V − 2.70 V

CAT1161WI−45−GT3 4.50 V − 4.75 V

SOIC−8

CAT1161WI−42−GT3 4.25 V − 4.50 V

CAT1161WI−30−GT3 3.00 V − 3.15 V

CAT1161WI−28−GT3 2.85 V − 3.00 V

CAT1161WI−25−GT3 2.55 V − 2.70 V

CAT1162LI−45−G4.50 V − 4.75 V

PDIP−8

CAT1162LI−42−G4.25 V − 4.50 V

CAT1162LI−30−G3.00 V − 3.15 V

CAT1162LI−28−G2.85 V − 3.00 V

CAT1162LI−25−G2.55 V − 2.70 V

CAT1162WI−45−GT3 4.50 V − 4.75 V

SOIC−8

CAT1162WI−42−GT3 4.25 V − 4.50 V

CAT1162WI−30−GT3 3.00 V − 3.15 V

CAT1162WI−28−GT3 2.85 V − 3.00 V

CAT1162WI−25−GT3 2.55 V − 2.70 V

1. All packages are RoHS−compliant (Lead−free, Halogen−free).

2. The standard lead finish is NiPdAu.

3. For additional package and temperature options, please contact your nearest

ON Semiconductor Sales office.

4. For detailed information and a breakdown of device nomenclature and numbering

systems, please see the ON Semiconductor Device Nomenclature document,

TND310/D, available at www.onsemi.com

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PACKAGE DIMENSIONS

PDIP−8, 300 mils

CASE 646AA−01

ISSUE A

TOP VIEW

SIDE VIEW END VIEW

PIN # 1

IDENTIFICATION

Notes:

(1) All dimensions are in millimeters.

(2) Complies with JEDEC MS-001.

SYMBOL MIN NOM MAX

0.38

2.92

0.36

6.10

1.14

0.20

9.02

2.54 BSC

3.30

5.33

4.95

0.56

7.11

1.78

0.36

10.16

eB 7.87 10.92

E 7.62 8.25

2.92 3.80

3.30

0.46

6.35

1.52

0.25

9.27

7.87

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SOIC 8, 150 mils

CASE 751BD−01

ISSUE O

E1 E

PIN # 1

IDENTIFICATION

TOP VIEW

SIDE VIEW END VIEW

Notes:

(1) All dimensions are in millimeters. Angles in degrees.

(2) Complies with JEDEC MS-012.

SYMBOL MIN NOM MAX

0º 8º

0.10

0.33

0.19

0.25

4.80

5.80

3.80

1.27 BSC

1.75

0.25

0.51

0.25

0.50

5.00

6.20

4.00

L0.40 1.27

1.35

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Phone: 81−3−5817−1050

CAT1161/D

LITERATURE FULFILLMENT:

Literature Distribution Center for ON Semiconductor

P.O. Box 5163, Denver, Colorado 80217 USA

Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada

Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada

Email: orderlit@onsemi.com

ON Semiconductor Website: www.onsemi.com

Order Literature: http://www.onsemi.com/orderlit

For additional information, please contact your local

Sales Representative

Mouser Electronics

Authorized Distributor

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ON Semiconductor:

CAT1162WI42 CAT1162WI-28-G CAT1161WI-25-G CAT1162WI-30-G CAT1162LI-45 CAT1162WI-25-G