MC14012B Dual 4-Input NAND Gates The MC14012B dual 4-input NAND gates are constructed with P-Channel and N-Channel enhancement mode devices in a single monolithic structure (Complementary MOS). Their primary use is where low power dissipation and/or high noise immunity is desired. http://onsemi.com Features * Supply Voltage Range = 3.0 Vdc to 18 Vdc * All Outputs Buffered * Capable of Driving Two Low-Power TTL Loads or One Low-Power * * * * MARKING DIAGRAMS Schottky TTL Load Over the Rated Temperature Range Double Diode Protection on All Inputs Pin-for-Pin Replacements for Corresponding CD4000 Series B Suffix Devices These Devices are Pb-Free and are RoHS Compliant NLV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC-Q100 Qualified and PPAP Capable 14 PDIP-14 P SUFFIX CASE 646 1 14 SOIC-14 D SUFFIX CASE 751A Value Unit -0.5 to +18.0 V -0.5 to VDD + 0.5 V Input or Output Current (DC or Transient) per Pin 10 mA PD Power Dissipation, per Package (Note 1) 500 mW TA Ambient Temperature Range -55 to +125 C Tstg Storage Temperature Range -65 to +150 C TL Lead Temperature (8-Second Soldering) 260 C VDD Parameter Vin, Vout Iin, Iout DC Supply Voltage Range Input or Output Voltage Range (DC or Transient) 14012BG AWLYWW 1 MAXIMUM RATINGS (Voltages Referenced to VSS) Symbol MC14012BCP AWLYYWWG A WL, L YY, Y WW, W G = Assembly Location = Wafer Lot = Year = Work Week = Pb-Free Package ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 2 of this data sheet. Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. Temperature Derating: Plastic "P and D/DW" Packages: - 7.0 mW/_C From 65_C To 125_C This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, Vin and Vout should be constrained to the range VSS v (Vin or Vout) v VDD. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD). Unused outputs must be left open. (c) Semiconductor Components Industries, LLC, 2013 April, 2013 - Rev. 10 1 Publication Order Number: MC14012B/D MC14012B MC14012B Dual 4-Input NAND Gate OUTA 1 14 VDD IN 1A 2 13 OUTB IN 2A 3 12 IN 4B IN 3A 4 11 IN 3B IN 4A 5 10 IN 2B NC 6 9 IN 1B VSS 7 8 NC 2 3 4 5 9 10 11 12 1 13 NC = 6, 8 VDD = PIN 14 VSS = PIN 7 NC = NO CONNECTION Figure 1. Pin Assignment Figure 2. Logic Diagram ORDERING INFORMATION Package Shipping MC14012BCPG PDIP-14 (Pb-Free) 25 Units / Rail MC14012BDG SOIC-14 (Pb-Free) 55 Units / Rail SOIC-14 (Pb-Free) 2500 Units / Tape & Reel Device NLV14012BDG* MC14012BDR2G NLV14012BDR2G* For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. *NLV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC-Q100 Qualified and PPAP Capable. http://onsemi.com 2 MC14012B IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIII IIIII IIIIIIIII IIIII III IIIIII IIIIIIIIIIIIII IIIIIII IIIIII IIIIII IIII IIII IIIIIII IIIIIII IIIIII IIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIII IIII III III III IIII III IIII III III III IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIII IIII III III III IIII III IIII III III III IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIII III IIII III III III IIII IIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIII IIII III IIIIIIIIIIIIIIIII III IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS) Characteristic Output Voltage Vin = VDD or 0 Symbol - 55_C 25_C 125_C VDD Vdc Min Max Min Typ (Note 2) Max Min Max Unit "0" Level VOL 5.0 10 15 - - - 0.05 0.05 0.05 - - - 0 0 0 0.05 0.05 0.05 - - - 0.05 0.05 0.05 Vdc "1" Level VOH 5.0 10 15 4.95 9.95 14.95 - - - 4.95 9.95 14.95 5.0 10 15 - - - 4.95 9.95 14.95 - - - Vdc Input Voltage "0" Level (VO = 4.5 or 0.5 Vdc) (VO = 9.0 or 1.0 Vdc) (VO = 13.5 or 1.5 Vdc) VIL 5.0 10 15 - - - 1.5 3.0 4.0 - - - 2.25 4.50 6.75 1.5 3.0 4.0 - - - 1.5 3.0 4.0 "1" Level VIH 5.0 10 15 3.5 7.0 11 - - - 3.5 7.0 11 2.75 5.50 8.25 - - - 3.5 7.0 11 - - - 5.0 5.0 10 15 - 3.0 - 0.64 - 1.6 - 4.2 - - - - - 2.4 - 0.51 - 1.3 - 3.4 - 4.2 - 0.88 - 2.25 - 8.8 - - - - - 1.7 - 0.36 - 0.9 - 2.4 - - - - IOL 5.0 10 15 0.64 1.6 4.2 - - - 0.51 1.3 3.4 0.88 2.25 8.8 - - - 0.36 0.9 2.4 - - - mAdc Input Current Iin 15 - 0.1 - 0.00001 0.1 - 1.0 mAdc Input Capacitance (Vin = 0) Cin - - - - 5.0 7.5 - - pF Quiescent Current (Per Package) IDD 5.0 10 15 - - - 0.25 0.5 1.0 - - - 0.0005 0.0010 0.0015 0.25 0.5 1.0 - - - 7.5 15 30 mAdc IT 5.0 10 15 Vin = 0 or VDD (VO = 0.5 or 4.5 Vdc) (VO = 1.0 or 9.0 Vdc) (VO = 1.5 or 13.5 Vdc) Output Drive Current (VOH = 2.5 Vdc) (VOH = 4.6 Vdc) (VOH = 9.5 Vdc) (VOH = 13.5 Vdc) (VOL = 0.4 Vdc) (VOL = 0.5 Vdc) (VOL = 1.5 Vdc) Source Sink Total Supply Current (Notes 3, 4) (Dynamic plus Quiescent, Per Gate, CL = 50 pF) IOH Vdc Vdc mAdc IT = (0.3 mA/kHz) f + IDD/N IT = (0.6 mA/kHz) f + IDD/N IT = (0.9 mA/kHz) f + IDD/N mAdc 2. Data labelled "Typ" is not to be used for design purposes but is intended as an indication of the IC's potential performance. 3. The formulas given are for the typical characteristics only at 25_C. 4. To calculate total supply current at loads other than 50 pF: IT(CL) = IT(50 pF) + (CL - 50) Vfk where: IT is in mA (per package), CL in pF, V = (VDD - VSS) in volts, f in kHz is input frequency, and k = 0.001 x the number of exercised gates per package. http://onsemi.com 3 MC14012B IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIII IIIII IIII IIII IIII IIII III IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII SWITCHING CHARACTERISTICS (Note 5) (CL = 50 pF, TA = 25_C) Characteristic Symbol Output Rise Time tTLH = (1.35 ns/pF) CL + 33 ns tTLH = (0.60 ns/pF) CL + 20 ns tTLH = (0.40 ns/PF) CL + 20 ns tTLH Output Fall Time tTHL = (1.35 ns/pF) CL + 33 ns tTHL = (0.60 ns/pF) CL + 20 ns tTHL = (0.40 ns/pF) CL + 20 ns tTHL Propagation Delay Time tPLH, tPHL = (0.90 ns/pF) CL + 115 ns tPLH, tPHL = (0.36 ns/pF) CL + 47 ns tPLH, tPHL = (0.26 ns/pF) CL + 37 ns VDD Vdc Min Typ (Note 6) Max 5.0 10 15 - - - 100 50 40 200 100 80 5.0 10 15 - - - 100 50 40 200 100 80 5.0 10 15 - - - 160 65 50 300 130 100 Unit ns ns tPLH, tPHL ns 5. The formulas given are for the typical characteristics only at 25_C. 6. Data labelled "Typ" is not to be used for design purposes but is intended as an indication of the IC's potential performance. 14 PULSE GENERATOR 20 ns VDD 20 ns 90% 50% 10% INPUT INPUT OUTPUT tPHL CL * 7 OUTPUT INVERTING *All unused inputs of AND, NAND gates must be connected to VDD. All unused inputs of OR, NOR gates must be connected to VSS. tTHL tPLH Figure 3. Switching Time Test Circuit and Waveforms VDD VDD 2, 9 * 3, 10 VSS 4, 11 5, 12 1, 13 SAME AS ABOVE 7 *Inverter omitted VSS Figure 4. Circuit Schematic - One of Two Gates Shown http://onsemi.com 4 VOH tTLH tPHL tTLH 14 0V tPLH 90% 50% 10% OUTPUT NON-INVERTING VSS VDD 90% 50% 10% tTHL VOL VOH VOL MC14012B TYPICAL B-SERIES GATE CHARACTERISTICS N-CHANNEL DRAIN CURRENT (SINK) P-CHANNEL DRAIN CURRENT (SOURCE) -10 5.0 ID , DRAIN CURRENT (mA) ID , DRAIN CURRENT (mA) -9.0 4.0 TA = -55C 3.0 -40C +85C +25C 2.0 +125C 1.0 -8.0 TA = -55C -7.0 -40C -6.0 -5.0 +25C +85C -4.0 -3.0 +125C -2.0 -1.0 0 0 1.0 2.0 3.0 4.0 0 5.0 0 VDS, DRAIN-TO-SOURCE VOLTAGE (Vdc) Figure 5. VGS = 5.0 Vdc 16 14 -40C 12 +25C +85C 10 ID , DRAIN CURRENT (mA) ID , DRAIN CURRENT (mA) -4.0 -5.0 -45 TA = -55C +125C 8.0 6.0 -40 -35 TA = -55C -30 -25 + 25C -20 +125C 4.0 -10 2.0 -5.0 0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 0 0 10 -1.0 -2.0 -3.0 -4.0 -5.0 -6.0 -7.0 -8.0 -9.0 -10 VDS, DRAIN-TO-SOURCE VOLTAGE (Vdc) Figure 7. VGS = 10 Vdc Figure 8. VGS = - 10 Vdc - 100 45 - 90 40 - 80 ID , DRAIN CURRENT (mA) 50 TA = -55C 35 30 -40C 25 +25C 20 +85C +125C 15 -40C +85C -15 VDS, DRAIN-TO-SOURCE VOLTAGE (Vdc) ID , DRAIN CURRENT (mA) -3.0 -50 18 10 5.0 0 -2.0 Figure 6. VGS = - 5.0 Vdc 20 0 -1.0 VDS, DRAIN-TO-SOURCE VOLTAGE (Vdc) - 70 - 60 TA = -55C - 50 +25C - 40 -40C +85C - 30 +125C - 20 - 10 0 2.0 4.0 6.0 8.0 10 12 14 16 18 0 20 0 VDS, DRAIN-TO-SOURCE VOLTAGE (Vdc) Figure 9. VGS = 15 Vdc -2.0 -4.0 -6.0 -8.0 -10 -12 -14 -16 -18 -20 VDS, DRAIN-TO-SOURCE VOLTAGE (Vdc) Figure 10. VGS = - 15 Vdc These typical curves are not guarantees, but are design aids. Caution: The maximum rating for output current is 10 mA per pin. http://onsemi.com 5 MC14012B V out , OUTPUT VOLTAGE (Vdc) V out , OUTPUT VOLTAGE (Vdc) VOLTAGE TRANSFER CHARACTERISTICS SINGLE INPUT NAND, AND MULTIPLE INPUT NOR, OR 5.0 4.0 SINGLE INPUT NOR, OR MULTIPLE INPUT NAND, AND 3.0 2.0 1.0 0 0 1.0 8.0 SINGLE INPUT NOR, OR MULTIPLE INPUT NAND, AND 6.0 4.0 2.0 0 2.0 3.0 4.0 5.0 Vin, INPUT VOLTAGE (Vdc) SINGLE INPUT NAND, AND MULTIPLE INPUT NOR, OR 10 2.0 0 4.0 6.0 8.0 10 Vin, INPUT VOLTAGE (Vdc) Figure 11. VDD = 5.0 Vdc DC NOISE MARGIN SINGLE INPUT NAND, AND MULTIPLE INPUT NOR, OR 16 V out , OUTPUT VOLTAGE (Vdc) Figure 12. VDD = 10 Vdc The DC noise margin is defined as the input voltage range from an ideal "1" or "0" input level which does not produce output state change(s). The typical and guaranteed limit values of the input values VIL and VIH for the output(s) to be at a fixed voltage VO are given in the Electrical Characteristics table. VIL and VIH are presented graphically in Figure 11. Guaranteed minimum noise margins for both the "1" and "0" levels = 1.0 V with a 5.0 V supply 2.0 V with a 10.0 V supply 2.5 V with a 15.0 V supply 14 12 SINGLE INPUT NOR, OR MULTIPLE INPUT NAND, A 10 8.0 6.0 4.0 2.0 0 0 2.0 4.0 6.0 8.0 10 Vin, INPUT VOLTAGE (Vdc) Figure 13. VDD = 15 Vdc VDD Vout Vout VO VO VO VO VDD VDD VDD 0 Vin 0 VIL VIH Vin VIL VIH VSS = 0 VOLTS DC (a) Inverting Function (b) Non-Inverting Function Figure 14. DC Noise Immunity http://onsemi.com 6 MC14012B PACKAGE DIMENSIONS SOIC-14 NB CASE 751A-03 ISSUE K D A B 14 8 NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE PROTRUSION SHALL BE 0.13 TOTAL IN EXCESS OF AT MAXIMUM MATERIAL CONDITION. 4. DIMENSIONS D AND E DO NOT INCLUDE MOLD PROTRUSIONS. 5. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE. A3 E H L 1 0.25 M DETAIL A 7 B 13X M b 0.25 M C A S B S e DETAIL A h A X 45 _ M A1 C SEATING PLANE DIM A A1 A3 b D E e H h L M MILLIMETERS MIN MAX 1.35 1.75 0.10 0.25 0.19 0.25 0.35 0.49 8.55 8.75 3.80 4.00 1.27 BSC 5.80 6.20 0.25 0.50 0.40 1.25 0_ 7_ SOLDERING FOOTPRINT* 6.50 14X 1.18 1 1.27 PITCH 14X 0.58 DIMENSIONS: MILLIMETERS *For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. http://onsemi.com 7 INCHES MIN MAX 0.054 0.068 0.004 0.010 0.008 0.010 0.014 0.019 0.337 0.344 0.150 0.157 0.050 BSC 0.228 0.244 0.010 0.019 0.016 0.049 0_ 7_ MC14012B PACKAGE DIMENSIONS PDIP-14 CASE 646-06 ISSUE P 14 8 1 7 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 5. ROUNDED CORNERS OPTIONAL. B A F L N C -T- SEATING PLANE H G D 14 PL J K 0.13 (0.005) M DIM A B C D F G H J K L M N INCHES MIN MAX 0.715 0.770 0.240 0.260 0.145 0.185 0.015 0.021 0.040 0.070 0.100 BSC 0.052 0.095 0.008 0.015 0.115 0.135 0.290 0.310 --- 10 _ 0.015 0.039 MILLIMETERS MIN MAX 18.16 19.56 6.10 6.60 3.69 4.69 0.38 0.53 1.02 1.78 2.54 BSC 1.32 2.41 0.20 0.38 2.92 3.43 7.37 7.87 --- 10 _ 0.38 1.01 M ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC's product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent-Marking.pdf. SCILLC reserves the right to make changes without further notice to any products herein. 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