MMCP-672061HV-15 - Atmel Corporation

4144I–AERO–05/04

Features

•First-in First -out Dual Port Memory

•16384 bits x 9 Organizat ion

•Fast Flag and Access Times: 15, 30 ns

•Wi de Temperat ure Range: -55°C to +125°C

•Programmable Half Full Flag

•Fully Expandable by Word Width or Depth

•Asynchronous Read/W rite Operat ions

•Empty, Full and Half Fla gs in Sing le Devi ce M ode

•Retransmit Capability

•Bi-directional Applicat ions

•Battery Back-up Operation: 2V Data Retention

•TTL Compatible

•Single 5V + 10% Power Supply

•No Single Event Latch U p Below an LET threshold of 80 MeV/mg/cm2

•Tested up to a Total Dose of 30 Kra ds (accorcing to MIL-STD-883 TM 1019)

•QML Q and V with SMD 5962-93177

•ESSC B wit h Specificati on 9301/48

Description

The M672061H implements a first-in first-out algorithm, featuring asynchronous

read/wri te o perations . The FULL and E MPTY flags prevent data overf low and un der-

flow. The Expans ion logic a llows unl imited expansion i n word size an d de pth with no

timing penaltie s. Twin address pointers auto matically generate int ernal read and write

addresses, and no external address information are required for the Atmel FIFOs.

Address pointers are automatically incremented with the wr ite pin and read pin. The 9

bits wide data are used in data communications applications where a parity bit for

error checking is necessary. The Retransm it pin resets the Read pointer to zero with-

out affect ing the write pointer. This is very useful for retransmitting data when an error

is detected in the system.

Using an array of eight transistors (8T) memory cell, the M672061H combines an

extremely low standby supply current (typ = 0.1 µ A) with a fast access time at 15 ns

over the full t emperatu re range. All vers ions offer battery ba ckup data rete ntion capa-

bility with a typical power consump tion at less than 2 µW.

For m ilitary /spa ce ap plica tio ns th at dem and su perio r leve ls of perfo rm ance and r el i-

abilit y the M 67206 1H is proc ess ed acc ording to th e metho ds of t he latest revisio n of

the MIL PRF 38535 (Q and V) or ESA SCC 9000.

Rad. Tolerant

High Speed

16 Kb x 9

Parallel FIFO with

Programm able

Flag

M672061H

4144I–AERO–05/04

Block Diagram

Pin Configuration

DIL ceramic 28-pin 300 mils

FP 28-pin 400 mils

M672061H

4144I–AERO–05/04

Pin Description

Data In (I0 - I8)Da ta inputs for 9-bit data

Reset (RS) Reset o ccurs whenev er the Reset (RS) input is taken t o a low s tate. Reset returns both

internal re ad and wri te pointers to the first location. A reset is req uired after powe r-up

before a write operation can be enabled. Both the Read Enable (R) and Write Enable

(W) inputs must be in the high state during the period shown in Figure 2 (i.e. tRSS before

the rising edge of RS) and should not change until tRSR after the rising edge of RS.

Othe rwise, p ulse write (or read) low durin g th e reset o peration lo ads th e Programm abl e

Half Full Flag register f rom the data Inputs I0 - I8 ( or data out puts Q0 - Q8) (shown i n fig-

ure 2). In these two cases the Full Flag and the Programmable Half Full Flag are

reseted to high and the Empty Flag to low.

Figu re 1. Reset (no write to Programmable Half Full Flag register)

Notes: 1. EF, FF and HF may change status during reset, but flags will be valid at tRSC.

2. W and R = VIH around the r ising edge of RS.

Pin Name Description

I0 - 8 Inputs

Q0 - 8 Outputs

W Wr ite Enable

R Read Enable

RS Reset

EF Empty Fla g

FF Full Flag

XO /HF Ex pa nsion Ou t/H a lf-Fu ll Flag

XI Expansion IN

FL/RT First Load/Ret ransmit

VCC Power Supply

GND Ground

M672061H

4144I–AERO–05/04

Figu re 2. Reset (write (read) to Programmable Half Full Flag register)

Wr ite Enab le (W )A w rite cycle is initiated on the falling edge of this input if the Full Flag (FF) is not set.

D ata s et-u p and hold time s mus t be mai ntai ned in the rise time of th e lea ding edge of

the Write Enable (W). Data is stored sequentially in the Ram array, regardless of any

current read operation.

Once half the memory is filled, and during the falling edge of the next write operation,

the Half-Full Flag (HF) w ill be set to low and remain in this s tate until the di fference

between the write and read pointers is less than or equal to half of the total available

memory in the device. The Half-Full Flag (HF) is then reset by the rising edge of the

read operation.

To prevent data overflow, the Full Flag (FF) will go low, inhibiting further write opera-

tions. On completion of a valid read operation, the Full Flag (FF) will go high af ter TRFF,

allowing a valid write to begin. When the FIFO stack is full, the internal write pointer is

blocked f rom W, so that external changes to W will have no effect on the full FIFO stac k.

Read Enable (R)A read cycle is initiated on the falling edge of the Read Enable (R) provided that the

Empty Flag ( EF) is not set. The data is accessed on a first i n/first out basis, not including

any current write operations. After Read Enable (R) goes high, the Data Out puts

(Q0 - Q8 ) will return t o a high imp edance s tate until the next Read operation. When al l

the dat a in the FIFO s tack has bee n read, the E mp ty Flag (E F) will g o low, a ll o w ing t he

“final” read cycle, but inhibiting f urth er read operat ions while the data output s remain in

a high impedance state. Once a valid write operation has been completed, the E mpty

Flag (EF) will go high after tWEF and a valid read may then be initiated. When the FIFO

stack is empty, the internal read pointer is blocked from R, so that external changes to R

will have no effect on the empty FIFO stack.

First Load/Retransm it

(FL/RT) This is a dual-purpose input. In the Depth Expansion Mode, this pin is connected to

ground t o i ndicat e that it is the first loaded (see Operating Mo des ). In the Single Device

Mode , this pin acts as the retransmi t input . Th e Single Device Mod e is initiated by con-

necting the Expansion In (XI) to ground.

The M 672061H ca n be s et to ret ransmi t data when the Retransmit Enable Cont rol (R T)

input is pulsed low. A retransmit operation will set the internal read point to the first loca-

tion and will not affect the write pointer. Read Enable (R) and Write Enable (W) must be

in the high state during retransmit. The retransmit feature is intended for use when a

numb er of writes are equal to or less than the depth of the FIF O has occured since t he

last RS cycle. The retransmit feature is not compatible with the Depth Expansion Mode

and will affect the Half-Full Flag (HF), in accordance with the relative locations of the

read and write pointers.

M672061H

4144I–AERO–05/04

Expansion In (XI)Thi s input is a du al-pur pose pin. E xpans ion In (XI ) is conn ected to GN D to indi cate a n

ope rati on in th e si ngle device mod e. E xpans ion In (XI) is connected to Expansion Out

(XO) of the previous device in the Depth Expansion or Dais y Chain modes.

Full Flag (FF)The Full Flag (FF) wi ll go low, inhibiting further write operations when the write pointer is

one location less than the read pointer, indicating that the device is full. If the read

pointer is not moved after Reset (RS), the Full Flag (FF) will go low after 16384 writes.

Emp ty Flag (EF)The Em pty Flag (EF) will go low, inhibiting further read operations when the read pointer

is equal to the write pointer, indicating tha t the device is empty.

Expansion Out/Half-full

Flag (XO/HF) This is a dual-purpose output. In the single device mode, when Expansion I n (XI) is con-

nected to ground, this outpu t acts as an in dication of a half-full mem ory .

Th e M6 7206 1H offer s a v ariab le o ffs et for the Half F ull c ondi tion . The o ff set is l oade d

into a register d uring a re set cycle. W hen RS is low, the Programmable Half Full Flag

(PHF) can be loaded from the DATA inputs I0 - I8 by pulsing W low or from the DATA

out puts Q0 - Q8 by pulsing R low. Th e offs et o ptions are l isted in ta ble 1. If PHF i s not

loaded during the reset cycl e, t he default offset will be the half of the total memory of the

device.

Th e Pro gram ma ble H alf -Full F lag (PH F) will be set to l ow and wil l rem ain set until the

difference between t he write and read pointers is less than or equal to the Program ma-

ble offset (if the Half Full Flag register has been loaded during the reset cycle) or the half

of the total memory (if the Half Full register has n ot been loaded during the reset cycle).

After half the memory is filled and on the falling edge of the next write operation, the

Half-F ull Flag (HF ) will be set t o low a nd will rem ain set until the d ifference b etwe en t he

write and read pointers is less than or equal to half of the total memory of the device.

The Half-Full Flag (HF) is then reset by the rising edge of the read operation.

In the Depth Expansion Mod e, Expansion In (XI) is connected t o Expansion Out ( X O) of

the previous device. This output acts as a signal to t he next device in the Daisy Chain by

providing a pulse to the next dev ice when t he previo us device reaches t he l ast mem ory

location.

Data Output (Q0 - Q8)D ATA outp ut fo r 9-bit w ide d ata. This data i s in a high impe danc e con dit ion w henev er

Read (R) is in a high state.

M672061H

4144I–AERO–05/04

Functional Description

Single Device Mode A single M672061H may be used when the application requirements are for 16384

words or less. The M672061H i s i n a S in g le De vi ce C onf i gu ra ti o n w he n t he E xp an si o n I n (X I )

cont ro l in put i s g round ed ( see Figure 3). In t hi s mo de th e Ha lf-F ul l Fl ag ( HF) , which is an active

low output, is shared with Expansion Out (XO).

Fi gure 3. Block Diagram of Single 16384 × 9

Width Expansion Mode W ord width m ay be increas ed simply by connec ting the c orrespondin g input c ont rol sig-

nals of multiple devices. Status flags (EF, FF and HF) can be detect ed from any device.

Figure 4 demonstrates an 18-bit word width by using two M672061H. Any word width can be

att ain ed by add ing a ddi ti onal M6 72061H .

Figu re 4. Block Diagram of 16384 bits x 18 FI FO Memory Used in Width Expansion Mode

Note: Flag detection is accomplished by m onitoring the FF, EF and the HF signals on either (any) device used in the width expansion

configuration. Do not connect any out put control si gnals together.

(HALF-FULL FLAG)

WRITE (W

)

(R) READ

DATAIN

(I) DATAOUT

(Q)

FULL FLAG

RESET

(FF)

(RS)

EMPT Y FLAG

RETRANSMIT

(EF)

(RT)

EXPANSION IN (XI)

M672061H

4144I–AERO–05/04

Note: 1. Pointer will increment if flag is high.

Note: 1. XI is connected to XO o f pre vio us de vice.

See Figur e 5.

Tab le 1. Programmable Half Full Flag Offset

I8I7I6I5I4I3I2I1I0Offset

000000000 0

000000001 32

000000010 64

...

100000000 8192 (Half Full)

De fa u lt O ffs e t

...

111111110 16384-64

111111111 16384-32

Tab le 2. Reset and Ret ransmit Single Device Conf iguration/Width E xpansion Mode

Mode

Inputs Intern al Status Outputs

RS RT XI Re a d Po in te r Writ e Poin ter EF FF HF

Reset 0 X 0 Location Zero Location Zero 0 1 1

Retransmit 1 0 0 Location Zero Unchanged X X X

Read/Write 1 1 0 Increment(1) Increment(1) XXX

Tab le 3. Reset and First Load Tr uth Table

Depth Expan sion/C omp ound Exp ansion Mo de

Mode

Inputs Internal Status Outputs

RS FL XI Read Pointer Write Pointer EF FF

Re s e t Fi rs t D e vi ce 0 0 (1) Location Zer o Location Zero 0 1

Reset All Other Devices 0 1 (1) Location Zero Location Zero 0 1

Read/Write 1 X (1) XX XX

M672061H

4144I–AERO–05/04

Depth Expansion (Daisy

Chain) Mode The M672 061H c an be easily a dap ted for appli cations wh ich require more th an 1 6384

word s. Figure 5 demonst ra tes Depth Expans ion using three M672061H . Any depth can

be achieved by adding additional 672061H.

The M672061H operates in the Depth Expansion configuration if the following condi-

tions are met:

1. The first device must be designated by connecting the First Load (FL) control

i nput t o gro und.

2. All othe r devices must have FL in the h igh s t ate.

3. The Expansion Out (XO) pi n of each d evi ce must be con nect ed to the Ex pan sio n In

(XI) pi n of t he next devi ce . See Figure 5.

4. External logic is needed to generate a composite Full Flag (F F) and Em pty F lag

(EF). Thi s requires that al l EF’s and al l FFs be ORed (i.e. al l must be set to gener ate th e

correct composite FF or EF) . Se e F i gu r e 5.

5. The Retransmit (RT) func tion and H alf -Ful l Fla g (HF) are not avai l able i n the D epth

Ex pans ion Mode.

Co mp ou nd Expansio n

Module It i s quite si mple to apply the two expansion techniques described above together to cre-

ate large FIFO arrays (see Figure 6).

Bi directional Mo de Applications which require data buffering between two systems (each system being

capable of Read and Write operations) can be created by coupling M672061H as shown

in Fi gure 7 Care must be tak en to ens ure that t he app ropriat e flag is m onitored by each

system (i.e. FF i s monit ored on the d ev ice on wh ich W i s in use; EF is monit o red on the dev ice

on whi ch R is i n use ). B oth De pth E xpans ion and Wi dth E xpans ion may be us ed in thi s mode.

Data Flow – Through

Modes Two types of flow-through modes are permitted: a read flow-through and a write flow-

through mode. In the read flow-through mode ( F i gure 18) the FIFO stack allows a single

word to be read after one word has been written to an empty FIFO stack. The data is

enabl ed on th e bus at (tWE F + tA) ns after t he leading ed ge of W whi ch is known as t he

firs t wr it e edge a nd r emain s on the bu s unt il t he R line is raised from low to hi gh, after which the

bus wi ll go i nt o a t hree-state mod e after tRHZ ns. T he EF line will show a pulse indic ating tem-

porar y res et and t he n will be se t. In t he in te rval in whi ch R is low, more words may be written to

the FI FO st ack (the subse que nt wr it es af ter t he fi rs t wr it e edge wi l l re set the Empt y Fl ag) ; how-

ever, the same word (written on the first write edge) presented to the outp ut bus as the read

pointer wi ll not be in crem ent ed if R is lo w. On t og gling R, th e r emaining word s w rit ten to the

FIF O will appe ar o n the o ut put bu s in acco rdanc e wit h th e re ad cy cle ti mi ngs.

In the write flow-through mode (Fi gure 19), the FIFO stac k a llows a single word of data

to be written immediately after a single word of data has been read from a full FIFO

stack. The R lin e caus es the FF to be reset, but the W li ne, be ing low, cause s i t to be se t aga in

in anti cipation of a new data word. The new word is lo aded i nto the FIFO st ack on t he l eading

edge of W. The W line must be toggled when FF is not set in order to write new data into the

FIF O stack and to i nc remen t th e wri te po int er.

M672061H

4144I–AERO–05/04

Figu re 5. Block Diagram of 49152 x 9 FIFO Memory (Depth Expansion)

Figu re 6. Comp ound FIFO Expansio n

Notes: 1. For depth expansion block see secti on on De pth Expan sion and Figure 4.

2. For Flag det ection see secti on on Width Expansion and Figur e 3

Figu re 7. Bidirectional FIFO Mode

M672061H

4144I–AERO–05/04

Electrical Characteristics

Ab solu te Maximum Rating s

DC Param eters

Notes: 1. Icc measurements are made with outputs open.

2. R = W = RS = F L / RT = VIH.

3. All input = Vcc

Notes: 1. 0.4 ≤ Vin ≤ Vcc.

2. R = VIH, 0.4 ≤ VOUT ≤ VCC.

3. VIH max = Vcc + 0.3V. VIL min = -0.3V or -1V pulse wi dth 50 ns. For XI input, VIH= 2.8 V

4. Vcc min, IOL = 8 mA, IOH = -2 mA

5. Guara nteed but not tes ted.

Su pp l y volta g e (VC C - GN D ):...... ... ..... .. ... ..... .. ... -0.5 V to 7.0V

Input or Output voltage applied: ...(GND -0.3V) t o (Vcc +0.3V)

Storage temperature:... ... .. ... .. ... .. ..... .. ........ .. . -65 °C to +150°C

*NO TICE: Stresses beyond those listed under "Absol ute Max i-

mum Ratings” may cause permanent damage to the

device. This is a stress rating only and functional oper-

ation of the d evice at these or any other conditio ns

beyond th ose indicated in the operation al secti ons of

this specification is not implied. Expo sure to absolute

maximum rating conditions for extended periods may

affect device reliability.

Tab le 4. DC Test Con ditions

TA = -5 5°C to +125°C; Vss = 0V; Vcc = 4.5V to 5.5V

Parameter Description M672061H-30 M672061H-15 Unit Value

ICCOP (1) Operati ng supply current 110 120 mA Max

ICCSB(2) Standby supply curr ent 5 5 mA Max

ICCPD(3) Power down current 400 400 µAMax

Parameter Description M672061H Unit Value

ILI(1) Input leakage current ± 1µAMax

ILO(2) Output leakage current ± 1µAMax

VIL(3) Input low voltage 0.8 V Max

VIH(3) Input high vol tage 2.2 V Min

VOL(4) Output low voltage 0.4 V Max

VOH(4) Output high voltage 2.4 V Min

C IN(5) Input capacitance 8 pF Max

C OUT(5) Output capacitance 8 pF Max

M672061H

4144I–AERO–05/04

AC Parameters

AC Test Conditions Input pulse levels: Gnd to 3.0V

Input rise/F all times: 5 ns

Input timing reference levels: 1.5V

Outp ut reference levels: 1.5V

Outp ut load: See Figure 8

Fi gure 8. Output Load

Note: 1. Includes jig and scope capacitance.

(1)

Tab le 5. AC Test Condit ions

Symbol (1) Symbol (2) Parameter (3) (4) M67206 1H- 30 M67 2061H- 15 Unit

Min Max Min Max

Read Cycle

TR LRL tRC Read cycle t ime 40 - 25 - ns

TRLQV tA Access time - 30 - 15 ns

TRHRL tRR Read recovery ti me 10 - 10 - ns

TRLRH tRPW Read pulse widt h (5) 30 - 15 - ns

TRLQX tRLZ Read low to data low Z (6) 0-0-ns

TWHQX tWLZ Writ e low to dat a low Z (6 ) (7) 5-3-ns

TRHQX tDV Data valid fro m read hig h 5 - 5 - ns

TRHQZ tRHZ Read high to data high Z (6) - 20 - 15 ns

Wr ite Cycle

TWLWL tWC Write cycle time 40 - 25 - ns

TWLWH tWP W Wr i te pul s e wi dt h (5) 30 - 15 - ns

TWHWL tWR Write recovery time 10 - 10 - ns

TDVWH tDS Data set-up time 18 - 9 - ns

TWHDX tDH Dat a hold time 0 - 0 - ns

Reset Cycle

TRSLW L tRSC Reset cycle time 40 - 25 - ns

TRSLRSH tRS Reset pulse width (5) 30 - 15 - ns

TWHRSH tRSS Reset set-up time 30 - 20 - ns

M672061H

4144I–AERO–05/04

TRSHWL tRSR Reset recovery tim e 10 – 10 – ns

Retransmit Cycle

TRTLWL tRTC Retransmit cycle time 40 – 25 – ns

TRTLRTH tRT Retransmit pul se width(5) 30–15–ns

TWHRTH tRTS Retransmit set-up time(6) 30–15–ns

TRTHWL tRTR Retransmit recovery time 10 – 10 – ns

Flags

TRSLEFL tEFL Reset to EF low – 30 – 25 ns

TR SLFFH tHFH, tFFH Reset to HF/FF high – 30 – 25 ns

TRLEFL tREF Read low to EF low – 30 – 25 ns

TRHFFH tRFF Read high to FF high – 30 – 25 ns

TEFHRH tRPE Read widt h after EF high 30 – 15 – ns

TW H EF H tWE F Writ e high to EF hig h – 30 – 15 n s

TWLFFL t WFF Write low to FF low – 30 – 20 ns

TWLHFL tWHF Write low t o HF low – 30 – 30 ns

TRHHFH tRHF Read high to HF high – 30 – 30 ns

TFFHWH tWPF Write widt h after FF high 30 – 15 – ns

Expansion

TWLXOL tXOL Read/Wr it e to XO low – 30 – 15 ns

TWHXOH tXOH Read/Writ e to XO high – 30 – 15 ns

TXILXIH tXI XI pulse width 30 – 15 – ns

TXIHXIL tXIR XI recover y time 10 – 10 – ns

TXILRL tXIS XI set-up time 10 – 10 – ns

1. STD symbol.

2. ALT symbo l.

3. Ti mings referenced as in ac test conditions.

4. All paramete rs t ested only.

5. Pulse widths less than minimum value ar e not allowed.

6. Values guaranteed by design, not currently tested.

7. Only applies to read data flow- through mo de.

Tab le 5. AC Test Condit ions (Cont i nued)

Symbol (1) Symbol (2) Parameter (3) (4) M67206 1H- 30 M67 2061H- 15 Unit

Min Max Min Max

M672061H

4144I–AERO–05/04

Figu re 9. Asynchronou s Write and Read Ope ration

Figu re 10. Full Flag from Last Write to First Read

Figu re 11. Empty Flag from Last Read to First Write

M672061H

4144I–AERO–05/04

Figu re 12. Retransmit

Note: 1. EF, FF and PHF ma y change status during Ret ransmit, but fl ags will be valid at t RTC

Figu re 13. Empty Flag Timi ng

Figu re 14. Full Flag Timing

tWEF

tRPE

M672061H

4144I–AERO–05/04

Figu re 15. Programmable Half-Full Flag Timing

Figu re 16. Expa nsion Out

Figu re 17. Expa nsion In

M672061H

4144I–AERO–05/04

Figu re 18. Read Data Flow - Through M ode

Figu re 19. Write Data Flow - Through Mode

M672061H

4144I–AERO–05/04

Ordering Information

Note: 1. Contact Atmel for availability.

Reference Number Temper ature Range S peed Package Qualit y Flow

MMCP-672061HV-15-E(1) 25°C 15 ns SB28.3 Engineering Samples

MMCP-672061HV- 15 -55 to +125°C 15 ns SB28.3 Standard Mil.

MMCP-672061HV- 30 -55 to +125°C 30 ns SB28.3 Standard Mil.

SMCP-672061HV-15SB -55 to +125°C 1 5 n s S B2 8. 3 SC C B

SMCP-672061HV-30SB -55 to +125°C 3 0 n s S B2 8. 3 SC C B

5962-9317710QTC -55 to +125°C 15 n s S B2 8. 3 QM L Q

5962-9317709QTC -55 to +125°C 30 n s S B2 8. 3 QM L Q

5962-9317710VTC -55 to +125°C 15 n s S B2 8. 3 QML V

5962-9317709VTC -55 to +125°C 30 n s S B2 8. 3 QML V

5962D9317710VTC -55 to +125°C 15 ns SB28.3 QML V RHA

5962D9317709VTC -55 to +125°C 30 ns SB28.3 QML V RHA

MMDP-672061HV-15-E 25°C 15 ns FP28.4 Engineering Samples

MMDP-672061HV- 15 -55 to +125°C 15 ns FP28. 4 Mil.

MMDP-672061HV- 30 -55 to +125°C 30 ns FP28.4 Mil.

SMDP-672061HV-15SB -55 to +125°C 15 ns FP28. 4 SCC B

SMDP-672061HV-30SB -55 to +125°C 30 ns FP28. 4 SCC B

5962-9317710QNC -55 to +125°C 15 ns FP28.4 QML Q

5962-9317709QNC -55 to +125°C 30 ns FP28.4 QML Q

5962-9317710VNC -55 to +125°C 15 ns FP28. 4 QML V

5962-9317709VNC -55 to +125°C 30 ns FP28. 4 QML V

5962D9317710VN C -55 to +125°C 15 ns FP28.4 QML V RHA

5962D9317709VN C -55 to +125°C 30 ns FP28.4 QML V RHA

MM0 -672061 HV-15-E(1) 25°C 15 ns Die Engineering Samples

5962-9317710Q9A(1) -55 to +125°C15 ns Die QML Q

5962-9317710V9A(1) -55 to +125°C15 ns Die QML V

M672061H

4144I–AERO–05/04

Pac kag e Dra win g s

28-lead Side Braze (300 mils)

M672061H

4144I–AERO–05/04

28-lead Flat Pack (400 mils)

Pr inted o n rec ycled paper.

Disclaimer: Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company’s standard

warranty which is detailed in A tmel’s Terms and Conditions located on the Company’s web site. The Company assumes no responsibil it y for any

erro r s whic h m a y ap pear in this do c um en t, res e r ve s th e r i gh t t o c h an ge de v ic es o r s pe ci fic a t io ns d etaile d he re i n at any tim e w it hout notic e, and

does not make any commitment to update the information contained herein. No licenses to patents or other intellectual property of Atmel are

gra nted by th e Co mpany in c on nect ion w ith th e sa le of Atme l p roduc ts, ex pre ssl y or by imp lica tio n. A tmel ’s p rod ucts a re n ot au thorized for use

as c rit ic al c om po ne nts i n l ife s up po rt de vi ce s or sys tem s .

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Fax : (8 1) 3-3 523-758 1

Memory

2325 O rch ard Parkw ay

San Jo se, C A 95131

Tel : 1(408 ) 441-031 1

Fax: 1(408) 43 6-43 14

Microcontrollers

2325 O rch ard Parkw ay

San Jo se, C A 95131

Tel : 1(408 ) 441-031 1

Fax: 1(408) 43 6-43 14

La Ch antrer ie

BP 70 602

44306 Na ntes Cede x 3, Fra nce

Tel : (33) 2-4 0-18 -18-18

Fax: (33) 2-40-18-19-60

ASIC/ASSP/Smart Cards

Zone In dustrielle

13106 Rousse t Ced ex, France

Tel : (33) 4-4 2-53 -60-00

Fax: (33) 4-42-53-60-01

1150 E ast C heyenn e Mtn. Blvd.

Col orado Sp rings, CO 8 0906

Tel : 1(719 ) 576-330 0

Fax: 1(719) 54 0-17 59

Scottish Enterprise Technology Park

Maxwell Building

East Kilbrid e G7 5 0QR, S cotlan d

Tel : (44) 13 55-803- 000

Fax: (44) 1355 -242 -743

RF/Automotive

Theresienstrasse 2

Postfach 3535

74025 H eilbr onn, Ge rmany

Tel: (49) 71-31-67-0

Fax : (4 9) 71- 31-67-234 0

1150 Ea st Ch eyenne M tn. B lvd.

Colo rado Spr ings, CO 80 906

Tel: 1(7 19) 57 6-3300

Fax : 1 (719) 540 -1759

Biometrics/Imaging/Hi-Rel MPU/

High Speed Converters/RF Datacom

Avenue de R ocheplei ne

BP 123

38521 S aint- Egreve Cedex, France

Tel: (33) 4-76-58-30-00

Fax : (3 3) 4-7 6-58-34- 80

e-mail

literature@atmel.com

Web Site

http://www.atmel.com

4144I–AERO–05/04 /xM

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