MCP3201T-I/ST - Microchip Technology, Inc.

MCP3201

Features

• 12-bit resolution

• ±1 LSB max DNL

• ±1 LSB max INL (MCP3201-B)

• ±2 LSB max INL (MCP3201-C)

• On-chip sample and hold

• SPI™ serial interface (modes 0,0 and 1,1)

• Single supply operation: 2.7V - 5.5V

• 100ksps max. sampling rate at VDD = 5V

• 50ksps max. sampling rate at VDD = 2.7V

• Low power CMOS technology

• 500 nA typical standby current, 2 µA max.

• 400 µA max. active current at 5V

• Industrial temp range: -40°C to +85°C

• 8-pin MSOP, PDIP, SOIC and TSSOP packag es

Applications

• Sensor Interface

• Process Control

• Data Acquisition

• Bat ter y Operated Systems

Description

The Microchip Technology Inc. MCP3201 is a succes-

sive approximation 12-bit Analog-to-Digital (A/D) Con-

verter with on-board sample and hold circuitry. The

dev ice prov ides a si ngle pseu do-differ entia l input. D if-

ferential N o nli ne arity (DN L) is s pecified a t ±1 LSB, and

Integral Nonlinearity (INL) is offered in ±1 LSB

(MCP3201-B) and ±2 LSB (MCP3201-C) versions.

Communication with the device is done using a simple

serial interface compatible with the SPI protocol. The

device is capable of sample rates of up to 100 ksps at

a clock rate of 1.6 MHz. The MCP3201 operates over

a broad voltage range (2.7V - 5.5V). Low current

design permits operation with typical standby and

active currents of only 500 nA and 300 µA, respec-

tively. The device is offered in 8-pin MSOP, PDIP,

TSSOP and 150 mil SOIC packages.

Package Types

Functional Block Diagram

VREF

IN+

IN–

VSS

VDD

CLK

DOUT

CS/SHDN

MSOP, PDIP, SOIC, TSSOP

MCP3201

Comparator

Sample

and

Hold

12-Bit SAR

DAC

Control Logic

CS/SHDN

VREF

IN+

IN-

VSS

VDD

CLK DOUT

Shift

2.7V 12-Bit A/D Converter with SPI™ Serial Interface

MCP3201

1.0 ELECTRICAL

CHARACTERISTICS

1.1 Maximum Ratings*

VDD.........................................................................7.0V

All inputs and outputs w.r.t. VSS ...... -0.6V to VDD +0.6V

Storage temperature ..........................-65°C to +150°C

Ambient temp. with power applied .....-65°C to +125°C

ESD protection on all pins (HBM).......................> 4 kV

*Notice: Stresses above those listed under “Maximum ratings” may

cause permanent damage to the device. This is a stress rating only and

functional operation of the device at those or any other conditions

above tho s e in dicated in the oper atio nal li st ings of this sp ecific a tion i s

not implied. Exposure to maximum rating conditions for extended peri-

ods may affect device reliability.

PIN FUNCTION TABLE

Name Function

VDD +2.7V to 5.5V Power Supply

VSS Ground

IN+ Positive Analog Input

IN- Negative Analog Input

CLK Serial Clock

DOUT Serial Data Out

CS/SHDN Chip Select/Shutdown Input

VREF Refe renc e Voltage Input

ELECTRICAL CHARACTERISTICS

All parameters apply at VDD = 5V, VSS = 0V, VREF = 5V, TAMB = -40°C to +85°C, fSAMPLE = 100 ksps, and fCLK = 16*fSAMPLE

unless otherwise noted.

Parameter Sym Min Typ Max Units Conditions

Conversion Rate:

Conversion Time tCONV — — 12 clock

cycles

Analog Input Sample Time tSAMPLE 1.5 clock

cycles

Throughput Rate fSAMPLE — — 100

50 ksps

ksps VDD = V REF = 5V

VDD = VREF = 2.7V

DC Accuracy:

Resolution 12 bits

Integral Nonlinearity INL —

—±0.75

±1 ±1

±2 LSB

LSB MCP3201-B

MCP3201-C

Differential Nonlinear ity DNL — ±0.5 ±1 LSB No missing codes over

temperature

Offset Error — ±1.25 ±3 LSB

Gain Erro r — ±1.25 ± 5 LSB

Dynamic Performance:

Total Harmonic Distortion THD — -82 — dB VIN = 0.1V to 4.9V@1 kHz

Signal to Noise and Distortion

(SINAD) SINAD — 72 — dB VIN = 0.1V to 4.9V@1 k Hz

Spurious Free Dynamic Range SFDR — 86 — dB VIN = 0.1V to 4.9V@1 k Hz

Reference Input:

Voltage Range 0.25 — VDD VNote 2

Current Drain —

—100

.001 150

3µA

µA CS = VDD = 5V

Analog In puts:

Input Voltage Range (IN+) IN+ IN- — VREF+IN- V

Input Voltage Range (IN-) IN- VSS-100 VSS+100 mV

Leakage Current — 0.001 ±1 µA

Switch Resistance RSS — 1K — W See Figure 4-1

Note 1: This parameter is established by characterization and not 100% tested.

2: See graph that relates linearity performance to VREF level.

3: Because the sample cap will eventually lose charge, effective clock rates below 10 kHz can affect linearity performance,

especially at elevated temperatures. See Section 6.2 for more information.

© 2007 Microchip Technology Inc. DS21290D-page 3
MCP3201
Sample Capacitor CSAMPLE — 20 — pF See F igure 4-1
Digital Input/Out put:
Data Coding Format Straight Binary
High Level Input Voltage VIH 0.7 VDD ——V
Low Level Input Voltage VIL — — 0.3 VDD V
High Level Output Voltage V OH 4.1 — — V IOH = -1 mA, VDD = 4.5V
Low Level Output Voltage VOL ——0.4VI
OL = 1 mA, VDD = 4.5V
Input Leakage Current ILI -10 — 10 µA VIN = VSS or VDD
Output Leakage Current ILO -10 — 10 µA VOUT = VSS or VDD
Pin Capacitance
(all inputs/outputs) CIN, COUT — — 10 pF VDD = 5.0V (Note 1)
TAMB = 25°C, f = 1 MHz
Timing Parameters:
Clock Frequency fCLK —
——
—1.6
0.8 MHz
MHz VDD = 5V (Note 3)
VDD = 2.7V (Note 3)
Clock High Time tHI 312 — — ns
Clock Low Time tLO 312 — — ns
CS Fall To First Rising CLK Edge tSUCS 100 — — ns
CLK Fall To Output Data Valid tDO — — 200 ns See Test Circuits, Figure 1- 2
CLK Fall To Output Enable tEN — — 200 ns See Test Circuits, Figure 1- 2
CS Rise To Output Disable tDIS — — 100 ns See Test Circuits, Figure 1-2 
(Note 1)
CS Disable Time tCSH 625 — — ns
DOUT Rise Time tR— — 100 ns See Test Circuits, Figure 1- 2 
(Note 1)
DOUT Fall Ti me tF— — 100 ns See Test Circuits, Figure 1- 2 
(Note 1)
Power Requirements:
Operating Voltage VDD 2.7 — 5.5 V
Operating Current IDD —
—300
210 400
—µA
µA VDD = 5.0V, DOUT unloaded
VDD = 2.7V, DOUT unloaded
Standby Current IDDS —0.5 2 µACS = VDD = 5.0V 
Temperature Ranges:
Specified Temperature Range TA-40 — +85 °C
Operating Temperature Range TA-40 — +85 °C
Storage Temperature Range TA-65 — +150 °C
Thermal Package Resistance:
Thermal Resistance, 8L-PDIP qJA —85—°C/W
Thermal Resistance, 8L-SOIC qJA — 163 — °C/W
Thermal Resistance, 8L-MSOP qJA — 206 — °C/W
Thermal Resistance, 8L-TSSOP qJA — 124 — °C/W
ELECTRIC AL CHARACTERISTICS (CONTINUED)
All parameters apply at VDD = 5V, VSS = 0V, VREF = 5V, TAMB = -40°C to +85°C, fSAMPLE = 100 ksps, and fCLK = 16*fSAMPLE 
unless otherwise noted.
Parameter Sym Min Typ Max Units Conditions
Note 1: This parameter is established by characterization and not 100% tested.
2: See graph that relates linearity performance to VREF level.
3: Because the sample cap will eventually lose charge, effective clock rates below 10 kHz can affect linearity performance, 
especially at elevated temperatures. See Section 6.2 for more information.

MCP3201

FIGURE 1-1: Serial Timing.

FIGURE 1-2: Test Circuits.

CLK

tSUCS

tCSH

tHI tLO

DOUT

tEN tDO tRtF

LSB

MSB OUT

tDIS

NULL BIT

HI-Z HI-Z

VIH

tDIS

DOUT

Waveform 1*

DOUT

Waveform 2†

90%

10%

* Waveform 1 is for an output with internal condi-

tions such that the output is high, unless disabled

by the output control.

† Waveform 2 is for an output with internal condi-

tions such that the output is low, unless disabled

by the output control.

Voltage Waveforms for tDIS

Test Point

1.4V

DOUT

Load circuit for tR, tF, tDO

3kΩ

CL = 30 pF

Test Point

DOUT

Load circuit for tDIS and tEN

3kΩ

30 pF

tDIS Waveform 2

tDIS Waveform 1

CLK

DOUT

tEN

Voltage Waveforms for tEN

tEN Waveform

VDD

VDD/2

VSS

DOUT

Voltage Waveforms for tR, tF

CLK

DOUT

tDO

Voltage Waveforms for tDO

VOH

VOL

MCP3201

2.0 TYPICAL PERFORMANCE CHARACTERISTICS

Note: Unless otherwise indicated, VDD = VREF = 5V, VSS = 0V, fSAMPLE = 100 ksps, fCLK = 16*fSAMPLE,TA = 25°C

FIGURE 2-1: Integral Nonlinearity (INL) vs. Sample

Rate.

FIGURE 2-2: Integral Nonlinearity (INL) vs. VREF.

FIGURE 2-3: Integral Nonlinearity (INL) vs. Code

(Representative Part).

FIGURE 2-4: Integral Nonlinearity (INL) vs. Sample

Rate (VDD = 2.7V).

FIGURE 2-5: Integral Nonlinearity (INL) vs. VREF

(VDD = 2.7V).

FIGURE 2-6: Integral Nonlinearity (INL) vs. Code

(Representative Part, VDD = 2.7V).

Note: The graphs provided following this note are a statistical summary based on a limited number of samples

and are provided for informational purposes only. The performance characteristics listed herein are not

tested or guaranteed. In some graphs, the data presented may be outside the specified operating range

(e.g., outside specified power supply range) and therefore outside the warranted range.

-1.0

-0.8

-0.6

-0.4

-0.2

0.0

0.2

0.4

0.6

0.8

1.0

0 25 50 75 100 125 150

Sample Rate (ksps)

INL (LSB)

Positive INL

Negative INL

-2.0

-1.5

-1.0

-0.5

0.0

0.5

1.0

1.5

2.0

012345

VREF (V)

INL (LSB)

Positive INL

Negat ive INL

-1.0

-0.8

-0.6

-0.4

-0.2

0.0

0.2

0.4

0.6

0.8

1.0

0 512 1024 1536 2048 2560 3072 3584 4096

Digi t al Code

INL (LSB)

-2.0

-1.5

-1.0

-0.5

0.0

0.5

1.0

1.5

2.0

0 20406080100

Sample Rate (ksps)

INL (LSB)

VDD = VREF = 2.7V

Positive INL

Negative INL

-2.0

-1.5

-1.0

-0.5

0.0

0.5

1.0

1.5

2.0

0.0 0.5 1.0 1.5 2.0 2.5 3.0

VREF (V)

INL (LSB)

Positive INL

Negative INL

VDD = 2.7V

FSAMPLE = 50 ksps

-1.0

-0.8

-0.6

-0.4

-0.2

0.0

0.2

0.4

0.6

0.8

1.0

0 512 1024 1536 2048 2560 3072 3584 4096

Di git al Code

INL (LSB)

VDD = VREF = 2.7V

FSAMPLE = 50 ksps

MCP3201

Note: Unless otherwise indicated, VDD = VREF = 5V, VSS = 0V, fSAMPLE = 100 ksps, fCLK = 16*fSAMPLE,TA = 25°C

FIGURE 2-7: Integral Nonlinearity (INL) vs.

Temperature.

FIGURE 2-8: Differential Nonlinearity (DNL) vs.

Sample Rate.

FIGURE 2-9: Differential Nonlinearity (DNL) vs.

VREF.

FIGURE 2-10: Integral Nonlinearity (INL) vs.

Temperature (VDD = 2.7V).

FIGURE 2-11: Differential Nonlinearity (DNL) vs.

Sample Rate (VDD = 2.7V).

FIGURE 2-12: Differe ntia l Nonl inearity (DNL) vs. V REF

(VDD = 2.7V).

-1.0

-0.8

-0.6

-0.4

-0.2

0.0

0.2

0.4

0.6

0.8

1.0

-50-250 255075100

Temperature (° C)

INL (LSB)

Positive INL

Nega t i ve INL

-1.0

-0.8

-0.6

-0.4

-0.2

0.0

0.2

0.4

0.6

0.8

1.0

0 255075100125150

Sample Rate (ksps)

DNL (LSB)

Positive DNL

Negati ve DNL

-2.0

-1.0

0.0

1.0

2.0

3.0

012345

VREF (V)

DNL (LSB)

Negat i ve DNL

P ositive DNL

-1.0

-0.8

-0.6

-0.4

-0.2

0.0

0.2

0.4

0.6

0.8

1.0

-50 -25 0 25 50 75 100

Temperature (°C)

INL (LSB)

Positive INL

VDD = VREF = 2. 7V

FSAMPLE = 50 k s ps

Negative INL

-2.0

-1.5

-1.0

-0.5

0.0

0.5

1.0

1.5

2.0

020406080100

Sample Rate ( ksps)

DNL (LSB)

VDD = VREF = 2.7V

Positive DNL

Neg ative DNL

-3.0

-2.0

-1.0

0.0

1.0

2.0

3.0

0.0 0.5 1.0 1.5 2.0 2.5 3.0

VREF(V)

DNL (LSB)

P o si ti ve DNL

Negative DN L

VDD = 2.7V

FSAMPLE = 50 k sps

MCP3201

Note: Unless otherwise indicated, VDD = VREF = 5V, VSS = 0V, fSAMPLE = 100 ksps, fCLK = 16*fSAMPLE,TA = 25°C

FIGURE 2-13: Differential Nonlinearity (DNL) vs.

Code (Representative Part).

FIGURE 2-14: Differential Nonlinearity (DNL) vs.

Temperature.

FIGURE 2-15: Gain Error vs. VREF.

FIGURE 2-16: Differential Nonlinearity (DNL) vs.

Code (Representat ive Part, VDD = 2.7V).

FIGURE 2-17: Differential Nonlinearity (DNL) vs.

Temperature (VDD = 2.7V).

FIGURE 2-18: Offset Error vs. VREF.

-1.0

-0.8

-0.6

-0.4

-0.2

0.0

0.2

0.4

0.6

0.8

1.0

0 512 1024 1536 2048 2560 3072 3584 4096

Digit al Code

DNL (LSB)

-1.0

-0.8

-0.6

-0.4

-0.2

0.0

0.2

0.4

0.6

0.8

1.0

-50 -25 0 25 50 75 100

Tempe rature (°C)

DNL (LSB)

Positive DNL

Negative DNL

-2

-1

012345

VREF(V)

Gain Error (LSB)

VDD = 2.7V

FSAMPLE = 50 ksps

VDD = 5V

FSAMPLE = 100 k sps

-1.0

-0.8

-0.6

-0.4

-0.2

0.0

0.2

0.4

0.6

0.8

1.0

0 512 1024 1536 2048 2560 3072 3584 4096

Digital Code

DNL (LSB)

VDD = VREF = 2. 7V

FSAMPLE = 50 k sps

-1.0

-0.8

-0.6

-0.4

-0.2

0.0

0.2

0.4

0.6

0.8

1.0

-50 -25 0 25 50 75 100

Temper at ure ( ° C)

DNL (LSB)

Positive DNL

VDD = VREF = 2.7V

FSAMPLE = 50 ksps

Negati ve DNL

012345

VREF (V)

Offset Error (LSB)

VDD = 5V

FSAMPLE = 100 k s ps

VDD = 2. 7V

FSAMPLE = 50ksps

MCP3201

Note: Unless otherwise indicated, VDD = VREF = 5V, VSS = 0V, fSAMPLE = 100 ksps, fCLK = 16*fSAMPLE,TA = 25°C

FIGURE 2-19: Gain Error vs. Temperature.

FIGURE 2-20: Signal to Noise Ratio (SNR) vs. Input

Frequency.

FIGURE 2-21: Total Harmonic Distortion (THD) vs.

Input Frequency.

FIGURE 2-22: Offset Error vs. Temperature.

FIGURE 2-23: Signal to Noise and Distortion

(SINAD) vs. Input Freq uen cy.

FIGURE 2-24: Signal to Noise and Distortion

(SINAD) vs. Input Sign al Level .

-1.0

-0.8

-0.6

-0.4

-0.2

0.0

0.2

0.4

0.6

0.8

1.0

-50 -25 0 25 50 75 100

Temperature (°C)

Gain Error (LSB)

VDD = VREF = 5V

FSAMPLE = 100 ksps

VDD = VREF = 2.7V

FSAMPLE = 50 ksps

100

1 10 100

I nput Freque ncy ( k Hz)

SNR (dB)

VDD = VREF = 2.7V

FSAMPLE = 50 ksps

VDD = VREF = 5V

FSAMPLE = 100 k sps

-100

-90

-80

-70

-60

-50

-40

-30

-20

-10

110100

Input Frequency (k Hz)

THD (dB)

VDD = VREF = 2.7V

FSAMPLE = 50 ksps

VDD = VREF = 5V, FSAMPLE = 100 ks ps

0.0

0.2

0.4

0.6

0.8

1.0

1.2

1.4

1.6

1.8

2.0

-50 -25 0 25 50 75 100

Tem p er a ture ( °C)

Offset Error (LSB)

VDD = VREF = 5V

FSAMPLE = 100 k s ps

VDD = VREF = 2.7V

FSAMPLE = 50 k s ps

100

110100

I nput Fr eque ncy (kHz)

SINAD (dB)

VDD = VREF = 2.7V

FSAMPLE = 50 ks p s

VDD = VREF = 5V

FSAMPLE = 100 ks ps

-40-35-30-25-20-15-10 -5 0

Input Signal Level ( dB)

SINAD (dB)

VDD = VREF = 2.7V

FSAMPLE = 50 ksps

VDD = VREF = 5V

FSAMPLE = 100 ksps

MCP3201

Note: Unless otherwise indicated, VDD = VREF = 5V, VSS = 0V, fSAMPLE = 100 ksps, fCLK = 16*fSAMPLE,TA = 25°C

FIGURE 2-25: Effective Number of Bits (ENOB) vs.

VREF.

FIGURE 2-26: Spurious Free Dynamic Range

(SFDR) vs. Input Frequency.

FIGURE 2-27: Frequency Spectrum of 10 kHz input

(Representative Part).

FIGURE 2-28: Effective Number of Bits (ENOB) vs.

Input Frequency.

FIGURE 2-29: Power Supply Rejection (PSR) vs.

Ripple Frequency.

FIGURE 2-30: Frequency Spectrum of 1 kHz input

(Representative Part, VDD = 2.7V).

9.00

9.25

9.50

9.75

10.00

10.25

10.50

10.75

11.00

11.25

11.50

11.75

12.00

0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0

VREF (V)

ENOB (rms)

VDD = VREF = 2.7V

FSAMPLE = 50 ksps

VDD = VREF = 5V

FSAMPLE =100 ks ps

100

110100

Input Fre quency (kHz)

SFDR (dB)

VDD = VREF = 2.7V

FSAMPLE = 50 ksps

VDD = VREF = 5V, FSAMPLE = 100 k s ps

-130

-120

-110

-100

-90

-80

-70

-60

-50

-40

-30

-20

-10

0 10000 20000 30000 40000 50000

Frequency ( Hz)

Amplitude (dB)

VDD = VREF = 5V

FSAMPLE = 10 0 ks p s

FINPUT = 9. 985k Hz

4096 points

8.0

8.5

9.0

9.5

10.0

10.5

11.0

11.5

12.0

1 10 100

I nput Fr equency (k Hz)

ENOB (rms)

VDD = 2.7V

FSAMPLE = 50 ksps

VDD = 5V

FSAMPLE = 100 k sps

-80

-70

-60

-50

-40

-30

-20

-10

1 10 100 1000 10000

Ripple Fre quency (kHz)

Power Supply Reje ction (dB)

-130

-120

-110

-100

-90

-80

-70

-60

-50

-40

-30

-20

-10

0 5000 10000 15000 20000 25000

Frequency (Hz)

Amplitude (dB)

VDD = VREF = 2.7V

FSAMPLE = 50 ksps

FINPUT = 998.76 Hz

4096 poi nts

MCP3201

Note: Unless otherwise indicated, VDD = VREF = 5V, VSS = 0V, fSAMPLE = 100 ksps, fCLK = 16*fSAMPLE,TA = 25°C

FIGURE 2-31: IDD vs . VDD.

FIGURE 2-32: IDD vs. Clock Frequency.

FIGURE 2-33: IDD vs . Temperature.

FIGURE 2-34: IREF vs. VDD.

FIGURE 2-35: IREF vs. Clock Frequency.

FIGURE 2-36: IREF vs. Temperature.

100

150

200

250

300

350

400

450

500

2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0

VDD (V)

IDD (µA)

VREF = VDD

A ll points at FCLK = 1.6 M Hz, ex c ept

at V REF = VDD = 2.5V , FCLK

= 800 kHz

100

150

200

250

300

350

400

10 100 1000 10000

Clock Frequency ( kHz)

IDD (µA)

VDD = VREF = 5V

VDD = VREF = 2. 7V

100

150

200

250

300

350

400

-50 -25 0 25 50 75 100

Temper atur e (°C)

IDD (µA)

VDD = VREF = 5V

FCLK = 1.6 MHz

VDD = VREF = 2.7V

FCLK = 80 0 kHz

100

2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0

VDD (V)

IREF (µA)

VRE F = VDD

All points at FCLK = 1.6 MHz, except

at VREF = VDD = 2.5V, FCLK

= 800 k Hz

100

10 100 1000 10000

Clock Frequency ( kHz)

IREF (µA)

VDD = VREF = 5V

VDD = VREF = 2.7V

100

-50-250 255075100

Tem pe r ature ( ° C)

IREF (µA)

VDD = VREF = 5V

FCLK = 1.6 MHz

VDD = VREF = 2.7V

FCLK = 800 kHz

MCP3201

Note: Unless otherwise indicated, VDD = VREF = 5V, VSS = 0V, fSAMPLE = 100 ksps, fCLK = 16*fSAMPLE,TA = 25°C

FIGURE 2-37: IDDS vs. VDD.

FIGURE 2-38: IDDS vs. Temperature.

FIGURE 2-39: Analog Input Leakage Current vs.

Temperature.

2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0

VDD (V)

IDDS (pA)

VREF = CS = VDD

0.01

0.10

1.00

10.00

100.00

-50 -25 0 25 50 75 100

Temperature (°C)

IDDS (nA)

VDD = VREF = CS = 5V

0.0

0.2

0.4

0.6

0.8

1.0

1.2

1.4

1.6

1.8

2.0

-50 -25 0 25 50 75 100

Temperature (°C)

Analog Input Leakage (nA)

VDD = VREF = 5V

FCLK = 1.6 M Hz

MCP3201

3.0 PIN DESCRIPTIONS

3.1 IN+

Positive analog input. This input can vary from IN- to

VREF + IN-.

3.2 IN-

Negative analog input. This input can vary ±100 mV

from VSS.

3.3 Chip Select/Shutdown (CS/SHDN)

The CS/SHDN pin is used to initiate communication

with the device when pulled low and will end a conver-

sion and put the device in low power standby when

pulled high. The CS/SHDN pin must be pulled high

between conversions.

3.4 Serial Clock (CLK)

The SPI c lock pi n is used to initi ate a co nversion and to

clock out each bit of the conversion as it takes place.

See S ection 6.2 for const raints on cl ock speed.

3.5 Serial Data Output (DOUT)

The SPI serial data output pin is used to shift out the

results of the A/D conversion. Data will always change

on the falling edge of each clock as the conversion

takes place.

4.0 DEVICE OPERATION

The MCP3201 A/D Converter employs a conventional

SAR architecture. With this architecture, a sample is

acquired on an internal sample/hold capacitor for

1.5 clock cycles starting on the first rising edge of the

serial clock after CS has been pulled low . Following this

sample time, the input switch of the converter opens

and the device uses the collected charge on the inter-

nal sample and hold capacitor to produce a serial 12-bit

digital output code. Conversion rates of 100 ksps are

possible on the MCP3201. See Section 6.2 for informa-

tion on minimum clock rates. Communication with the

device is done using a 3-wire SPI-compatible interface.

4.1 Analog Inputs

The MCP3201 provides a single pseudo-differential

input. The IN+ input can range from IN- to VREF

(VREF +IN-). The IN- input is limited to ± 100 mV from the

VSS rail. The IN- input can be used to cancel small sig-

nal common-mode noise which is present on both the

IN+ and IN- inputs.

For the A/D Converter to m eet specifi cation, the charg e

holding capacitor (CSAMPLE) must be gi ve n enough time

to acquire a 12-bit accurate voltage level during the

1.5 clock cycle sampling period. The analog input

model is shown in Figure 4-1.

In this diagram, it is shown that the source impedance

(RS) adds to the internal sampling switch (RSS) imped-

ance, directly affecting the time that is required to

charge the capacitor (CSAMPLE). Consequently, a larger

source impedance increases the offset, gain, and inte-

gral linearity errors of the conversion.

Ideally, the impedance of the signal source should be

near zero. Th is is achievab le with an operat ional ampli-

fier such as the M C P601 , whic h h as a clo se d lo op ou t-

put imped anc e of tens of ohm s. The ad verse affect s of

higher source impedances are shown in Figure 4-2.

If the voltage level of IN+ is equa l to or less than IN-, th e

result ant code will be 000h. If the voltage at IN+ is equal

to or greater than {[VREF + (IN-)] - 1 LSB}, then the out-

put code w ill be FFFh. If the volta ge level at IN - is more

than 1 LSB below VSS, then the vo lta ge lev el at the IN+

input will have to go below VSS to see the 000h output

code. Conversely, if IN- is more than 1 LSB above

Vss, then the FFFh code will not be seen unless the

IN+ input level go es above VREF level.

4.2 Reference Input

The refer ence input (VREF) determ ines the an alog inp ut

voltage range and the LSB size, as shown below.

As the reference input is reduced, the LSB size is

reduced accordingly . The theoretical digital output c ode

produ ced by the A/D Converter is a functi on of the ana-

log input signal and the reference input as shown

below.

where:

VIN = analog input voltage = V(IN+) - V(IN-)

VREF = reference voltage

When using an external voltage reference device, the

system designer should always refer to the manufac-

turer’s recom mendations for circ uit layo ut. Any in stabi l-

ity in the operation of the reference device will have a

direct effect on the operation of the A/D Converter.

LSB Size VREF

4096

-------------=

Digital Output Code 4096*VIN

VREF

------------------------=

MCP3201

FIGURE 4-1: Analog Input Model.

FIGURE 4-2: Maximum Clock Frequency vs. Input

Resistance (RS) to maintain less than a 0.1 LSB

deviati on in IN L from nom in al con di tion s.

CPIN

RSS CHx

7pF

VT = 0.6V

VT = 0.6V ILEAKAGE

Sampling

Switch

SS RS = 1 kΩ

CSAMPLE

= DAC capacitance

VSS

VDD

= 20 pF

±1 nA

LEGEND

VA = Signal Source

Rss = Source Impedance

CHX= I nput Channel Pad

CPIN = Input Pin Capacit ance

VT= Threshold Voltage

ILEAKAGE = Leakage Current At The Pin

Due To Various Junc tions

SS = Sampling Switch

Rs= Sampling Switch Resistor

CSAMPLE = Sam ple/hold Capacitance

0.0

0.2

0.4

0.6

0.8

1.0

1.2

1.4

1.6

1.8

100 1000 10000

I nput Resi st ance ( Ohms)

Clock Frequency (MHz)

VDD = VREF = 5V

VDD = VREF = 2.7V

MCP3201

5.0 SERIAL COMMUNICATIONS

Communication with the device is done using a stan-

dard SPI-compatible serial interface. Initiating commu-

nication with the MCP3201 begins with the CS going

low. If the device was powered up with the CS pin lo w,

it mus t be b rought hig h and bac k low to initia te comm u-

nication. The device will begin to sample the analog

input on the first rising edge after CS goes low. The

sample period wil l end i n the fa lling e dge of the se cond

clock , at which time th e devic e will o utput a low nul l bit.

The next 12 clocks will output the result of the conver-

sion with MSB first, as shown in Figure 5-1. Data is

alway s output from the device on the fal ling edge of the

clock. If all 12 data bits have been transmitted and the

device contin ues to rec eive cl ocks whi le the CS is held

low, the device will output the conversion result LSB

first, as shown in Figure 5-2. If more clocks are pro-

vided to th e devi ce whi le C S is still low (after the LSB

first data has been transmitted), the device will clock

out zeros indefinitely.

FIGURE 5-1: Communication with MCP3201 using MSB first Format.

FIGURE 5-2: Communication with MCP3201 using LSB first Format.

CLK

DOUT

tCYC

POWER

DOWN

TSUCS

TSAMPLE tCONV tDATA**

* After completing the data transfer , if further clocks are applied with CS low , the A/D Converter will output LSB first data, followed

by zeros indefinitely. See Figure below.

** tDATA: during thi s time , the bi as cur re nt an d the com parato r po wer down a nd th e reference inpu t becomes a high impeda nce

node, leaving the CLK running to clock out the LSB-first data or zeros.

TCSH

NULL

BIT B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0*

HI-Z HI-Z B11 B10 B9 B8

NULL

BIT

CLK

DOUT

tCYC

POWER DOWN

tSUCS

tSAMPLE tCONV tDATA**

* After completing the data transfer, if further clocks are applied with CS low, the A/D Converter will output zeros indefinitely.

** tDATA: during th is ti me , the b ias cur ren t an d the compar ato r po w er do wn an d th e ref ere nce in put beco me s a high im pe dan ce

node, leaving the CLK running to clock out the LSB-first data or zeros.

tCSH

NULL

BIT B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0

HI-Z B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11* HI-Z

MCP3201

6.0 APPLICATIONS INFORMATION

6.1 Using the MCP3201 with

Microcontroller SPI Ports

With most microcontroller SPI ports, it is required to

clock out e ight b its at a time. If this i s the case , it will be

necessary to provide more clocks than are required for

the MCP3201. As an example, Figure 6-1 and

Figure 6-2 show how the MCP3201 can be interfaced

to a mi cro con trol le r w ith a st a nda rd SPI port. Since the

MCP32 01 alway s cl ocks dat a out o n t he fall ing ed ge of

clock, the MCU SPI port must be configured to match

this operation. SPI Mode 0,0 (clock idles low) and SPI

Mode 1,1 (clock idles high) are both compatible with

the MCP3201. Figure 6-1 depict s the operation shown

in SPI Mode 0,0, which requires that the CLK from the

microcontroller idles in the ‘low’ state. As shown in the

diagram, the MSB is clocked out of the A/D Conv erter

on the fa lling edge o f the third cl ock pulse. After the first

eight clocks have been sent to the device, the micro-

controll er’s receive buf fer will con tain tw o unknown bit s

(the output is at high impedance for the first two

clock s), the null bit and the hi ghest or der five bits of the

conversion. After the second eight clocks have been

sent to th e device, the MCU receive register will contain

the lowest order seven bits and the B1 bit repeated as

the A/D Conv erte r has beg un to shift ou t LSB firs t data

with the extra clock. Typical procedure would then call

for the lo wer order byte of data t o be shifted righ t by one

bit to remove the extra B1 bit. The B7 bit is then trans-

ferred from the high order byte to the lower order byte,

and then the higher order byte is shifted one bit to the

right as well. Eas ier manipul ation of the conv erted dat a

can be obtained by using this method.

Figure 6-2 shows the same thing in SPI Mode 1,1

which requires that the clock idles in the high state. As

with mode 0,0, the A/D Converter outputs data on the

falling edge of the clock and th e MCU latches d ata from

the A/D Converter in on the rising edge of the clock.

FIGURE 6-1: SPI Communication using 8-bit segments (Mode 0,0: SCLK idles low).

FIGURE 6-2: SPI Communication using 8-bit segments (Mod e 1,1: SCLK idles high).

CLK 9 10111213141516

DOUT NULL

BIT B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0

HI-Z

B7 B6 B5 B4 B3 B2 B1 B0B11 B10 B9 B8??0

MCU latches data from A/D

Data is clocked out of A/D

Converter on falling edges

Convert er on risi ng edges of SCL K

12345678

HI-Z

LSB first data begins

to come out

Data stored into MCU receive register

after transmission of first 8 bits Data stored into MCU receive register

after transmission of second 8 bits

CLK 9 10111213141516

DOUT NULL

BIT B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0

HI-Z

B7 B6 B5 B4 B3 B2 B1 B0

B11 B10 B9 B8??0

MCU latches data from A/D

Data is clocked out of A/D

Converter on falling edges

Converter on rising edges of SCLK

1234567 8

LSB first data begins

to come out

HI-Z

Data stored into MCU receive register

after transmission of first 8 bits Data stored int o MCU re ceive regist er

after transmission of second 8 bits

MCP3201

6.2 Maintaining Minimum Clock Speed

When the MCP320 1 initiates the samp le period, charge

is stored on the sample capacitor. When the sample

period is comple te, the device co nverts one bi t for each

clock tha t is rec eived. It is import ant for th e user to note

that a slow clock rate will allow charge to bleed off the

sample cap while the conversion is taking place. At

85°C (worst case condition), the part will maintain

proper charge on the sample capacitor for at least

1.2 ms after the sam ple perio d has ende d. This mean s

that the time be tween the end of the samp le period and

the time that all 12 data bits have been clocked out

must not exceed 1.2 ms (effective clock frequency of

10 kHz). Fail ure to meet this c rite ria may in duce l inear-

ity errors into the conversion outside the rated specifi-

cations. It should be noted that during the entire

convers ion cycle, the A/D Converter doe s not require a

const ant clock speed or duty cycle, as long as all timin g

specifications are met.

6.3 Buffering/Filtering th e Analog Inputs

If the signal source for the A/D Converter is not a low

impeda nce sou rce, it w ill ha ve to b e buf fered or inaccu-

rate conve rsion res ult s ma y occur. See Figure 4-2. It is

also recommended that a filter be used to el iminate any

signals that may be aliased back into the conversion

results. This is illustrated in Figure 6-3 where an op

amp is u sed to drive the analog inpu t of th e M CP3201.

This a mp lifi er pro vid es a lo w i mpedance source fo r th e

converter input and a low pass filter, which eliminates

unwan ted hig h fr equ enc y noi se .

Low pass (anti-aliasing) filters can be designed using

Microchip’s interactive FilterLab™ software. FilterLab

will calculate capacitor and resistor values, as well as

determi ne the numbe r of po les th at are require d for th e

application. For more information on filtering signals,

see the application note AN699 “Anti-Aliasing Analog

Filters for Data Acquisition Systems.”

FIGURE 6-3: The MCP601 Operational Amplifier is

used to implement a 2nd order anti-aliasing filter for

the signal being converted by the MCP3201.

6.4 Layout Considerations

When laying out a printed circuit board for use with

analog components, care should be taken to reduce

noise wherever possible. A bypass capacitor should

alwa ys b e us ed wi th t his devi ce a nd shoul d be pl aced

as clos e as pos sible to the devic e pin. A by pass ca pac-

itor value of 1 µF is recommended.

Digit al and analog t races should be sep arated as much

as possible on the board and no traces should run

underneath the device or the bypass capacitor. Extra

precautions should be taken to keep traces with high

frequenc y s ign al s (s uch as clock lines ) as far as po ss i-

ble from analog traces.

Use of an analog ground plane is recommended in

order to keep the ground potential the same for all

devices on the board. Providing VDD connections to

devices in a “star” configuration can also reduce noise

by eliminating current return paths and associated

errors. See Figure 6-4. For more information on layout

tips when usi ng A/D C o nve rter, refer to AN688 “Layout

Tips for 12-Bit A/D Converter Applications”.

FIGURE 6-4: VDD traces arranged in a ‘Star’

configuration in order to reduce errors caused by

current return paths.

MCP3201

VDD

10 µF

IN-

IN+

VIN

VREF

4.096V

Reference

1µF

10 µF

0.1 µF

MCP601

R3R4

MCP1541 CL

VDD

Connection

Device 1

Device 2

Device 3

Device 4

MCP3201

7.0 PACKAGING INFORMATION

7.1 Package Marking Information

Legend: XX...X Customer-specific information

Y Year code (last digit of calendar year)

YY Year code (last 2 digits of calendar year)

WW Week code (week of January 1 is week ‘01’)

NNN Alphanumeric traceability code

Pb-free JEDEC designator for Matte Tin (Sn)

*This package is Pb-free. The Pb-free JEDEC designator ( )

can be found on the outer packaging for this package.

Note: In the eve nt the ful l Micro chip pa rt num ber cannot be ma rked on o ne line, it wil

be carried over to the next line, thus limiting the number of available

characters for customer-specific information.

XXXXXXXX

XXXXXNNN

YYWW

8-Lead PDIP (300 mil) Example:

8-Lead SOIC (150 mil) Example:

XXXXXXXX

XXXXYYWW

NNN

8-Lead TSSOP Example:

MCP3201

I/PNNN

0725

MCP3201

ISN 0725

NNN

8-Lead MSOP Example:

XXXX

YYWW

NNN

XXXXXX

YWWNNN

3201

0725

NNN

3201I

725NNN

MCP3201

8-Lead Plastic Dual In-Line (P) – 300 mil Body [PDIP]

otes:

. Pin 1 visual index feature may vary, but must be located with the hatched area.

. § Significant Characteristic.

. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" per side.

. Dimens ioning and tolerancing per ASME Y14.5M.

BSC: Basic Dimension. Theoretically exact value shown without tolerances.

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

Units INCHES

Dimension Limits MIN NOM MAX

Number of Pins N 8

Pitch e .100 BSC

Top to Seating Plane A – – .210

Molded Package Thickness A2 .115 .130 .195

Base to Seating Plane A1 .015 – –

Shoulder to Shoulder Width E .290 .310 .325

Molded Package Width E1 .240 .250 .280

Overall Length D .348 .365 .400

Tip to Seating Plane L .115 .130 .150

Lead Thickness c .008 . 010 .015

Upper Lead Width b1 .040 .060 .070

Lower Lead Width b .014 .018 .022

Overall Row Spacing § eB – – .430

NOTE 1

Microchip Technology Drawing C04-018

MCP3201

8-Lead Plastic Small Outline (SN) – Narrow, 3.90 mm Body [SOIC]

Notes:

1. Pin 1 visual index feature may vary, but must be located within the hatched area.

2. § Significant Characteristic.

3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.15 mm per side.

4. Dimensioning and tolerancing per ASME Y14.5M.

BSC: Basic Dimension. Theoretically exact value shown without tolerances.

REF: Reference Dimension, usually without tolerance, for information purposes only.

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

Units MILLMETERS

Dimension Limits MIN NOM MAX

Number of Pins N 8

Pitch e 1.27 BSC

Overall Height A – – 1.75

Molded Package Thickness A2 1.25 – –

Standoff

A1 0.10 – 0.25

Overall Width E 6.00 BSC

Molded Package Width E1 3.90 BSC

Overall Length D 4.90 BSC

Chamfer (optional) h 0.25 – 0.50

Foot Length L 0.40 – 1.27

Footprint L1 1.04 REF

Foot Angle φ0° – 8°

Lead Thickness c 0.17 – 0.25

Lead Width b 0.31 – 0.51

Mold Draft Angle To p α5° – 15°

Mold Draft Angle Bottom β5° – 15°

NOTE 1

12 3

Microchip Technology Drawing C04-057

MCP3201

8-Lead Plastic Micro Small Outline Package (MS) [MSOP]

otes:

. Pin 1 visual index feature may vary, but must be located within the hatched area.

. Dimens ions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.15 mm per side.

. Dimens ioning and tolerancing per ASME Y14.5M.

BSC: Basic Dimension. Theoretically exact value shown without tolerances.

REF: Reference Dimen sion, usually without tolerance, for information purposes only.

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

Units MILLIMETERS

Dimension Limits MIN NOM MAX

Number of Pins N 8

Pitch e 0.65 BSC

Overall Height A – – 1.10

Molded Package Thickness A2 0.75 0.85 0.95

Standoff A1 0.00 – 0.15

Overall Width E 4.90 BSC

Molded Package Width E1 3.00 BSC

Overall Length D 3.00 BSC

Foot Length L 0.40 0.60 0.80

Footprint L1 0.95 REF

Foot Angle φ0° – 8°

Lead Thickness c 0.08 – 0.23

Lead Width b 0.22 – 0.40

NOTE 1

L1 L

Microchip Technology Drawing C04-111

MCP3201

8-Lead Plastic Thin Shri nk Small Outline (ST) – 4.4 mm Body [TSSOP]

otes:

. Pin 1 visual index feature may vary, but must be located within the hatched area.

. Dimens ions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.15 mm per side.

. Dimens ioning and tolerancing per ASME Y14.5M.

BSC: Basic Dimension. Theoretically exact value shown without tolerances.

REF: Reference Dimen sion, usually without tolerance, for information purposes only.

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

Units MILLIMETERS

Dimension Limits MIN NOM MAX

Number of Pins N 8

Pitch e 0.65 BSC

Overall Height A – – 1.20

Molded Package Thickness A2 0.80 1.00 1.05

Standoff A1 0.05 – 0.15

Overall Width E 6.40 BSC

Molded Package Width E1 4.30 4.40 4.50

Molded Package Length D 2.90 3.00 3.10

Foot Length L 0.45 0.60 0.75

Footprint L1 1.00 REF

Foot Angle φ0° – 8°

Lead Thickness c 0.09 – 0.20

Lead Width b 0.19 – 0.30

NOTE 1

L1 L

Microchip Technology Drawing C04-086

MCP3201

NOTES:

MCP3201

APPENDIX A: REVISION HISTORY

Revision D (January 2007)

This revision includes updates to the packaging

diagrams.

MCP3201

NOTES:

MCP3201

PRODUCT IDENTIFICATION SYSTEM

To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.

PART NO. X/XX

PackageTemperature

Range

Device

Device: MCP3201: 12-Bit A/D Converter w/SPI Interface

MCP3201T: 12-Bit A/D Converter w/SPI Interface

(Tape and Reel) (SOIC and TSSOP only)

Temperatu re Range: I = -40°C to +85°C

Package: MS = Plastic Micro Small Outline (MSOP), 8-lead

P = Plastic DIP (300 mil Body), 8-lead

SN = Plastic SOIC (150 mil Body), 8-lead

ST = Plastic TSSOP (4. 4 mm), 8-lead

Examples:

a) MCP3201-I/P: Industrial Temperature,

PDIP package.

b) MCP3201-I/SN: Indus trial Temperat ure,

SOIC package.

c) MCP3201-I/ST: Industrial Temperature,

TSSOP package.

d) MCP3201-I/MS: Industrial Temperature,

MSOP package.

MCP3201

NOTES:

Information contained in this publication regarding device

applications a nd the lik e is pro vid ed only fo r yo ur c onvenien ce

and may be supers eded by updates. It is y our resp o ns i bil it y to

ensure that your application meets with your specifications.

MICROCHIP MAKES NO REPRESENTATIONS OR

WARRANTIES OF ANY KIND WHETHER EXPRESS OR

IMPLIED, WRITTEN OR ORAL, STATUTORY OR

OTHERWISE, RELATED TO THE INFORMATION,

INCLUDING BUT NOT LIMITED TO ITS CONDITION,

QUALITY, PERFORMANCE, MERCHANTABILITY OR

FITNESS FOR PURPOSE. Microchip disclaims all liability

arising from this information and its use. Use of Microchip

devices in life support and/or safety applications is entirely at

the buyer’s risk, and the buyer agrees to defend, indemnify and

hold harmless Microchip from any and all damages, claims,

suits, or expenses resulting from such use. No licenses are

conveyed, implicitly or otherwise, under any Microchip

intellectual property rights.

Trademarks

The Microchip name and logo, the Microchip logo, Accuron,

dsPIC, KEELOQ, microID, MPLAB, PIC, PICmicro, PICST ART ,

PRO MATE, PowerSmart, rfPIC, and SmartShunt are

registered trademarks of Microchip Technology Incorporated

in the U.S.A. and other countries.

AmpLab, FilterLab, Migratable Memory, MXDEV, MXLAB,

SEEV AL, SmartSensor and The Embedded Control Solutions

Company are registered trademarks of Microchip Technology

Incorporated in the U.S.A.

Analog-for-the-Digital Age, Application Maestro, CodeGuard,

dsPICDEM, dsPICDEM.net, dsPICworks, ECAN,

ECONOMONITOR, FanSense, FlexROM, fuzzyLAB,

In-Circuit Serial Programming, ICSP, ICEPIC, Linear Active

Thermistor, Mindi, MiWi, MPASM, MPLIB, MPLINK, PIC kit,

PICDEM, PICDEM.net, PICLAB, PICtail, PowerCal,

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Endurance, UNI/O, WiperLock and ZENA are trademarks of

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SQTP is a service mark of Microchip Technology Incorporated

in the U.S.A.

All other trademarks mentioned herein are property of their

respective companies.

Printed on recycled paper.

Note the following details of the code protection feature on Microchip devices:

• Microchip products meet the specification contained in their particular Microchip Data Sheet.

• Microchip believes that i t s family of products is one of the most secure families of it s kind on the market today, when used in the

intended manner and under normal conditions.

• The re are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our

knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data

Sheets. Most likely, the person doing so is engaged in theft of int ellectual property.

• Microchip is willing to work with the customer who is concerned about the integrity of their code.

• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not

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Code protection is c onstantly evolving. We a t Microchip are commit ted to continuously improving the code protect ion f eatures of our

products. Attempts to break Microchip’ s code protection f eature may be a violati on of t he Digit al Millennium Copyright Act. If such act s

allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Microchip received ISO/TS-16949:2002 certification for its worldwide

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China - Wuhan

Tel: 86-27-5980-5300

Fax: 86-27-5980-5118

China - Xian

Tel: 86-29-8833-7250

Fax: 86-29-8833-7256

ASIA/PACIFIC

India - Bangalore

Tel: 91-80-4182-8400

Fax: 91-80-4182-8422

India - New Delhi

Tel: 91-11-4160-8631

Fax: 91-11-4160-8632

India - Pune

Tel: 91-20-2566-1512

Fax: 91-20-2566-1513

Japan - Yokohama

Tel: 81-45-471- 6166

Fax: 81-45-471-6122

Korea - Gumi

Tel: 82-54-473-4301

Fax: 82-54-473-4302

Korea - Seoul

Tel: 82-2-554-7200

Fax: 82-2-558-5932 or

82-2-558-5934

Malaysia - Penang

Tel: 60-4-646-8870

Fax: 60-4-646-5086

Philippines - Manila

Tel: 63-2-634-9065

Fax: 63-2-634-9069

Singapore

Tel: 65-6334-8870

Fax: 65-6334-8850

Taiwan - Hsin Chu

Tel: 886-3-572-9526

Fax: 886-3-572-6459

Taiwan - Kaohsiung

Tel: 886-7-536-4818

Fax: 886-7-536-4803

Taiwan - Taipei

Tel: 886-2-2500-6610

Fax: 886-2-2508-0102

Thail a nd - Bangkok

Tel: 66-2-694-1351

Fax: 66-2-694-1350

EUROPE

Austria - Wels

Tel: 43-7242-2244-39

Fax: 43-7242-2244-393

Denmark - Copenhage n

Tel: 45-4450-2828

Fax: 45-4485-2829

France - Paris

Tel: 33-1-69-53-63-20

Fax: 33-1-69-30-90-79

Germany - Munich

Tel: 49-89-627-144-0

Fax: 49-89-627-14 4-44

Italy - Milan

Tel: 39-0331-742611

Fax: 39-0331-466781

Netherlands - Drunen

Tel: 31-416-690399

Fax: 31-416-690340

Sp ain - Madr i d

Tel: 34-91-708-08-90

Fax: 34-91-708-08 -91

UK - Wokingham

Tel: 44-118-921-5869

Fax: 44-118-921-5820

WORLDWIDE SALES AND SERVICE

12/08/06