NT2GC72B89G0NL(K)/NT2GC72C89G0NL(K) NT4GC72B4PG0NL(K)/NT4GC72C4PG0NL(K)/NT4GC72B8PG0NL(K)/NT4GC72C8PG0NL(K) NT8GC72B4NG0NL(K)/NT8GC72C4NG0NL(K) 2GB: 256M x 72 / 4GB: 512M x 72 / 8GB: 1G x 72 PC3-10600 / PC3(L)-12800 / PC3-14900 Registered DDR3 SDRAM DIMM Based on DDR3-1333/1600/1866 256Mx8 (2GB/4GB) / 512Mx4 (4GB/8GB) SDRAM G-Die Features *Performance: Speed Sort DIMM CAS Latency PC3-10600 PC3-12800 PC3-14900 -CG -DI -EK 9 11 13 Unit fck - Clock Frequency 667 800 933 tck - Clock Cycle 1.5 1.25 1.07 ns 1333 1600 1866 Mbps fDQ - DQ Burst Frequency MHz * 240-Pin Registered Dual In-Line Memory Module (RDIMM) * 2GB/4GB: 256Mx72/512Mx72 DDR3 Registered DIMM based on 256Mx8 DDR3 SDRAM G-Die devices * 4GB/8GB: 512Mx72/1024Mx72 DDR3 Registered DIMM based on 512Mx4 DDR3 SDRAM G-Die devices * Intended for 667MHz/800MHz/933MHz applications * Inputs and outputs are SSTL-15 compatible *VDD = VDDQ = 1.5V 0.075V (for DDR3) *VDD = VDDQ = 1.35V -0.0675/+0.1V (for DDR3L) (Backward Compatible to VDD = VDDQ = 1.5V 0.075V) * SDRAMs have 8 internal banks for concurrent operation * Differential clock inputs * Data is read or written on both clock edges * DRAM DLL aligns DQ and DQS transitions with clock transitions. * Address and control signals are fully synchronous to positive clock edge * Nominal and Dynamic On-Die Termination support * Programmable Operation: - DIMM Latency: 5,6,7,8,9,10,11,12,13 - Burst Type: Sequential or Interleave - Burst Length: BC4, BL8 - Operation: Burst Read and Write * Two different termination values (Rtt_Nom & Rtt_WR) * 15/10/1 (row/column/rank) Addressing for 2GB * 15/11/1 (row/column/rank) Addressing for 4GB (512Mx4 Device) * 15/10/2 (row/column/rank) Addressing for 4GB (256Mx8 Device) * 15/11/2 (row/column/rank) Addressing for 8GB * Extended operating temperature rage * Auto Self-Refresh option * Serial Presence Detect * Gold contacts * SDRAMs are in 78-ball BGA Package * RoHS compliance and Halogen free Description NT2GC72B89G0NL(K) / NT2GC72C89G0NL (K)/ NT4GC72B4PG0NL(K) / NT4GC72C4PG0NL(K)/ NT4GC72B8PG0NL(K) / NT4GC72C8PG0NL(K)/ NT8GC72B4NG0NL(K) and NT8GC72C4NG0NL(K) are 240-Pin Double Data Rate 3 (DDR3) Synchronous DRAM Registered Dual In-Line Memory Module, organized as one rank of 256Mx72 (2GB), one rank or two ranks of 512Mx72 (4GB) and two ranks of 1Gx72 (8GB) high-speed memory array. Modules use nine 256Mx8 (2GB) 78-ball BGA packaged devices, eighteen 256Mx8 (4GB) 78-ball BGA packaged devices and thirty-six 512Mx4 (8GB) 78-ball BGA packaged devices. These DIMMs are manufactured using raw cards developed for broad industry use as reference designs. The use of these common design files minimizes electrical variation between suppliers. All NANYA DDR3 SDRAM DIMMs provide a high-performance, flexible 8-byte interface in a 5.25" long space-saving footprint. The DIMM is intended for use in applications operating of 667MHz/800MHz/933MHz clock speeds and achieves high-speed data transfer rates of 1333Mbps/1600Mbps/1866Mbps. Prior to any access operation, the device latency and burst/length/operation type must be programmed into the DIMM by address inputs A0-A14 and I/O inputs BA0~BA2 using the mode register set cycle. The DIMM uses serial presence-detect implemented via a serial EEPROM using a standard IIC protocol. The first 128 bytes of SPD data are programmed and locked during module assembly. The remaining 128 bytes are available for use by the customer. REV 1.1 10/2011 1 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. NT2GC72B89G0NL(K)/NT2GC72C89G0NL(K) NT4GC72B4PG0NL(K)/NT4GC72C4PG0NL(K)/NT4GC72B8PG0NL(K)/NT4GC72C8PG0NL(K) NT8GC72B4NG0NL(K)/NT8GC72C4NG0NL(K) 2GB: 256M x 72 / 4GB: 512M x 72 / 8GB: 1G x 72 PC3-10600 / PC3(L)-12800 / PC3-14900 Registered DDR3 SDRAM DIMM Ordering Information Part Number Speed Organization NT2GC72B89G0NL(K)-CG DDR3-1333 PC3-10600 667MHz (1.5ns @ CL = 9) NT2GC72B89G0NL(K)-DI DDR3-1600 PC3-12800 800MHz (1.25ns @ CL = 11) NT4GC72B4PG0NL(K)-CG DDR3-1333 PC3-10600 667MHz (1.5ns @ CL = 9) NT4GC72B4PG0NL(K)-DI DDR3-1600 PC3-12800 800MHz (1.25ns @ CL = 11) NT4GC72B4PG0NL(K)-EK DDR3-1866 PC3-14900 933MHz (1.07ns @ CL = 13) NT4GC72B8PG0NL(K)-CG DDR3-1333 PC3-10600 667MHz (1.5ns @ CL = 9) NT4GC72B8PG0NL(K)-DI DDR3-1600 PC3-12800 800MHz (1.25ns @ CL = 11) NT8GC72B4NG0NL(K)-CG DDR3-1333 PC3-10600 667MHz (1.5ns @ CL = 9) NT8GC72B4NG0NL(K)-DI DDR3-1600 PC3-12800 800MHz (1.25ns @ CL = 11) NT8GC72B4NG0NL(K)-EK DDR3-1866 PC3-14900 933MHz (1.07ns @ CL = 13) NT2GC72C89G0NL(K)-CG DDR3L-1333 PC3L-10600 667MHz (1.5ns @ CL = 9) NT2GC72C89G0NL(K)-DI 800MHz (1.25ns @ CL = 11) DDR3L-1600 PC3L-12800 NT4GC72C4PG0NL(K)-CG DDR3L-1333 PC3L-10600 667MHz (1.5ns @ CL = 9) NT4GC72C4PG0NL(K)-DI DDR3L-1600 PC3L-12800 800MHz (1.25ns @ CL = 11) NT4GC72C8PG0NL(K)-CG DDR3L-1333 PC3L-10600 667MHz (1.5ns @ CL = 9) NT4GC72C8PG0NL(K)-DI DDR3L-1600 PC3L-12800 800MHz (1.25ns @ CL = 11) NT8GC72C4NG0NL(K)-CG DDR3L-1333 PC3L-10600 667MHz (1.5ns @ CL = 9) NT8GC72C4NG0NL(K)-DI DDR3L-1600 PC3L-12800 800MHz (1.25ns @ CL = 11) Power Leads Note 256Mx72 512Mx72 1.5V 1Gx72 Gold 256Mx72 1.35V 512Mx72 1Gx72 Note : L is Inphi Register, K is IDT Register. Pin Description Pin Name Description CK0, CK1 Clock Inputs, positive line , Clock Inputs, negative line CKE0, CKE1 Pin Name Description ODT0, ODT1 DQ0-DQ63 Clock Enable Active termination control lines Data input/output DQS0-DQS17 Data strobes - Data strobes complement Row Address Strobe Column Address Strobe TDQS9-TDQS17 Termination data strobes Write Enable - Termination data strobes - Chip Selects DM0-DM8 Data Masks Address Inputs CB0-CB7 ECC Check Bits A0-A9, A11, A13-A14 A10/AP Address Input/Auto-Precharge Temperature event pin A12/ Address Input/Burst Chop Reset pin BA0-BA2 SDRAM Bank Address Inputs SCL Serial Presence Detect Clock Input SDA Serial Presence Detect Data input/output Par_In Parity bit for the Address and Control bus NC REV 1.1 10/2011 VREFDQ , VREFCA VDDSPD Input/Output Reference SPD and Temp sensor power SA0, SA1, SA2 Serial Presence Detect Address Inputs Vtt Termination voltage Parity error found on the Address and Control bus VSS Ground No Connect VDD Core and I/O power 2 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. NT2GC72B89G0NL(K)/NT2GC72C89G0NL(K) NT4GC72B4PG0NL(K)/NT4GC72C4PG0NL(K)/NT4GC72B8PG0NL(K)/NT4GC72C8PG0NL(K) NT8GC72B4NG0NL(K)/NT8GC72C4NG0NL(K) 2GB: 256M x 72 / 4GB: 512M x 72 / 8GB: 1G x 72 PC3-10600 / PC3(L)-12800 / PC3-14900 Registered DDR3 SDRAM DIMM DDR3 SDRAM Pin Assignment Pin Front Pin Back Pin Front Pin Back Pin Front Pin Back Pin Front Pin Back 1 VREFDQ 121 VSS 31 DQ25 151 VSS 61 A2 181 A1 91 DQ41 211 VSS 2 VSS 122 DQ4 32 VSS 152 DM3/DQS12 /TDQS12 62 VDD 182 VDD 92 VSS 212 DM5/DQS14 /TDQS14 3 DQ0 123 DQ5 33 153 NC/ / 63 NC 183 VDD 93 213 NC/ / 4 DQ1 124 VSS 34 DQS3 154 VSS 64 NC 184 CK0 94 DQS5 214 VSS 5 VSS 125 DM0/DQS9/ TDQS9 35 VSS 155 DQ30 65 VDD 185 95 VSS 215 DQ46 6 126 NC/ / 36 DQ26 156 DQ31 66 VDD 186 VDD 96 DQ42 216 DQ47 7 DQS0 127 VSS 37 DQ27 157 VSS 67 VREFCA 187 97 DQ43 217 VSS 8 VSS 128 DQ6 38 VSS 158 CB4 68 Par_In/NC 188 A0 98 VSS 218 DQ52 9 DQ2 129 DQ7 39 CB0 159 CB5 69 VDD 189 VDD 99 DQ48 219 DQ53 10 DQ3 130 VSS 40 CB1 160 VSS 70 A10/AP 190 BA1 100 DQ49 220 VSS 11 VSS 131 DQ12 41 VSS 161 DM8/DQS17 /TDQS17 71 BA0 191 VDD 101 VSS 221 DM6/DQS15 /TDQS15 12 DQ8 132 DQ13 42 162 NC/ / 72 VDD 192 102 222 NC/ / 13 DQ9 133 VSS 43 DQS8 163 VSS 73 193 103 DQS6 223 VSS 44 VSS 164 CB6 74 194 VDD 104 VSS 224 DQ54 14 VSS 134 DM1/DQS10 /TDQS10 15 135 NC/ / 45 CB2 165 CB7 75 VDD 195 ODT0 105 DQ50 225 DQ55 16 DQS1 136 VSS 46 CB3 166 VSS 76 /NC 196 A13 106 DQ51 226 VSS 17 VSS 137 DQ14 47 VSS 167 NC 77 ODT1/NC 197 VDD 107 VSS 227 DQ60 18 DQ10 138 DQ15 48 VTT/NC 168 78 VDD 198 /NC 108 DQ56 228 DQ61 19 DQ11 139 VSS 49 VTT/NC 169 CKE1/NC 79 /NC 199 VSS 109 DQ57 229 VSS 20 VSS 140 DQ20 50 CKE0 170 VDD 80 VSS 200 DQ36 110 VSS 230 DM7/DQS16 /TDQS16 21 DQ16 141 DQ21 51 VDD 171 A15 81 DQ32 201 DQ37 111 231 NC/ / 22 DQ17 142 VSS 52 BA2 172 A14 82 DQ33 202 VSS 112 DQS7 232 VSS 23 VSS 143 DM2/DQS11 /TDQS11 53 /NC 173 VDD 83 VSS 203 DM4/DQS13 /TDQS13 113 VSS 233 DQ62 24 144 NC/ / 54 VDD 174 A12/ 84 204 NC/ / 114 DQ58 234 DQ63 25 DQS2 145 VSS 55 A11 175 A9 85 DQS4 205 VSS 115 DQ59 235 VSS 26 VSS 146 DQ22 56 A7 176 VDD 86 VSS 206 DQ38 116 VSS 236 VDDSPD 27 DQ18 147 DQ23 57 VDD 177 A8 87 DQ34 207 DQ39 117 SA0 237 SA1 28 DQ19 148 VSS 58 A5 178 A6 88 DQ35 208 VSS 118 SCL 238 SDA 29 VSS 149 DQ28 59 A4 179 VDD 89 VSS 209 DQ44 119 SA2 239 VSS 30 DQ24 150 DQ29 60 VDD 180 A3 90 DQ40 210 DQ45 120 VTT 240 VTT Note: 1. CKE1, and ODT1 are for 2GB/4GB/8GB only. 2. and are for 8GB only. 3. TDQS9-TDQS17 and - are for 1GB/2GB only. REV 1.1 10/2011 3 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. NT2GC72B89G0NL(K)/NT2GC72C89G0NL(K) NT4GC72B4PG0NL(K)/NT4GC72C4PG0NL(K)/NT4GC72B8PG0NL(K)/NT4GC72C8PG0NL(K) NT8GC72B4NG0NL(K)/NT8GC72C4NG0NL(K) 2GB: 256M x 72 / 4GB: 512M x 72 / 8GB: 1G x 72 PC3-10600 / PC3(L)-12800 / PC3-14900 Registered DDR3 SDRAM DIMM Input/Output Functional Description Symbol Type Polarity Function CK0, CK1 , Input Cross point The system clock inputs. All address and command lines are sampled on the cross point of the rising edge of CK and falling edge of . A Delay Locked Loop (DLL) circuit is driven from the clock inputs and output timing for read operations is synchronized to the input clock. However, CK1 and are terminated but not used on RDIMMs. CKE0, CKE1 Input Active High Activates the DDR3 SDRAM CK signal when high and deactivates the CK signal when low. By deactivating the clocks, CKE low initiates the Power Down mode or the Self Refresh mode. - Input Active Low Enable the command decoders for the associated rank of SDRAM when low and disables decoders when high. When decoders are disabled, new commands are ignored and previous operations continue. Other combinations of these input signals perform unique functions, including disabling all outputs (except CKE and ODT) of the register(s) on the DIMM or accessing internal control words in the register device(s). For modules with two registers, and operate similarly to and for the second set of register outputs or register control words. , , Input Active Low When sampled at the positive rising edge of CK and falling edge of , signals , , define the operation to be executed by the SDRAM. ODT0, ODT1 Input Active High Asserts on-die termination for DQ, DM, DQS, and signals if enabled via the DDR3 SDRAM mode register. DM0 - DM8 Input Active High The data write masks, associated with one data byte. In Write mode, DM operates as a byte mask by allowing input data to be written if it is low but blocks the write operation if it is high. In Read mode, DM lines have no effect. Cross point The data strobes, associated with one data byte, sourced with data transfers. In Write mode, the data strobe is sourced by the controller and is centered in the data window. In Read mode, the data strobe is sourced by the DDR3 SDRAM and is sent at the leading edge of the data window. signals are complements, and timing is relative to the cross point of respective DQS and . If the module is to be operated in single ended strobe mode, all signals must be tied on the system board to VSS and DDR3 SDRAM mode registers programmed appropriately. DQS0 - DQS17 - I/O TDQS9 - TDQS17 - Output BA0, BA1, BA2 Input TDQS/ is applicable for x8 DRAMs only. When enabled via mode register A11=1 in MR1, DRAM will enable the same termination resistance function on TDQS/ that is applied to DQS/. When disabled via mode register A11=0 in MR1, DM/TDQS will provide the data mask function is not used. X4/x16 DRAMs must disable the TDQS function via mode register A11=0 in MR1. - Selects which DDR3 SDRAM internal bank of four or eight is activated. A0 - A9 A10/AP A11 A12/ A13-A14 Input - During a Bank Activate command cycle, defines the row address when sampled at the cross point of the rising edge of CK and falling edge of . During a Read or Write command cycle, defines the column address when sampled at the cross point of the rising edge of CK and falling edge of . In addition to the column address, AP is used to invoke autoprecharge operation at the end of the burst read or write cycle. If AP is high, autoprecharge is selected and BA0-BAn defines the bank to be precharged. If AP is low, autoprecharge is disabled. During a Precharge command cycle, AP is used in conjunction with BA0-BAn to control which bank(s) to precharge. If AP is high, all banks will be precharged regardless of the state of BA0-BAn inputs. If AP is low, then BA0-BAn are used to define which bank to precharge. DQ0 - DQ63 Input - Data Input/Output pins. CB0 - CB7 I/O - Check bits are used for ECC. VDD, VDDSPD, VSS Supply - Power supplies for core, I/O, Serial Presence Detect, Temp sensor, and ground for the module. VREFDQ, VREFCA Supply - Reference voltage for SSTL15 inputs. SDA I/O - This is a bidirectional pin used to transfer data into or out of the SPD EEPROM and temp sensor. A resistor must be connected from the SDA bus line to VDDSPD on the system planar to act as a pull up. SCL Input - This signal is used to clock data into and out of the SPD EEPROM and Temp sensor. SA0 - SA2 Input - Address pins used to select the Serial Presence Detect and Temp sensor base address. Output - The pin is reserved for use to flag critical module temperature. Input - This signal resets the DDR3 SDRAM. Par_In Input - Parity bit for the Address and Control bus. Output - Parity error detected on the Address and Control bus. A resistor may be connected from bus line to VDD on the system planar to act as a pull up. REV 1.1 10/2011 4 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. NT2GC72B89G0NL(K)/NT2GC72C89G0NL(K) NT4GC72B4PG0NL(K)/NT4GC72C4PG0NL(K)/NT4GC72B8PG0NL(K)/NT4GC72C8PG0NL(K) NT8GC72B4NG0NL(K)/NT8GC72C4NG0NL(K) 2GB: 256M x 72 / 4GB: 512M x 72 / 8GB: 1G x 72 PC3-10600 / PC3(L)-12800 / PC3-14900 Registered DDR3 SDRAM DIMM DQS3 DM3/DQS12 DQ[31:24] DQS TDQS DQ[7:0] DQS2 DM2/DQS11 DQ[23:16] DQS TDQS DQ[7:0] DQS1 DM1/DQS10 DQ[15:8] DQS TDQS DQ[7:0] DQS0 DM0/DQS9 DQS TDQS DQ[7:0] ZQ D8 DQS4 DM4/DQS13 DQ[39:32] DQS TDQS DQ[7:0] DQS5 DM5/DQS14 DQ[47:40] DQS TDQS DQ[7:0] DQS6 DM6/DQS15 DQ[55:48] DQS TDQS DQ[7:0] DQS7 DM7/DQS16 DQ[63:56] DQS TDQS DQ[7:0] ZQ D4 ZQ D5 CK CKE ODT A[14:0] BA[2:0] CK CKE ODT A[14:0] BA[2:0] D3 ZQ ZQ D6 CK CKE ODT A[14:0] BA[2:0] CK CKE ODT A[14:0] BA[2:0] D2 ZQ ZQ D7 CK CKE ODT A[14:0] BA[2:0] CK CKE ODT A[14:0] BA[2:0] D1 Vtt ZQ VDDSPD VDD VTT VREFCA VREFDQ VSS D0 CK CKE ODT A[14:0] BA[2:0] DQ[7:0] ZQ CK CKE ODT A[14:0] BA[2:0] DQS TDQS DQ[7:0] CK CKE ODT A[14:0] BA[2:0] DQS8 DM8/DQS17 CB[7:0] PCK0A P RCKE0B RODT0B A[14:0]B/ BA[2:0]B PCK0A P RCKE0A RODT0A A[14:0]A/ BA[2:0]A Functional Block Diagram (Part 1 of 2) [2GB - 1 Rank, 256Mx8 DDR3 SDRAMs] Vtt SPD D0-D8 D0-D8 D0-D8 D0-D8 D0-D8 SPD w/ Integrated Thermal Sensor SCL SA0 SA1 SA2 SCL A0 A1 A2 SDA Notes : 1. DQ-to-I/O wiring is shown as recommended but may be changed. 2. ZQ resistors are 240 1%. For all other resistor values refer to the appropriate wiring diagram. REV 1.1 10/2011 5 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. NT2GC72B89G0NL(K)/NT2GC72C89G0NL(K) NT4GC72B4PG0NL(K)/NT4GC72C4PG0NL(K)/NT4GC72B8PG0NL(K)/NT4GC72C8PG0NL(K) NT8GC72B4NG0NL(K)/NT8GC72C4NG0NL(K) 2GB: 256M x 72 / 4GB: 512M x 72 / 8GB: 1G x 72 PC3-10600 / PC3(L)-12800 / PC3-14900 Registered DDR3 SDRAM DIMM Functional Block Diagram (Part 2 of 2) [2GB - 1 Rank, 256Mx8 DDR3 SDRAMs] : SDRAMs D[3:0], D8 : SDRAMs D[7:4] BA[2:0] A[14:0] CKE0 ODT0 CK0 120 1% Register / PLL RBA[2:0]A BA[2:0]: SDRAMs D[3:0], D8 RBA[2:0]B BA[2:0]: SDRAMs D[7:4] RA[14:0]A A[14:0]: SDRAMs D[3:0], D8 RA[14:0]B A[14:0]: SDRAMs D[7:4] : SDRAMs D[3:0], D8 : SDRAMs D[7:4] : SDRAMs D[3:0], D8 : SDRAMs D[7:4] : SDRAMs D[3:0], D8 : SDRAMs D[7:4] RCKE0A CKE0: SDRAMs D[3:0], D8 RCKE0B CKE0: SDRAMs D[7:4] RODT0A ODT0: SDRAMs D[3:0], D8 RODT0B ODT0: SDRAMs D[7:4] PCK0A CK: SDRAMs D[3:0], D8 PCK0B CK: SDRAMs D[7:4] P : SDRAMs D[3:0], D8 P : SDRAMs D[7:4] CK1 120 5% PAR_IN U : SDRAMs D[8:0] Note: S[3:2], CKE1, ODT1 are NC (Unused register inputs ODT1 and CKE1 have a 330 resistor to ground) REV 1.1 10/2011 6 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. NT2GC72B89G0NL(K)/NT2GC72C89G0NL(K) NT4GC72B4PG0NL(K)/NT4GC72C4PG0NL(K)/NT4GC72B8PG0NL(K)/NT4GC72C8PG0NL(K) NT8GC72B4NG0NL(K)/NT8GC72C4NG0NL(K) 2GB: 256M x 72 / 4GB: 512M x 72 / 8GB: 1G x 72 PC3-10600 / PC3(L)-12800 / PC3-14900 Registered DDR3 SDRAM DIMM ZQ DQS TDQS DQ[7:0] ZQ DQS7 DM7/DQS16 DQ[63:56] DQS TDQS DQ[7:0] ZQ DQS TDQS DQ[7:0] D11 D10 PCK1B P RCKE1B RODT1B CK CKE ODT A[14:0] BA[2:0] CK CKE ODT A[14:0] BA[2:0] DQS TDQS DQ[7:0] ZQ D6 D15 DQS TDQS DQ[7:0] ZQ D7 D16 D9 VDDSPD VDD VTT VREFCA VREFDQ VSS ZQ SPD D0-D17 D0-D17 D0-D17 D0-D17 D0-D17 SPD w/ Integrated Thermal Sensor SCL Notes : 1. DQ-to-I/O wiring is shown as recommended but may be changed. 2. ZQ resistors are 240 1%. For all other resistor values refer to the appropriate wiring diagram. 3. Unless otherwise noted, resistor values are 15 5%. 4. See the wiring diagrams for all resistors associated with the command, address and control bus. 10/2011 D14 Vtt Vtt REV 1.1 PCK0B P RCKE0B RODT0B A[14:0]B/ BA[2:0]B PCK1A P RCKE1A RODT1A DQS TDQS DQ[7:0] ZQ D5 CK CKE ODT A[14:0] BA[2:0] CK CKE ODT A[14:0] BA[2:0] CK CKE ODT A[14:0] BA[2:0] CK CKE ODT A[14:0] BA[2:0] CK CKE ODT A[14:0] BA[2:0] D0 DQS TDQS DQ[7:0] ZQ D13 CK CKE ODT A[14:0] BA[2:0] DQS TDQS DQ[7:0] DQS6 DM6/DQS15 DQ[55:48] CK CKE ODT A[14:0] BA[2:0] DQS0 DM0/DQS9 DQ[7:0] D1 D12 DQS TDQS DQ[7:0] ZQ CK CKE ODT A[14:0] BA[2:0] DQS TDQS DQ[7:0] ZQ DQS TDQS DQ[7:0] ZQ D4 CK CKE ODT A[14:0] BA[2:0] DQS1 DM1/DQS10 DQ[15:8] D2 DQS TDQS DQ[7:0] ZQ DQS TDQS DQ[7:0] ZQ CK CKE ODT A[14:0] BA[2:0] DQS TDQS DQ[7:0] ZQ DQS5 DM5/DQS14 DQ[47:40] CK CKE ODT A[14:0] BA[2:0] DQS2 DM2/DQS11 DQ[23:16] D3 DQS TDQS DQ[7:0] ZQ CK CKE ODT A[14:0] BA[2:0] DQS TDQS DQ[7:0] ZQ D17 DQS4 DM4/DQS13 DQ[39:32] CK CKE ODT A[14:0] BA[2:0] DQS3 DM3/DQS12 DQ[31:24] D8 DQS TDQS DQ[7:0] ZQ CK CKE ODT A[14:0] BA[2:0] DQS TDQS DQ[7:0] ZQ CK CKE ODT A[14:0] BA[2:0] DQS8 DM8/DQS17 CB[7:0] CK CKE ODT A[14:0] BA[2:0] PCK0A P RCKE0A RODT0A A[14:0]A/ BA[2:0]A Functional Block Diagram (Part 1 of 2) [4GB - 2 Ranks, 256Mx8 DDR3 SDRAMs] SA0 SA1 SA2 SCL A0 A1 A2 SDA 7 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. NT2GC72B89G0NL(K)/NT2GC72C89G0NL(K) NT4GC72B4PG0NL(K)/NT4GC72C4PG0NL(K)/NT4GC72B8PG0NL(K)/NT4GC72C8PG0NL(K) NT8GC72B4NG0NL(K)/NT8GC72C4NG0NL(K) 2GB: 256M x 72 / 4GB: 512M x 72 / 8GB: 1G x 72 PC3-10600 / PC3(L)-12800 / PC3-14900 Registered DDR3 SDRAM DIMM Functional Block Diagram (Part 2 of 2) [4GB - 2 Ranks, 256Mx8 DDR3 SDRAMs] BA[2:0] A[14:0] : SDRAMs D[3:0], D8 : SDRAMs D[7:4] : SDRAMs D[12:9], D17 : SDRAMs D[16:13] RBA[2:0]A BA[2:0]: SDRAMs D[3:0], D[12:8], D17 RBA[2:0]B BA[2:0]: SDRAMs D[7:4], D[16:13] RA[14:0]A A[14:0]: SDRAMs D[3:0], D[12:8], D17 RA[14:0]B A[14:0]: SDRAMs D[7:4], D[16:13] : SDRAMs D[7:4], D[16:13] : SDRAMs D[3:0], D[12:8], D17 : SDRAMs D[7:4], D[16:13] : SDRAMs D[3:0], D[12:8], D17 Register / PLL CKE0 CKE1 ODT0 ODT1 CK0 120 1% : SDRAMs D[3:0], D[12:8], D17 : SDRAMs D[7:4], D[16:13] RCKE0A CKE0: SDRAMs D[3:0], D8 RCKE0B CKE0: SDRAMs D[7:4] RCKE1A CKE1: SDRAMs D[12:9], D17 RCKE1B CKE1: SDRAMs D[16:13] RODT0A ODT0: SDRAMs D[3:0], D8 RODT0B ODT0: SDRAMs D[7:4] RODT1A ODT1: SDRAMs D[12:9], D17 RODT1B ODT1: SDRAMs D[16:13] PCK0A CK: SDRAMs D[3:0], D8 PCK0B CK: SDRAMs D[7:4] PCK1A CK: SDRAMs D[12:9], D17 PCK1B CK: SDRAMs D[16:13] P : SDRAMs D[3:0], D8 P : SDRAMs D[7:4] P : SDRAMs D[12:9], D17 P : SDRAMs D[16:13] CK1 120 5% PAR_IN U : SDRAMs D[17:0] REV 1.1 10/2011 8 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. NT2GC72B89G0NL(K)/NT2GC72C89G0NL(K) NT4GC72B4PG0NL(K)/NT4GC72C4PG0NL(K)/NT4GC72B8PG0NL(K)/NT4GC72C8PG0NL(K) NT8GC72B4NG0NL(K)/NT8GC72C4NG0NL(K) 2GB: 256M x 72 / 4GB: 512M x 72 / 8GB: 1G x 72 PC3-10600 / PC3(L)-12800 / PC3-14900 Registered DDR3 SDRAM DIMM PCK0A P RCKE0A RODT0A A[14:0]A BA[2:0]A PCK0A P RCKE0A RODT0A A[14:0]A BA[2:0]A Functional Block Diagram (Part 1 of 3) [4GB - 1 Rank, 512Mx4 DDR3 SDRAMs] DQS8 CB[3:0] VSS DQS DQ[4:0] DM ZQ DQS17 CB[7:4] VSS DQS DQ[4:0] DM DQS3 DQ[27:24] VSS DQS DQ[4:0] DM CK CKE ODT A[14:0] BA[2:0] D17 CK CKE ODT A[14:0] BA[2:0] D8 ZQ DQS12 DQ[31:28] VSS DQS DQ[4:0] DM DQS DQ[4:0] DM ZQ CK CKE ODT A[14:0] BA[2:0] D12 CK CKE ODT A[14:0] BA[2:0] D3 DQS2 DQ[19:16] VSS ZQ ZQ DQS11 DQ[23:20] VSS D2 DQS DQ[4:0] DM ZQ DQS1 DQ[11:8] VSS DQS DQ[4:0] DM CK CKE ODT A[14:0] BA[2:0] CK CKE ODT A[14:0] BA[2:0] D11 ZQ DQS10 DQ[15:12] VSS D1 DQS DQ[4:0] DM ZQ DQS0 DQ[3:0] VSS DQS DQ[4:0] DM CK CKE ODT A[14:0] BA[2:0] CK CKE ODT A[14:0] BA[2:0] D10 ZQ DQS9 DQ[7:4] VSS D0 DQS DQ[4:0] DM ZQ CK CKE ODT A[14:0] BA[2:0] CK CKE ODT A[14:0] BA[2:0] D9 Vtt REV 1.1 10/2011 9 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. NT2GC72B89G0NL(K)/NT2GC72C89G0NL(K) NT4GC72B4PG0NL(K)/NT4GC72C4PG0NL(K)/NT4GC72B8PG0NL(K)/NT4GC72C8PG0NL(K) NT8GC72B4NG0NL(K)/NT8GC72C4NG0NL(K) 2GB: 256M x 72 / 4GB: 512M x 72 / 8GB: 1G x 72 PC3-10600 / PC3(L)-12800 / PC3-14900 Registered DDR3 SDRAM DIMM PCK0B P RCKE0B RODT0B A[14:0]B BA[2:0]B PCK0B P RCKE0B RODT0B A[14:0]B BA[2:0]B Functional Block Diagram (Part 2 of 3) [4GB - 1 Rank, 512Mx4 DDR3 SDRAMs] DQS4 DQ[35:32] VSS DQS DQ[4:0] DM ZQ DQS13 DQ[39:36] VSS DQS DQ[4:0] DM D13 CK CKE ODT A[14:0] BA[2:0] CK CKE ODT A[14:0] BA[2:0] D4 DQS5 DQ[43:40] VSS DQS DQ[4:0] DM ZQ DQS14 DQ[47:44] VSS DQS DQ[4:0] DM D14 CK CKE ODT A[14:0] BA[2:0] DQS DQ[4:0] DM ZQ DQS15 DQ[55:52] VSS DQS DQ[4:0] DM D6 DQS DQ[4:0] DM ZQ D15 CK CKE ODT A[14:0] BA[2:0] CK CKE ODT A[14:0] BA[2:0] DQS7 DQ[59:56] VSS ZQ CK CKE ODT A[14:0] BA[2:0] D5 DQS6 DQ[51:48] VSS ZQ ZQ DQS16 DQ[63:60] VSS DQS DQ[4:0] DM ZQ D16 CK CKE ODT A[14:0] BA[2:0] CK CKE ODT A[14:0] BA[2:0] D7 Vtt VDDSPD SPD SPD w/ Integrated Thermal Sensor VDD D0-D17 SCL SCL VTT D0-D17 A0 SA0 VREFCA D0-D17 A1 SA1 VREFDQ D0-D17 A2 SA2 VSS D0-D17 Notes : 1. DQ-to-I/O wiring is shown as recommended but may be changed. 2. ZQ resistors are 240 1%. For all other resistor values refer to the appropriate wiring diagram. 3. Unless otherwise noted, resistor values are 15 5%. 4. See the wiring diagrams for all resistors associated with the command, address and control bus. REV 1.1 10/2011 SDA 10 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. NT2GC72B89G0NL(K)/NT2GC72C89G0NL(K) NT4GC72B4PG0NL(K)/NT4GC72C4PG0NL(K)/NT4GC72B8PG0NL(K)/NT4GC72C8PG0NL(K) NT8GC72B4NG0NL(K)/NT8GC72C4NG0NL(K) 2GB: 256M x 72 / 4GB: 512M x 72 / 8GB: 1G x 72 PC3-10600 / PC3(L)-12800 / PC3-14900 Registered DDR3 SDRAM DIMM Functional Block Diagram (Part 3 of 3) [4GB - 1 Rank, 512Mx4 DDR3 SDRAMs] CS0_A: SDRAMs D[3:0], D[12:8], D17 CS0_B: SDRAMs D[7:4], D[16:13] BA[2:0] A[14:0] Register / PLL CKE0 CKE1 ODT0 ODT1 BA[2:0]A BA[2:0]: SDRAMs D[3:0], D[12:8],D17 BA[2:0]B BA[2:0]: SDRAMs D[7:4], D[16:13] A[14:0]A A[14:0]: SDRAMs D[3:0], D[12:8], D17 A[14:0]B A[14:0]: SDRAMs D[7:4], D[16:13] RAS: SDRAMs D[3:0], D[12:8], D17 RAS: SDRAMs D[7:4], D[16:13] CAS: SDRAMs D[3:0], D[12:8], D17 CAS: SDRAMs D[7:4], D[16:13] WE: SDRAMs D[3:0], D[12:8], D17 WE: SDRAMs D[7:4], D[16:13] RCKE0A CKE0: SDRAMs D[3:0], D[12:8], D17 RCKE0B CKE0: SDRAMs D[7:4], D[16:13] RODT0A ODT0: SDRAMs D[3:0], D[12:8], D17 RODT0B ODT0: SDRAMs D[7:4], D[16:13] PCK0A CK: SDRAMs D[3:0], D[12:8], D17 PCK0B CK: SDRAMs D[7:4], D[16:13] CK0 120 1% P CK: SDRAMs D[3:0], D[12:8], D17 P CK: SDRAMs D[7:4], D[16:13] CK1 120 5% PAR_IN U : SDRAMs D[17:0] REV 1.1 10/2011 11 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. NT2GC72B89G0NL(K)/NT2GC72C89G0NL(K) NT4GC72B4PG0NL(K)/NT4GC72C4PG0NL(K)/NT4GC72B8PG0NL(K)/NT4GC72C8PG0NL(K) NT8GC72B4NG0NL(K)/NT8GC72C4NG0NL(K) 2GB: 256M x 72 / 4GB: 512M x 72 / 8GB: 1G x 72 PC3-10600 / PC3(L)-12800 / PC3-14900 Registered DDR3 SDRAM DIMM DQS DM DQ[3:0] DQS DM DQ[3:0] D9 D27 CK CKE ODT A[14:0] BA[2:0] D18 DQS DM DQ[3:0] D19 CK CKE ODT A[14:0] BA[2:0] CK CKE ODT A[14:0] BA[2:0] DQS9 VSS DQ[7:4] PCK1A P RCKE1A RODT1A CK CKE ODT A[14:0] BA[2:0] CK CKE ODT A[14:0] BA[2:0] CK CKE ODT A[14:0] BA[2:0] CK CKE ODT A[14:0] BA[2:0] D20 D1 CK CKE ODT A[14:0] BA[2:0] CK CKE ODT A[14:0] BA[2:0] 10/2011 DQS DM DQ[3:0] DQS DM DQ[3:0] D28 CK CKE ODT A[14:0] BA[2:0] CK CKE ODT A[14:0] BA[2:0] DQS1 VSS DQ[11:8] Vtt REV 1.1 D21 D2 DQS DM DQ[3:0] D0 DQS DM DQ[3:0] DQS DM DQ[3:0] D29 CK CKE ODT A[14:0] BA[2:0] CK CKE ODT A[14:0] BA[2:0] DQS2 VSS DQ[19:16] DQS DM DQ[3:0] DQS DM DQ[3:0] D26 D3 DQS DM DQ[3:0] DQS DM DQ[3:0] DQS DM DQ[3:0] D30 D10 DQS0 VSS DQ[3:0] DQS3 VSS DQ[27:24] CK CKE ODT A[14:0] BA[2:0] CK CKE ODT A[14:0] BA[2:0] DQS DM DQ[3:0] DQS DM DQ[3:0] D8 DQS DM DQ[3:0] D11 DQS10 VSS DQ[15:12] PCK0A P RCKE0A RODT0A A[14:0]A/ BA[2:0]A D35 D12 DQS11 VSS DQ[23:20] DQS DM DQ[3:0] CK CKE ODT A[14:0] BA[2:0] DQS DM DQ[3:0] DQS8 VSS CB[3:0] CK CKE ODT A[14:0] BA[2:0] CK CKE ODT A[14:0] BA[2:0] D17 DQS12 VSS DQ[31:28] PCK1A P RCKE1A RODT1A DQS DM DQ[3:0] CK CKE ODT A[14:0] BA[2:0] DQS DM DQ[3:0] CK CKE ODT A[14:0] BA[2:0] DQS17 VSS CB[7:4] PCK0A P RCKE0A RODT0A A[14:0]A/ BA[2:0]A Functional Block Diagram (Part 1 of 3) [8GB - 2 Ranks, 512Mx4 DDR3 SDRAMs] Vtt 12 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. NT2GC72B89G0NL(K)/NT2GC72C89G0NL(K) NT4GC72B4PG0NL(K)/NT4GC72C4PG0NL(K)/NT4GC72B8PG0NL(K)/NT4GC72C8PG0NL(K) NT8GC72B4NG0NL(K)/NT8GC72C4NG0NL(K) 2GB: 256M x 72 / 4GB: 512M x 72 / 8GB: 1G x 72 PC3-10600 / PC3(L)-12800 / PC3-14900 Registered DDR3 SDRAM DIMM DQS DM DQ[3:0] CK CKE ODT A[14:0] BA[2:0] D23 DQS DM DQ[3:0] DQS DM DQ[3:0] CK CKE ODT A[14:0] BA[2:0] D33 CK CKE ODT A[14:0] BA[2:0] DQS6 VSS DQ[51:48] PCK1B P RCKE1B RODT1B CK CKE ODT A[14:0] BA[2:0] DQS DM DQ[3:0] D15 DQS DM DQ[3:0] D6 D24 CK CKE ODT A[14:0] BA[2:0] D25 CK CKE ODT A[14:0] BA[2:0] CK CKE ODT A[14:0] BA[2:0] DQS DM DQ[3:0] D34 CK CKE ODT A[14:0] BA[2:0] CK CKE ODT A[14:0] BA[2:0] DQS15 VSS DQ[55:52] DQS DM DQ[3:0] D7 PCK0B P RCKE0B RODT0B A[14:0]B/ BA[2:0]B DQS DM DQ[3:0] DQS DM DQ[3:0] D31 D5 CK CKE ODT A[14:0] BA[2:0] CK CKE ODT A[14:0] BA[2:0] DQS5 VSS DQ[43:40] D22 D16 DQS7 VSS DQ[59:56] D13 DQS DM DQ[3:0] DQS DM DQ[3:0] DQS DM DQ[3:0] D22 D4 DQS16 VSS DQ[63:60] DQS DM DQ[3:0] CK CKE ODT A[14:0] BA[2:0] DQS DM DQ[3:0] DQS13 VSS DQ[39:36] CK CKE ODT A[14:0] BA[2:0] CK CKE ODT A[14:0] BA[2:0] D14 DQS4 VSS DQ[35:32] PCK1B P RCKE1B RODT1B DQS DM DQ[3:0] CK CKE ODT A[14:0] BA[2:0] DQS DM DQ[3:0] CK CKE ODT A[14:0] BA[2:0] DQS14 VSS DQ[47:44] PCK0B P RCKE0B RODT0B A[14:0]B/ BA[2:0]B Functional Block Diagram (Part 2 of 3) [8GB - 2 Ranks, 512Mx4 DDR3 SDRAMs] Vtt Vtt VDDSPD VDD VTT VREFCA VREFDQ VSS Notes : 1. DQ-to-I/O wiring is shown as recommended but may be changed. 2. ZQ pins of each SDRAM are connected to individual RZQ resistors (240 1%). 3. See the wiring diagrams for resistor values. SPD D0-D35 D0-D35 D0-D35 D0-D35 D0-D35 SPD w/ Integrated Thermal Sensor SCL SA0 SA1 SA2 SCL A0 A1 A2 SDA REV 1.1 10/2011 13 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. NT2GC72B89G0NL(K)/NT2GC72C89G0NL(K) NT4GC72B4PG0NL(K)/NT4GC72C4PG0NL(K)/NT4GC72B8PG0NL(K)/NT4GC72C8PG0NL(K) NT8GC72B4NG0NL(K)/NT8GC72C4NG0NL(K) 2GB: 256M x 72 / 4GB: 512M x 72 / 8GB: 1G x 72 PC3-10600 / PC3(L)-12800 / PC3-14900 Registered DDR3 SDRAM DIMM Functional Block Diagram (Part 3 of 3) [8GB - 2 Ranks, 512Mx4 DDR3 SDRAMs] : SDRAMs D[3:0], D[12:8], D17 : SDRAMs D[25:21], D[34:31] : SDRAMs D[21:18]B, D[30:26], D35 : SDRAMs D[7:4], D[16:13] BA[2:0] RBA[2:0]A BA[2:0]: SDRAMs D[3:0], D[12:8], D[21:17], D[30:26], D35 RBA[2:0]B BA[2:0]: SDRAMs D[7:4], D[16:13], D[25:22], D[34:31] RA[14:0]A A[14:0]: SDRAMs D[3:0], D[12:8], D[21:17], D[30:26], D35 RA[14:0]B A[14:0]: SDRAMs D[7:4], D[16:13], D[25:22], D[34:31] A[14:0] Register / PLL CKE0 CKE1 ODT0 ODT1 CK0 120 1% : SDRAMs D[3:0], D[12:8], D[21:17], D[30:26], D35 : SDRAMs D[7:4], D[16:13], D[25:22], D[34:31] : SDRAMs D[3:0], D[12:8], D[21:17], D[30:26], D35 : SDRAMs D[7:4], D[16:13], D[25:22], D[34:31] : SDRAMs D[3:0], D[12:8], D[21:17], D[30:26], D35 : SDRAMs D[7:4], D[16:13], D[25:22], D[34:31] RCKE0A CKE0: SDRAMs D[3:0], D[12:8], D17 RCKE0B CKE0: SDRAMs D[25:22], D[34:31] RCKE1A CKE1: SDRAMs D[21:18], D[30:26], D35 RCKE1B CKE1: SDRAMs D[7:4], D[16:13] RODT0A ODT0: SDRAMs D[3:0], D[12:8], D17 RODT0B ODT0: SDRAMs D[7:4], D[34:31] RODT1A ODT1: SDRAMs D[21:18], D[30:26], D35 RODT1B ODT1: SDRAMs D[7:4], D[16:13] PCK0A CK: SDRAMs D[3:0], D[12:8], D17 PCK0B CK: SDRAMs D[25:22], D[34:31] PCK1A CK: SDRAMs D[21:18], D[30:26], D35 PCK1B CK: SDRAMs D[7:4], D[16:13] P : SDRAMs D[3:0], D[12:8], D17 P : SDRAMs D[25:22], D[34:31] P : SDRAMs D[21:18], D[30:26], D35 P : SDRAMs D[7:4], D[16:13] CK1 120 5% PAR_IN U : SDRAMs D[17:0], D[35:18] REV 1.1 10/2011 14 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. NT2GC72B89G0NL(K)/NT2GC72C89G0NL(K) NT4GC72B4PG0NL(K)/NT4GC72C4PG0NL(K)/NT4GC72B8PG0NL(K)/NT4GC72C8PG0NL(K) NT8GC72B4NG0NL(K)/NT8GC72C4NG0NL(K) 2GB: 256M x 72 / 4GB: 512M x 72 / 8GB: 1G x 72 PC3-10600 / PC3(L)-12800 / PC3-14900 Registered DDR3 SDRAM DIMM Environmental Requirements Symbol Parameter Rating Units Note HOPR Operating Humidity (relative) 10 to 90 % 1 TSTG Storage Temperature (Plastic) -55 to 100 C 1 HSTG Storage Humidity (without condensation) 5 to 95 % 1 PBAR Barometric Pressure (operating & storage) 105 to 69 K Pascal 1, 2 Note: 1. Stresses greater than those listed may cause permanent damage to the device. This is a stress rating only and device functional operation at or above the conditions indicated is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. Up to 9850 ft. Absolute Maximum DC Ratings Symbol VDD VDDQ VIN, VOUT TSTG Parameter Rating Units Note Voltage on VDD pins relative to Vss -0.4 V ~ 1.975 V V 1, 3 Voltage on VDDQ pins relative to Vss -0.4 V ~ 1.975 V V 1, 3 Voltage on I/O pins relative to Vss -0.4 V ~ 1.975 V V 1 -55 to +100 C 1, 2 Storage Temperature Note: 1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability 2. Storage Temperature is the case surface temperature on the center/top side of the DRAM. 3. VDD and VDDQ must be within 300 mV of each other at all times;and VREF must be not greater Operating temperature Conditions Symbol TOPER Rating Units Note Normal Operating Temperature Range Parameter 0 to 85 C 1, 2 Extended Temperature Range (Optional) 85 to 95 C 1, 3 Note: 1. Operating Temperature TOPER is the case surface temperature on the center / top side of the DRAM. 2. The Normal Temperature Range specifies the temperatures where all DRAM specifications will be supported. During operation, the DRAM case temperature must be maintained between 0 to 85 C under all operating conditions 3. Some applications require operation of the DRAM in the Extended Temperature Range between 85 C and 95 C case temperature. Full specifications are supported in this range, but the following additional conditions apply: a) Refresh commands must be doubled in frequency, therefore reducing the Refresh interval tREFI to 3.9 s. It is also possible to specify a component with 1X refresh (tREFI to 7.8s) in the Extended Temperature Range. Please refer to supplier data sheet and/or the DIMM SPD for option availability. b) If Self-Refresh operation is required in the Extended Temperature Range, then it is mandatory to either use the Manual Self-Refresh mode with Extended Temperature Range capability (MR2 A6 = 0b and MR2 A7 = 1b) or enable the optional Auto Self-Refresh mode (MR2 A6 = 1b and MR2 A7 = 0b). Please refer to the supplier data sheet and/or the DIMM SPD for Auto Self-Refresh option availability, Extended Temperature Range support and tREFI requirements in the Extended Temperature Range. REV 1.1 10/2011 15 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. NT2GC72B89G0NL(K)/NT2GC72C89G0NL(K) NT4GC72B4PG0NL(K)/NT4GC72C4PG0NL(K)/NT4GC72B8PG0NL(K)/NT4GC72C8PG0NL(K) NT8GC72B4NG0NL(K)/NT8GC72C4NG0NL(K) 2GB: 256M x 72 / 4GB: 512M x 72 / 8GB: 1G x 72 PC3-10600 / PC3(L)-12800 / PC3-14900 Registered DDR3 SDRAM DIMM DC Electrical Characteristics and Operating Conditions Symbol VDD VDDQ VDD VDDQ Parameter Min Type Max Units Notes Supply Voltage 1.425 1.5 1.575 V 1,2 Output Supply Voltage 1.425 1.5 1.575 V 1,2 Supply Voltage 1.28 1.35 1.45 V DDR3L Output Supply Voltage 1.28 1.35 1.45 V DDR3L Note: 1. Under all conditions VDDQ must be less than or equal to VDD. 2. VDDQ tracks with VDD. AC parameters are measured with VDD and VDDQ tied together. Single-Ended AC and DC Input Levels for Command and Address DDR3-1066 (-BE) DDR3-1333 (-CG) Min. Max. Min. Vref + 0.100 VDD VSS Vref - 0.100 Vref + 0.175 Note 2 Note 2 Vref - 0.175 VIH.CA(AC150) AC Input Logic High Vref + 0.15 VIL.CA(AC150) AC Input Logic Low Symbol Parameter VIH.CA(DC) DC Input Logic High VIL.CA(DC) DC Input Logic Low VIH.CA(AC) AC Input Logic High VIL.CA(AC) AC Input Logic Low VRefCA(DC) Reference Voltage for ADD, CMD Inputs DDR3-1600(-DI) Units Note VDD V 1 Vref - 0.100 V 1 Note 2 V 1, 2 Vref - 0.175 V 1, 2 Note 2 V 1, 2 Note 2 Vref - 0.15 V 1, 2 0.49 x VDD 0.51 x VDD V 3, 4 Max. Min. Max. Vref + 0.100 VDD Vref + 0.100 VSS Vref - 0.100 VSS Vref + 0.175 Note 2 Vref + 0.175 Note 2 Vref - 0.175 Note 2 Note 2 Vref + 0.15 Note 2 Vref + 0.15 Note 2 Vref - 0.15 Note 2 Vref - 0.15 0.49 x VDD 0.51 x VDD 0.49 x VDD 0.51 x VDD Note: 1. For input only pins except RESET#. Vref = VrefCA(DC). 2. See "Overshoot and Undershoot Specifications" in the device datasheet. 3. The ac peak noise on VRef may not allow VRef to deviate from VRefDQ(DC) by more than +/-1% VDD (for reference: approx. +/- 15 mV). 4. For reference: approx. VDD/2 +/- 15 mV. DDR3L-1066 (BE) DDR3L-1333 (CG) Min. Max. Min. Max. Min. Max. Vref + 0.09 VDD Vref + 0.09 VDD Vref + 0.09 VIL.CA(DC90) DC Input Logic Low VSS Vref - 0.09 VSS Vref - 0.09 VIH.CA(AC160) AC Input Logic High Vref + 0.160 Note 2 Vref + 0.160 Note 2 Symbol Parameter VIH.CA(DC90) DC Input Logic High DDR3L-1600(DI) Units Note VDD V 1 VSS Vref - 0.09 V 1 Vref + 0.160 Note 2 V 1, 2 VIL.CA(AC160) AC Input Logic Low Note 2 Vref - 0.160 Note 2 Vref - 0.160 Note 2 Vref - 0.160 V 1, 2 VIH.CA(AC135) AC Input Logic High Vref + 0.135 Note 2 Vref + 0.135 Note 2 Vref + 0.135 Note 2 V 1, 2 VIL.CA(AC135) AC Input Logic Low Note 2 Vref - 0.135 Note 2 Vref - 0.135 Note 2 Vref - 0.135 V 1, 2 0.49 x VDD 0.51 x VDD 0.49 x VDD 0.51 x VDD 0.49 x VDD 0.51 x VDD V 3, 4 VRefCA(DC) Reference Voltage for ADD, CMD Inputs Note: 1 For input only pins except RESET#. Vref = VrefCA(DC). 2 See JESD79-3E, 9.6 "Overshoot and Undershoot Specifications", 9.6.1. 3 The AC peak noise on VRef may not allow VRef to deviate from VRefDQ(DC) by more than +/-1% VDD (for reference: approx. +/- 13.5 mV). 4 For reference: approx. VDD/2 +/- 13.5 mV 5 These levels apply for 1.35 Volt (see Table 23) operation only. If the device is operated at 1.5 V (see Table 24), the respective levels in JESD79-3 (VIH/L.CA(DC100), VIH/L.CA(AC175), VIH/L.CA(AC150), etc.) apply. The 1.5 V levels (VIH/L.CA(DC100), VIH/L.CA(AC175), VIH/L.CA(AC150), etc.) do not apply when the device is operated in the 1.35 voltage range. REV 1.1 10/2011 16 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. NT2GC72B89G0NL(K)/NT2GC72C89G0NL(K) NT4GC72B4PG0NL(K)/NT4GC72C4PG0NL(K)/NT4GC72B8PG0NL(K)/NT4GC72C8PG0NL(K) NT8GC72B4NG0NL(K)/NT8GC72C4NG0NL(K) 2GB: 256M x 72 / 4GB: 512M x 72 / 8GB: 1G x 72 PC3-10600 / PC3(L)-12800 / PC3-14900 Registered DDR3 SDRAM DIMM Single-Ended AC and DC Input Levels for DQ and DM Symbol Parameter DDR3-1066 (BE) DDR3-1333 (CG) DDR3-1600 (DI) Min. Max. Min. DDR3-1866 (EK) Max. Min. Units Note Max. VIH.DQ(DC100) DC Input Logic High Vref + 0.100 VDD Vref + 0.100 VDD Vref + 0.100 VDD V 1,5 VIL.DQ(DC100) DC Input Logic Low VSS Vref - 0.100 VSS Vref - 0.100 VSS Vref - 0.100 V 1,6 VIH.DQ(AC175) AC Input Logic High Vref + 0.175 Note 2 - - - - V 1, 2, 7 VIL.DQ(AC175) AC Input Logic Low Note 2 Vref - 0.175 - - - - V 1, 2, 8 VIH.DQ(AC150) AC Input Logic High Vref + 0.15 Note 2 Vref + 0.15 Note 2 - - V 1, 2, 7 VIL.DQ(AC150) AC Input Logic Low Note 2 Vref - 0.15 Note 2 Vref - 0.15 - - V 1, 2, 8 VIH.DQ(AC135) AC Input Logic High - - - - Vref + 0.135 Note 2 V 1, 2, 7 VIL.DQ(AC135) AC Input Logic Low - - - - Note 2 Vref - 0.135 V 1, 2, 8 0.49 x VDD 0.51 x VDD 0.49 x VDD 0.51 x VDD 0.49 x VDD 0.51 x VDD V 3, 4 VRefDQ(DC) Reference Voltage for DQ, DM Inputs Note: 1. Vref = VrefDQ(DC). 2. See 9.6 "Overshoot and Undershoot Specifications" on page 126. 3. The ac peak noise on VRef may not allow VRef to deviate from VRefDQ(DC) by more than +/-1% VDD (for reference: approx. +/- 15 mV). 4. For reference: approx. VDD/2 +/- 15 mV. 5. VIH(dc) is used as a simplified symbol for VIH.DQ(DC100) 6. VIL(dc) is used as a simplified symbol for VIL.DQ(DC100) 7. VIH(ac) is used as a simplified symbol for VIH.DQ(AC175), VIH.DQ(AC150), and VIH.DQ(AC135); VIH.DQ(AC175) value is used when Vref + 0.175V is referenced, VIH.DQ(AC150) value is used when Vref + 0.150V is referenced, and VIH.DQ(AC135) value is used when Vref + 0.135V is referenced. 8. VIL(ac) is used as a simplified symbol for VIL.DQ(AC175), VIL.DQ(AC150), and VIL.DQ(AC135); VIL.DQ(AC175) value is used when Vref - 0.175V is referenced, VIL.DQ(AC150) value is used when Vref -0.150V is referenced, and VIL.DQ(AC135) value is used when Vref 0.135V is referenced. Symbol Parameter VIH.DQ(DC90) DC Input Logic High DDR3L-1066 (BE) DDR3L-1333 (CG) DDR3L-1600 (DI) Units Note VDD V 1 Min. Max. Min. Max. Vref + 0.09 VDD Vref + 0.09 VIL.DQ(DC90) DC Input Logic Low VSS Vref - 0.09 VSS Vref - 0.09 V 1 VIH.DQ(AC160) AC Input Logic High Vref + 0.160 Note 2 - - V 1, 2, 5 VIL.DQ(AC160) AC Input Logic Low Note 2 Vref - 0.160 - - V 1, 2, 5 VIH.DQ(AC135) AC Input Logic High Vref + 0.135 Note2 Vref + 0.135 Note2 V 1, 2, 5 VIL.DQ(AC135) AC Input Logic Low Note2 Vref - 0.135 Note2 Vref - 0.135 V 1, 2, 5 0.49 x VDD 0.51 x VDD 0.49 x VDD 0.51 x VDD V 3, 4 VRefDQ(DC) Reference Voltage for DQ, DM Inputs Note: 1 For input only pins except RESET#. Vref = VrefDQ(DC). 2 See JESD79-3E, 9.6 "Overshoot and Undershoot Specifications", 9.6.2. 3 The AC peak noise on VRef may not allow VRef to deviate from VRefDQ(DC) by more than +/-1% VDD (for reference: approx. +/- 13.5 mV). 4 For reference: approx. VDD/2 +/- 13.5 mV. 5 These levels apply for 1.35 Volt (see Table 23) operation only. If the device is operated at 1.5 V (see Table 24), the respective levels in JESD79-3 ( VIH/L.DQ(DC100), VIH/L.DQ(AC175), VIH/L.DQ(AC150), etc. ) apply. The 1.5 V levels (VIH/L.DQ(DC100), VIH/L.DQ(AC175), VIH/L.DQ(AC150), etc. ) do not apply when the device is operated in the 1.35 voltage range. REV 1.1 10/2011 17 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. NT2GC72B89G0NL(K)/NT2GC72C89G0NL(K) NT4GC72B4PG0NL(K)/NT4GC72C4PG0NL(K)/NT4GC72B8PG0NL(K)/NT4GC72C8PG0NL(K) NT8GC72B4NG0NL(K)/NT8GC72C4NG0NL(K) 2GB: 256M x 72 / 4GB: 512M x 72 / 8GB: 1G x 72 PC3-10600 / PC3(L)-12800 / PC3-14900 Registered DDR3 SDRAM DIMM Operating, Standby, and Refresh Currents TCASE = 0 C ~ 85 C; VDDQ = VDD = 1.5V 0.075V [2GB - 1 Rank, 256Mx8 DDR3 SDRAMs] Symbol IDD0 IDD1 IDD2P0 IDD2P1 IDD2Q IDD2N IDD3P IDD3N IDD4R IDD4W IDD5B IDD6 IDD7 PC3-10600 (-CG) 644 743 119 317 347 376 446 495 1386 1287 1881 119 2228 Parameter/Condition Operating One Bank Active-Precharge Current Operating One Bank Active-Read-Precharge Current Precharge Power-Down Current Slow Exit Precharge Power-Down Current Fast Exit Precharge Quiet Standby Current Precharge Standby Current Active Power-Down Current Active Standby Current Operating Burst Read Current Operating Burst Write Current Burst Refresh Current Self Refresh Current: Normal Temperature Range Operating Bank Interleave Read Current PC3-12800 (-DI) 693 792 119 366 396 426 495 545 1535 1436 1881 119 2376 Unit mA mA mA mA mA mA mA mA mA mA mA mA mA TCASE = 0 C ~ 85 C; VDDQ = VDD = 1.35V -0.0675/+0.1V [2GB - 1 Rank, 256Mx8 DDR3 SDRAMs] Symbol IDD0 IDD1 IDD2P0 IDD2P1 IDD2Q IDD2N IDD3P IDD3N IDD4R IDD4W IDD5B IDD6 IDD7 REV 1.1 10/2011 PC3-10600 (-CG) 545 693 119 277 297 347 416 465 1238 1089 1832 119 2030 Parameter/Condition Operating One Bank Active-Precharge Current Operating One Bank Active-Read-Precharge Current Precharge Power-Down Current Slow Exit Precharge Power-Down Current Fast Exit Precharge Quiet Standby Current Precharge Standby Current Active Power-Down Current Active Standby Current Operating Burst Read Current Operating Burst Write Current Burst Refresh Current Self Refresh Current: Normal Temperature Range Operating Bank Interleave Read Current PC3-12800 (-DI) Unit mA mA mA mA mA mA mA mA mA mA mA mA mA 18 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. NT2GC72B89G0NL(K)/NT2GC72C89G0NL(K) NT4GC72B4PG0NL(K)/NT4GC72C4PG0NL(K)/NT4GC72B8PG0NL(K)/NT4GC72C8PG0NL(K) NT8GC72B4NG0NL(K)/NT8GC72C4NG0NL(K) 2GB: 256M x 72 / 4GB: 512M x 72 / 8GB: 1G x 72 PC3-10600 / PC3(L)-12800 / PC3-14900 Registered DDR3 SDRAM DIMM TCASE = 0 C ~ 85 C; VDDQ = VDD = 1.5V 0.075V [4GB - 2 Rank, 256Mx8 DDR3 SDRAMs] Symbol IDD0 IDD1 IDD2P0 IDD2P1 IDD2Q IDD2N IDD3P IDD3N IDD4R IDD4W IDD5B IDD6 IDD7 PC3-10600 (-CG) 1020 1119 238 634 693 752 891 871 1762 1663 2257 238 2604 PC3-12800 (-DI) 1119 1218 238 733 792 851 990 970 1960 1861 2307 238 2802 PC3-10600 (-CG) PC3-12800 (-DI) Parameter/Condition Operating One Bank Active-Precharge Current Operating One Bank Active-Read-Precharge Current Precharge Power-Down Current Slow Exit Precharge Power-Down Current Fast Exit Precharge Quiet Standby Current Precharge Standby Current Active Power-Down Current Active Standby Current Operating Burst Read Current Operating Burst Write Current Burst Refresh Current Self Refresh Current: Normal Temperature Range Operating Bank Interleave Read Current Unit mA mA mA mA mA mA mA mA mA mA mA mA mA TCASE = 0 C ~ 85 C; VDDQ = VDD = 1.35V -0.0675/+0.1V [4GB - 2 Rank, 256Mx8 DDR3 SDRAMs] Symbol IDD0 IDD1 IDD2P0 IDD2P1 IDD2Q IDD2N IDD3P IDD3N IDD4R IDD4W IDD5B IDD6 IDD7 REV 1.1 10/2011 Parameter/Condition Operating One Bank Active-Precharge Current Operating One Bank Active-Read-Precharge Current Precharge Power-Down Current Slow Exit Precharge Power-Down Current Fast Exit Precharge Quiet Standby Current Precharge Standby Current Active Power-Down Current Active Standby Current Operating Burst Read Current Operating Burst Write Current Burst Refresh Current Self Refresh Current: Normal Temperature Range Operating Bank Interleave Read Current 891 1040 238 554 594 693 832 812 1584 1436 2178 238 2376 Unit mA mA mA mA mA mA mA mA mA mA mA mA mA 19 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. NT2GC72B89G0NL(K)/NT2GC72C89G0NL(K) NT4GC72B4PG0NL(K)/NT4GC72C4PG0NL(K)/NT4GC72B8PG0NL(K)/NT4GC72C8PG0NL(K) NT8GC72B4NG0NL(K)/NT8GC72C4NG0NL(K) 2GB: 256M x 72 / 4GB: 512M x 72 / 8GB: 1G x 72 PC3-10600 / PC3(L)-12800 / PC3-14900 Registered DDR3 SDRAM DIMM TCASE = 0 C ~ 85 C; VDDQ = VDD = 1.5V 0.075V [4GB - 1 Rank, 512Mx4 DDR3 SDRAMs] Symbol Parameter/Condition IDD0 IDD1 IDD2P0 IDD2P1 IDD2Q IDD2N IDD3P IDD3N IDD4R IDD4W IDD5B IDD6 IDD7 Operating One Bank Active-Precharge Current Operating One Bank Active-Read-Precharge Current Precharge Power-Down Current Slow Exit Precharge Power-Down Current Fast Exit Precharge Quiet Standby Current Precharge Standby Current Active Power-Down Current Active Standby Current Operating Burst Read Current Operating Burst Write Current Burst Refresh Current Self Refresh Current: Normal Temperature Range Operating Bank Interleave Read Current PC3-10600 (-CG) 1287 743 238 634 693 752 891 990 2475 2277 3762 238 4455 PC3-12800 (-DI) 1386 792 238 733 792 851 990 1089 2772 2574 3762 238 4752 PC3-14900 (-EK) Unit mA mA mA mA mA mA mA mA mA mA mA mA mA TCASE = 0 C ~ 85 C; VDDQ = VDD = 1.35V -0.0675/+0.1V [4GB - 1 Rank, 512Mx4 DDR3 SDRAMs] Symbol IDD0 IDD1 IDD2P0 IDD2P1 IDD2Q IDD2N IDD3P IDD3N IDD4R IDD4W IDD5B IDD6 IDD7 REV 1.1 10/2011 PC3-10600 (-CG) 1089 693 238 554 594 693 832 931 2178 1980 3663 238 4059 Parameter/Condition Operating One Bank Active-Precharge Current Operating One Bank Active-Read-Precharge Current Precharge Power-Down Current Slow Exit Precharge Power-Down Current Fast Exit Precharge Quiet Standby Current Precharge Standby Current Active Power-Down Current Active Standby Current Operating Burst Read Current Operating Burst Write Current Burst Refresh Current Self Refresh Current: Normal Temperature Range Operating Bank Interleave Read Current PC3-12800 (-DI) Unit mA mA mA mA mA mA mA mA mA mA mA mA mA 20 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. NT2GC72B89G0NL(K)/NT2GC72C89G0NL(K) NT4GC72B4PG0NL(K)/NT4GC72C4PG0NL(K)/NT4GC72B8PG0NL(K)/NT4GC72C8PG0NL(K) NT8GC72B4NG0NL(K)/NT8GC72C4NG0NL(K) 2GB: 256M x 72 / 4GB: 512M x 72 / 8GB: 1G x 72 PC3-10600 / PC3(L)-12800 / PC3-14900 Registered DDR3 SDRAM DIMM TCASE = 0 C ~ 85 C; VDDQ = VDD = 1.5V 0.075V [8GB - 2 Rank, 512Mx4 DDR3 SDRAMs] Symbol Parameter/Condition IDD0 IDD1 IDD2P0 IDD2P1 IDD2Q IDD2N IDD3P IDD3N IDD4R IDD4W IDD5B IDD6 IDD7 Operating One Bank Active-Precharge Current Operating One Bank Active-Read-Precharge Current Precharge Power-Down Current Slow Exit Precharge Power-Down Current Fast Exit Precharge Quiet Standby Current Precharge Standby Current Active Power-Down Current Active Standby Current Operating Burst Read Current Operating Burst Write Current Burst Refresh Current Self Refresh Current: Normal Temperature Range Operating Bank Interleave Read Current PC3-10600 (-CG) 2039 2237 475 1267 1386 1505 1782 1742 3227 3029 4514 475 5207 PC3-12800 (-DI) 2237 2435 475 1465 1584 1703 1980 1940 3623 3425 4613 475 5603 PC3-14900 (-EK) Unit mA mA mA mA mA mA mA mA mA mA mA mA mA TCASE = 0 C ~ 85 C; VDDQ = VDD = 1.35V -0.0675/+0.1V [8GB - 2 Rank, 512Mx4 DDR3 SDRAMs] Symbol IDD0 IDD1 IDD2P0 IDD2P1 IDD2Q IDD2N IDD3P IDD3N IDD4R IDD4W IDD5B IDD6 IDD7 REV 1.1 10/2011 PC3-10600 (-CG) 1782 2079 475 1109 1188 1386 1663 1624 2871 2673 4356 475 4752 Parameter/Condition Operating One Bank Active-Precharge Current Operating One Bank Active-Read-Precharge Current Precharge Power-Down Current Slow Exit Precharge Power-Down Current Fast Exit Precharge Quiet Standby Current Precharge Standby Current Active Power-Down Current Active Standby Current Operating Burst Read Current Operating Burst Write Current Burst Refresh Current Self Refresh Current: Normal Temperature Range Operating Bank Interleave Read Current PC3-12800 (-DI) Unit mA mA mA mA mA mA mA mA mA mA mA mA mA 21 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. NT2GC72B89G0NL(K)/NT2GC72C89G0NL(K) NT4GC72B4PG0NL(K)/NT4GC72C4PG0NL(K)/NT4GC72B8PG0NL(K)/NT4GC72C8PG0NL(K) NT8GC72B4NG0NL(K)/NT8GC72C4NG0NL(K) 2GB: 256M x 72 / 4GB: 512M x 72 / 8GB: 1G x 72 PC3-10600 / PC3(L)-12800 / PC3-14900 Registered DDR3 SDRAM DIMM Standard Speed Bins DDR3-1066MHz Speed Bin CL-nRCD-nRP Parameter Internal read command to first data ACT to internal read or write delay time PRE command period ACT to ACT or REF command period ACT to PRE command period CWL=5 CL=5 CWL=6 CWL=5 CL=6 CWL=6 CWL=5 CL=7 CWL=6 CWL=5 CL=8 CWL=6 Supported CL Settings Supported CWL Settings DDR3-1066 7-7-7 (-BE) Min 13.125 13.125 13.125 50.625 37.500 3.000 Reserved 2.500 Reserved Reserved 1.875 Reserved 1.875 5,6,7,8 5,6 Symbol tAA tRCD tRP tRC tRAS tCK(AVG) tCK(AVG) tCK(AVG) tCK(AVG) tCK(AVG) tCK(AVG) tCK(AVG) tCK(AVG) Unit Max 20.000 9*tREFI 3.300 3.300 <2.5 <2.5 ns ns ns ns ns ns ns ns ns ns ns ns ns nCK nCK DDR3-1333MHz Speed Bin CL-nRCD-nRP Parameter Symbol Internal read command to first data tAA ACT to internal read or write delay time tRCD PRE command period tRP ACT to ACT or REF command period tRC ACT to PRE command period CWL=5 CL=5 CWL=6 CWL=7 CWL=5 CL=6 CWL=6 CWL=7 CWL=5 CL=7 CWL=6 CWL=7 CWL=5 CL=8 CWL=6 CWL=7 CWL=5 CL=9 CWL=6 CWL=7 CWL=5 CL=10 CWL=6 CWL=7 Supported CL Settings Supported CWL Settings tRAS tCK(AVG) tCK(AVG) tCK(AVG) tCK(AVG) tCK(AVG) tCK(AVG) tCK(AVG) tCK(AVG) tCK(AVG) tCK(AVG) tCK(AVG) tCK(AVG) tCK(AVG) tCK(AVG) tCK(AVG) tCK(AVG) tCK(AVG) tCK(AVG) REV 1.1 10/2011 DDR3-1333 9-9-9 (-CG) Min 13. 5 (13.125)5,11 13. 5 (13.125)5,11 13. 5 (13.125)5,11 49.5 (49.125)5,11 36.000 3.0 Reserved Reserved 2.500 Reserved Reserved Reserved 1.875* Reserved Reserved 1.875 Reserved Reserved Reserved 1.500 Reserved Reserved 1.500* 5,6,8,(7),9,(10) 5,6,7 Unit Max 20.000 ns - ns - ns - ns 9*tREFI 3.3 Reserved Reserved 3.300 Reserved Reserved Reserved <2.5* Reserved Reserved <2.5 Reserved Reserved Reserved <1.875 Reserved Reserved <1.875* ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns nCK nCK 22 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. NT2GC72B89G0NL(K)/NT2GC72C89G0NL(K) NT4GC72B4PG0NL(K)/NT4GC72C4PG0NL(K)/NT4GC72B8PG0NL(K)/NT4GC72C8PG0NL(K) NT8GC72B4NG0NL(K)/NT8GC72C4NG0NL(K) 2GB: 256M x 72 / 4GB: 512M x 72 / 8GB: 1G x 72 PC3-10600 / PC3(L)-12800 / PC3-14900 Registered DDR3 SDRAM DIMM DDR3-1600MHz Speed Bin CL-nRCD-nRP Parameter Symbol Internal read command to first data tAA ACT to internal read or write delay time tRCD PRE command period tRP ACT to ACT or REF command period tRC ACT to PRE command period CWL=5 CL=5 CWL=6 CWL=7 CWL=5 CL=6 CWL=6 CWL=7 CWL=5 CL=7 CWL=6 CWL=7 CWL=5 CL=8 CWL=6 CWL=7 CWL=5 CL=9 CWL=6 CWL=7 CWL=5 CL=10 CWL=6 CWL=7 CWL=5 CWL=6 CL=11 CWL=7 CWL=8 Supported CL Settings Supported CWL Settings *: Optional tRAS tCK(AVG) tCK(AVG) tCK(AVG) tCK(AVG) tCK(AVG) tCK(AVG) tCK(AVG) tCK(AVG) tCK(AVG) tCK(AVG) tCK(AVG) tCK(AVG) tCK(AVG) tCK(AVG) tCK(AVG) tCK(AVG) tCK(AVG) tCK(AVG) tCK(AVG) tCK(AVG) tCK(AVG) tCK(AVG) REV 1.1 10/2011 DDR3-1600 11-11-11 (-DI) Min Max 13.75 20.000 (13.125)5,11 13.75 (13.125)5,11 13.75 (13.125)5,11 48.75 (48.125)5,11 35.000 9*tREFI 3.000 3.300 Reserved Reserved Reserved Reserved 2.500 3.300 Reserved Reserved Reserved Reserved Reserved Reserved 1.875* <2.5* Reserved Reserved Reserved Reserved 1.875 <2.5 Reserved Reserved Reserved Reserved Reserved Reserved 1.500 <1.875 Reserved Reserved Reserved Reserved 1.500* <1.875* Reserved Reserved Reserved Reserved Reserved Reserved 1.25* <1.5* 5,6,(7),8,(9),10,11 5,6,7,8 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns nCK nCK 23 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. NT2GC72B89G0NL(K)/NT2GC72C89G0NL(K) NT4GC72B4PG0NL(K)/NT4GC72C4PG0NL(K)/NT4GC72B8PG0NL(K)/NT4GC72C8PG0NL(K) NT8GC72B4NG0NL(K)/NT8GC72C4NG0NL(K) 2GB: 256M x 72 / 4GB: 512M x 72 / 8GB: 1G x 72 PC3-10600 / PC3(L)-12800 / PC3-14900 Registered DDR3 SDRAM DIMM DDR3-1866MHz Speed Bin CL-nRCD-nRP Parameter Symbol Internal read command to first data tAA ACT to internal read or write delay time tRCD PRE command period tRP ACT to ACT or REF command period tRC ACT to PRE command period CWL=5 CL=5 CWL=6, 7, 8, 9 CWL=5 CL=6 CWL=6 CWL=7, 8, 9 CWL=5 CL=7 CWL=6 CWL=7, 8, 9 CWL=5 CL=8 CWL=6 CWL=7, 8, 9 CWL=5 CL=9 CWL=6 CWL=7, 8, 9 CWL=5, 6 CL=10 CWL=7 CWL=8 CWL=5, 6, 7 CL=11 CWL=8 CWL=9 CWL=5, 6, 7, 8 CL=12 CWL=9 CWL=5, 6, 7, 8 CL=13 CWL=9 Supported CL Settings Supported CWL Settings *: Optional tRAS tCK(AVG) tCK(AVG) tCK(AVG) tCK(AVG) tCK(AVG) tCK(AVG) tCK(AVG) tCK(AVG) tCK(AVG) tCK(AVG) tCK(AVG) tCK(AVG) tCK(AVG) tCK(AVG) tCK(AVG) tCK(AVG) tCK(AVG) tCK(AVG) tCK(AVG) tCK(AVG) tCK(AVG) tCK(AVG) tCK(AVG) tCK(AVG) REV 1.1 10/2011 DDR3-1866 13-13-13 (-EK) Min Max 13.91 20.000 (13.125) 13.91 (13.125) 13.91 (13.125) 47.91 (47.125) 34.000 9*tREFI Reserved Reserved Reserved Reserved 2.500 3.300 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved 1.875 <2.5 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved 1.500 <1.875 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved 1.07 <1.25* 6,(7), 8,(9), 10, (11),13 5,6,7,8, 9 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns nCK nCK 24 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. NT2GC72B89G0NL(K)/NT2GC72C89G0NL(K) NT4GC72B4PG0NL(K)/NT4GC72C4PG0NL(K)/NT4GC72B8PG0NL(K)/NT4GC72C8PG0NL(K) NT8GC72B4NG0NL(K)/NT8GC72C4NG0NL(K) 2GB: 256M x 72 / 4GB: 512M x 72 / 8GB: 1G x 72 PC3-10600 / PC3(L)-12800 / PC3-14900 Registered DDR3 SDRAM DIMM AC Timing Specifications for DDR3 SDRAM Devices Used on Module (1066MHz) Parameter DDR3-1066 Symbol Min. Max. 8 - Units Notes Clock Timing Minimum Clock Cycle Time (DLL off mode) tCK (DLL_OFF) Average Clock Period tCK(avg) Average high pulse width tCH(avg) 0.47 0.53 tCK(avg) Average low pulse width tCL(avg) 0.47 0.53 tCK(avg) Refer to "Standard Speed Bins) ns ps Min.: tCK(avg)min + tJIT(per)min Absolute Clock Period tCK(abs) Absolute clock HIGH pulse width tCH(abs) 0.43 - tCK(avg) Absolute clock LOW pulse width tCL(abs) 0.43 - tCK(avg) Clock Period Jitter JIT(per) -90 90 ps Clock Period Jitter during DLL locking period JIT(per, lck) -80 80 ps Cycle to Cycle Period Jitter tJIT(cc) 180 180 ps Cycle to Cycle Period Jitter during DLL locking period JIT(cc, lck) 160 160 ps Duty Cycle Jitter tJIT(duty) - - ps Cumulative error across 2 cycles tERR(2per) -132 132 ps Cumulative error across 3 cycles tERR(3per) -157 157 ps Cumulative error across 4 cycles tERR(4per) -175 175 ps Cumulative error across 5 cycles tERR(5per) -188 188 ps Cumulative error across 6 cycles tERR(6per) -200 200 ps Cumulative error across 7 cycles tERR(7per) -209 209 ps Cumulative error across 8 cycles tERR(8per) -217 217 ps Cumulative error across 9 cycles tERR(9per) -224 224 ps Cumulative error across 10 cycles tERR(10per) -231 231 ps Cumulative error across 11 cycles tERR(11per) -237 237 ps Cumulative error across 12 cycles tERR(12per) -242 242 ps Cumulative error across n = 13, 14 . . . 49, 50 cycles Max.: tCK(avg)max + tJIT(per)max tERR(nper)min = (1 + 0.68ln(n)) * tJIT(per)min tERR(nper) tERR(nper)max = (1 + 0.68ln(n)) * tJIT(per)max ps ps Data Timing DQS, DQS# to DQ skew, per group, per access tDQSQ - 150 DQ output hold time from DQS, DQS# tQH 0.38 - DQ low-impedance time from CK, CK# tLZ(DQ) -600 300 ps DQ high impedance time from CK, CK# tHZ(DQ) - 300 ps Data setup time to DQS, DQS# referenced to Vih(ac) / Vil(ac) levels tDS(base) ps tCK(avg) 25 ps 75 ps 100 ps tDIPW 490 ps DQS,DQS# differential READ Preamble tRPRE 0.9 Note 19 tCK(avg) DQS, DQS# differential READ Postamble tRPST 0.3 Note 11 tCK(avg) DQS, DQS# differential output high time tQSH 0.38 - tCK(avg) DQS, DQS# differential output low time tQSL 0.38 - tCK(avg) DQS, DQS# differential WRITE Preamble tWPRE 0.9 - tCK(avg) DQS, DQS# differential WRITE Postamble tWPST 0.3 - tCK(avg) DQS, DQS# rising edge output access time from rising CK, CK# tDQSCK -300 300 tCK(avg) tLZ(DQS) -600 300 tCK(avg) tHZ(DQS) - 300 tCK(avg) Data setup time to DQS, DQS# referenced to Vih(ac) / Vil(ac) levels Data hold time from DQS, DQS# referenced to Vih(dc) / Vil(dc) levels DQ and DM Input pulse width for each input AC175 tDS(base) AC150 tDH(base) DC100 Data Strobe Timing DQS and DQS# low-impedance time (Referenced from RL - 1) DQS and DQS# high-impedance time (Referenced from RL + BL/2) DQS, DQS# differential input low pulse width tDQSL 0.45 0.55 tCK(avg) DQS, DQS# differential input high pulse width tDQSH 0.45 0.55 tCK(avg) DQS, DQS# rising edge to CK, CK# rising edge tDQSS -0.25 0.25 tCK(avg) DQS, DQS# falling edge setup time to CK, CK# rising edge tDSS 0.2 - tCK(avg) DQS, DQS# falling edge hold time from CK, CK# rising edge tDSH 0.2 - tCK(avg) Command and Address Timing REV 1.1 10/2011 25 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. NT2GC72B89G0NL(K)/NT2GC72C89G0NL(K) NT4GC72B4PG0NL(K)/NT4GC72C4PG0NL(K)/NT4GC72B8PG0NL(K)/NT4GC72C8PG0NL(K) NT8GC72B4NG0NL(K)/NT8GC72C4NG0NL(K) 2GB: 256M x 72 / 4GB: 512M x 72 / 8GB: 1G x 72 PC3-10600 / PC3(L)-12800 / PC3-14900 Registered DDR3 SDRAM DIMM DLL locking time Internal READ Command to PRECHARGE Command delay Delay from start of internal write transaction to internal read command tDLLK 512 - nCK tRTPmin.: max(4nCK, 7.5ns) tRTP tRTPmax.: tWTRmin.: max(4nCK, 7.5ns) tWTR tWTRmax.: WRITE recovery time tWR 15 - ns Mode Register Set command cycle time tMRD 4 - nCK - nCK Mode Register Set command update delay tMOD ACT to internal read or write delay time tRCD PRE command period tRP ACT to ACT or REF command period tRC CAS# to CAS# command delay tCCD Auto precharge write recovery + precharge time tDAL(min) Multi-Purpose Register Recovery Time tMPRR ACTIVE to PRECHARGE command period tRAS ACTIVE to ACTIVE command period for 1KB page size tRRD tMODmin.: max(12nCK, 15ns) tMODmax.: 4 WR + roundup(tRP / tCK(avg)) nCK 1 - nCK Standard Speed Bins max(4nCK, 7.5ns) - tRRDmin.: max(4nCK, 10ns) ACTIVE to ACTIVE command period for 2KB page size tRRD Four activate window for 1KB page size tFAW 37.5 - ns Four activate window for 2KB page size tFAW 50 - ns tIS(base) 125 - ps tIH(base) 200 - ps 125+150 - ps tIPW 780 - ps Power-up and RESET calibration time tZQinit 512 - nCK Normal operation Full calibration time tZQoper 256 - nCK Normal operation Short calibration time tZQCS 64 - nCK Command and Address setup time to CK, CK# referenced to Vih(ac) / Vil(ac) levels Command and Address hold time from CK, CK# referenced to Vih(dc) / Vil(dc) levels Command and Address setup time to CK, CK# referenced to Vih(ac) / Vil(ac) levels Control and Address Input pulse width for each input tRRDmax.: tIS(base) AC150 Calibration Timing Reset Timing Exit Reset from CKE HIGH to a valid command tXPRmin.: max(5nCK, tRFC(min) + 10ns) tXPR tXPRmax.: - Self Refresh Timings Exit Self Refresh to commands not requiring a locked DLL Exit Self Refresh to commands requiring a locked DLL tXSDLL Minimum CKE low width for Self Refresh entry to exit timing tCKESR Valid Clock Requirement after Self Refresh Entry (SRE) or Power-Down Entry (PDE) Valid Clock Requirement before Self Refresh Exit (SRX) or Power-Down Exit (PDX) or Reset Exit tXSmin.: max(5nCK, tRFC(min) + 10ns) tXS tXSmax.: tXSDLLmin.: tDLLK(min) nCK tXSDLLmax.: tCKESRmin.: tCKE(min) + 1 nCK tCKESRmax.: tCKSREmin.: max(5 nCK, 10 ns) tCKSRE tCKSREmax.: tCKSRXmin.: max(5 nCK, 10 ns) tCKSRX tCKSRXmax.: - Power Down Timings Exit Power Down with DLL on to any valid command; Exit Precharge Power Down with DLL frozen to commands tXPmin.: max(3nCK, 7.5ns) tXP tXPmax.: - not requiring a locked DLL Exit Precharge Power Down with DLL frozen to commands requiring a locked DLL CKE minimum pulse width tCPDED Power Down Entry to Exit Timing tPD Timing of ACT command to Power Down entry tACTPDEN Timing of PRE or PREA command to Power Down entry tPRPDEN 10/2011 tXPDLLmax.: tCKEmin.: max(3nCK 5.625ns) tCKE Command pass disable delay REV 1.1 tXPDLLmin.: max(10nCK, 24ns) tXPDLL tCKEmax.: tCPDEDmin.: 1 tCPDEDmin.: - nCK tPDmin.: tCKE(min) tPDmax.: 9*tREFI tACTPDENmin.: 1 tACTPDENmax.: tPRPDENmin.: 1 nCK nCK 26 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. NT2GC72B89G0NL(K)/NT2GC72C89G0NL(K) NT4GC72B4PG0NL(K)/NT4GC72C4PG0NL(K)/NT4GC72B8PG0NL(K)/NT4GC72C8PG0NL(K) NT8GC72B4NG0NL(K)/NT8GC72C4NG0NL(K) 2GB: 256M x 72 / 4GB: 512M x 72 / 8GB: 1G x 72 PC3-10600 / PC3(L)-12800 / PC3-14900 Registered DDR3 SDRAM DIMM tPRPDENmax.: Timing of RD/RDA command to Power Down entry Timing of WR command to Power Down entry (BL8OTF, BL8MRS, BC4OTF) Timing of WRA command to Power Down entry (BL8OTF, BL8MRS, BC4OTF) Timing of WR command to Power Down entry (BC4MRS) Timing of WRA command to Power Down entry (BC4MRS) tRDPDENmin.: RL+4+1 tRDPDEN tWRPDENmin.: WL + 4 + (tWR / tCK(avg)) tWRPDEN tWRPDENmax.: tWRAPDENmin.: WL+4+WR+1 tWRAPDEN tWRPDEN tREFPDEN Timing of MRS command to Power Down entry tMRSPDEN nCK nCK tWRAPDENmax.: tWRPDENmin.: WL + 2 + (tWR / tCK(avg))tWRPDENmax.: tWRAPDENmin.: WL + 2 +WR + 1 tWRAPDEN Timing of REF command to Power Down entry nCK tRDPDENmax.: - tWRAPDENmax.: tREFPDENmin.: 1 nCK nCK nCK tREFPDENmax.: tMRSPDENmin.: tMOD(min) tMRSPDENmax.: - ODT Timings ODT high time without write command or with write command and BC4 ODT high time with Write command and BL8 Asynchronous RTT turn-on delay ODTH4min.: 4 ODTH4 nCK ODTH4max.: ODTH8min.: 6 ODTH8 nCK ODTH8max.: - tAONPD 2 8.5 ns tAOFPD 2 8.5 ns tAON -300 300 ps tAOF 0.3 0.7 tCK(avg) tADC 0.3 0.7 tCK(avg) tWLMRD 40 - nCK tWLDQSEN 25 - nCK tWLS 245 - ps tWLH 245 - ps Write leveling output delay tWLO 0 9 ns Write leveling output error tWLOE 0 2 ns (Power-Down with DLL frozen) Asynchronous RTT turn-off delay (Power-Down with DLL frozen) RTT turn-on RTT_Nom and RTT_WR turn-off time from ODTLoff reference RTT dynamic change skew Write Leveling Timings First DQS/DQS# rising edge after write leveling mode is programmed DQS/DQS# delay after write leveling mode is programmed Write leveling setup time from rising CK, CK# crossing to rising DQS, DQS# crossing Write leveling hold time from rising DQS, DQS# crossing to rising CK, CK# crossing REV 1.1 10/2011 27 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. NT2GC72B89G0NL(K)/NT2GC72C89G0NL(K) NT4GC72B4PG0NL(K)/NT4GC72C4PG0NL(K)/NT4GC72B8PG0NL(K)/NT4GC72C8PG0NL(K) NT8GC72B4NG0NL(K)/NT8GC72C4NG0NL(K) 2GB: 256M x 72 / 4GB: 512M x 72 / 8GB: 1G x 72 PC3-10600 / PC3(L)-12800 / PC3-14900 Registered DDR3 SDRAM DIMM AC Timing Specifications for DDR3 SDRAM Devices Used on Module (1333MHz) Parameter DDR3-1333 Symbol Min. Max. 8 - Units Notes Clock Timing Minimum Clock Cycle Time (DLL off mode) tCK (DLL_OFF) Average Clock Period tCK(avg) Average high pulse width tCH(avg) 0.47 0.53 tCK(avg) Average low pulse width tCL(avg) 0.47 0.53 tCK(avg) Refer to "Standard Speed Bins) ns ps Min.: tCK(avg)min + tJIT(per)min Absolute Clock Period tCK(abs) Absolute clock HIGH pulse width tCH(abs) 0.43 - tCK(avg) Absolute clock LOW pulse width tCL(abs) 0.43 - tCK(avg) Clock Period Jitter JIT(per) -80 80 ps Clock Period Jitter during DLL locking period JIT(per, lck) -70 70 ps Cycle to Cycle Period Jitter tJIT(cc) 160 160 ps Cycle to Cycle Period Jitter during DLL locking period JIT(cc, lck) 140 140 ps Duty Cycle Jitter tJIT(duty) - - ps Cumulative error across 2 cycles tERR(2per) -118 118 ps Cumulative error across 3 cycles tERR(3per) -140 140 ps Cumulative error across 4 cycles tERR(4per) -155 155 ps Cumulative error across 5 cycles tERR(5per) -168 168 ps Cumulative error across 6 cycles tERR(6per) -177 177 ps Cumulative error across 7 cycles tERR(7per) -186 186 ps Cumulative error across 8 cycles tERR(8per) -193 193 ps Cumulative error across 9 cycles tERR(9per) -200 200 ps Cumulative error across 10 cycles tERR(10per) -205 205 ps Cumulative error across 11 cycles tERR(11per) -210 210 ps Cumulative error across 12 cycles tERR(12per) -215 215 ps Cumulative error across n = 13, 14 . . . 49, 50 cycles Max.: tCK(avg)max + tJIT(per)max tERR(nper)min = (1 + 0.68ln(n)) * tJIT(per)min tERR(nper) tERR(nper)max = (1 + 0.68ln(n)) * tJIT(per)max ps ps Data Timing DQS, DQS# to DQ skew, per group, per access tDQSQ - 125 DQ output hold time from DQS, DQS# tQH 0.38 - DQ low-impedance time from CK, CK# tLZ(DQ) -500 250 ps DQ high impedance time from CK, CK# tHZ(DQ) - 250 ps Data setup time to DQS, DQS# referenced to Vih(ac) / Vil(ac) levels Data setup time to DQS, DQS# referenced to Vih(ac) / Vil(ac) levels Data hold time from DQS, DQS# referenced to Vih(dc) / Vil(dc) levels DQ and DM Input pulse width for each input tDS(base) AC175 tDS(base) AC150 tDH(base) DC100 ps tCK(avg) - ps 30 ps 65 ps tDIPW 400 - ps DQS,DQS# differential READ Preamble tRPRE 0.9 Note 19 tCK(avg) DQS, DQS# differential READ Postamble tRPST 0.3 Note 11 tCK(avg) DQS, DQS# differential output high time tQSH 0.4 - tCK(avg) DQS, DQS# differential output low time tQSL 0.4 - tCK(avg) DQS, DQS# differential WRITE Preamble tWPRE 0.9 - tCK(avg) DQS, DQS# differential WRITE Postamble tWPST 0.3 - tCK(avg) DQS, DQS# rising edge output access time from rising CK, CK# tDQSCK -255 255 tCK(avg) tLZ(DQS) -500 250 tCK(avg) tHZ(DQS) - 250 tCK(avg) Data Strobe Timing DQS and DQS# low-impedance time (Referenced from RL - 1) DQS and DQS# high-impedance time (Referenced from RL + BL/2) DQS, DQS# differential input low pulse width tDQSL 0.45 0.55 tCK(avg) DQS, DQS# differential input high pulse width tDQSH 0.45 0.55 tCK(avg) DQS, DQS# rising edge to CK, CK# rising edge tDQSS -0.25 0.25 tCK(avg) DQS, DQS# falling edge setup time to CK, CK# rising edge tDSS 0.2 - tCK(avg) DQS, DQS# falling edge hold time from CK, CK# rising edge tDSH 0.2 - tCK(avg) Command and Address Timing REV 1.1 10/2011 28 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. NT2GC72B89G0NL(K)/NT2GC72C89G0NL(K) NT4GC72B4PG0NL(K)/NT4GC72C4PG0NL(K)/NT4GC72B8PG0NL(K)/NT4GC72C8PG0NL(K) NT8GC72B4NG0NL(K)/NT8GC72C4NG0NL(K) 2GB: 256M x 72 / 4GB: 512M x 72 / 8GB: 1G x 72 PC3-10600 / PC3(L)-12800 / PC3-14900 Registered DDR3 SDRAM DIMM DLL locking time Internal READ Command to PRECHARGE Command delay Delay from start of internal write transaction to internal read command tDLLK 512 - nCK tRTPmin.: max(4nCK, 7.5ns) tRTP tRTPmax.: tWTRmin.: max(4nCK, 7.5ns) tWTR tWTRmax.: WRITE recovery time tWR 15 - ns Mode Register Set command cycle time tMRD 4 - nCK Mode Register Set command update delay tMOD ACT to internal read or write delay time tRCD PRE command period tRP ACT to ACT or REF command period tRC CAS# to CAS# command delay tCCD Auto precharge write recovery + precharge time tDAL(min) Multi-Purpose Register Recovery Time tMPRR ACTIVE to PRECHARGE command period tRAS ACTIVE to ACTIVE command period for 1KB page size tRRD tMODmin.: max(12nCK, 15ns) tMODmax.: 4 nCK WR + roundup(tRP / tCK(avg)) nCK 1 - nCK Standard Speed Bins tRRDmin.: max(4nCK, 6ns) tRRDmax.: tRRDmin.: max(4nCK, 7.5ns) ACTIVE to ACTIVE command period for 2KB page size tRRD Four activate window for 1KB page size tFAW 30 0 ns Four activate window for 2KB page size tFAW 45 0 ns tIS(base) 65 - ps tIH(base) 140 - ps 65+125 - ps tIPW 620 - ps Power-up and RESET calibration time tZQinit 512 - nCK Normal operation Full calibration time tZQoper 256 - nCK Normal operation Short calibration time tZQCS 64 - nCK Command and Address setup time to CK, CK# referenced to Vih(ac) / Vil(ac) levels Command and Address hold time from CK, CK# referenced to Vih(dc) / Vil(dc) levels Command and Address setup time to CK, CK# referenced to Vih(ac) / Vil(ac) levels Control and Address Input pulse width for each input tRRDmax.: tIS(base) AC150 Calibration Timing Reset Timing Exit Reset from CKE HIGH to a valid command tXPRmin.: max(5nCK, tRFC(min) + 10ns) tXPR tXPRmax.: - Self Refresh Timings Exit Self Refresh to commands not requiring a locked DLL Exit Self Refresh to commands requiring a locked DLL tXSDLL Minimum CKE low width for Self Refresh entry to exit timing tCKESR Valid Clock Requirement after Self Refresh Entry (SRE) or Power-Down Entry (PDE) Valid Clock Requirement before Self Refresh Exit (SRX) or Power-Down Exit (PDX) or Reset Exit tXSmin.: max(5nCK, tRFC(min) + 10ns) tXS tXSmax.: tXSDLLmin.: tDLLK(min) nCK tXSDLLmax.: tCKESRmin.: tCKE(min) + 1 nCK tCKESRmax.: tCKSREmin.: max(5 nCK, 10 ns) tCKSRE tCKSREmax.: tCKSRXmin.: max(5 nCK, 10 ns) tCKSRX tCKSRXmax.: - Power Down Timings Exit Power Down with DLL on to any valid command; tXPmin.: max(3nCK, 6ns) Exit Precharge Power Down with DLL frozen to commands tXP tXPmax.: - not requiring a locked DLL Exit Precharge Power Down with DLL frozen to commands requiring a locked DLL CKE minimum pulse width tCKE Command pass disable delay tCPDED Power Down Entry to Exit Timing tPD Timing of ACT command to Power Down entry REV 1.1 10/2011 tXPDLLmin.: max(10nCK, 24ns) tXPDLL tXPDLLmax.: tCKEmin.: max(3nCK ,5.625ns) tCKEmax.: tCPDEDmin.: 1 tCPDEDmin.: - nCK tPDmin.: tCKE(min) tPDmax.: 9*tREFI tACTPDENmin.: 1 tACTPDEN tACTPDENmax.: - nCK 29 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. NT2GC72B89G0NL(K)/NT2GC72C89G0NL(K) NT4GC72B4PG0NL(K)/NT4GC72C4PG0NL(K)/NT4GC72B8PG0NL(K)/NT4GC72C8PG0NL(K) NT8GC72B4NG0NL(K)/NT8GC72C4NG0NL(K) 2GB: 256M x 72 / 4GB: 512M x 72 / 8GB: 1G x 72 PC3-10600 / PC3(L)-12800 / PC3-14900 Registered DDR3 SDRAM DIMM Timing of PRE or PREA command to Power Down entry tPRPDEN Timing of RD/RDA command to Power Down entry tRDPDEN Timing of WR command to Power Down entry (BL8OTF, BL8MRS, BC4OTF) Timing of WRA command to Power Down entry (BL8OTF, BL8MRS, BC4OTF) Timing of WR command to Power Down entry (BC4MRS) Timing of WRA command to Power Down entry (BC4MRS) tPRPDENmin.: 1 tRDPDENmin.: RL+4+1 tWRPDENmin.: WL + 4 + (tWR / tCK(avg)) tWRPDENmax.: tWRAPDENmin.: WL+4+WR+1 tWRAPDEN tREFPDEN Timing of MRS command to Power Down entry tMRSPDEN nCK nCK tWRAPDENmax.: tWRPDENmin.: WL + 2 + (tWR / tCK(avg))tWRPDENmax.: tWRAPDENmin.: WL + 2 +WR + 1 tWRAPDEN Timing of REF command to Power Down entry nCK tRDPDENmax.: - tWRPDEN tWRPDEN nCK tPRPDENmax.: - tWRAPDENmax.: tREFPDENmin.: 1 nCK nCK nCK tREFPDENmax.: tMRSPDENmin.: tMOD(min) tMRSPDENmax.: - ODT Timings ODT high time without write command or with write command and BC4 ODT high time with Write command and BL8 Asynchronous RTT turn-on delay ODTH4min.: 4 ODTH4 nCK ODTH4max.: ODTH8min.: 6 ODTH8 nCK ODTH8max.: - tAONPD 2 8.5 ns tAOFPD 2 8.5 ns tAON -250 250 ps tAOF 0.3 0.7 tCK(avg) tADC 0.3 0.7 tCK(avg) tWLMRD 40 - nCK tWLDQSEN 25 - nCK tWLS 195 - ps tWLH 195 - ps Write leveling output delay tWLO 0 9 ns Write leveling output error tWLOE 0 2 ns (Power-Down with DLL frozen) Asynchronous RTT turn-off delay (Power-Down with DLL frozen) RTT turn-on RTT_Nom and RTT_WR turn-off time from ODTLoff reference RTT dynamic change skew Write Leveling Timings First DQS/DQS# rising edge after write leveling mode is programmed DQS/DQS# delay after write leveling mode is programmed Write leveling setup time from rising CK, CK# crossing to rising DQS, DQS# crossing Write leveling hold time from rising DQS, DQS# crossing to rising CK, CK# crossing REV 1.1 10/2011 30 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. NT2GC72B89G0NL(K)/NT2GC72C89G0NL(K) NT4GC72B4PG0NL(K)/NT4GC72C4PG0NL(K)/NT4GC72B8PG0NL(K)/NT4GC72C8PG0NL(K) NT8GC72B4NG0NL(K)/NT8GC72C4NG0NL(K) 2GB: 256M x 72 / 4GB: 512M x 72 / 8GB: 1G x 72 PC3-10600 / PC3(L)-12800 / PC3-14900 Registered DDR3 SDRAM DIMM AC Timing Specifications for DDR3 SDRAM Devices Used on Module (1600MHz) Parameter DDR3-1600 Symbol Min. Max. 8 - Units Notes Clock Timing Minimum Clock Cycle Time (DLL off mode) tCK (DLL_OFF) Average Clock Period tCK(avg) Average high pulse width tCH(avg) 0.47 0.53 tCK(avg) Average low pulse width tCL(avg) 0.47 0.53 tCK(avg) Refer to "Standard Speed Bins) ns ps Min.: tCK(avg)min + tJIT(per)min Absolute Clock Period tCK(abs) Absolute clock HIGH pulse width tCH(abs) 0.43 - tCK(avg) Absolute clock LOW pulse width tCL(abs) 0.43 - tCK(avg) Clock Period Jitter JIT(per) -70 70 ps Clock Period Jitter during DLL locking period JIT(per, lck) -60 60 ps Cycle to Cycle Period Jitter tJIT(cc) 140 140 ps Cycle to Cycle Period Jitter during DLL locking period JIT(cc, lck) 120 120 ps Duty Cycle Jitter tJIT(duty) - - ps Cumulative error across 2 cycles tERR(2per) -103 103 ps Cumulative error across 3 cycles tERR(3per) -122 122 ps Cumulative error across 4 cycles tERR(4per) -136 136 ps Cumulative error across 5 cycles tERR(5per) -147 147 ps Cumulative error across 6 cycles tERR(6per) -155 155 ps Cumulative error across 7 cycles tERR(7per) -163 163 ps Cumulative error across 8 cycles tERR(8per) -169 169 ps Cumulative error across 9 cycles tERR(9per) -175 175 ps Cumulative error across 10 cycles tERR(10per) -180 180 ps Cumulative error across 11 cycles tERR(11per) -184 184 ps Cumulative error across 12 cycles tERR(12per) -188 188 ps Cumulative error across n = 13, 14 . . . 49, 50 cycles Max.: tCK(avg)max + tJIT(per)max tERR(nper)min = (1 + 0.68ln(n)) * tJIT(per)min tERR(nper) tERR(nper)max = (1 + 0.68ln(n)) * tJIT(per)max ps ps Data Timing DQS, DQS# to DQ skew, per group, per access tDQSQ - 100 DQ output hold time from DQS, DQS# tQH 0.38 - DQ low-impedance time from CK, CK# tLZ(DQ) -450 225 ps DQ high impedance time from CK, CK# tHZ(DQ) - 225 ps Data setup time to DQS, DQS# referenced to Vih(ac) / Vil(ac) levels Data setup time to DQS, DQS# referenced to Vih(ac) / Vil(ac) levels Data hold time from DQS, DQS# referenced to Vih(dc) / Vil(dc) levels DQ and DM Input pulse width for each input tDS(base) AC175 tDS(base) AC150 tDH(base) DC100 ps tCK(avg) - ps 10 ps 45 ps tDIPW 360 - ps DQS,DQS# differential READ Preamble tRPRE 0.9 Note 19 tCK(avg) DQS, DQS# differential READ Postamble tRPST 0.3 Note 11 tCK(avg) DQS, DQS# differential output high time tQSH 0.4 - tCK(avg) DQS, DQS# differential output low time tQSL 0.4 - tCK(avg) DQS, DQS# differential WRITE Preamble tWPRE 0.9 - tCK(avg) DQS, DQS# differential WRITE Postamble tWPST 0.3 - tCK(avg) DQS, DQS# rising edge output access time from rising CK, CK# tDQSCK -255 255 tCK(avg) tLZ(DQS) -450 225 tCK(avg) tHZ(DQS) - 225 tCK(avg) Data Strobe Timing DQS and DQS# low-impedance time (Referenced from RL - 1) DQS and DQS# high-impedance time (Referenced from RL + BL/2) DQS, DQS# differential input low pulse width tDQSL 0.45 0.55 tCK(avg) DQS, DQS# differential input high pulse width tDQSH 0.45 0.55 tCK(avg) DQS, DQS# rising edge to CK, CK# rising edge tDQSS -0.27 0.27 tCK(avg) DQS, DQS# falling edge setup time to CK, CK# rising edge tDSS 0.18 - tCK(avg) DQS, DQS# falling edge hold time from CK, CK# rising edge tDSH 0.18 - tCK(avg) Command and Address Timing REV 1.1 10/2011 31 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. NT2GC72B89G0NL(K)/NT2GC72C89G0NL(K) NT4GC72B4PG0NL(K)/NT4GC72C4PG0NL(K)/NT4GC72B8PG0NL(K)/NT4GC72C8PG0NL(K) NT8GC72B4NG0NL(K)/NT8GC72C4NG0NL(K) 2GB: 256M x 72 / 4GB: 512M x 72 / 8GB: 1G x 72 PC3-10600 / PC3(L)-12800 / PC3-14900 Registered DDR3 SDRAM DIMM DLL locking time Internal READ Command to PRECHARGE Command delay Delay from start of internal write transaction to internal read command tDLLK 512 - nCK tRTPmin.: max(4nCK, 7.5ns) tRTP tRTPmax.: tWTRmin.: max(4nCK, 7.5ns) tWTR tWTRmax.: WRITE recovery time tWR 15 - ns Mode Register Set command cycle time tMRD 4 - nCK Mode Register Set command update delay tMOD ACT to internal read or write delay time tRCD PRE command period tRP ACT to ACT or REF command period tRC CAS# to CAS# command delay tCCD Auto precharge write recovery + precharge time tDAL(min) Multi-Purpose Register Recovery Time tMPRR ACTIVE to PRECHARGE command period tRAS ACTIVE to ACTIVE command period for 1KB page size tRRD tMODmin.: max(12nCK, 15ns) tMODmax.: 4 nCK WR + roundup(tRP / tCK(avg)) nCK 1 - nCK Standard Speed Bins tRRDmin.: max(4nCK, 6ns) tRRDmax.: tRRDmin.: max(4nCK, 7.5ns) ACTIVE to ACTIVE command period for 2KB page size tRRD Four activate window for 1KB page size tFAW 30 - ns Four activate window for 2KB page size tFAW 40 - ns tIS(base) 45 - ps tIH(base) 120 - ps tIS(base) AC150 170 - ps tIPW 560 - ps Power-up and RESET calibration time tZQinit 512 - nCK Normal operation Full calibration time tZQoper 256 - nCK Normal operation Short calibration time tZQCS 64 - nCK Command and Address setup time to CK, CK# referenced to Vih(ac) / Vil(ac) levels Command and Address hold time from CK, CK# referenced to Vih(dc) / Vil(dc) levels Command and Address setup time to CK, CK# referenced to Vih(ac) / Vil(ac) levels Control and Address Input pulse width for each input tRRDmax.: Calibration Timing Reset Timing Exit Reset from CKE HIGH to a valid command tXPRmin.: max(5nCK, tRFC(min) + 10ns) tXPR tXPRmax.: - Self Refresh Timings Exit Self Refresh to commands not requiring a locked DLL Exit Self Refresh to commands requiring a locked DLL tXSDLL Minimum CKE low width for Self Refresh entry to exit timing tCKESR Valid Clock Requirement after Self Refresh Entry (SRE) or Power-Down Entry (PDE) Valid Clock Requirement before Self Refresh Exit (SRX) or Power-Down Exit (PDX) or Reset Exit tXSmin.: max(5nCK, tRFC(min) + 10ns) tXS tXSmax.: tXSDLLmin.: tDLLK(min) nCK tXSDLLmax.: tCKESRmin.: tCKE(min) + 1 nCK tCKESRmax.: tCKSREmin.: max(5 nCK, 10 ns) tCKSRE tCKSREmax.: tCKSRXmin.: max(5 nCK, 10 ns) tCKSRX tCKSRXmax.: - Power Down Timings Exit Power Down with DLL on to any valid command; tXPmin.: max(3nCK, 6ns) Exit Precharge Power Down with DLL frozen to commands tXP tXPmax.: - not requiring a locked DLL Exit Precharge Power Down with DLL frozen to commands requiring a locked DLL CKE minimum pulse width tCKE Command pass disable delay tCPDED Power Down Entry to Exit Timing tPD Timing of ACT command to Power Down entry REV 1.1 10/2011 tXPDLLmin.: max(10nCK, 24ns) tXPDLL tXPDLLmax.: tCKEmin.: max(3nCK ,5ns) tCKEmax.: tCPDEDmin.: 1 tCPDEDmin.: - nCK tPDmin.: tCKE(min) tPDmax.: 9*tREFI tACTPDENmin.: 1 tACTPDEN tACTPDENmax.: - nCK 32 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. NT2GC72B89G0NL(K)/NT2GC72C89G0NL(K) NT4GC72B4PG0NL(K)/NT4GC72C4PG0NL(K)/NT4GC72B8PG0NL(K)/NT4GC72C8PG0NL(K) NT8GC72B4NG0NL(K)/NT8GC72C4NG0NL(K) 2GB: 256M x 72 / 4GB: 512M x 72 / 8GB: 1G x 72 PC3-10600 / PC3(L)-12800 / PC3-14900 Registered DDR3 SDRAM DIMM Timing of PRE or PREA command to Power Down entry tPRPDEN Timing of RD/RDA command to Power Down entry tRDPDEN Timing of WR command to Power Down entry (BL8OTF, BL8MRS, BC4OTF) Timing of WRA command to Power Down entry (BL8OTF, BL8MRS, BC4OTF) Timing of WR command to Power Down entry (BC4MRS) Timing of WRA command to Power Down entry (BC4MRS) tPRPDENmin.: 1 tRDPDENmin.: RL+4+1 tWRPDENmin.: WL + 4 + (tWR / tCK(avg)) tWRPDENmax.: tWRAPDENmin.: WL+4+WR+1 tWRAPDEN tREFPDEN Timing of MRS command to Power Down entry tMRSPDEN nCK nCK tWRAPDENmax.: tWRPDENmin.: WL + 2 + (tWR / tCK(avg))tWRPDENmax.: tWRAPDENmin.: WL + 2 +WR + 1 tWRAPDEN Timing of REF command to Power Down entry nCK tRDPDENmax.: - tWRPDEN tWRPDEN nCK tPRPDENmax.: - tWRAPDENmax.: tREFPDENmin.: 1 nCK nCK nCK tREFPDENmax.: tMRSPDENmin.: tMOD(min) tMRSPDENmax.: - ODT Timings ODT high time without write command or with write command and BC4 ODT high time with Write command and BL8 Asynchronous RTT turn-on delay ODTH4min.: 4 ODTH4 nCK ODTH4max.: ODTH8min.: 6 ODTH8 nCK ODTH8max.: - tAONPD 2 8.5 ns tAOFPD 2 8.5 ns tAON -225 225 ps tAOF 0.3 0.7 tCK(avg) tADC 0.3 0.7 tCK(avg) tWLMRD 40 - nCK tWLDQSEN 25 - nCK tWLS 165 - ps tWLH 165 - ps Write leveling output delay tWLO 0 7.5 ns Write leveling output error tWLOE 0 2 ns (Power-Down with DLL frozen) Asynchronous RTT turn-off delay (Power-Down with DLL frozen) RTT turn-on RTT_Nom and RTT_WR turn-off time from ODTLoff reference RTT dynamic change skew Write Leveling Timings First DQS/DQS# rising edge after write leveling mode is programmed DQS/DQS# delay after write leveling mode is programmed Write leveling setup time from rising CK, CK# crossing to rising DQS, DQS# crossing Write leveling hold time from rising DQS, DQS# crossing to rising CK, CK# crossing REV 1.1 10/2011 33 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. NT2GC72B89G0NL(K)/NT2GC72C89G0NL(K) NT4GC72B4PG0NL(K)/NT4GC72C4PG0NL(K)/NT4GC72B8PG0NL(K)/NT4GC72C8PG0NL(K) NT8GC72B4NG0NL(K)/NT8GC72C4NG0NL(K) 2GB: 256M x 72 / 4GB: 512M x 72 / 8GB: 1G x 72 PC3-10600 / PC3(L)-12800 / PC3-14900 Registered DDR3 SDRAM DIMM AC Timing Specifications for DDR3 SDRAM Devices Used on Module (1866MHz) Parameter DDR3-1866 Symbol Min. Max. 8 - Units Notes Clock Timing Minimum Clock Cycle Time (DLL off mode) tCK (DLL_OFF) Average Clock Period tCK(avg) Average high pulse width tCH(avg) 0.47 0.53 tCK(avg) Average low pulse width tCL(avg) 0.47 0.53 tCK(avg) Refer to "Standard Speed Bins) ns ps Min.: tCK(avg)min + tJIT(per)min Absolute Clock Period tCK(abs) Absolute clock HIGH pulse width tCH(abs) 0.43 - tCK(avg) Absolute clock LOW pulse width tCL(abs) 0.43 - tCK(avg) Clock Period Jitter JIT(per) -60 60 ps Clock Period Jitter during DLL locking period JIT(per, lck) -50 50 ps Cycle to Cycle Period Jitter tJIT(cc) 120 120 ps Cycle to Cycle Period Jitter during DLL locking period JIT(cc, lck) 100 100 ps Duty Cycle Jitter tJIT(duty) - - ps Cumulative error across 2 cycles tERR(2per) -88 88 ps Cumulative error across 3 cycles tERR(3per) -105 105 ps Cumulative error across 4 cycles tERR(4per) -117 117 ps Cumulative error across 5 cycles tERR(5per) -126 126 ps Cumulative error across 6 cycles tERR(6per) -133 133 ps Cumulative error across 7 cycles tERR(7per) -139 139 ps Cumulative error across 8 cycles tERR(8per) -145 145 ps Cumulative error across 9 cycles tERR(9per) -150 150 ps Cumulative error across 10 cycles tERR(10per) -154 154 ps Cumulative error across 11 cycles tERR(11per) -158 158 ps Cumulative error across 12 cycles tERR(12per) -161 161 ps Cumulative error across n = 13, 14 . . . 49, 50 cycles Max.: tCK(avg)max + tJIT(per)max tERR(nper)min = (1 + 0.68ln(n)) * tJIT(per)min tERR(nper) tERR(nper)max = (1 + 0.68ln(n)) * tJIT(per)max ps ps Data Timing DQS, DQS# to DQ skew, per group, per access tDQSQ - 100 DQ output hold time from DQS, DQS# tQH 0.38 - DQ low-impedance time from CK, CK# tLZ(DQ) -390 195 ps DQ high impedance time from CK, CK# tHZ(DQ) - 195 ps Data setup time to DQS, DQS# referenced to Vih(ac) / Vil(ac) levels Data setup time to DQS, DQS# referenced to Vih(ac) / Vil(ac) levels Data hold time from DQS, DQS# referenced to Vih(dc) / Vil(dc) levels DQ and DM Input pulse width for each input tDS(base) AC175 tDS(base) AC150 tDH(base) DC100 ps tCK(avg) - ps - ps - ps tDIPW 320 - ps DQS,DQS# differential READ Preamble tRPRE 0.9 Note 19 tCK(avg) DQS, DQS# differential READ Postamble tRPST 0.3 Note 11 tCK(avg) DQS, DQS# differential output high time tQSH 0.4 - tCK(avg) DQS, DQS# differential output low time tQSL 0.4 - tCK(avg) DQS, DQS# differential WRITE Preamble tWPRE 0.9 - tCK(avg) DQS, DQS# differential WRITE Postamble tWPST 0.3 - tCK(avg) DQS, DQS# rising edge output access time from rising CK, CK# tDQSCK -195 195 tCK(avg) tLZ(DQS) -390 195 tCK(avg) tHZ(DQS) - 195 tCK(avg) Data Strobe Timing DQS and DQS# low-impedance time (Referenced from RL - 1) DQS and DQS# high-impedance time (Referenced from RL + BL/2) DQS, DQS# differential input low pulse width tDQSL 0.45 0.55 tCK(avg) DQS, DQS# differential input high pulse width tDQSH 0.45 0.55 tCK(avg) DQS, DQS# rising edge to CK, CK# rising edge tDQSS -0.27 0.27 tCK(avg) DQS, DQS# falling edge setup time to CK, CK# rising edge tDSS 0.18 - tCK(avg) DQS, DQS# falling edge hold time from CK, CK# rising edge tDSH 0.18 - tCK(avg) Command and Address Timing REV 1.1 10/2011 34 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. NT2GC72B89G0NL(K)/NT2GC72C89G0NL(K) NT4GC72B4PG0NL(K)/NT4GC72C4PG0NL(K)/NT4GC72B8PG0NL(K)/NT4GC72C8PG0NL(K) NT8GC72B4NG0NL(K)/NT8GC72C4NG0NL(K) 2GB: 256M x 72 / 4GB: 512M x 72 / 8GB: 1G x 72 PC3-10600 / PC3(L)-12800 / PC3-14900 Registered DDR3 SDRAM DIMM DLL locking time Internal READ Command to PRECHARGE Command delay Delay from start of internal write transaction to internal read command tDLLK 512 - nCK tRTPmin.: max(4nCK, 7.5ns) tRTP tRTPmax.: tWTRmin.: max(4nCK, 7.5ns) tWTR tWTRmax.: WRITE recovery time tWR 15 - ns Mode Register Set command cycle time tMRD 4 - nCK Mode Register Set command update delay tMOD ACT to internal read or write delay time tRCD PRE command period tRP ACT to ACT or REF command period tRC CAS# to CAS# command delay tCCD Auto precharge write recovery + precharge time tDAL(min) Multi-Purpose Register Recovery Time tMPRR ACTIVE to PRECHARGE command period tRAS ACTIVE to ACTIVE command period for 1KB page size tRRD tMODmin.: max(12nCK, 15ns) tMODmax.: 4 nCK WR + roundup(tRP / tCK(avg)) nCK 1 - nCK Standard Speed Bins tRRDmin.: max(4nCK, 5ns) tRRDmax.: tRRDmin.: max(4nCK, 6ns) ACTIVE to ACTIVE command period for 2KB page size tRRD Four activate window for 1KB page size tFAW 27 - ns Four activate window for 2KB page size tFAW 35 - ns tIS(base) - - ps tIH(base) - - ps tIS(base) AC150 - - ps tIPW 535 - ps Power-up and RESET calibration time tZQinit 512 - nCK Normal operation Full calibration time tZQoper 256 - nCK Normal operation Short calibration time tZQCS 64 - nCK Command and Address setup time to CK, CK# referenced to Vih(ac) / Vil(ac) levels Command and Address hold time from CK, CK# referenced to Vih(dc) / Vil(dc) levels Command and Address setup time to CK, CK# referenced to Vih(ac) / Vil(ac) levels Control and Address Input pulse width for each input tRRDmax.: Calibration Timing Reset Timing Exit Reset from CKE HIGH to a valid command tXPRmin.: max(5nCK, tRFC(min) + 10ns) tXPR tXPRmax.: - Self Refresh Timings Exit Self Refresh to commands not requiring a locked DLL Exit Self Refresh to commands requiring a locked DLL tXSDLL Minimum CKE low width for Self Refresh entry to exit timing tCKESR Valid Clock Requirement after Self Refresh Entry (SRE) or Power-Down Entry (PDE) Valid Clock Requirement before Self Refresh Exit (SRX) or Power-Down Exit (PDX) or Reset Exit tXSmin.: max(5nCK, tRFC(min) + 10ns) tXS tXSmax.: tXSDLLmin.: tDLLK(min) nCK tXSDLLmax.: tCKESRmin.: tCKE(min) + 1 nCK tCKESRmax.: tCKSREmin.: max(5 nCK, 10 ns) tCKSRE tCKSREmax.: tCKSRXmin.: max(5 nCK, 10 ns) tCKSRX tCKSRXmax.: - Power Down Timings Exit Power Down with DLL on to any valid command; tXPmin.: max(3nCK, 6ns) Exit Precharge Power Down with DLL frozen to commands tXP tXPmax.: - not requiring a locked DLL Exit Precharge Power Down with DLL frozen to commands requiring a locked DLL CKE minimum pulse width tCKE Command pass disable delay tCPDED Power Down Entry to Exit Timing tPD Timing of ACT command to Power Down entry REV 1.1 10/2011 tXPDLLmin.: max(10nCK, 24ns) tXPDLL tXPDLLmax.: tCKEmin.: max(3nCK ,5ns) tCKEmax.: tCPDEDmin.: 2 tCPDEDmin.: - nCK tPDmin.: tCKE(min) tPDmax.: 9*tREFI tACTPDENmin.: 1 tACTPDEN tACTPDENmax.: - nCK 35 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. NT2GC72B89G0NL(K)/NT2GC72C89G0NL(K) NT4GC72B4PG0NL(K)/NT4GC72C4PG0NL(K)/NT4GC72B8PG0NL(K)/NT4GC72C8PG0NL(K) NT8GC72B4NG0NL(K)/NT8GC72C4NG0NL(K) 2GB: 256M x 72 / 4GB: 512M x 72 / 8GB: 1G x 72 PC3-10600 / PC3(L)-12800 / PC3-14900 Registered DDR3 SDRAM DIMM Timing of PRE or PREA command to Power Down entry tPRPDEN Timing of RD/RDA command to Power Down entry tRDPDEN Timing of WR command to Power Down entry (BL8OTF, BL8MRS, BC4OTF) Timing of WRA command to Power Down entry (BL8OTF, BL8MRS, BC4OTF) Timing of WR command to Power Down entry (BC4MRS) Timing of WRA command to Power Down entry (BC4MRS) tPRPDENmin.: 1 tRDPDENmin.: RL+4+1 tWRPDENmin.: WL + 4 + (tWR / tCK(avg)) tWRPDENmax.: tWRAPDENmin.: WL+4+WR+1 tWRAPDEN tWRPDENmin.: WL + 2 + (tWR / tCK(avg)) tWRPDENmax.: tWRAPDENmin.: WL + 2 +WR + 1 tWRAPDEN Timing of MRS command to Power Down entry tMRSPDEN nCK nCK tWRAPDENmax.: - tWRPDEN tREFPDEN nCK tRDPDENmax.: - tWRPDEN Timing of REF command to Power Down entry nCK tPRPDENmax.: - tWRAPDENmax.: tREFPDENmin.: 1 nCK nCK nCK tREFPDENmax.: tMRSPDENmin.: tMOD(min) tMRSPDENmax.: - ODT Timings ODT high time without write command or with write command and BC4 ODT high time with Write command and BL8 Asynchronous RTT turn-on delay ODTH4min.: 4 ODTH4 nCK ODTH4max.: ODTH8min.: 6 ODTH8 nCK ODTH8max.: - tAONPD 2 8.5 ns tAOFPD 2 8.5 ns tAON -195 195 ps tAOF 0.3 0.7 tCK(avg) tADC 0.3 0.7 tCK(avg) tWLMRD 40 - nCK tWLDQSEN 25 - nCK tWLS 140 - ps tWLH 140 - ps Write leveling output delay tWLO 0 7.5 ns Write leveling output error tWLOE 0 2 ns (Power-Down with DLL frozen) Asynchronous RTT turn-off delay (Power-Down with DLL frozen) RTT turn-on RTT_Nom and RTT_WR turn-off time from ODTLoff reference RTT dynamic change skew Write Leveling Timings First DQS/DQS# rising edge after write leveling mode is programmed DQS/DQS# delay after write leveling mode is programmed Write leveling setup time from rising CK, CK# crossing to rising DQS, DQS# crossing Write leveling hold time from rising DQS, DQS# crossing to rising CK, CK# crossing REV 1.1 10/2011 36 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. NT2GC72B89G0NL(K)/NT2GC72C89G0NL(K) NT4GC72B4PG0NL(K)/NT4GC72C4PG0NL(K)/NT4GC72B8PG0NL(K)/NT4GC72C8PG0NL(K) NT8GC72B4NG0NL(K)/NT8GC72C4NG0NL(K) 2GB: 256M x 72 / 4GB: 512M x 72 / 8GB: 1G x 72 PC3-10600 / PC3(L)-12800 / PC3-14900 Registered DDR3 SDRAM DIMM Package Dimensions [2GB - 1 Rank, 256Mx8 DDR3 SDRAMs] FRONT 133.35 +/- 0.15 3.0 (x4) Registering Clock Driver 5.175 47.00 4.00 Max. Detail B Detail A 9.50 17.30 SPD/TS 30.00 +/-0.15 SIDE 5.00 71.00 1.27 +0.07/-0.10 BACK 2.50 Detail B 4.00 3.80 Detail A 0.80 +0.04/- 0.05 1.00 Pitch 1.50 +/- 0.10 Units: Millimeters Note: Device position and scale are only for reference. REV 1.1 10/2011 37 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. NT2GC72B89G0NL(K)/NT2GC72C89G0NL(K) NT4GC72B4PG0NL(K)/NT4GC72C4PG0NL(K)/NT4GC72B8PG0NL(K)/NT4GC72C8PG0NL(K) NT8GC72B4NG0NL(K)/NT8GC72C4NG0NL(K) 2GB: 256M x 72 / 4GB: 512M x 72 / 8GB: 1G x 72 PC3-10600 / PC3(L)-12800 / PC3-14900 Registered DDR3 SDRAM DIMM Package Dimensions [4GB - 2 Ranks, 256Mx8 DDR3 SDRAMs] FRONT 133.35 +/- 0.15 3.0 (x4) Registering Clock Driver 9.50 17.30 SPD/TS 47.00 4.00 Max. Detail B Detail A 5.175 30.00 +/-0.15 SIDE 5.00 71.00 1.27 +0.07/-0.10 BACK 2.50 Detail B 4.00 3.80 Detail A 0.80 +0.04/- 0.05 1.00 Pitch 1.50 +/- 0.10 Units: Millimeters Note: Device position and scale are only for reference. REV 1.1 10/2011 38 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. NT2GC72B89G0NL(K)/NT2GC72C89G0NL(K) NT4GC72B4PG0NL(K)/NT4GC72C4PG0NL(K)/NT4GC72B8PG0NL(K)/NT4GC72C8PG0NL(K) NT8GC72B4NG0NL(K)/NT8GC72C4NG0NL(K) 2GB: 256M x 72 / 4GB: 512M x 72 / 8GB: 1G x 72 PC3-10600 / PC3(L)-12800 / PC3-14900 Registered DDR3 SDRAM DIMM Package Dimensions [4GB - 1 Rank, 512Mx4 DDR3 SDRAMs] FRONT 133.35 +/- 0.15 3.0 (x4) Registering Clock Driver 9.50 17.30 SPD/TS 47.00 4.00 Max. Detail B Detail A 5.175 30.00 +/-0.15 SIDE 5.00 71.00 1.27 +0.07/-0.10 BACK 2.50 Detail B 4.00 3.80 Detail A 0.80 +0.04/- 0.05 1.00 Pitch 1.50 +/- 0.10 Units: Millimeters Note: Device position and scale are only for reference. REV 1.1 10/2011 39 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. NT2GC72B89G0NL(K)/NT2GC72C89G0NL(K) NT4GC72B4PG0NL(K)/NT4GC72C4PG0NL(K)/NT4GC72B8PG0NL(K)/NT4GC72C8PG0NL(K) NT8GC72B4NG0NL(K)/NT8GC72C4NG0NL(K) 2GB: 256M x 72 / 4GB: 512M x 72 / 8GB: 1G x 72 PC3-10600 / PC3(L)-12800 / PC3-14900 Registered DDR3 SDRAM DIMM Package Dimensions [8GB - 2 Ranks, 512Mx4 DDR3 SDRAMs without H/S] FRONT 133.35 +/- 0.15 30.00 +/- 0.15 17.30 4.00 Max. 9.50 3.0 (x4) SIDE Detail B Detail A 5.175 47.00 71.00 1.27 +0.07/-0.10 5.00 REAR 2.50 Detail B 4.00 3.80 Detail A 0.80 +0.04/- 0.05 1.00 Pitch 1.50 +/- 0.10 Units: Millimeters Note: Device position and scale are only for reference. REV 1.1 10/2011 40 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice. NT2GC72B89G0NL(K)/NT2GC72C89G0NL(K) NT4GC72B4PG0NL(K)/NT4GC72C4PG0NL(K)/NT4GC72B8PG0NL(K)/NT4GC72C8PG0NL(K) NT8GC72B4NG0NL(K)/NT8GC72C4NG0NL(K) 2GB: 256M x 72 / 4GB: 512M x 72 / 8GB: 1G x 72 PC3-10600 / PC3(L)-12800 / PC3-14900 Registered DDR3 SDRAM DIMM Revision Log Rev Date Modification 0.1 03/2011 Preliminary Release 1.0 05/2011 Official Release 1.1 10/2011 Added 1.35V/1600MHz Spec. Nanya Technology Corporation Hwa Ya Technology Park 669 Fu Hsing 3rd Rd., Kueishan, Taoyuan, 333, Taiwan, R.O.C. Tel: +886-3-328-1688 Please visit our home page for more information: www.nanya.com Printed in Taiwan (c) 2011 REV 1.1 10/2011 41 (c) NANYA TECHNOLOGY CORPORATION NANYA reserves the right to change products and specifications without notice.