©2004 Integrated Device Technology, Inc.
MAY 2004
DSC 2654/9
1
I/O
Control
Address
Decoder MEMORY
ARRAY
ARBITRATION
INTERRUPT
LOGIC
Address
Decoder
I/O
Control
R/W
L
CE
L
OE
L
BUSY
L
A
10L
A
0L
2654 drw 01
I/O
0L
-I/O
8L
CE
L
OE
L
R/W
L
INT
L
BUSY
R
I/O
0R
-I/O
8R
A
10R
A
0R
INT
R
CE
R
OE
R
(2)
(1,2) (1,2)
(2)
R/W
R
CE
R
OE
R
R/W
R
11
11
HIGH-SPEED
2K x 9 DUAL-PORT
STATIC RAM
WITH BUSY & INTERRUPT
IDT70121S/L
IDT70125S/L
NOTES:
1. 70121 (MASTER): BUSY is non-tri-stated push-pull output.
70125 (SLAVE): BUSY is input.
2. INT is non-tri-stated push-pull output.
Functional Block Diagram
Features
✵High-speed access
– Commercial: 25/35/45/55ns (max.)
– Industrial: 35ns (max.)
◆Low-power operation
– IDT70121/70125S
Active: 675mW (typ.)
Standby: 5mW (typ.)
– IDT70121/70125L
Active: 675mW (typ.)
Standby: 1mW (typ.)
◆Fully asychronous operation from either port
◆◆
◆◆
◆MASTER IDT70121 easily expands data bus width to 18 bits or
more using SLAVE IDT70125 chip
◆On-chip port arbitration logic (IDT70121 only)
◆BUSY output flag on Master; BUSY input on Slave
◆INT flag for port-to-port communication
◆Battery backup operation—2V data retention
◆TTL-compatible, signal 5V (±10%) power supply
◆Available in 52-pin PLCC
◆Industrial temperature range (–40°C to +85°C) is available for
selected speeds
6.42
IDT70121/IDT70125
High-Speed 2K x 9 Dual-Port Static RAM with Busy & Interrupt Industrial and Commercial Temperature Ranges
2
.
05/27/04
A
9R
GND
21
22
23
24
25
26
27
28
29
30
31
32
7
6
5
4
3
2
52
51
50
49
48
47
33
8
9
10
11
12
13
14
15
16
17
18
IDT70121/125J
J52-1
(4)
19
A
6L
A
7L
A
1L
A
2L
A
3L
A
4L
A
5L
A
8L
I/O
0L
I/O
1L
I/O
2L
I/O
3L
46
45
44
43
42
41
40
39
38
37
36
35
A
5R
A
6R
A
0R
A
1R
A
2R
A
3R
A
4R
A
7R
A
8R
I/O
8R
I/O
7R
1
INDEX
3420
OE
R
A
9L
2654 drw 02
52-Pin PLCC
Top View
(5)
A
10R
INT
R
R/W
R
CE
R
V
CC
CE
L
INT
L
A
10L
OE
L
A
0L
I/O
4L
I/O
5L
I/O
6L
I/O
7L
I/O
8L
I/O
0R
I/O
1R
I/O
2R
I/O
3R
I/O
4R
I/O
5R
I/O
6R
BUSY
R
R/W
L
BUSY
L
Pin Configurations(1,2,3)
Description
The IDT70121/IDT70125 are high-speed 2K x 9 Dual-Port Static
RAMs. The IDT70121 is designed to be used as a stand-alone 9-bit Dual-
Port RAM or as a “MASTER” Dual-Port RAM together with the IDT70125
“SLAVE” Dual-Port in 18-bit-or-more word width systems. Using the IDT
MASTER/SLAVE Dual-Port RAM approach in 18-bit-or-wider memory
system applications results in full-speed, error-free operation without the
need for additional discrete logic.
Both devices provide two independent ports with separate control,
address, and I/O pins that permit independent, asynchronous access for
reads or writes to any location in memory. An automatic power-down
feature, controlled by CE, permits the on-chip circuitry of each port to enter
a very low standby power mode.
The IDT70121/IDT70125 utilizes a 9-bit wide data path to allow for
Data/Control and parity bits at the user’s option. This feature is especially
useful in data communications applications where it is necessary to use a
parity bit for transmission/reception error checking.
Fabricated using IDT’s CMOS high-performance technology, these
devices typically operate on only 675mW of power. Low-power (L)
versions offer battery backup data retention capability with each port
typically consuming 200µW from a 2V battery.
The IDT70121/IDT70125 devices are packaged in a 52-pin PLCC.
NOTES:
1. All VCC pins must be connected to power supply.
2. All GND pins must be connected to ground supply.
3. Package body is approximately .75 in x .75 in x .17 in.
4. This package code is used to reference the package diagram.
5. This text does not indicate orientation of the actual part-marking.
3
IDT70121/IDT70125
High-Speed 2K x 9 Dual-Port Static RAM with Busy & Interrupt Industrial and Commercial Temperature Ranges
Maximum Operating Temperature
and Supply Voltage(1)
Recommended DC
Operating Conditions
Absolute Maximum Ratings(1)
Capacitance (TA = +25°C, f = 1.0MHz)
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated
in the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliabilty.
2. VTERM must not exceed Vcc + 10% for more than 25% of the cycle time or 10ns
maximum, and is limited to < 20mA for the period of VTERM > Vcc + 10%.
NOTES:
1. VIL > -1.5V for pulse width less than 10ns.
2. VTERM must not exceed Vcc + 10%.
NOTES:
1. This is the parameter TA. This is the "instant on" case temperature.
NOTE:
1. This parameter is determined by device characterization but is not production
tested.
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range (VCC = 5.0V ± 10%)
NOTE:
1. At Vcc < 2.0V leakages are undefined.
Symbol Rating Commercial
& Industrial
Unit
V
TERM
(2)
Terminal Voltage
with Respect
to GND
-0.5 to +7.0 V
T
BIAS
Temperature
Under Bias
-55 to +125 oC
T
STG
Storage
Temperature
-65 to +150 oC
I
OUT
DC Output
Current
50 mA
2654 tbl 01
Grade Ambient
Temperature
GND Vcc
Commercial 0
O
C to +70
O
C0V 5.0V
+
10%
Industrial -40
O
C to +85
O
C0V 5.0V
+
10%
2654 tbl 02
Symbol Parameter Min. Typ. Max. Unit
V
CC
Supply Voltage 4.5 5.0 5.5 V
GND Ground 0 0 0 V
V
IH
Input High Voltage 2.2
____
6.0
(2)
V
V
IL
Input Low Voltage -0.5
(1)
____
0.8 V
2654 tbl 03
Symbol Parameter Conditions
(1 )
Max. Unit
C
IN
Input Capacitance V
IN
= 3dV 9 pF
C
OUT
Output Capacitance V
OUT
= 3dV 10 pF
2654 tbl 04
Symbol Parameter Test Conditions
70121S
70125S
70121L
70125L
UnitMin. Max. Min. Max.
|I
LI
| Input Leakage Current
(1)
V
CC
= 5.5V, V
IN
= 0V to V
CC
___
10
___
5µA
|I
LO
| Output Leakage Current V
CC
= 5.5V, CE = V
IH
, V
OUT
= 0V to V
CC
___
10
___
5µA
V
OL
Output Low Voltage I
OL
= +4mA
___
0.4
___
0.4 V
V
OH
Output High Voltage I
OH
= -4mA 2.4
___
2.4
___
V
2654 tbl 05
6.42
IDT70121/IDT70125
High-Speed 2K x 9 Dual-Port Static RAM with Busy & Interrupt Industrial and Commercial Temperature Ranges
4
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range(1,4) (VCC = 5V ± 10%)
NOTES:
1. 'X' in part numbers indicates power rating (S or L).
2. At f = fMAX, address and control lines (except Output Enable) are cycling at the maximum frequency read cycle of 1/tRC, and using “AC TEST CONDITIONS” of
input levels of GND to 3V.
3. f = 0 means no address or control lines change. Applies only to inputs at CMOS level standby.
4. Vcc=5V, TA=+25°C for Typ, and is not production tested.
5. Port "A" may be either left or right port. Port "B" is opposite from port "A".
70121X25
70125X25
Com'l Only
70121X35
70125X35
Com'l
& Ind
Symbol Parameter Test Condition Version Typ. Max. Typ. Max. Unit
I
CC
Dynamic Operating Current
(Both Ports Active)
CE = V
IL
, Outputs Disabled
f = f
MAX
(2)
COM'L S
L
135
135
260
220
135
135
250
210
mA
IND S
L
___
___
___
___
135
135
275
250
I
SB1
Standby Current
(Both Ports - TTL Level Inputs)
CE
"A"
= CE
"B"
= V
IH
f = f
MAX
(2)
COM'L S
L
30
30
65
45
30
30
65
45
mA
IND S
L
___
___
___
___
30
30
80
65
I
SB2
Standby Current
(One Port - TTL Level Inputs)
CE
"A"
= V
IL
and CE
"B"
= V
IH
(5)
Active Port Outputs Disabled,
f=f
MAX
(2)
COM'L S
L
80
80
175
145
80
80
165
135
mA
IND S
L
___
___
___
___
80
80
190
165
I
SB3
Full Standby Current (Both Ports
- CMOS Level Inp uts)
CE
"A"
and CE
"B"
> V
CC
- 0.2V
V
IN
> V
CC
- 0.2V or
VIN < 0.2V, f = 0
(3)
COM'L S
L
1.0
0.2
15
5
1.0
0.2
15
5
mA
IND S
L
___
___
___
___
1.0
0.2
15
5
I
SB4
Full Standby Current
(One Port - CMOS Level Inputs)
CE
"A"
< 0.2V and
CE
"B"
> V
CC
- 0.2V
(5)
V
IN
> V
CC
- 0.2V or V
IN
< 0.2V
Active Port Outputs Disabled,
f = f
MAX
(2)
COM'L S
L
70
70
170
140
70
70
160
130
mA
IND S
L
___
___
___
___
70
70
185
160
2654 tbl 06a
70121X45
70125X45
Com'l Only
70121X55
70125X55
Com'l Only
Symbol Parameter Test Condition Version Typ. Max. Typ. Max. Unit
I
CC
Dynamic Operating Current
(Both Ports Active)
CE = V
IL
, Outputs Disabled
f = f
MAX
(2)
COM'L S
L
135
135
245
205
135
135
240
200
mA
IND S
L
___
___
___
___
___
___
___
___
I
SB1
Standby Current
(Both Ports - TTL Level Inputs)
CE
"A"
= CE
"B"
= V
IH
f = f
MAX
(2)
COM'L S
L
30
30
65
45
30
30
65
45
mA
IND S
L
___
___
___
___
___
___
___
___
I
SB2
Standby Current
(One Port - TTL Level Inputs)
CE
"A"
= V
IL
and CE
"B"
= V
IH
(5)
Active Port Outputs Disabled,
f=f
MAX
(2)
COM'L S
L
80
80
160
130
80
80
155
125
mA
IND S
L
___
___
___
___
___
___
___
___
I
SB3
Full Standby Current
(Both Ports - CMOS Level
Inputs)
CE
"A"
and CE
"B"
> V
CC
- 0.2V
V
IN
> V
CC
- 0.2V or
V
IN
< 0.2V, f = 0
(3)
COM'L S
L
1.0
0.2
15
5
1.0
0.2
15
5
mA
IND S
L
___
___
___
___
___
___
___
___
I
SB4
Full Standby Current
(One Port - CMOS Level Inputs)
CE
"A"
< 0.2V and
CE
"B"
> V
CC
- 0.2V
(5)
V
IN
> V
CC
- 0.2V or V
IN
< 0.2V
Active Port Outputs Disabled,
f = f
MAX
(2)
COM'L S
L
70
70
155
125
70
70
150
120
mA
IND S
L
___
___
___
___
___
___
___
___
2654 tbl 06b
5
IDT70121/IDT70125
High-Speed 2K x 9 Dual-Port Static RAM with Busy & Interrupt Industrial and Commercial Temperature Ranges
Data Retention Characteristics (L Version Only)
Data Retention Waveform
AC Test Conditions
Figure 1. AC Output Test Load Figure 2. Output Test Load
(For tLZ, tHZ, tWZ, tOW)
*Including scope and jig.
NOTES:
1. VCC = 2V, TA = +25°C, and are not production tested.
2. tRC = Read Cycle Time.
3. This parameter is guaranteed but is not production tested.
V
DR
2V
≥
DATA RETENTION MODE
Vcc
CE
4.5V
t
CDR
t
R
V
IH
V
DR
V
IH
4.5V
2654 drw 03
1250Ω
30pF
775Ω
DATA
OUT
BUSY
INT
5V 5V
1250Ω
5pF*
775Ω
DATA
OUT
2654 drw 04
Symbol Parameter Test Condition Min. Typ.
(1)
Max. Unit
V
DR
V
CC
for Data Retention 2.0
___ ___
V
I
CCDR
Data Retention Current V
CC
= 2V, CE > V
CC
- 0.2V IND.
___
100 4000 µA
t
CDR
(3)
Chip Deselect to Data Retention Time V
IN
> V
CC
- 0.2V or V
IN
< 0.2 COM'L.
___
100 1500
t
R
(3)
Operation Recovery Time t
RC
(2)
___ ___
V
2654 tb l 07
Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load
GND to 3.0V
3ns
1.5V
1.5V
Figures 1 and 2
2654 tbl 08
6.42
IDT70121/IDT70125
High-Speed 2K x 9 Dual-Port Static RAM with Busy & Interrupt Industrial and Commercial Temperature Ranges
6
AC Electrical Characteristics Over the
Operating Temperature and Supply Voltage Range(3)
NOTES:
1. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2).
2. This parameter guaranteed by device characterization, but is not production tested.
3. 'X' in part numbers indicates power rating (S or L).
70121X25
70125X25
Com'l Only
70121X35
70125X35
Com'l
& Ind
UnitSymbol Parameter Min. Max. Min. Max.
READ CYCLE
t
RC
Read Cycle Time 25
____
35
____
ns
t
AA
Address Access Time
____
25
____
35 ns
t
ACE
Chip Enable Access Time
____
25
____
35 ns
t
AOE
Output Enable Access Time
____
12
____
25 ns
t
OH
Output Hold from Address Change 0
____
0
____
ns
t
LZ
Output Low-Z Time
(1,2)
0
____
0
____
ns
t
HZ
Output High-Z Time
(1,2)
____
10
____
15 ns
t
PU
Chip Enable to Power Up Time
(2)
0
____
0
____
ns
t
PD
Chip Disable to Power Down Time
(2)
____
50
____
50 ns
2654 tbl 09a
70121X45
70125X45
Com'l Only
70121X55
70125X55
Com'l Only
UnitSymbol Parameter Min. Max. Min. Max.
READ CYCLE
t
RC
Read Cycle Time 45
____
55
____
ns
t
AA
Address Access Time
____
45
____
55 ns
t
ACE
Chip Enable Access Time
____
45
____
55 ns
t
AOE
Output Enable Access Time
____
30
____
35 ns
t
OH
Output Hold from Address Change 0
____
0
____
ns
t
LZ
Output Low-Z Time
(1,2)
0
____
0
____
ns
t
HZ
Output High-Z Time
(1,2)
____
20
____
30 ns
t
PU
Chip Enable to Power Up Time
(2)
0
____
0
____
ns
t
PD
Chip Disable to Power Down Time
(2)
____
50
____
50 ns
2654 tbl 09b
7
IDT70121/IDT70125
High-Speed 2K x 9 Dual-Port Static RAM with Busy & Interrupt Industrial and Commercial Temperature Ranges
Timing Waveform of Read Cycle No. 1, Either Side(1,2,4)
NOTES:
1. Timing depends on which signal is aserted last, OE or CE.
2. Timing depends on which signal is deaserted first, OE or CE.
3. tBDD delay is required only in a case where the opposite port is completing a write operation to the same address location. For simultaneous read operations
BUSY has no relationship to valid output data.
4. Start of valid data depends on which timing becomes effective last, tAOE, tACE, tAA, or tBDD.
5. R/W = VIH, CE = VIL, and OE = VIL, and the address is valid prior to other coincidental with CE transition LOW.
Timing Waveform of Read Cycle No. 2, Either Side(5)
ADDRESS
DATA
OUT
t
RC
t
OH
PREVIOUS DATA VALID
t
AA
t
OH
DATA VALID
2654 drw 05
t
BDD
(3,4)
BUSY
OUT
CE
t
ACE
t
HZ
t
LZ
t
PD
VALID DATA
t
PU
50%
OE
DATA
OUT
CURRENT
I
CC
I
SS
50%
2654 drw 06
(4)
(1)
(1) (2)
(2)
(4)
t
LZ
t
HZ
t
AOE
6.42
IDT70121/IDT70125
High-Speed 2K x 9 Dual-Port Static RAM with Busy & Interrupt Industrial and Commercial Temperature Ranges
8
AC Electrical Characteristics Over the
Operating Temperature and Supply Voltage Range(4)
NOTES:
1. Transition is measured 0mV from Low or High-impedance voltage with Output Test Load (Figure 2).
2. This parameter guaranteed by device characterization, but is not production tested.
3. For MASTER/SLAVE combination, tWC = tBAA + tWP, since R/W = VIL must occur after tBAA .
4. 'X' in part numbers indicates power rating (S or L).
5. The specified tDH must be met by the device supplying write date to the RAM under all operating conditions.
Although tDH and t
OW
values will vary over voltage and temperature. The actual tDH will always be smaller than the actual tOW.
6. If OE is LOW during a R/W controlled write cycle, the write pulse width must be the larger of tWP or (tWZ + tDW) to allow the I/O drivers to turn off data to be
placed on the bus for the required tDW. If OE is HIGH during a R/W controlled write cycle, this requirement does not apply and the write pulse can be as short
as the specified tWP.
Symbol Parameter
70121X25
70125X25
Com'l Only
70121X35
70125X35
Com'l
& Ind
UnitMin. Max. Min. Max.
WRITE CYCLE
t
WC
Write Cycle Time
(4)
25
____
35
____
ns
t
EW
Chip Enable to End-of-Write 20
____
30
____
ns
t
AW
Address Valid to End-of-Write 20
____
30
____
ns
t
AS
Address Set-up Time 0
____
0
____
ns
t
WP
Write Pulse Width
(6)
20
____
30
____
ns
t
WR
Write Recovery Time 0
____
0
____
ns
t
DW
Data Valid to End-of-Write 12
____
20
____
ns
t
HZ
Output High-Z Time
(1, 2 ,3 )
____
10
____
15 ns
t
DH
Data Ho ld Time
(5)
0
____
0
____
ns
t
WZ
Write Enable to Output in High-Z
(1,3)
____
10
____
15 ns
t
OW
Output Active from End-of-Write
(1,2,3,5)
0
____
0
____
ns
2654 tbl 10a
Symbol Parameter
70121X45
70125X45
Com'l Only
70121X55
70125X55
Com'l Only
UnitMin. Max. Min. Max.
WRIT E CYCLE
t
WC
Write Cycle Time
(4)
45
____
55
____
ns
t
EW
Chip Enable to End-of-Write 35
____
40
____
ns
t
AW
Address Valid to End-of-Write 35
____
40
____
ns
t
AS
Address Set-up Time 0
____
0
____
ns
t
WP
Write Pulse Width
(6)
35
____
40
____
ns
t
WR
Write Recovery Time 0
____
0
____
ns
t
DW
Data Valid to End-of-Write 20
____
20
____
ns
t
HZ
Output High-Z Time
(1, 2 ,3 )
____
20
____
30 ns
t
DH
Data Hold Time
(5)
0
____
0
____
ns
t
WZ
Write Enable to Output in High-Z
(1,3)
____
20
____
30 ns
t
OW
Output Active from End-of-Write
(1,2,3,5)
0
____
0
____
ns
2654 tbl 10b
9
IDT70121/IDT70125
High-Speed 2K x 9 Dual-Port Static RAM with Busy & Interrupt Industrial and Commercial Temperature Ranges
NOTES:
1. R/W or CE must be HIGH during all address transitions.
2. A write occurs during the overlap (tEW or tWP) of a CE = VIL and a R/W = VIL
3. tWR is measured from the earlier of CE or R/W going HIGH to the end of the write cycle.
4. During this period, the I/O pins are in the output state and input signals must not be applied.
5. If the CE LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in the High-impedance state.
6. Timing depends on which enable signal (CE or R/W) is asserted last.
7. This parameter is determined be device characterization, but is not production tested. Transition is measured 0mV from steady state with the Output Test Load
(Figure 2).
8. If OE is LOW during a R/W controlled write cycle, the write pulse width must be the larger of tWP or (tWZ + tDW) to allow the I/O drivers to turn off data to be
placed on the bus for the required tDW. If OE is HIGH during a R/W controlled write cycle, this requirement does not apply and the write pulse can be as short
as the specified tWP.
Timing Waveform of Write Cycle No. 2, CE Controlled Timing(1,5)
Timing Waveform of Write Cycle No. 1, R/W Controlled Timing(1,5,8)
R/W
t
WC
t
HZ
t
AW
t
HZ
t
AS
t
WP
DATA
OUT
t
DW
t
DH
t
OW
OE
ADDRESS
DATA
IN
CE
t
WZ
(4) (4)
t
WR
2654 drw 07
(3)
(7)
(2)
(6)
(7)
(7)
CE
t
WC
t
AS
t
WR
t
DW
t
DH
ADDRESS
DATA
IN
R/W
t
AW
t
EW
2654 drw 08
(6) (2) (3)
6.42
IDT70121/IDT70125
High-Speed 2K x 9 Dual-Port Static RAM with Busy & Interrupt Industrial and Commercial Temperature Ranges
10
AC Electrical Characteristics Over the Operating Temperature
and Supply Voltage Range(6)
NOTES:
1. Port-to-port delay through RAM cells from writing port to reading port, refer to “Timing Waveform of Write with Port-to-Port Read and BUSY.
2. To ensure that the earlier of the two ports wins.
3. tBDD is a calculated parameter and is the greater of 0, tWDD – tWP (actual) or tDDD – tDW (actual).
4. To ensure that a write cycle is inhibited on port 'B' during contention on port 'A'..
5. To ensure that a write cycle is completed on port 'B' after contention on port 'A'.
6. 'X' in part numbers indicates power rating (S or L).
70121X25
70125X25
Com'l Only
70121X35
70125X35
Com'l
& Ind
Symbol Parameter Min.Max.Min.Max.Unit
BUSY TIMING (For MASTER IDT70121)
t
BAA
BUSY Access Time from Address
____
20
____
20 ns
t
BDA
BUSY Disable Time from Address
____
20
____
20 ns
t
BAC
BUSY Access Time from Chip Enable
____
20
____
20 ns
t
BDC
BUSY Disable Time from Chip Enable
____
20
____
20 ns
t
WDD
Write Pulse to Data Delay
(1)
50 60
t
DDD
Write Data Valid to Read Data Delay
(1)
35 45
t
APS
Arbitration Prio rity Se t-up Time
(2)
5
____
5
____
ns
t
BDD
BUSY Disable to Valid Data
(3)
____
30
____
30 ns
t
WH
Write Hold After BUSY
(5)
15
____
20
____
ns
BUSY INPUT TIMING (For SLAVE IDT70125)
t
WB
Write to BUSY Input
(4)
0
____
0
____
ns
t
WH
Write Hold After BUSY
(5)
15
____
20
____
ns
t
WDD
Write Pulse to Data Delay
(1)
____
50
____
60 ns
t
DDD
Write Data Valid to Read Data Delay
(1)
____
35
____
45 ns
2654 tbl 11a
70121X45
70125X45
Com'l Only
70121X55
70125X55
Com'l Only
Symbol Parameter Min.Max.Min.Max.Unit
BUSY TIMING (For MASTER IDT 70121)
t
BAA
BUSY Access Time from Address
____
20
____
30 ns
t
BDA
BUSY Disable Time from Address
____
20
____
30 ns
t
BAC
BUSY Access Time from Chip Enable
____
20
____
30 ns
t
BDC
BUSY Disable Time from Chip Enable
____
20
____
30 ns
t
WDD
Write Pulse to Data Delay
(1)
70 80
t
DDD
Write Data Valid to Read Data Delay
(1)
55 65
t
APS
Arbitration Priority Set-up Time
(2)
5
____
5
____
ns
t
BDD
BUSY Disable to Valid Data
(3)
____
35
____
45 ns
t
WH
Write Hold After BUSY
(5)
20
____
20
____
ns
BUSY INPUT TIMING (For SLAVE IDT 70125)
t
WB
Write to BUSY Input
(4)
0
____
0
____
ns
t
WH
Write Hold After BUSY
(5)
20
____
20
____
ns
t
WDD
Write Pulse to Data Delay
(1)
____
70
____
80 ns
t
DDD
Write Data Valid to Read Data Delay
(1)
____
55
____
65 ns
2654 tbl 11b
11
IDT70121/IDT70125
High-Speed 2K x 9 Dual-Port Static RAM with Busy & Interrupt Industrial and Commercial Temperature Ranges
tAPS
ADDR'A'
DATAIN'A'
MATCH
tWC
tWP
R/W'A'
ADDR'B'
DATAOUT 'B'
MATCH
BUSY'B'
tBDA
tDW tDH
VALID
VALID
tDDD
(4)
tWDD
tBDD
2654 drw 09
(1)
Timing Waveform of BUSY Arbritration Controlled by CE Timing(1)
Timing Waveform of Write with Port-to-Port Read and BUSY(1,2,3)
Timing Waveform of Write with BUSY(3)
NOTES:
1. tWH must be met for both BUSY input (slave) and output (master).
2. BUSY is asserted on port 'B' blocking R/W'B', until BUSY'B' goes HIGH.
3. All timing is the same for left and right ports. Port"A" may be either left or right port. Port "B" is the opposite from port "A".
NOTES:
1. To ensure that the earlier of the two ports wins. tAPS is ignored for Slave (IDT70125).
2. CEL = CER = VIL
3. OE = VIL for the reading port.
4. All timing is the same for the left and right ports. Port 'A' may be either the left or right port. Port "B" is oppsite from port "A".
2654 drw 10
R/W
"A"
BUSY
"B"
t
WP
t
WB
R/W
"B"
t
WH
(1)
(2)
,
t
BDC
ADDR
"A
and
B"
BUSY
"B"
CE
"A"
t
APS
(2)
t
BAC
ADDRESSES MATCH
CE
"B"
2654 drw 11
(1)
NOTES:
1. All timing is the same for left and right ports. Port “A” may be either left or right port. Port “B” is the opposite from port “A”.
2. If tAPS is not satisified, the BUSY will be asserted on one side or the other, but there is no guarantee on which side BUSY will be asserted
(70121 only).
6.42
IDT70121/IDT70125
High-Speed 2K x 9 Dual-Port Static RAM with Busy & Interrupt Industrial and Commercial Temperature Ranges
12
Timing Waveform of BUSY Arbritration Controlled by Address(1)
AC Electrical Characteristics Over the
Operating Temperature and Supply Voltage Range(1)
NOTES:
1. 'X' in part numbers indicates power rating (S or L).
t
BAA
ADDR
'A'
BUSY
'B'
ADDRESSES MATCH ADDRESSES DO NOT MATCH
t
RC
OR t
WC
t
APS
(2)
t
BDA
ADDR
'B'
2654 drw 12
70121X25
70125X25
Com'l Only
70121X35
70125X35
Com'l
& Ind
Symbol Parameter Min. Max. Min. Max. Unit
INTERRUPT TIMING
tAS Address Set-up Time 0
____
0
____
ns
tWR Write Recovery Time 0
____
0
____
ns
tINS Interrupt Se t Time
____
25
____
35 ns
tINR Interrupt Reset Time
____
25
____
35 ns
2654 tbl 12a
70121X45
70125X45
Com'l Only
70121X55
70125X55
Com'l Only
Symbol Parameter Min.Max.Min.Max.Unit
INTERRUPT TIMING
t
AS
Address Set-up Time 0
____
0
____
ns
t
WR
Write Recovery Time 0
____
0
____
ns
t
INS
Inte rrupt Se t Time
____
40
____
45 ns
t
INR
Interrupt Reset Time
____
40
____
45 ns
2654 tbl 12b
NOTES:
1. All timing is the same for left and right ports. Port “A” may be either left or right port. Port “B” is the opposite from port “A”.
2. If tAPS is not satisified, the BUSY will be asserted on one side or the other, but there is no guarantee on which side BUSY will be asserted
(70121 only).
13
IDT70121/IDT70125
High-Speed 2K x 9 Dual-Port Static RAM with Busy & Interrupt Industrial and Commercial Temperature Ranges
Timing Waveform of Interrupt Mode(1)
Truth Tables
Truth Table II. Interrupt Flag(1,4)
Truth Table I. Non-Contention Read/Write Control(4)
NOTES:
1. A0L – A10L ≠ A0R – A10R.
2. If BUSY = L, data is not written.
3. If BUSY = L, data may not be valid, see tWDD and tDDD timing.
4. 'H' = VIH, 'L' = VIL, 'X' = DON’T CARE, 'Z' = HIGH IMPEDANCE
NOTES:
1. Assumes BUSYL = BUSYR = VIH
2. If BUSYL = VIL, then No Change.
3. If BUSYR = VIL, then No Change.
4. 'H' = HIGH,' L' = LOW,' X' = DON’T CARE
t
INS
ADDR
'A'
INT
'B'
INTERRUPT SET ADDRESS
t
WC
t
AS
R/W
'A'
t
WR
2654 drw 13
(3)
(3)
(2)
(4)
Left or Right Port
(1)
FunctionR/WCE OE D
0-8
X H X Z Port Disable and in Power-Down Mode, I
SB2
or I
SB4
XHX Z
CE
R
= CE
L
= H, Power-DownMode, I
SB1
or I
SB3
LLXDATA
IN
Data on Port Written Into Memory
(2)
HL LDATA
OUT
Data in Memory Output on Port
(3)
H L H Z High-Impedance Outputs
2654 tbl 13
Left Port Right Port
FunctionR/W
L
CE
L
OE
L
A
10L
-A
0L
INT
L
R/W
R
CE
R
OE
R
A
10R
-A
0R
INTR
LLX7FFXXXX X L
(2)
Set Rig ht INT
R
Flag
XXXXXXLL7FFH
(3)
Rese t Right INT
R
Flag
XXX X L
(3 )
L L X 7FE X Se t Left INT
L
Flag
XLL7FEH
(2)
X X X X X Reset Left INT
L
Flag
2654 tbl 14
NOTES:.
1. All timing is the same for left and right ports. Port “A” may be either left or right port. Port “B” is the opposite from port “A”.
2. See Interupt Truth Table.
3. Timing depends on which enable signal (CE or R/W) is asserted last.
4. Timing depends on which enable signal (CE or R/W) is de-asserted first.
6.42
IDT70121/IDT70125
High-Speed 2K x 9 Dual-Port Static RAM with Busy & Interrupt Industrial and Commercial Temperature Ranges
14
Functional Description
The IDT70121/125 provides two ports with separate control, address
and I/O pins that permit independent access for reads or writes to any
location in memory. The IDT70121/125 has an automatic power down
feature controlled by CE. The CE controls on-chip power down circuitry
that permits the respective port to go into a standby mode when not selected
(CE HIGH). When a port is enabled, access to the entire memory array
is permitted.
Interrupts
If the user chooses the interrupt function, a memory location (mail box
or message center) is assigned to each port. The left port interrupt flag
(INTL) is asserted when the right port writes to memory location 7FE
(HEX), where a write is defined as the CE = R/W = VIL per Truth Table
II. The left port clears the interrupt by access address location 7FE access
when CER = OER = VIL, R/W is a "don't care". Likewise, the right port
interrupt flag (INTR) is asserted when the left port writes to memory location
7FF (HEX) and to clear the interrupt flag (INTR), the right port must access
the memory location 7FF. The message (9 bits) at 7FE or 7FF is user-
defined, since it is an addressable SRAM location. If the interrupt function
is not used, address locations 7FE and 7FF are not used as mail boxes,
but as part of the random access memory. Refer to Table II for the interrupt
operation.
Busy Logic
Busy Logic provides a hardware indication that both ports of the RAM
have accessed the same location at the same time. It also allows one of the
two accesses to proceed and signals the other side that the RAM is “busy”.
The BUSY pin can then be used to stall the access until the operation on
the other side is completed. If a write operation has been attempted from
the side that receives a BUSY indication, the write signal is gated internally
to prevent the write from proceeding.
The use of BUSY logic is not required or desirable for all applications.
In some cases it may be useful to logically OR the BUSY outputs together
and use any BUSY indication as an interrupt source to flag the event of
an illegal or illogical operation. If the write inhibit function of BUSY logic is
not desirable, the BUSY logic can be disabled by using the IDT70125
(SLAVE). In the IDT70125, the BUSY pin operates solely as a write inhibit
input pin. Normal operation can be programmed by tying the BUSY pins
HIGH. Once in slave mode the BUSY pin operates solely as a write inhibit
input pin. If desired, unintended write operations can be prevented to a
port by tying the BUSY pin for that port LOW.
The BUSY outputs on the IDT70121/125 RAM in master mode, are
push-pull type outputs and do not require pull up resistors to operate. If
these RAMs are being expanded in depth, then the BUSY indication for
the resulting array requires the use of an external AND gate.
Width Expansion with Busy Logic
Master/Slave Arrays
When expanding an IDT70121/125 RAM array in width while using
BUSY logic, one master part is used to decide which side of the RAM array
will receive a BUSY indication, and to output that indication. Any number
of slaves to be addressed in the same address range as the master use
the BUSY signal as a write inhibit signal. Thus on the IDT70121 RAM the
BUSY pin is an output of the part, and the BUSY pin is an input of the
IDT70125 as shown in Figure 3.
If two or more master parts were used when expanding in width, a split
decision could result with one master indicating BUSY on one side of the
array and another master indicating BUSY on one other side of the array.
This would inhibit the write operations from one port for part of a word and
Figure 3. Busy and chip enable routing for both width and depth
expansion with 70121 (Master) and 70125 (Slave) RAMs.
2654 drw 14
MASTER
Dual Port
RAM BUSY
R
CE
MASTER
Dual Port
RAM BUSY
R
CE
SLAVE
Dual Port
RAM BUSY
R
CE
SLAVE
Dual Port
RAM BUSY
R
CE
BUSY
L
BUSY
R
DECODER
BUSY
L
BUSY
L
BUSY
L
BUSY
L
,
inhibit the write operations from the other port for the other part of the word.
The BUSY arbitration, on a master, is based on the chip enable and
address signals only. It ignores whether an access is a read or write. In
a master/slave array, both address and chip enable must be valid long
enough for a BUSY flag to be output from the master before the actual write
pulse can be initiated with either the R/W signal or the byte enables. Failure
to observe this timing can result in a glitched internal write inhibit signal and
corrupted data in the slave.
15
IDT70121/IDT70125
High-Speed 2K x 9 Dual-Port Static RAM with Busy & Interrupt Industrial and Commercial Temperature Ranges
Ordering Information
NOTE:
1. Industrial temperature: for other speeds, packages and powers contact your sales office.
X
Power XXX
Speed X
Package X
Process/
Temperature
Range
Blank
I
(1)
Commercial (0°C to +70°C)
Industrial (-40°C to +85°C)
J52-pin PLCC (J52-1)
25
35
45
55
L
SLow Power
Standard Power
XXXXX
Device
Type
70121
70125
18K (2K x 9-Bit) MASTER Dual-Port RAM
w/ Interrupt
18K (2K x 9-Bit) SLAVE Dual-Port RAM
w/ Interrupt
IDT
Speed in nanoseconds
2654 drw 15
Commercial Only
Commercial & Industrial
Commercial Only
Commercial Only
,
CORPORATE HEADQUARTERS for SALES: for Tech Support:
2975 Stender Way 800-345-7015 or 408-727-5166 831-754-4613
Santa Clara, CA 95054 fax: 408-492-8674 DualPortHelp@idt.com
www.idt.com
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
Datasheet Document History
01/06/99: Initiated datasheet document history
Converted to new format
Cosmetic and typographical corrections
Pages 2 and 3 Added additional notes to pin configurations
06/03/99: Changed drawing format
Page 1 Corrected DSC number
05/28/04: Page 3 Changed storage temperature parameter from -55 to +125 to -65 to +150
Clarified TA parameter footnote
Page 4 DC Electrical parameters–changed test condition wording from "open" to "disabled"
Page 9 Changed ±500mV to 0mV in notes
Page 2 Added date revision for pin configuration
Page 4, 6, 8, 10 & 12 Added Industrial temp to column headings for 35ns speed to DC and AC Electrical Characteristics
Page 4 Removed Industrial temp from 25, 45 & 55ns speeds from DC Electrical Characteristics
Page 3, 4, 6, 8, 10 & 12 Removed Industrial temp footnote from all tables
Page 10 Corrected error in AC BUSY timing tables changing 71V33 to 70121 and changing 71V43 to 70125
Page 15 Added Industrial temp offering to 35ns ordering information
Page 1 & 15 Replaced old TM logo with new TM logo
Page 6 Footnote reference 5 removed from AC Electrical Characteristics READ table
Page 1 Changed wording of footnote 1 from "INT is totem-pole output" to "INT is non-tr-stated push-pull output"
Page 5 Updated AC Test Conditions Input Rise/Fall Times from 5ns to 3ns