EZ-USB FX1™ USB Microcontroller
Full-speed USB Peripheral Controller
CY7C64713/14
Cypress Semiconductor Corporation •3901 North First Street •San Jose, CA 95134 •408-943-2600
Document #: 38-08039 Rev. *B Revised February 14, 2005
1.0 Features
• Single-chip integrated USB transceiver, SIE, and
enhanced 8051 microprocessor
• Fit, form and function upgradable to the FX2LP
(CY7C68013A)
—Pin-compatible
—Object-code-compatible
—Functionally-compatible (FX1 functionality is a
Subset of the FX2LP)
• Draws no more than 65 mA in any mode making the FX1
suitable for bus powered applications
• Software: 8051 runs from internal RAM, which is:
—Downloaded via USB
—Loaded from EEPROM
—External memory device (128-pin configuration only)
• 16 KBytes of on-chip Code/Data RAM
• Four programmable BULK/INTERRUPT/ISOCH-
RONOUS endpoints
—Buffering options: double, triple, and quad
• Additional progra mmable (BULK/INTERRUPT) 64-b yte
endpoint
• 8- or 16-bit external data interface
• Smart Media Standard ECC generation
•GPIF
—Allows direct connection to most parallel interfaces;
8- and 16-bit
—Programmable waveform descriptors and configu-
ration registers to define waveforms
—Supports multiple Ready (RDY) inputs and Control
(CTL) outputs
• Integrated, industry standard 8051 with enhanced
features
—Up to 48-MHz clock rate
—Four clocks per instruction cycle
—Two USARTS
—Three counter/timers
—Expanded interrupt system
—Two data pointers
• 3.3V operation with 5V tolerant inputs
•Smart SIE
• Vectored USB interrupts
•Sep arate dat a b uffers for the Setup and DATA portio ns
of a CONTROL transfer
•Integrated I2C controller, runs at 100 or 400 KHz
•48-MHz, 24-MHz, or 12-MHz 8051 operation
•Four integrated FIFOs
—Brings glue and FIFOs inside for lower system cost
—Automatic conversion to and from 16-bit buses
—Master or slave operation
—FIFOs can use externally supplied clock or
asynchronous strobes
—Easy interface to ASIC and DSP ICs
•Vectored for FIFO and GPIF interrupts
•Up to 40 general purpose I/Os
•Three package options—128-pin TQFP, 100-pin TQFP,
and 56-pin QFN Lead-free
Address (16)
x20
PLL
/0.5
/1.0
/2.0
8051 Core
12/24/48 MHz,
four clocks/cycle
I2C
VCC
1.5k
D+
D–
Address (16) / Data Bus (8)
FX1
GPIF
CY
Smart
USB
Engine
USB
XCVR
16 KB
RAM
4 kB
FIFO
Integrated
full-speed XCVR
Additional I/Os (24)
ADDR (9)
CTL (6)
RDY (6)
8/16
Data (8)
24 MHz
Ext. XTAL
Enhanced USB core
Simplifies 8051 code “Soft Configur atio n”
Easy firmware changes FIFO and endpoint memory
(master or slave operation)
Up to 96 MBytes/s
burst rate
General
programmable I/F
to ASIC/DSP or bus
standards such as
ATA PI, EPP, etc.
Abundant I/O
including two USARTS
High-performance micro
using standard tools
with lower-power options
Master
Figure 1-1. Block Diagram
connected for
enumeration
ECC
CY7C64713/14
Document #: 38-08039 Rev. *B Page 2 of 50
2.0 Functional Descri ption
EZ-USB FX1 (CY7C64713/4) is a full-speed highly
integrate d, USB mic rocontroll er . By integrati ng the U SB trans-
ceiver , serial interface engine (SIE), enhanced 8051 microcon-
troller, and a programmable peripheral interface in a single
chip, Cypress has created a very cost-effective solution that
provides superior time-to-market advantages.
Because it incorporates the USB transceiver , the EZ-USB FX1
is mo re econo mical, providing a sma ller foot print sol ution tha n
USB SIE or external transceiver implementations. With
EZ-USB FX1, the Cypress Smart SIE handles most of the USB
protocol in hardware, freeing the embedded microcontroller for
application-specific functions and decreasing development
time to ensure USB compatibility.
The General Programmable Interface (GPIF) and Master/
Slave Endpoint FIFO (8- or 16-bit data bus) provides an easy
and glueless interface to popular interfaces such as ATA,
UTOPIA, EPP, PCMCIA, and most DSP/processors.
Three lead-free packages are defined for the family: 56 QFN,
100 TQFP, and 128 TQFP.
3.0 Applications
•DSL modems
•ATA interface
•Memory card readers
•Legacy conversion devices
•Home PNA
•Wireless LAN
•MP3 players
•Networking
The “Reference Designs” section of the cypress website
provides additional tools for typical USB applications. Each
reference design comes complete with firmware source and
object code, schematics, and documentation. Please visit
http://www.cypress.com for more information.
4.0 Functional Overview
4.1 USB Signaling Speed
FX1 operates at one of the three rates defined in the USB
Specification Revision 2.0, dated April 27, 2000:
•Full speed, with a signaling bit rate of 12 Mbps.
FX1 does not support the low-speed signaling mode of 1.5
Mbps or the high-speed mode of 480 Mbps.
4.2 8051 Microprocessor
The 8051 microprocessor embedded in the FX1 family has
256 bytes of register RAM, an expanded interrupt system,
three timer/cou nte rs, and two USARTs.
4.2.1 8051 Clock Frequency
FX1 has an o n-chip oscillator c ircuit that uses an external 24-
MHz (±100 ppm) crystal with the following characteristics:
•Parallel res ona nt
•Fundamental mode
•500-µW driv e level
•12-pF (5% tolerance) load capacitors.
An on-chip PLL multiplies the 24-MHz oscillator up to 480
MHz, as required by the transceiver/PHY, and internal
counters div id e it do w n for use as th e 805 1 cl oc k. Th e de fau lt
8051 clock frequency is 12 MHz. The clock frequency of the
8051 can be changed by the 8051 through the CPUCS
register, dynamically.
The CLKOUT pin, which can be three-stated and inverted
using internal control bits, outputs the 50% duty cycle 8051
clock, at the selected 8051 clock frequency—48, 24, or 12
MHz.
4.2.2 USARTS
FX1 contains two standard 8051 USARTs, addressed via
Special Function Register (SFR) bits. The USART interface
pins are available on separate I/O pins, and are not multi-
plexed with port pins.
UAR T0 and UAR T1 can operate using an intern al clock at 230
KBaud with no more than 1% baud rate error. 230-KBaud
operation is achieved by an internally derived clock source that
generates overflow pulses at the appropriate time. The
internal cl ock ad jus ts for t he 8 051 cl oc k ra te (4 8, 2 4, 1 2 M Hz)
such that it always presents the correct frequency for 230-
KBaud operation.[1]
4.2.3 Special Function Registers
Certain 8051 SFR addresses are populated to provide fast
access to critical FX1 functions. These SFR additions are
shown in Table 4-1. Bold type indicates non-standard,
enhance d 8051 reg isters . The two SFR rows that end wit h “0”
and “8” contain bit-addressable registers. The four I/O ports
A–D use the SFR addresses used in the standard 8051 for
ports 0–3, which are not implemented in FX1. Because of the
faster and more efficient SFR addressing, the FX1 I/O ports
are not addr ess ab le in ex tern al R AM space (using the MOVX
instruction).
Note:
1. 115-KBaud operation is also possible by programming the 8051 SMOD0 or SMOD1 bits to a “1” for UART0 and/or UART1, respectively.
12 pf
12 pf
24 MHz
20 × PLL
C1 C2
12-pF capacitor values assumes a trace
capacitance of 3 pF per side on a four-layer FR4 PCA
Figure 4-1. Crystal Configuration
CY7C64713/14
Document #: 38-08039 Rev. *B Page 3 of 50
4.3 I2C Bus
FX1 supports the I2C bus as a master only at 100/400 KHz.
SCL and SDA pins have open-drain outputs and hysteresis
input s. The se signa ls must be pulled up to 3.3 V, ev en if no I2C
device is connected.
4.4 Buses
All packages: 8- or 16-bit “FIFO” bidirectional data bus, multi-
plexed on I/O ports B and D. 128-pin package: adds 16-bit
output-only 8051 address bus, 8-bit bidirectional data bus.
4.5 USB Boot Methods
During the power-up sequence, internal logic checks the I2C
port for the connection of an EEPROM whose first byte is
eith er 0x C0 or 0x C 2. I f f ou n d, it us es th e V ID/ PI D/ D ID val u es
in the EEPROM in place of the internally stored values (0xC0),
or it boot-loads the EEPROM contents into internal RAM
(0xC2). If no EEPROM is detected, FX1 enumerates using
inter nally stored descriptors. The default ID v alues for FX1 a re
VID/PID/DID (0x04B4, 0x6473, 0xAxxx where xxx=Chip
revision).[2]
4.6 ReNumeration™
Because the FX1’s configuration is soft, one chip can take on
the identities of multiple distinct USB devices.
When first plugged into USB, the FX1 enumerates automati-
cally a nd downl oads fi rmwa re and USB des cr iptor t ables over
the USB cable. Next, the FX1 enumerates again, this time as
a device defined by the downloaded information. This
patented two-step process, called ReNumeration, happens
instantly when the device is plugged in, with no hint that the
initial download step has occurred.
Two control bits in the USBCS (USB Control and Status)
register control the ReNumeration process: DISCON and
RENUM. To simulate a USB disconnect, the firmware sets
DISCON to 1. To reconnect, the firmwa re clears DISCON to 0.
Before reconnecting, the firmware sets or clears the RENUM
bit to i ndicate wh ether the f irmware or t he Default USB Device
will h andle de vice req uests over end point zero: if R ENUM = 0,
the Default USB Device will handle device requests; if RENUM
= 1, the firmware will.
4.7 Bus-powered Applications
The FX1 fully supports bus-powered designs by enumerating
with less than 100 mA as required by the USB specification.
4.8 Interrupt System
4.8.1 INT2 Interrupt Request and Enable Registers
FX1 implements an autovector feature for INT2 and INT4.
There are 27 INT2 (USB) vectors, and 14 INT4 (FIFO/GPIF)
vectors. See EZ-USB Technical Reference Manual (TRM) for
more details.
Note:
2. The I2C bus SCL and SDA pins must be pulled up, even if an EEPROM is not connected. Otherwise this detection method does not work properly.
Table 4-1. Special Function Registers
x8x 9x Ax Bx CxDxExFx
0IOA IOB IOC IOD SCON1 PSW ACC B
1SP EXIF INT2CLR IOE SBUF1
2DPL0 MPAGE INT4CLR OEA
3DPH0 OEB
4DPL1 OEC
5DPH1 OED
6DPS OEE
7PCON
8 TCON SCON0 IE IP T2CON EICON EIE EIP
9 TMOD SBUF0
ATL0AUTOPTRH1 EP2468STAT EP01STAT RCAP2L
BTL1AUTOPTRL1 EP24FIFOFLGS GPIFTRIG RCAP2H
CTH0reserved EP68FIFOFLGS TL2
DTH1AUTOPTRH2 GPIFSGLDATH TH2
ECKCON AUTOPTRL2 GPIFSGLDATLX
Freserved AUTOPTRSETUP GPIFSGLDATLNOX
Table 4-2. Default ID Values for FX1
Default VID/PID/DID
Vendor ID 0x04B4 Cypress Semiconductor
Product ID 0x6473 EZ-USB FX1
Device
release 0xAnnn Depends chip revision (nnn = chip
revision where first silicon = 001)
CY7C64713/14
Document #: 38-08039 Rev. *B Page 4 of 50
4.8.2 USB-Interrupt Autov ectors
The main USB interrupt is shared by 27 interrupt sources. To
save the code and processing time that normally would be
required to identify the individual USB interrupt source, the
FX1 provides a second level of interrupt vectoring, called
Autovectoring. When a USB interrupt is asserted, the FX1
pushes the program counter onto its stack then jumps to
address 0x0043, where it expects to find a “jump” instru ction
to the USB Interrupt service routine.
The FX1 jump instruction is encoded as shown in Table 4-3.
If Autovectoring is enabled (AV2EN = 1 in the INTSETUP
register), the FX1 substitutes its INT2VEC byte. Therefore, if
the high by te (“page”) of a jump-table address is preloaded at
location 0x0044, the automatically-inserted INT2VEC byte at
0x0045 w ill direct the jump to the co rrect address out of th e 27
address es within the p ag e.
4.8.3 FIFO/GPIF Interrupt (INT4)
Just a s the U SB Inte rrupt is shar ed amon g 27 indiv idual USB-
interrupt sources, the FIFO/GPIF interrupt is shared among 14
individual FIFO/GPIF sources. The FIFO/GPIF Interrupt, like
the USB Interrupt, can employ autovectoring. Table 4-4 shows
the priority and INT4VEC values for the 14 FIFO/GPIF
interr upt sources.
Table 4-3. INT2 USB Interrupts
USB INTERRUPT TABLE FOR INT2
Priority INT2VEC Value Source Notes
1 00 SUDAV Setup Data Available
2 04 SO F Start of Fra me
3 08 SUTOK Setup Token Received
4 0C SUSPEND USB Suspend request
5 10 USB RESET Bus reset
6 14 reserved
7 18 EP0ACK FX1 ACK’d the CONTROL Handshake
8 1C reserved
9 20 EP0-IN EP0-IN ready to be loaded with data
10 24 EP0-OUT EP0-OUT has USB data
11 28 EP1-IN EP1-IN ready to be loaded with data
12 2C EP1-OUT EP1-OUT has USB data
13 30 EP2 IN: buffer available. OUT: buffer has data
14 34 EP4 IN: buffer available. OUT: buffer has data
15 38 EP6 IN: buffer available. OUT: buffer has data
16 3C EP8 IN: buffer available. OUT: buffer has data
17 40 IBN IN-Bulk-NAK (any IN endpoint)
18 44 reserved
19 48 EP0PING EP0 OUT was Pinged and it NAK’d
20 4C EP1PING EP1 OUT was Pinged and it NAK’d
21 50 EP2PING EP2 OUT was Pinged and it NAK’d
22 54 EP4PING EP4 OUT was Pinged and it NAK’d
23 58 EP6PING EP6 OUT was Pinged and it NAK’d
24 5C EP8PING EP8 OUT was Pinged and it NAK’d
25 60 ERRLIMIT Bus errors exceeded the programmed limit
26 64
27 68 reserved
28 6C reserved
29 70 EP2ISOERR ISO EP2 OUT PID sequence error
30 74 EP4ISOERR ISO EP4 OUT PID sequence error
31 78 EP6ISOERR ISO EP6 OUT PID sequence error
32 7C EP8ISOERR ISO EP8 OUT PID sequence error
CY7C64713/14
Document #: 38-08039 Rev. *B Page 5 of 50
If Autovectoring is enabled (AV4EN = 1 in the INTSETUP
register), the FX1 substitutes its INT4VEC byte. Therefore, if
the high by te (“page”) of a jump-table address is preloaded at
location 0x0054, the automatically-inserted INT4VEC byte at
0x0055 will dire ct the jump to the correct add ress out of the 14
addresses within the page. When the ISR occurs, the FX1
pushes the program counter onto its stack then jumps to
address 0x0053, where it expects to find a “jump” instru ction
to the ISR Interrupt service routine.
4.9 Reset and Wakeup
4.9.1 Reset Pin
The input pin, RESET#, will reset the FX1 when asserted. This
pin has hysteresis and is active LOW. When a crystal is used
with the CY7C64713/4 the reset period must allow for the
stabilization of the crystal and the PLL. This reset period
should be approximately 5 ms after VCC has reached 3.0
Volts. If the crystal input pin is driven by a clock signal the
internal PLL stabilizes in 200 µs after VCC has reached
3.0V[3]. Figure 4-2 shows a power on reset condition and a
reset applied during operation. A power on reset is defined as
the time reset is asserted while power is being applied to the
circuit. A powered reset is defined to be when the FX1 has
previously been powered on and operating and the RESET#
pin is asserted.
Cypress provides an application note which describes and
recommends power on reset implementation and can be found
on the Cy press web si te. While the a pplicatio n note disc usses
the FX2, th e inform ation provid ed app lies a lso to the FX1. F or
more informa tion on reset i mplem entation f or the FX2 fami ly
of products visit the http://www.cypress.com.
Note:
3. If the external clock is powered at the same time as the CY7C64713/4 and has a stabilization wait period, it must be added to the 200 µs.
Table 4-4. Individual FIFO/GPIF Interrupt Sources
Priority INT4VEC Value Source Notes
1 80 EP2PF Endpoint 2 Programmable Flag
2 84 EP4PF Endpoint 4 Programmable Flag
3 88 EP6PF Endpoint 6 Programmable Flag
4 8C EP8PF Endpoint 8 Programmable Flag
5 90 EP2EF Endpoint 2 Empty Flag
6 94 EP4EF Endpoint 4 Empty Flag
7 98 EP6EF Endpoint 6 Empty Flag
8 9C EP8EF Endpoint 8 Empty Flag
9 A0 EP2FF Endpoint 2 Full Flag
10 A4 EP4FF Endpoint 4 Full Flag
11 A 8 EP6FF Endpoint 6 Full Flag
12 AC EP8FF Endpoint 8 Full Flag
13 B0 GPIFDONE GPIF Operation Complete
14 B4 GPIFWF GP IF Waveform
CY7C64713/14
Document #: 38-08039 Rev. *B Page 6 of 50
4.9.2 Wakeup Pins
The 8051 pu ts it self and the rest of the chip in to a power-down
mode by setting PCON.0 = 1. This stops the oscillator and
PLL. When WAKEUP is asserted by external logic, the oscil-
lator restarts, after the PLL stabilizes, and then the 8051
receives a wakeup interrupt. This applies whether or not FX1
is connected to the USB.
The FX1 exits the power-down (USB suspend) state using one
of the following methods:
•USB bus activity (if D+/D– lines are left floating, noise on
these lines may indicate activity to the FX1 and initiate a
wakeup).
•External logic asserts the WAKEUP pin
•External logic asser ts the PA3/WU 2 pin.
The second wakeup pin, WU2, can also be configured as a
general purpose I/O pin. This allows a simple external R-C
network to be used as a periodic wakeup source. Note that
WAKEUP is by default active low.
4.10 Program/Data RAM
4.10.1 Size
The FX1 has 1 6 KBytes of inter nal progr am/ dat a RAM, whe re
PSEN#/RD# signals are internally ORed to allow the 8051 to
access it as both program and data memory. No USB control
registers appear in this space.
Two memory maps are shown in the following diagrams:
Figure 4-3 Internal Code Memory, EA = 0
Figure 4-4 External Code Memory, EA = 1.
4.10.2 Internal Code Memory, EA = 0
This mode implements the internal 16-KByte block of RAM
(starting at 0) as combined code and data memory. When
external RAM or ROM is added, the external read and write
strobes are suppressed for memory spaces that exist inside
the chip. This allows the user to connect a 64-KByte memory
without requiring address decodes to keep clear of internal
memory spaces.
Only the internal 16 KBytes and scratch pad 0.5 KBytes RAM
spaces have the following access:
•USB download
•USB upload
•Setup data pointer
•I2C interface boot load.
4.10.3 External Code Memory, EA = 1
The bottom 16 KBytes of program memory is external, and
therefore the bottom 16 KBytes of internal RAM is accessible
only as data memory.
Figure 4-2. Reset Timing Plots
VIL
0V
3.3V
3.0V
TRESET
VCC
RESET#
Power on Reset
TRESET
VCC
RESET# VIL
Powered Reset
3.3V
0V
Table 4-5. Reset Timing Values
Condition TRESET
Power-On Reset with crystal 5 ms
Power-On Reset with external
clock 200 µs + Clock stability time
Powered Reset 200 µs
CY7C64713/14
Document #: 38-08039 Rev. *B Page 7 of 50
Figure 4-3. Internal Code Memory, EA = 0
Inside FX1 Outside FX1
7.5 KBytes
USB regs and
4K FIFO buffers
(RD#,WR#)
0.5 KBytes RAM
Data (RD#,WR#)*
(OK to populate
data memory
here—RD#/WR#
strobes are not
active)
40 KBytes
External
Data
Memory
(RD#,WR#)
(Ok to populate
data memory
here—RD#/WR#
strobes are not
active)
16 KBytes RAM
Code and Data
(PSEN#,RD#,WR#)*
48 KBytes
External
Code
Memory
(PSEN#)
(OK to populate
program
memory here—
PSEN# strobe
is not active)
*SUDPTR, USB upload/download, I2C interface boot access
FFFF
E200
E1FF
E000
3FFF
0000 Data Code
Figure 4-4. External Code Memory, EA = 1
Inside FX1 Outside FX1
7.5 KBytes
USB regs and
4K FIFO buffers
(RD#,WR#)
0.5 KBytes RAM
Data (RD#,WR#)*
(OK to populate
data memory
here—RD#/WR#
strobes are not
active)
40 KBytes
External
Data
Memory
(RD#,WR#)
(Ok to populate
data memory
here—RD#/WR#
strobes are not
active)
16 KBytes
RAM
Data
(RD#,WR#)*
64 KBytes
External
Code
Memory
(PSEN#)
*SUDPTR, USB upload/download, I2C interface boot access
FFFF
E200
E1FF
E000
3FFF
0000 Data Code
CY7C64713/14
Document #: 38-08039 Rev. *B Page 8 of 50
4.11 Register Addresses
4.12 Endpoint RAM
4.12.1 Size
•3 × 64 bytes (Endpoints 0 and 1)
•8 × 512 bytes (Endpoints 2, 4, 6, 8)
4.12.2 Organization
•EP0—Bidirectional endpoint zero, 64-byte buffer
•EP1IN, EP1OUT—64-byte buffers, bulk or interrupt
•EP2,4,6,8—Eight 512-byte buffers, bulk, interrupt, or isoch-
ronous, of which only the transfer size is available.
EP4 and EP8 can be double buffered, while EP2 and 6 can
be either double, triple, or quad buffered. Regardless of the
physic al si ze of the bu f fe r, eac h en d point buffer accommo-
dates only one full -speed packet. For bulk endpoints the
maximum number of byt es it can accommoda te is 64, even
though the physical buffer size is 512 or 1024. For an
ISOCHRONOUS endpoint the maximum number of bytes
it can accommodate is 1023. For endpoint configuration
options, see Figure 4-5.
4.12. 3 S e tup Data Buffer
A separate 8-byte buffer at 0xE6B8-0xE6BF holds the Setup
data from a CONTRO L transfe r.
FFFF
E800
E7BF
E740
E73F
E700
E6FF
E500
E4FF
E480
E47F
E400
E200
E1FF
E000
E3FF
EFFF 2 KBytes RESERVED
64 Bytes EP0 IN/OUT
64 Bytes RESERVED
8051 Addr essa ble Regi ste rs
Reserved (128)
128 b ytes GPIF Wavef orms
512 bytes
8051 xdata RAM
F000
(512)
Reser ved (51 2)
E780 64 Bytes EP1OUT
E77F
64 Bytes EP1IN
E7FF
E7C0
4 KBytes EP2-EP8
buffers
(8 x 512)
Not all Space is available
for all transfer types
CY7C64713/14
Document #: 38-08039 Rev. *B Page 9 of 50
4.12.4 Endpoint Configurations
Endpoints 0 and 1 are the same for every configuration.
Endpoint 0 is the only CONTROL endpoint, and endpoint 1 can
be either BULK or INTERRUPT. The endpoint buffers can be
configured in any 1 of the 12 configurations shown in the
vertical c ol um ns. In full-spe ed, BU LK mod e u se s onl y the firs t
64 bytes of each buffer, even though memory exists for the
allocation of the isochronous transfers in BULK mode the
unused endpo int buf fer sp ace is not av ailab le for other opera-
tions. An example endpoint conf igura tion would be:
EP2—1023 dou ble buf fere d; EP6—64 quad buffered (column
8).
4.12.5 Default Alternate Settings
4.13 Extern al FI FO Inte rf ace
4.13.1 Architecture
The FX1 slave FIF O arc hit ec ture has eight 5 12-byte blocks i n
the e ndpo i nt RA M tha t d ire ct l y s er v e a s FIF O m emori e s, and
are controlled by FIFO control signals (such as IFCLK, SLCS#,
SLRD, SLWR, SLOE, PKTEND, and flags). The usa ble size of
these b uf fers depen d on the USB t rans fer mode as des c ribe d
in Section 4.12.2.
In ope rati on, some of the ei ght RAM bl ocks fill or empt y fro m
the SIE, while the others are connected to the I/O transfer
logic. The transfer logic takes two forms, the GPIF for internally
generated control signals, or the slave FIFO interface for
externally controlled transfers.
4.13.2 Master/Slave Control Signals
The FX1 end point FIFOS ar e implemente d as eight physi cally
distinct 256x16 RAM blocks. The 8051/SIE can switch any of
the RAM bl ocks betwe en two domain s, the USB (SIE) domai n
and the 8051-I/O U n it do ma in. This swi t ch in g is don e vi rtually
instantaneously, giving essentially zero transfer time between
“USB FIFOS” and “Slave FIFOS.” Since they are physically the
same memory, no bytes are actually transferred between
buffers.
Notes:
4. “0” means “not implemented.”
5. “2×” means “double bu ffered.”
64
64
64
64
64
1023
1023
1023
1023
1023
1023
1023
64
64
64
64
64
64
64
64
64
64
EP2 EP2 EP2
EP6
EP6
EP8 EP8
EP0 IN&OUT
EP1 IN
EP1 OUT
Figure 4-5. Endpoint Configuration
1023
1023
EP6 1023
64
64
EP8
64
64
EP6
64
64
64
64
EP2
64
64
EP4
64
64
EP2
64
64
EP4
64
64
EP2
64
64
EP4
64
64
EP2
64
64
64
64
EP2
64
64
64
64
EP2
64
64
1023
EP2
1023
1023
EP2
1023
1023
EP2
1023
64
64
EP6
1023
1023
EP6
64
64
EP8
64
64
EP6
64
64
64
64
EP6
1023
1023
EP6
64
64
EP8
64
64
EP6
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
12345678910 11 12
Table 4-6. Default Alternate Settings[4, 5 ]
Alternate
Setting 0 1 2 3
ep0 64 64 64 64
ep1out 0 64 bulk 64 int 64 int
ep1in 0 64 bulk 64 int 64 int
ep2 0 64 bulk out (2×)64 int out (2×) 64 iso out (2×)
ep4 0 64 bulk out (2×) 64 bulk out (2×)64 bul k out (2×)
ep6 0 64 bulk in (2×) 64 int in (2×) 64 iso in (2×)
ep8 0 64 bulk in (2×) 64 bulk in (2×) 64 bulk in (2×)
CY7C64713/14
Document #: 38-08039 Rev. *B Page 10 of 50
At any given time, some RAM blocks are filling/emptying with
USB data under SIE control, while other RAM blocks are
available to the 8051 and/or the I/O control unit. The RAM
blocks operate as single-port in the USB domain, and dual-
port in the 8 051-I/O domai n. Th e bl oc ks can be c onf igu r ed a s
single, double, triple, or quad buffered as previously shown.
The I/O control unit implements either an internal-master (M
for master) or external-master (S for Slave) interface.
In Master (M) mode, the GPIF internally controls
FIFOADR[1..0 ] to select a FIFO. Th e RDY pins (two in the 56-
pin pa ckage , six in the 10 0-pin and 128-pin p ackage s) ca n be
used as flag inputs from an external FIFO or other logic if
desired . The GP IF can b e run from either an internal ly der ived
clock or externally supplied clock (IFCLK), at a rate that
transfers data up to 96 Megabytes/s (48-MHz IFCLK with 16-
bit interface).
In Slave (S) mode, the FX1 accepts either an internally derived
clock or externally supplied clock (IFCLK, max. frequency 48
MHz) and SLCS#, SLRD, SLWR, SLOE, PKTEND signals
from external logic. When using an external IFCLK, the
external clock must be present before swit ching to the external
clock with the IFCLKSRC bit. Each endpoint can individually
be selected for byte or word operation by an internal configu-
ration bit, and a Slave FIFO Output Enable signal SLOE
enables data of the selected width. External logi c mu st in su re
that the outpu t enab le sign al is inac tive when writing data to a
slave FIFO. The slave interface can also operate asynchro-
nously, where the SLRD and SLWR signals act directly as
strobes , rather tha n a cloc k qual ifier as in synchr onous m ode.
The signals SLRD, SLWR, SLOE and PKTEND are gated by
the signal SLCS#.
4.13.3 GPIF and FIFO Clock Rates
An 8051 register bit selects one of two frequencies for the
inter nally su ppl ied i nterfac e clock : 30 M Hz and 48 MHz. Alt er-
natively, an externally supplied clock of 5 MHz–48 MHz
feeding the IFCLK pin can be used as the interface clock.
IFCLK can be configured to function as an output clock when
the GPIF and FIFOs are internally clocked. An output enable
bit in the IFCONFIG register turns this clock output off, if
desired. Another bit within the IFCONFIG register will invert
the IFCLK signal whether internally or externally sourced.
4.14 GPIF
The GPIF is a flexible 8- or 16-bit parallel interface driven by a
user-programmable finite state machine. It allows the
CY7C64713/4 to perform local bus mastering, and can
implement a wide variety of protocols such as ATA interface,
printer parallel port, and Utopia.
The GPIF has six programmable control outputs (CTL), nine
address outputs (GPIFADRx), and six general-purpose ready
inputs (RDY). The data bus width can be 8 or 16 bits. Each
GPIF vector defines the state of the control outputs, and deter-
mines what state a ready input (or multiple inputs) must be
before proceeding. The GPIF vector can be programmed to
advance a FIFO to the next data value, advance an address,
etc. A sequence of the GPIF vectors make up a single
waveform that will be executed to perform the desired data
move between the FX1 and the external device.
4.14.1 Six Control OUT Signals
The 100- and 128-pin packages bring out all six Control Output
pins (CTL0-CTL5). The 8051 programs the GPIF unit to define
the CTL waveforms. The 56-pin package brings out three of
these signals, CTL0–CTL2. CTLx waveform edges can be
programmed to make transitions as fast as once per clock
(20.8 ns using a 48-MHz clock).
4.14.2 Six Ready IN Signals
The 100- and 128- pin p ac k ages bring out all six Re ady in puts
(RDY0–RDY5). The 8051 programs the GPIF unit to test the
RDY pins for GPIF branching. The 56-pin package brings out
two of these signals, RDY0–1.
4.14.3 Nine GPIF Address OUT Signals
Nine GPIF a ddress line s are avai lable in th e 100 - and 128-pi n
packages, GPIFADR[8..0]. The GPIF address lines allow
indexing through up to a 512-byte block of RAM. If more
address lines are needed, I/O port pins can be used.
4.14.4 Long Transfer Mode
In maste r mode, the 8051 app ropriate ly set s GPIF trans action
count registers (GPIFTCB3, GPIFTCB2, GPIFTCB1, or
GPIFTCB 0) for unattended transfe rs of up to 232 transa ctions.
The GPIF automa tical ly thro ttles dat a flow to preven t under or
overflow until the full number of requested transactions
complete. The GPIF decrements the value in these registers
to represent the current status of the transaction.
4.15 ECC Generation
The EZ-USB FX1 can calculate ECCs (Error-Correcting
Codes) on data that passes across its GPIF or Slave FIFO
interfaces. There are two ECC configurations: Two ECCs,
each calculated over 256 bytes (SmartMedia™ Standard); and
one ECC calculated over 512 bytes.
The ECC can correct any one-bit error or detect any two-bit
error.
Note: To use the ECC lo gic, t he GPI F or Slav e FIFO inte rface
must be configured for byte-wide operation.
4.15.1 ECC Implementation
The two ECC configurations are selected by the ECCM bit:
4.15.1.1 ECCM = 0
Two 3-byte ECCs, each calculated over a 256-byte block of
data. This configuration conforms to the SmartMedia
Standard.
Write any value to ECCRESET, then pass data across the
GPIF or Slave FIF O interface . The ECC for the first 256 bytes
of dat a will be calc ulated and s tored in ECC1. The ECC for the
next 256 bytes will be stored in ECC2. After the second ECC
is calc ulated , the va lues in the ECCx reg isters will not ch ange
until ECCRESET is written again, ev en if more dat a is subse-
quently passed across the interface.
4.15.1.2 ECCM=1
One 3-byte ECC calculated over a 512-byte block of data.
Write any value to ECCRESET then pass data across the
GPIF or Slave FIF O interface . The ECC for the first 512 bytes
of data will be calculated and stored in ECC1; ECC2 is unused.
Aft er the ECC is cal culated, t he value in ECC1 will no t change
CY7C64713/14
Document #: 38-08039 Rev. *B Page 11 of 50
until ECCRESET is written aga in, ev en if more dat a is subse-
quently passed across the interface
4.16 USB Uploads and Downloads
The core h as the abi lity to dire ctly e dit the dat a conte nts of th e
internal 16 KByte RAM and of the internal 512-byte scratch
pad RAM via a vendor-specific command. This capability is
normally used when “soft” downloading user code and is
available only to and from internal RAM, only when the 8051
is held in reset. The available RAM spaces are 16 KBytes from
0x0000–0x3FFF (code/data) and 512 bytes from
0xE000–0xE1FF (scratch pad data RAM).[6]
4.17 Autopointer Access
FX1 provides two identical autopointers. They are similar to
the intern al 80 51 data poi nters, but with an ad dit ion al fe atu re:
they can optionally increment after every memory access. This
capability is available to and from both internal and external
RAM. The autopointers are available in external FX1 registers,
under control of a mode bit (AUTOPTRSETUP.0). Using the
external FX1 autopointer access (at 0xE67B – 0xE67C) allows
the aut opo inter t o acces s al l RAM, interna l and exte rnal to the
part. Also, the autopointers can point to any FX1 register or
endpoint buffer space. When autopointer access to external
memory is enabled, location 0xE67B and 0xE67C in XDATA
and code space cannot be used.
4.18 I2C Controller
FX1 h as o ne I2C port that is driv en by two i nte rna l c on trol lers ,
one that automatically operates at boot time to load
VID/PID/DID and configuration information, and another that
the 8051, once running, uses to control external I2C devices.
The I2C port operat es in master mode on ly.
4.18.1 I2C Port Pins
The I2C- pins SCL and SDA must have external 2.2-kΩ pull-
up resistors even if no EEPROM is connected to the FX1.
External EEPROM device address pins must be configured
properly. See Table 4-7 for configuring the device address
pins.
4.18.2 I2C Interface Boot Load Access
At power-on reset the I2C interface boot loader will load the
VID/PID/DID configuration bytes and up to 16 KBytes of
progra m/dat a. The availa ble RA M sp aces ar e 16 KBytes from
0x0000–0x3FFF and 512 bytes from 0xE000–0xE1FF. The
8051 will be in reset. I2C interface boot loads only occur after
power-on reset.
4.18.3 I2C Interface General Purpose Access
The 8051 can control peripherals connected to the I2C bus
using t he I2CTL and I2DA T registers. FX1 provides I2C master
control only, it is never an I2C sl ave.
4.19 Compatible with Previous Generation
EZ-USB FX2
The EZ-USB FX1 is fit/form/function-upgradable to the EZ-
USB FX2LP. This makes for a easy transition for designers
wanting to upgrade their systems from full-speed to the high-
speed designs. The pinout and package selection are
identical, and all of the firmware developed for the FX1 will
function in the FX2LP with proper addition of High Speed
descriptors and speed switching code.
5.0 Pin Assignments
Figure 5-1 identifies all signals for the three package types.
The follow ing pages illustra te the individual pin diagra ms, plus
a combin ation diag ram showin g which of the ful l set of signal s
are available in the 128-, 100-, and 56-pin packages.
The sig nals on t he lef t edge of the 56-p in pac kage in Figure 5-
1 are common to all versions in the FX1 family. Three modes
are av ail abl e in all pac kage vers ions: Port , GPI F maste r, and
Slave FIFO . These modes defi ne the signals on the right edge
of the diagram. The 8051 select s the in terface m ode usin g the
IFCONFIG[1:0] register bits. Port mode is the power-on default
configuration.
The 100- pin pa ckage adds function al ity to the 56 -pin p ack age
by adding thes e pin s:
•PORTC or alternate GPIFADR[7:0] address signals
•PORTE or alternate GPIF ADR[8] address signal and seven
additional 8051 signals
•Three GPIF Co ntro l signals
•Four GPIF Ready signals
•Nine 8051 signals (two USARTs, three timer inputs,
INT4,and INT5#)
•BKPT, RD#, WR#.
The 128-pin package adds the 8051 address and data buses
plus c ontrol signals . Note th at two of the required s ignals, RD#
and WR#, are present in the 100-pin version. In the 100-pin
and 128-pin versions, an 8051 control bit can be set to pulse
the RD# and WR# pins when the 8051 reads from/writes to
PORTC.
Notes:
6. After the data has been downloaded from the host, a “loader” can execute from internal RAM in order to transfer downloaded data to external memory.
7. This EEPROM does not have address pins.
Table 4-7. Strap Boot EEPROM Address Lines to These
Values
Bytes Example EEPROM A2 A1 A0
16 24LC00[7] N/A N/A N/A
128 24LC01 0 0 0
256 24LC02 0 0 0
4K 24LC32 0 0 1
8K 24LC64 0 0 1
16K 24LC128 0 0 1
CY7C64713/14
Document #: 38-08039 Rev. *B Page 12 of 50
RDY0
RDY1
CTL0
CTL1
CTL2
INT0#/PA0
INT1#/PA1
PA2
WU2/PA3
PA4
PA5
PA6
PA7
56
BKPT
PORTC7/GPIFADR7
PORTC6/GPIFADR6
PORTC5/GPIFADR5
PORTC4/GPIFADR4
PORTC3/GPIFADR3
PORTC2/GPIFADR2
PORTC1/GPIFADR1
PORTC0/GPIFADR0
PE7/GPIFADR8
PE6/T2EX
PE5/INT6
PE4/RxD1OUT
PE3/RxD0OUT
PE2/T2OUT
PE1/T1OUT
PE0/T0OUT
RxD0
TxD0
RxD1
TxD1
INT4
INT5#
T2
T1
T0
100
D7
D6
D5
D4
D3
D2
D1
D0
EA
128
RD#
WR#
CS#
OE#
PSEN#
A15
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
XTALIN
XTALOUT
RESET#
WAKEUP#
SCL
SDA
T0OUT
T1OUT
IFCLK
CLKOUT
DPLUS
DMINUS
FD[15]
FD[14]
FD[13]
FD[12]
FD[11]
FD[10]
FD[9]
FD[8]
FD[7]
FD[6]
FD[5]
FD[4]
FD[3]
FD[2]
FD[1]
FD[0]
SLRD
SLWR
FLAGA
FLAGB
FLAGC
INT0#/ PA0
INT1#/ PA1
SLOE
WU2/PA3
FIFOADR0
FIFOADR1
PKTEND
PA7/FLAGD/SLCS#
FD[15]
FD[14]
FD[13]
FD[12]
FD[11]
FD[10]
FD[9]
FD[8]
FD[7]
FD[6]
FD[5]
FD[4]
FD[3]
FD[2]
FD[1]
FD[0]
PD7
PD6
PD5
PD4
PD3
PD2
PD1
PD0
PB7
PB6
PB5
PB4
PB3
PB2
PB1
PB0
INT0#/PA0
INT1#/PA1
PA2
WU2/PA3
PA4
PA5
PA6
PA7
Port GPIF Master Slave FIFO
CTL3
CTL4
CTL5
RDY2
RDY3
RDY4
RDY5
Figure 5-1. Signals
CY7C64713/14
Document #: 38-08039 Rev. *B Page 13 of 50
CLKOUT
VCC
GND
RDY0/*SLRD
RDY1/*SLWR
RDY2
RDY3
RDY4
RDY5
AVCC
XTALOUT
XTALIN
AGND
NC
NC
NC
AVCC
DPLUS
DMINUS
AGND
A11
A12
A13
A14
A15
VCC
GND
INT4
T0
T1
T2
*IFCLK
RESERVED
BKPT
EA
SCL
SDA
OE#
PD0/FD8
*WAKEUP
VCC
RESET#
CTL5
A3
A2
A1
A0
GND
PA7/*FLAGD/SLCS#
PA6/*PKTEND
PA5/FIFOADR1
PA4/FIFOADR0
D7
D6
D5
PA3/*WU2
PA2/*SLOE
PA1/INT1#
PA0/INT0#
VCC
GND
PC7/GPIFADR7
PC6/GPIFADR6
PC5/GPIFADR5
PC4/GPIFADR4
PC3/GPIFADR3
PC2/GPIFADR2
PC1/GPIFADR1
PC0/GPIFADR0
CTL2/*FLAGC
CTL1/*FLAGB
CTL0/*FLAGA
VCC
CTL4
CTL3
GND
PD1/FD9
PD2/FD10
PD3/FD11
INT5#
VCC
PE0/T0OUT
PE1/T1OUT
PE2/T2OUT
PE3/RXD0OUT
PE4/RXD1OUT
PE5/INT6
PE6/T2EX
PE7/GPIFADR8
GND
A4
A5
A6
A7
PD4/FD12
PD5/FD13
PD6/FD14
PD7/FD15
GND
A8
A9
A10
CY7C64713/4
128-pin TQFP
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
VCC
D4
D3
D2
D1
D0
GND
PB7/FD7
PB6/FD6
PB5/FD5
PB4/FD4
RXD1
TXD1
RXD0
TXD0
GND
VCC
PB3/FD3
PB2/FD2
PB1/FD1
PB0/FD0
VCC
CS#
WR#
RD#
PSEN#
Figure 5-2. CY7C64713/4 128-pin TQFP Pin Assignment
* denotes pr ogrammable polarity
CY7C64713/14
Document #: 38-08039 Rev. *B Page 14 of 50
PD0/FD8
*WAKEUP
VCC
RESET#
CTL5
GND
PA7/*FLAGD/SLCS#
PA6/*PKTEND
PA5/FIFOADR1
PA4/FIFOADR0
PA3/*WU2
PA2/*SLOE
PA1/INT1#
PA0/INT0#
VCC
GND
PC7/GPIFADR7
PC6/GPIFADR6
PC5/GPIFADR5
PC4/GPIFADR4
PC3/GPIFADR3
PC2/GPIFADR2
PC1/GPIFADR1
PC0/GPIFADR0
CTL2/*FLAGC
CTL1/*FLAGB
CTL0/*FLAGA
VCC
CTL4
CTL3
PD1/FD9
PD2/FD10
PD3/FD11
INT5#
VCC
PE0/T0OUT
PE1/T1OUT
PE2/T2OUT
PE3/RXD0OUT
PE4/RXD1OUT
PE5/INT6
PE6/T2EX
PE7/GPIFADR8
GND
PD4/FD12
PD5/FD13
PD6/FD14
PD7/FD15
GND
CLKOUT
CY7C64713/4
100-pin TQFP
GND
VCC
GND
PB7/FD7
PB6/FD6
PB5/FD5
PB4/FD4
RXD1
TXD1
RXD0
TXD0
GND
VCC
PB3/FD3
PB2/FD2
PB1/FD1
PB0/FD0
VCC
WR#
RD#
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
VCC
GND
RDY0/*SLRD
RDY1/*SLWR
RDY2
RDY3
RDY4
RDY5
AVCC
XTALOUT
XTALIN
AGND
NC
NC
NC
AVCC
DPLUS
DMINUS
AGND
VCC
GND
INT4
T0
T1
T2
*IFCLK
RESERVED
BKPT
SCL
SDA
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
Figure 5-3. CY7C64713/4 100-pin TQFP Pin Assignment
* denotes programmable polarity
CY7C64713/14
Document #: 38-08039 Rev. *B Page 15 of 50
28
27
26
25
24
23
22
21
20
19
18
17
16
15
43
44
45
46
47
48
49
50
51
52
53
54
55
56
1
2
3
4
5
6
7
8
9
10
11
12
13
14
42
41
40
39
38
37
36
35
34
33
32
31
30
29
* denotes programmable polarity
RESET#
GND
PA7/*FLAGD/SLCS#
PA6/*PKTEND
PA5/FIFOADR1
PA4/FIFOADR0
PA3/*WU2
PA2/*SLOE
PA1/INT1#
PA0/INT0#
VCC
CTL2/*FLAGC
CTL1/*FLAGB
CTL0/*FLAGA
RDY0/*SLRD
RDY1/*SLWR
AVCC
XTALOUT
XTALIN
AGND
AVCC
DPLUS
DMINUS
AGND
VCC
GND
*IFCLK/**PE0/T0OUT
RESERVED
VCC
*WAKEUP
PD0/FD8
PD1/FD9
PD2/FD10
PD3/FD11
PD4/FD12
PD5/FD13
PD6/FD14
PD7/FD15
GND
CLKOUT/**PE1/T1OUT
VCC
GND
GND
VCC
GND
PB7/FD7
PB6/FD6
PB5/FD5
PB4/FD4
PB3/FD3
PB2/FD2
PB1/FD1
PB0/FD0
VCC
SDA
SCL
CY7C64713/4
56-pin QFN
Figure 5-4. CY7C64713/4 56-pin QFN Pin Assignment
CY7C64713/14
Document #: 38-08039 Rev. *B Page 16 of 50
5.1 CY7C64713/4 Pin Definitions
Table 5-1. FX1 Pin Definitions [8]
128
TQFP 100
TQFP 56
QFN Name Type Default Description
10 9 3 AVCC Power N/A Analog VCC. Connect this pin t o 3.3V power sourc e. This si gnal provid es
power to the analog section of the chip.
17 16 7 AVCC Power N/A Analog VCC. Connect this pin to 3.3V power source. This signa l provides
power to the analog section of the chip.
13 12 6 AGND Ground N/A Analog Ground. Connect to ground with as short a path as possible.
20 19 10 AGND Ground N/A Analog Ground. Connect to ground with as short a path as possible.
19 18 9 DMINUS I/O/Z Z USB D– Signal. Connect to the USB D– si gna l.
18 17 8 DPLUS I/O/Z Z USB D+ Signal. Connect to the USB D+ signal.
94 A0 Output L 8051 Address Bus. This bus is driven at all times. When the 8051 is
addressing internal RAM it reflects the internal address.
95 A1 Output L
96 A2 Output L
97 A3 Output L
117 A4 Output L
118 A5 Output L
119 A6 Output L
120 A7 Output L
126 A8 Output L
127 A9 Output L
128 A10 Output L
21 A11 Output L
22 A12 Output L
23 A13 Output L
24 A14 Output L
25 A15 Output L
59 D0 I/O/Z Z 8051 Data Bus. This bidirectional bus is high-impedance when inactive,
input for bus reads, and output for bus writes. The data bus is used for
external 8051 program and data memory. The data bus is active only for
external bus accesses, and is driven LOW in suspend.
60 D1 I/O/Z Z
61 D2 I/O/Z Z
62 D3 I/O/Z Z
63 D4 I/O/Z Z
86 D5 I/O/Z Z
87 D6 I/O/Z Z
88 D7 I/O/Z Z
39 PSEN# Output H Program Store Enable. This active-LOW signal indicates an 8051 code
fetch from external memory. It is active for program memory fetches from
0x4000–0xFFFF when th e EA pin is L OW, or fro m 0x00 00 –0xFFFF when
the EA pin is HIGH.
34 28 BKPT Output L Breakpoint. This pin goes active (HIGH) when the 8051 address bus
matches the BPADDRH/L registers and breakpoints are enabled in the
BREAKPT register (BPEN = 1). If the BPPULSE bit in the BREAKPT
register i s HI GH, this sig nal pu lses HIGH for eigh t 12-/24 -/48-MH z cloc ks.
If the BPPULSE bit is LOW, the signal rema ins HIGH until the 8051 clears
the BREAK bit (by writing 1 to it) in the BREAKPT register.
Note:
8. Unused inputs should not be left floating. Tie either HIGH or LOW as appropriate. Outputs should only be pulled up or down to ensure signals at power-up
and in standby. Note also that no pins should be driven while the device is powered down.
CY7C64713/14
Document #: 38-08039 Rev. *B Page 17 of 50
99 77 42 RESET# Input N/A Active LOW Reset. Resets the entire chip. See section 4.9 ”Reset and
Wakeup”on page 5 for more details.
35 EA Input N/A External Access. This pin determines where the 8051 fetches code
between addresses 0x0000 and 0x3FFF. If EA = 0 the 8051 fetches this
code from its internal RAM. IF EA = 1 the 8051 fetches this code from
external me mo ry.
12 11 5 XTALIN Input N/A Crystal Input. Connect this signal to a 24-MHz parallel-resonant, funda-
mental mode crystal and load capacitor to GND .
It is also correct to drive XTALIN with an external 24 MHz square wave
derived f rom an other c lock source. W hen driving from an extern al so urce,
the driving signal should be a 3.3V square wave.
11 10 4 XTALOUT Output N/A Cryst al Outp ut. Co nnect this signa l to a 24-MH z p aral lel-res onant, funda-
mental mode crystal and load capacitor to GND .
If an external clock is used to drive XTALIN, leave this pin open.
1 100 54 CLKOUT O/Z 12
MHz CLKOUT: 12-, 24- or 48-MHz clock, phase locked to the 24-MHz input
clock. The 8051 defaults to 12-MHz operation. The 8051 may three-state
this output by setting CPUCS.1 = 1.
Port A
82 67 33 PA0 o r
INT0# I/O/Z I
(PA0) Multiplexed pin whose function is selected by PORTACFG.0
PA0 is a bidirectional IO port pin.
INT0# is the active-LOW 8051 INT0 interrupt input signal, which is either
edge triggered (IT0 = 1) or level triggered (IT0 = 0).
83 68 34 PA1 o r
INT1# I/O/Z I
(PA1) Multiplexed pin whose function is selected by:
PORTACFG.1
PA1 is a bidirectional IO port pin.
INT1# is the active-LOW 8051 INT1 interrupt input signal, which is either
edge triggered (IT1 = 1) or level triggered (IT1 = 0).
84 69 35 PA2 o r
SLOE I/O/Z I
(PA2) Multiplexed pin whose function is selected by two bits:
IFCONFIG[1:0].
PA2 is a bidirectional IO port pin.
SLOE is an input-only output enable with programmable polarity (FIFOPIN-
POLAR.4) for the slave FIFOs connected to FD[7..0] or FD[15..0].
85 70 36 PA3 o r
WU2 I/O/Z I
(PA3) Multiplexed pin whose function is selected by:
WAKEUP.7 and OEA.3
PA3 is a bidirectional I/O port pin.
WU2 is an alternate source for USB W ake up, enabled by WU2EN bit
(WAKEUP.1) and polarity set by WU2POL (WAKEUP.4). If the 8051 is in
suspend and WU2EN = 1, a transition on this pin starts up the oscillator
and interrupts the 8051 to allow it to exit the suspend mode. Asserting this
pin inhibits the chip from suspending, if WU2EN=1.
89 71 37 PA4 o r
FIFOADR0 I/O/Z I
(PA4) Multiplexed pin whose function is selected by:
IFCONFIG[1..0].
PA4 is a bidirectional I/O port pin.
FIFOADR0 is a n i npu t-on ly a ddre ss s ele ct fo r th e s la ve FIFOs con nec ted
to FD[7..0] or FD[15..0].
90 72 38 PA5 o r
FIFOADR1 I/O/Z I
(PA5) Multiplexed pin whose function is selected by:
IFCONFIG[1..0].
PA5 is a bidirectional I/O port pin.
FIFOADR1 is a n i npu t-on ly a ddre ss s ele ct fo r th e s la ve FIFOs con nec ted
to FD[7..0] or FD[15..0].
91 73 39 PA6 o r
PKTEND I/O/Z I
(PA6) Multiplexed pin whose function is selected by the IFCONFIG[1:0] bits.
PA6 is a bidirectional I/O port pin.
PKTEND is an inpu t used to commit th e FIF O pack et dat a to th e end po int
and whose polarity is programmable via FIFOPINPOLAR.5.
Table 5-1. FX1 Pin Definitions (continued)[8]
128
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92 74 40 PA7 o r
FLAGD or
SLCS#
I/O/Z I
(PA7) Multiplexed pin whose function is selected by the IFCONFIG[1:0] and
PORTACFG.7 bit s .
PA7 is a bidirectional I/O port pin.
FLAGD is a programmable slave-FIFO output status flag signal.
SLCS# gates all other slave FIFO enable/strobes
Port B
44 34 18 PB0 or
FD[0] I/O/Z I
(PB0) Multiplexed pin whose function is selected by the following bits:
IFCONFIG[1..0].
PB0 is a bidirectional I/O port pin.
FD[0] is th e bidirec tional FIFO/GPIF data bus.
45 35 19 PB1 or
FD[1] I/O/Z I
(PB1) Multiplexed pin whose function is selected by the following bits:
IFCONFIG[1..0].
PB1 is a bidirectional I/O port pin.
FD[1] is th e bidirec tional FIFO/GPIF data bus.
46 36 20 PB2 or
FD[2] I/O/Z I
(PB2) Multiplexed pin whose function is selected by the following bits:
IFCONFIG[1..0].
PB2 is a bidirectional I/O port pin.
FD[2] is th e bidirec tional FIFO/GPIF data bus.
47 37 21 PB3 or
FD[3] I/O/Z I
(PB3) Multiplexed pin whose function is selected by the following bits:
IFCONFIG[1..0].
PB3 is a bidirectional I/O port pin.
FD[3] is th e bidirec tional FIFO/GPIF data bus.
54 44 22 PB4 or
FD[4] I/O/Z I
(PB4) Multiplexed pin whose function is selected by the following bits:
IFCONFIG[1..0].
PB4 is a bidirectional I/O port pin.
FD[4] is th e bidirec tional FIFO/GPIF data bus.
55 45 23 PB5 or
FD[5] I/O/Z I
(PB5) Multiplexed pin whose function is selected by the following bits:
IFCONFIG[1..0].
PB5 is a bidirectional I/O port pin.
FD[5] is th e bidirec tional FIFO/GPIF data bus.
56 46 24 PB6 or
FD[6] I/O/Z I
(PB6) Multiplexed pin whose function is selected by the following bits:
IFCONFIG[1..0].
PB6 is a bidirectional I/O port pin.
FD[6] is th e bidirec tional FIFO/GPIF data bus.
57 47 25 PB7 or
FD[7] I/O/Z I
(PB7) Multiplexed pin whose function is selected by the following bits:
IFCONFIG[1..0].
PB7 is a bidirectional I/O port pin.
FD[7] is th e bidirec tional FIFO/GPIF data bus.
PORT C
72 57 PC0 or
GPIFADR0 I/O/Z I
(PC0) Multiplexed pin whose function is selected by PORTCCFG.0
PC0 is a bidirectional I/O port pin.
GPIFADR0 is a GPIF address output pin.
73 58 PC1 or
GPIFADR1 I/O/Z I
(PC1) Multiplexed pin whose function is selected by PORTCCFG.1
PC1 is a bidirectional I/O port pin.
GPIFADR1 is a GPIF address output pin.
74 59 PC2 or
GPIFADR2 I/O/Z I
(PC2) Multiplexed pin whose function is selected by PORTCCFG.2
PC2 is a bidirectional I/O port pin.
GPIFADR2 is a GPIF address output pin.
75 60 PC3 or
GPIFADR3 I/O/Z I
(PC3) Multiplexed pin whose function is selected by PORTCCFG.3
PC3 is a bidirectional I/O port pin.
GPIFADR3 is a GPIF address output pin.
76 61 PC4 or
GPIFADR4 I/O/Z I
(PC4) Multiplexed pin whose function is selected by PORTCCFG.4
PC4 is a bidirectional I/O port pin.
GPIFADR4 is a GPIF address output pin.
Table 5-1. FX1 Pin Definitions (continued)[8]
128
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TQFP 56
QFN Name Type Default Description
CY7C64713/14
Document #: 38-08039 Rev. *B Page 19 of 50
77 62 PC5 or
GPIFADR5 I/O/Z I
(PC5) Multiplexed pin whose function is selected by PORTCCFG.5
PC5 is a bidirectional I/O port pin.
GPIFADR5 is a GPIF address output pin.
78 63 PC6 or
GPIFADR6 I/O/Z I
(PC6) Multiplexed pin whose function is selected by PORTCCFG.6
PC6 is a bidirectional I/O port pin.
GPIFADR6 is a GPIF address output pin.
79 64 PC7 or
GPIFADR7 I/O/Z I
(PC7) Multiplexed pin whose function is selected by PORTCCFG.7
PC7 is a bidirectional I/O port pin.
GPIFADR7 is a GPIF address output pin.
PORT D
102 80 45 PD0 or
FD[8] I/O/Z I
(PD0) Multiplexed pin whose function is selected by the IFCONFIG[1..0] and
EPxFIFOCFG.0 (wordwide) bits.
FD[8] is th e bidirec tional FIFO/GPIF data bus.
103 81 46 PD1 or
FD[9] I/O/Z I
(PD1) Multiplexed pin whose function is selected by the IFCONFIG[1..0] and
EPxFIFOCFG.0 (wordwide) bits.
FD[9] is th e bidirec tional FIFO/GPIF data bus.
104 82 47 PD2 or
FD[10] I/O/Z I
(PD2) Multiplexed pin whose function is selected by the IFCONFIG[1..0] and
EPxFIFOCFG.0 (wordwide) bits.
FD[10] is the bidirectional FIFO/GPIF data bus.
105 83 48 PD3 or
FD[11] I/O/Z I
(PD3) Multiplexed pin whose function is selected by the IFCONFIG[1..0] and
EPxFIFOCFG.0 (wordwide) bits.
FD[11] is the bidirectional FIFO/GPIF data bus.
121 95 49 PD4 or
FD[12] I/O/Z I
(PD4) Multiplexed pin whose function is selected by the IFCONFIG[1..0] and
EPxFIFOCFG.0 (wordwide) bits.
FD[12] is the bidirectional FIFO/GPIF data bus.
122 96 50 PD5 or
FD[13] I/O/Z I
(PD5) Multiplexed pin whose function is selected by the IFCONFIG[1..0] and
EPxFIFOCFG.0 (wordwide) bits.
FD[13] is the bidirectional FIFO/GPIF data bus.
123 97 51 PD6 or
FD[14] I/O/Z I
(PD6) Multiplexed pin whose function is selected by the IFCONFIG[1..0] and
EPxFIFOCFG.0 (wordwide) bits.
FD[14] is the bidirectional FIFO/GPIF data bus.
124 98 52 PD7 or
FD[15] I/O/Z I
(PD7) Multiplexed pin whose function is selected by the IFCONFIG[1..0] and
EPxFIFOCFG.0 (wordwide) bits.
FD[15] is the bidirectional FIFO/GPIF data bus.
Port E
108 86 PE0 or
T0OUT I/O/Z I
(PE0) Multiplexed pin whose function is selected by the PORTECFG.0 bit.
PE0 is a bidirectional I/O port pin.
T0OUT is an active-HIGH signal from 8051 Timer-counter0. T0OUT
outputs a high level for one CLKOUT clock cycle when Timer0 overflows.
If Timer0 is operated in Mode 3 (two separate timer/counters), T0OUT is
active when the low byte timer/counter overflows.
109 87 PE1 or
T1OUT I/O/Z I
(PE1) Multiplexed pin whose function is selected by the PORTECFG.1 bit.
PE1 is a bidirectional I/O port pin.
T1OUT is an active-HIGH signal from 8051 Timer-counter1. T1OUT
outputs a high level for one CLKOUT clock cycle when Timer1 overflows.
If Timer1 is operated in Mode 3 (two separate timer/counters), T1OUT is
active when the low byte timer/counter overflows.
110 88 PE2 or
T2OUT I/O/Z I
(PE2) Multiplexed pin whose function is selected by the PORTECFG.2 bit.
PE2 is a bidirectional I/O port pin.
T2OUT is the active-HIGH output signal from 8051 Timer2. T2OUT is active
(HIGH) for one clock cycle when Timer/Counter 2 overflows.
Table 5-1. FX1 Pin Definitions (continued)[8]
128
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TQFP 56
QFN Name Type Default Description
CY7C64713/14
Document #: 38-08039 Rev. *B Page 20 of 50
111 89 PE 3 or
RXD0OUT I/O/Z I
(PE3) Multiplexed pin whose function is selected by the PORTECFG.3 bit.
PE3 is a bidirectional I/O port pin.
RXD0OUT is an active-HIGH signal from 8051 UART0. If RXD0OUT is
selected and UART0 is in Mode 0, this pin provides the output data for
UAR T0 only w hen it is in sync mode. Otherw i se it is a 1.
112 90 PE4 or
RXD1OUT I/O/Z I
(PE4) Multiplexed pin whose function is selected by the PORTECFG.4 bit.
PE4 is a bidirectional I/O port pin.
RXD1OUT is an acti ve-HIG H output from 8 051 UA RT 1. When RXD 1OUT
is selected and UART1 is in Mode 0, this pin provides the output data for
UART1 only when it is in sync mode. In Modes 1, 2, and 3, this pin is HIGH.
113 91 PE5 or
INT6 I/O/Z I
(PE5) Multiplexed pin whose function is selected by the PORTECFG.5 bit.
PE5 is a bidirectional I/O port pin.
INT6 is the 80 51 IN T6 int errupt re quest input signal . The I NT6 p in is edge-
sensitive, active HIGH.
114 92 PE6 or
T2EX I/O/Z I
(PE6) Multiplexed pin whose function is selected by the PORTECFG.6 bit.
PE6 is a bidirectional I/O port pin.
T2EX is an active-high input signal to the 8051 T imer2. T2EX reloads timer
2 on its fall ing edge . T2EX i s activ e on ly if the EXEN2 bit is set in T2 CON.
115 93 PE7 or
GPIFADR8 I/O/Z I
(PE7) Multiplexed pin whose function is selected by the PORTECFG.7 bit.
PE7 is a bidirectional I/O port pin.
GPIFADR8 is a GPIF address output pin.
4 3 1 RDY0 or
SLRD Input N/A Multiplexed pin whose function is selected by the following bits:
IFCONFIG[1..0].
RDY0 is a GPIF input signal.
SLRD is the input-only read strobe with programmable polarity (FIFOPIN-
POLAR.3) for the slave FIFOs connected to FD[7..0] or FD[15..0].
5 4 2 RDY1 or
SLWR Input N/A Multiplexed pin whose function is selected by the following bits:
IFCONFIG[1..0].
RDY1 is a GPIF input signal.
SLWR is the input-only write strobe with programma ble polarity (FIFO PIN-
POLAR.2) for the slave FIFOs connected to FD[7..0] or FD[15..0].
6 5 RDY2 Input N/A RDY2 is a GPIF input signal.
7 6 RDY3 Input N/A RDY3 is a GPIF input signal.
8 7 RDY4 Input N/A RDY4 is a GPIF input signal.
9 8 RDY5 Input N/A RDY5 is a GPIF input signal.
69 54 29 CTL0 or
FLAGA O/Z H Multiplexed pin whose function is selected by the following bits:
IFCONFIG[1..0].
CTL0 is a GPIF control output.
FLAGA is a programmable slave-FIFO output status flag signal.
Default s to programmab le for the FIFO sele cted by the FIFOADR[1:0] pins.
70 55 30 CTL1 or
FLAGB O/Z H Multiplexed pin whose function is selected by the following bits:
IFCONFIG[1..0].
CTL1 is a GPIF control output.
FLAGB is a programmable slave-FIFO output status flag signal.
Defaults to FULL for the FIFO selected by the FIFOADR[1:0] pins.
71 56 31 CTL2 or
FLAGC O/Z H Multiplexed pin whose function is selected by the following bits:
IFCONFIG[1..0].
CTL2 is a GPIF control output.
FLAGC is a programmable slave-FIFO output status flag signal.
Defaults to EMPTY for the FIFO selected by the FIFOADR[1:0] pins.
66 51 CTL3 O/Z H CTL3 is a GPIF control output.
67 52 CTL4 Output H CTL4 is a GPIF control output.
98 76 CTL5 Output H CTL5 is a GPIF control output.
Table 5-1. FX1 Pin Definitions (continued)[8]
128
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TQFP 56
QFN Name Type Default Description
CY7C64713/14
Document #: 38-08039 Rev. *B Page 21 of 50
32 26 13 IFCLK I/O/Z Z Interface Clock, used for synchronously clocking data into or out of the
slave FIFOs. IFCLK also serves as a timing reference for all slave FIFO
control signals and GPIF. When internal clocking is used (IFCONFIG.7 = 1)
the IFCL K pin c an be con figured to outp ut 30/48 MH z by bit s IFCONF IG.5
and IFCON FIG.6. IFCLK may be in ve rted, whether inte rnally or externally
sourced, by setting the bit IFCONFIG.4 =1.
28 22 INT4 Input N/A INT4 is the 80 51 IN T4 int errupt re quest input signal . T he INT4 p in is edge-
sensitive, active HIGH.
106 84 INT5# Input N/A INT5# is the 8051 INT5 interrupt request input signal . The INT5 pin is edge-
sensitive, active LOW.
31 25 T2 Input N/A T2 is the active-HIGH T2 input signal to 8051 Timer2, which provides the
input to Timer2 when C/T2 = 1. When C/T2 = 0, Timer2 does not use this
pin.
30 24 T1 Input N/A T1 is the active -HIGH T1 signal for 80 51 Timer1, which pro vides the in put
to Timer1 when C/T1 is 1. When C/T1 is 0, Timer1 does not use this bit.
29 23 T0 Input N/A T0 is the active -HIGH T0 signal for 80 51 Timer0, which pro vides the in put
to Timer0 when C/T0 is 1. When C/T0 is 0, Timer0 does not use this bit.
53 43 RXD1 Input N/A RXD1is an active-H IGH input signa l for 8051 UAR T1, which provi des data
to the UART in all modes.
52 42 TXD1 Output H TXD1is an active-HIGH output pin from 8051 UART1, which provides the
output clock in sync mode, and the output data in async mode.
51 41 RXD0 Input N/A RXD0 is the active-HIGH RXD0 input to 8051 UAR T0, which provides data
to the UART in all modes.
50 40 TXD0 Output H TXD0 is the ac ti ve-H I GH TXD0 output from 805 1 U ART0, whi ch prov id es
the output clock in sync mode, and the output data in async mode.
42 CS# Output H CS# is the active-LOW chip select for external memory.
41 32 WR# Output H WR# is the active-LOW write strobe output for external memory.
40 31 RD# Output H RD# is the active-LOW read strobe output for external memory.
38 OE# Output H OE# is the active-LOW output enable for external memory.
33 27 14 Reserved Input N/A Reserved. Connect to ground.
101 79 44 WAKEUP Input N/A USB Wakeup. If the 8051 is in suspend, asserting this pin starts up the
oscillator and interrupts the 8051 to allow it to exit the suspend mode.
Holding W AKEUP asserted inhibits the EZ-USB FX1 chip from suspending.
This pin has programmable polarity (WAKEUP.4).
36 29 15 SCL OD Z Clock for the I2C interface. Connect to VCC wi th a 2.2K res istor , even if no
I2C peripheral is attached.
37 30 16 SDA OD Z Data for I2C interface. Conn ect to VCC with a 2.2K resistor , even if no I2C
peripheral is attached.
2 1 55 VCC Power N/A VCC. Connect to 3.3V power source.
26 20 11 VCC Power N/A VCC. Connect to 3.3V power source.
43 33 17 VCC Power N/A VCC. Connect to 3.3V power source.
48 38 VCC Power N/A VCC. Connect to 3.3V power source.
64 49 27 VCC Power N/A VCC. Connect to 3.3V power source.
68 53 VCC Power N/A VCC. Connect to 3.3V power source.
81 66 32 VCC Power N/A VCC. Connect to 3.3V power source.
100 78 43 VCC Power N/A VCC. Connect to 3.3V power source.
107 85 VCC Power N/A VCC. Connect to 3.3V power source.
Table 5-1. FX1 Pin Definitions (continued)[8]
128
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TQFP 56
QFN Name Type Default Description
CY7C64713/14
Document #: 38-08039 Rev. *B Page 22 of 50
3 2 56 GND Ground N/A Ground.
27 21 12 GND Ground N/A Ground.
49 39 GND Ground N/A Ground.
58 48 26 GND Ground N/A Ground.
65 50 28 GND Ground N/A Ground.
80 65 GND Ground N/A Ground.
93 75 41 GND Ground N/A Ground.
116 94 GND Ground N/A Ground.
125 99 53 GND Ground N/A Ground.
14 13 NC N/A N/A No Connect. This pin must be left open.
15 14 NC N/A N/A No Connect. This pin must be left open.
16 15 NC N/A N/A No-connect. This pin must be left open.
Table 5-1. FX1 Pin Definitions (continued)[8]
128
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TQFP 56
QFN Name Type Default Description
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Document #: 38-08039 Rev. *B Page 23 of 50
6.0 Register Summary
FX1 register bit definitions are described in the EZ-USB TRM
in greater detail.
Table 6-1. FX1 Register Summary
Hex Size Name Description b7 b6 b5 b4 b3 b2 b1 b0 Default Access
GPIF Waveform Memories
E400 128 WAVEDATA GPIF Waveform
Descriptor 0, 1, 2, 3 data D7 D6 D5 D4 D3 D2 D1 D0 xxxxxxxx RW
E480 128 reserved
GENERAL CONFIGURAT ION
E600 1CPUCS CPU Control & Status 0 0 PORTCSTB CLKSPD1 CLKSPD0 CLKINV CLKOE 8051RES 00000010 rrbbbbbr
E601 1IFCONFIG Interface Configuration
(Ports, GPIF, slave FIFOs)IFCLKSRC 3048MHZ IFCLKOE IFCLKPOL ASYNC GSTATE IFCFG1 IFCFG0 10000000 RW
E602 1PINFLAGSAB[9]
Slave FIFO FLAGA and
FLAGB Pin Configuration FLAGB3 FLAGB2 FLAGB1 FLAGB0 FLAGA3 FLAGA2 FLAGA1 FLAGA0 00000000 RW
E603 1PINFLAGSCD[9] Slave FIFO FLAGC and
FLAGD Pin Configuration FLAGD3 FLAGD2 FLAGD1 FLAGD0 FLAGC3 FLAGC2 FLAGC1 FLAGC0 00000000 RW
E604 1FIFORESET[9]
Restore FIFOS to default
state NAKALL 0 0 0 EP3 EP2 EP1 EP0 xxxxxxxx W
E605 1BREAKPT Breakpoint Control 0 0 0 0 BREAK BPPULSE BPEN 000000000 rrrrbbbr
E606 1BPADDRH B reakpoint Address H A15 A14 A13 A12 A11 A10 A9 A8 xxxxxxxx RW
E607 1BPADDRL B reakpoint Address L A7 A6 A5 A4 A3 A2 A1 A0 xxxxxxxx RW
E608 1UART230 230 Kbaud internally
generated ref. clock 0 0 0 0 0 0 230UART1 230UART0 00000000 rrrrrrbb
E609 1FIFOPINPOLAR[9]
Slave FIFO Inte rface pi ns
polarity 0 0 PKTEND SLOE SLRD SLWR EF FF 00000000 rrbbbbbb
E60A 1REVID Chip Revision rv7 rv6 rv5 rv4 rv3 rv2 rv1 rv0 RevA
00000001 R
E60B 1REVCTL[9] Chip Revision Control 0 0 0 0 0 0 dyn_out enh_pkt 00000000 rrrrrrbb
UDMA
E60C 1GPIFHOLDAMOUNT MSTB Hold Time
(for UDMA) 0 0 0 0 0 0 HOLDTIME1 HOLDTIME0 00000000 rrrrrrbb
3reserved
ENDPOINT CONFIGURATION
E610 1EP1OUTCFG Endpoint 1-OUT
Configuration VALID 0TYPE1 TYPE0 0 0 0 0 10100000 brbbrrrr
E611 1EP1INCFG Endpoint 1-IN
Configuration VALID 0TYPE1 TYPE0 0 0 0 0 10100000 brbbrrrr
E612 1EP2CFG Endpoint 2 Configuration VALID DIR TYPE1 TYPE0 SIZE 0BUF1 BUF0 10100010 bbbbbrbb
E613 1EP4CFG Endpoint 4 Configuration VALID DIR TYPE1 TYPE0 0 0 0 0 10100000 bbbbrrrr
E614 1EP6CFG Endpoint 6 Configuration VALID DIR TYPE1 TYPE0 SIZE 0BUF1 BUF0 11100010 bbbbbrbb
E615 1EP8CFG Endpoint 8 Configuration VALID DIR TYPE1 TYPE0 0 0 0 0 11100000 bbbbrrrr
2reserved
E618 1EP2FIFOCFG[9]
Endpoint 2 / slave FIFO
configuration 0 INFM1 OEP1 AUTOOUT AUTOIN ZEROLENIN 0WORDWIDE 00000101 rbbbbbrb
E619 1EP4FIFOCFG[9]
Endpoint 4 / slave FIFO
configuration 0 INFM1 OEP1 AUTOOUT AUTOIN ZEROLENIN 0WORDWIDE 00000101 rbbbbbrb
E61A 1EP6FIFOCFG[9]
Endpoint 6 / slave FIFO
configuration 0 INFM1 OEP1 AUTOOUT AUTOIN ZEROLENIN 0WORDWIDE 00000101 rbbbbbrb
E61B 1EP8FIFOCFG[9]
Endpoint 8 / slave FIFO
configuration 0 INFM1 OEP1 AUTOOUT AUTOIN ZEROLENIN 0WORDWIDE 00000101 rbbbbbrb
E61C 4reserved
E620 1EP2AUTOINLENH[9] Endpoint 2 AUTOIN
Packet Length H 0 0 0 0 0 PL10 PL9 PL8 00000010 rrrrrbbb
E621 1EP2AUTOINLENL[9] Endpoint 2 AUTOIN
Packet Length L PL7 PL6 PL5 PL4 PL3 PL2 PL1 PL0 00000000 RW
E622 1EP4AUTOINLENH[9] Endpoint 4 AUTOIN
Packet Length H 0 0 0 0 0 0 PL9 PL8 00000010 rrrrrrbb
E623 1EP4AUTOINLENL[9] Endpoint 4 AUTOIN
Packet Length L PL7 PL6 PL5 PL4 PL3 PL2 PL1 PL0 00000000 RW
E624 1EP6AUTOINLENH[9] Endpoint 6 AUTOIN
Packet Length H 0 0 0 0 0 PL10 PL9 PL8 00000010 rrrrrbbb
E625 1EP6AUTOINLENL[9] Endpoint 6 AUTOIN
Packet Length L PL7 PL6 PL5 PL4 PL3 PL2 PL1 PL0 00000000 RW
E626 1EP8AUTOINLENH[9] Endpoint 8 AUTOIN
Packet Length H 0 0 0 0 0 0 PL9 PL8 00000010 rrrrrrbb
E627 1EP8AUTOINLENL[9] Endpoint 8 AUTOIN
Packet Length L PL7 PL6 PL5 PL4 PL3 PL2 PL1 PL0 00000000 RW
E628 1ECCCFG ECC Configuration 0 0 0 0 0 0 0 ECCM 00000000 rrrrrrrb
E629 1ECCRESET ECC Reset x x x x x x x x 00000000 W
E62A 1ECC1B0 ECC1 Byte 0 Address LINE15 LINE14 LINE13 LINE12 LINE11 LINE10 LINE9 LINE8 11111111 R
E62B 1ECC1B1 ECC1 Byte 1 Address LINE7 LINE6 LINE5 LINE4 LINE3 LINE2 LINE1 LINE0 11111111 R
E62C 1ECC1B2 ECC1 Byte 2 Address COL5 COL4 COL3 COL2 COL1 COL0 LINE17 LINE16 11111111 R
E62D 1ECC2B0 ECC2 Byte 0 Address LINE15 LINE14 LINE13 LINE12 LINE11 LINE10 LINE9 LINE8 11111111 R
E62E 1ECC2B1 ECC2 Byte 1 Address LINE7 LINE6 LINE5 LINE4 LINE3 LINE2 LINE1 LINE0 11111111 R
Note:
9. Read and writes to these register may require synchronization delay, see Technical Reference Manual for “Synchronization Delay.”
CY7C64713/14
Document #: 38-08039 Rev. *B Page 24 of 50
E62F 1ECC2B2 ECC2 Byte 2 Address COL5 COL4 COL3 COL2 COL1 COL0 0 0 11111111 R
E630 1EP2FIFOPFH[9]
Endpoint 2 / slave FIFO
Programmable Flag H ISO
Mode
DECIS PKTSTAT IN: PKTS[2]
OUT:PFC12 IN: PKTS[1]
OUT:PFC11 IN: PKTS[0]
OUT:PFC10 0PFC9 PFC8 10001000 bbbbbrbb
E630 1EP2FIFOPFH[9]
Endpoint 2 / slave FIFO
Programmable Flag H
Non-ISO Mode
DECIS PKTSTAT OUT:PFC12 OUT:PFC11 OUT:PFC10 0PFC9 IN:PKTS[2]
OUT:PFC8 10001000 bbbbbrbb
E631 1EP2FIFOPFL[9]
Endpoint 2 / slave FIFO
Programmable Flag L IN:PKTS[1]
OUT:PFC7 IN:PKTS[0]
OUT:PFC6 PFC5 PFC4 PFC3 PFC2 PFC1 PFC0 00000000 RW
E632 1EP4FIFOPFH[9]
Endpoint 4 / slave FIFO
Programmable Flag H ISO
Mode
DECIS PKTSTAT 0IN: PKTS[1]
OUT:PFC10 IN: PKTS[0]
OUT:PFC9 0 0 PFC8 10001000 bbrbbrrb
E632 1EP4FIFOPFH[9]
Endpoint 4 / slave FIFO
Programmable Flag H
Non-ISO Mode
DECIS PKTSTAT 0OUT:PFC10 OUT:PFC9 0 0 PFC8 10001000 bbrbbrrb
E633 1EP4FIFOPFL[9]
Endpoint 4 / slave FIFO
Programmable Flag L IN: PKTS[1]
OUT:PFC7 IN: PKTS[0]
OUT:PFC6 PFC5 PFC4 PFC3 PFC2 PFC1 PFC0 00000000 RW
E634 1EP6FIFOPFH[9]
Endpoint 6 / slave FIFO
Programmable Flag H ISO
Mode
DECIS PKTSTAT INPKTS[2]
OUT:PFC12 IN: PKTS[1]
OUT:PFC11 IN: PKTS[0]
OUT:PFC10 0PFC9 PFC8 00001000 bbbbbrbb
E634 1EP6FIFOPFH[9]
Endpoint 6 / slave FIFO
Programmable Flag H
Non-ISO Mode
DECIS PKTSTAT OUT:PFC12 OUT:PFC11 OUT:PFC10 0PFC9 IN:PKTS[2]
OUT:PFC8 00001000 bbbbbrbb
E635 1EP6FIFOPFL[9]
Endpoint 6 / slave FIFO
Programmable Flag L IN:PKTS[1]
OUT:PFC7 IN:PKTS[0]
OUT:PFC6 PFC5 PFC4 PFC3 PFC2 PFC1 PFC0 00000000 RW
E636 1EP8FIFOPFH[9]
Endpoint 8 / slave FIFO
Programmable Flag H ISO
Mode
DECIS PKTSTAT 0IN: PKTS[1]
OUT:PFC10 IN: PKTS[0]
OUT:PFC9 0 0 PFC8 00001000 bbrbbrrb
E636 1EP8FIFOPFH[9]
Endpoint 8 / slave FIFO
Programmable Flag H
Non-ISO Mode
DECIS PKTSTAT 0OUT:PFC10 OUT:PFC9 0 0 PFC8 00001000 bbrbbrrb
E637 1EP8FIFOPFL[9]
ISO Mode Endpoint 8 / slave FIFO
Programmable Flag L PFC7 PFC6 PFC5 PFC4 PFC3 PFC2 PFC1 PFC0 00000000 RW
E637 1EP8FIFOPFL[9]
Non-ISO Mode Endpoint 8 / slave FIFO
Programmable Flag L IN: PKTS[1]
OUT:PFC7 IN: PKTS[0]
OUT:PFC6 PFC5 PFC4 PFC3 PFC2 PFC1 PFC0 00000000 RW
8reserved
E640 1reserved
E641 1reserved
E642 1reserved
E643 1reserved
E644 4reserved
E648 1INPKTEND[9] Force IN Packet End Skip 0 0 0 EP3 EP2 EP1 EP0 xxxxxxxx W
E649 7 OUTPKTEND[9] Force OUT Packet End Skip 0 0 0 EP3 EP2 EP1 EP0 xxxxxxxx W
INTERRUPTS
E650 1EP2FIFOIE[9]
Endpoint 2 slave FIFO
Flag Interrupt Enable 0 0 0 0 EDGEPF PF EF FF 00000000 RW
E651 1EP2FIFOIRQ[9,10] Endpoint 2 slave FIFO
Flag Interrupt Request 0 0 0 0 0 PF EF FF 00000111 rrrrrbbb
E652 1EP4FIFOIE[9]
Endpoint 4 slave FIFO
Flag Interrupt Enable 0 0 0 0 EDGEPF PF EF FF 00000000 RW
E653 1EP4FIFOIRQ[9,10] Endpoint 4 slave FIFO
Flag Interrupt Request 0 0 0 0 0 PF EF FF 00000111 rrrrrbbb
E654 1EP6FIFOIE[9]
Endpoint 6 slave FIFO
Flag Interrupt Enable 0 0 0 0 EDGEPF PF EF FF 00000000 RW
E655 1EP6FIFOIRQ[9,10] Endpoint 6 slave FIFO
Flag Interrupt Request 0 0 0 0 0 PF EF FF 00000110 rrrrrbbb
E656 1EP8FIFOIE[9]
Endpoint 8 slave FIFO
Flag Interrupt Enable 0 0 0 0 EDGEPF PF EF FF 00000000 RW
E657 1EP8FIFOIRQ[9,10] Endpoint 8 slave FIFO
Flag Interrupt Request 0 0 0 0 0 PF EF FF 00000110 rrrrrbbb
E658 1IBNIE IN-BULK-NAK Interrupt
Enable 0 0 EP8 EP6 EP4 EP2 EP1 EP0 00000000 RW
Note:
10. SFRs not part of the standard 8051 architecture.
The register can only be reset, it cannot be set.
Table 6-1. FX1 Register Summary (continued)
Hex Size Name Description b7 b6 b5 b4 b3 b2 b1 b0 Default Access
CY7C64713/14
Document #: 38-08039 Rev. *B Page 25 of 50
E659 1IBNIRQ[10] IN-BULK-NAK inter rupt
Request 0 0 EP8 EP6 EP4 EP2 EP1 EP0 00xxxxxx rrbbbbbb
E65A 1NAKIE Endpoint Ping-NAK / IBN
Interrupt Enable EP8 EP6 EP4 EP2 EP1 EP0 0IBN 00000000 RW
E65B 1NAKIRQ[10] E ndpoint Ping-NAK / IBN
Interrupt Request EP8 EP6 EP4 EP2 EP1 EP0 0IBN xxxxxx0x bbbbbbrb
E65C 1USBIE USB Int Enables 0EP0ACK 0URES SUSP SUTOK SOF SUDAV 00000000 RW
E65D 1USBIRQ[10] USB Interrupt Requests 0EP0ACK 0URES SUSP SUTOK SOF SUDAV 0xxxxxxx rbbbbbbb
E65E 1EPIE Endpoint Interrupt
Enables EP8 EP6 EP4 EP2 EP1OUT EP1IN EP0OUT EP0IN 00000000 RW
E65F 1EPIRQ[10] Endpoint Interrupt
Requests EP8 EP6 EP4 EP2 EP1OUT EP1IN EP0OUT EP0IN 0RW
E660 1GPIFIE[9] GPIF Interrupt Enable 0 0 0 0 0 0 GPIFWF GPIFDONE 00000000 RW
E661 1GPIFIRQ[9] GPIF Interrupt Request 0 0 0 0 0 0 GPIFWF GPIFDONE 000000xx RW
E662 1USBERRIE USB Error Interrupt
Enables ISOEP8 ISOEP6 ISOEP4 ISOEP2 0 0 0 ERRLIMIT 00000000 RW
E663 1USBERRIRQ[10] USB Error Interrupt
Requests ISOEP8 ISOEP6 ISOEP4 ISOEP2 0 0 0 ERRLIMIT 0000000x bbbbrrrb
E664 1ERRCNTLIM USB Error counter and
limit EC3 EC2 EC1 EC0 LIMIT3 LIMIT2 LIMIT1 LIMIT0 xxxx0100 rrrrbbbb
E665 1CLRERRCNT Clear Er ror Counter EC3:0x x x x x x x x xxxxxxxx W
E666 1INT2IVEC Interrupt 2 (USB)
Autovector 0I2V4 I2V3 I2V2 I2V1 I2V0 0 0 00000000 R
E667 1INT4IVEC Interrupt 4 (slave FIFO &
GPIF) Autovector 1 0 I4V3 I4V2 I4V1 I4V0 0 0 10000000 R
E668 1 INTSETUP Interrupt 2&4 setup 0 0 0 0 AV2EN 0 INT4SRC AV4EN 00000000 RW
E669 7reserved
INPUT / OUTPUT
E670 1PORTACFG I/O PORTA Alternate
Configuration FLAGD SLCS 0 0 0 0 INT1 INT0 00000000 RW
E671 1PORTCCFG I/O PORTC Alternate
Configuration GPIFA7 GPIFA6 GPIFA5 GPIFA4 GPIFA3 GPIFA2 GPIFA1 GPIFA0 00000000 RW
E672 1PORTECFG I/O PORTE Alternate
Configuration GPIFA8 T2EX INT6 RXD1OUT RXD0OUT T2OUT T1OUT T0OUT 00000000 RW
E673 4XTALINSRC XTALIN Cl ock So ur c e 0 0 0 0 0 0 0 EXTCLK 00000000 rrrrrrrb
E677 1reserved
E678 1I2CS I²C Bus
Control & Status START STOP LASTRD ID1 ID0 BERR ACK DONE 000xx000 bbbrrrrr
E679 1I2DAT I²C Bus
Data d7 d6 d5 d4 d3 d2 d1 d0 xxxxxxxx RW
E67A 1I2CTL I²C Bus
Control 0 0 0 0 0 0 STOPIE 400KHZ 00000000 RW
E67B 1XAUTODAT1 Autoptr1 MOVX access,
when APTREN=1 D7 D6 D5 D4 D3 D2 D1 D0 xxxxxxxx RW
E67C 1XAUTODAT2 Autoptr2 MOVX access,
when APTREN=1 D7 D6 D5 D4 D3 D2 D1 D0 xxxxxxxx RW
UDMA CRC
E67D 1UDMACRCH[9] UDMA CRC MSB CRC15 CRC14 CRC13 CRC12 CRC11 CRC10 CRC9 CRC8 01001010 RW
E67E 1UDMACRCL[9] UDMA CRC LSB CRC7 CRC6 CRC5 CRC4 CRC3 CRC2 CRC1 CRC0 10111010 RW
E67F 1UDMACRC-
QUALIFIER UDMA CRC Qualifier QENABLE 0 0 0 QSTATE QSIGNAL2 QSIGNAL1 QSIGNAL0 00000000 brrrbbbb
USB CONTROL
E680 1USBCS USB Control & Status 0 0 0 0 DISCON NOSYNSOF RENUM SIGRSUME x0000000 rrrrbbbb
E681 1SUSPEND Put chip into suspend x x x x x x x x xxxxxxxx W
E682 1WAKEUPCS Wakeup Control & Status WU2 WU WU2POL WUPOL 0DPEN WU2EN WUEN xx000101 bbbbrbbb
E683 1TOGCTL Toggle Control Q S R IO EP3 EP2 EP1 EP0 x0000000 rrrbbbbb
E684 1USBFRAMEH USB Frame count H 0 0 0 0 0 FC10 FC9 FC8 00000xxx R
E685 1USBFRAMEL USB Frame count L FC7 FC6 FC5 FC4 FC3 FC2 FC1 FC0 xxxxxxxx R
E686 1reserved
E687 1FNADDR USB Function address 0FA6 FA5 FA4 FA3 FA2 FA1 FA0 0xxxxxxx R
E688 2reserved
ENDPOINTS
E68A 1EP0BCH[9] Endpoint 0 Byte Count H (BC15) (BC14) (BC13) (BC12) (BC11) (BC10) (BC9) (BC8) xxxxxxxx RW
E68B 1EP0BCL[9] Endpoint 0 Byte Count L (BC7) BC6 BC5 BC4 BC3 BC2 BC1 BC0 xxxxxxxx RW
E68C 1reserved
E68D 1EP1OUTBC Endpoint 1 OUT Byte
Count 0BC6 BC5 BC4 BC3 BC2 BC1 BC0 xxxxxxxx RW
E68E 1reserved
E68F 1EP1INBC Endpoint 1 IN Byte Count 0BC6 BC5 BC4 BC3 BC2 BC1 BC0 xxxxxxxx RW
E690 1EP2BCH[9] Endpoint 2 Byte Count H 0 0 0 0 0 BC10 BC9 BC8 xxxxxxxx RW
E691 1EP2BCL[9] Endpoint 2 Byte Count L BC7/SKIP BC6 BC5 BC4 BC3 BC2 BC1 BC0 xxxxxxxx RW
E692 2reserved
E694 1EP4BCH[9] Endpoint 4 Byte Count H 0 0 0 0 0 0 BC9 BC8 xxxxxxxx RW
E695 1EP4BCL[9] Endpoint 4 Byte Count L BC7/SKIP BC6 BC5 BC4 BC3 BC2 BC1 BC0 xxxxxxxx RW
E696 2reserved
Table 6-1. FX1 Register Summary (continued)
Hex Size Name Description b7 b6 b5 b4 b3 b2 b1 b0 Default Access
CY7C64713/14
Document #: 38-08039 Rev. *B Page 26 of 50
E698 1EP6BCH[9] Endpoint 6 Byte Count H 0 0 0 0 0 BC10 BC9 BC8 xxxxxxxx RW
E699 1EP6BCL[9] Endpoint 6 Byte Count L BC7/SKIP BC6 BC5 BC4 BC3 BC2 BC1 BC0 xxxxxxxx RW
E69A 2reserved
E69C 1EP8BCH[9] Endpoint 8 Byte Count H 0 0 0 0 0 0 BC9 BC8 xxxxxxxx RW
E69D 1EP8BCL[9] Endpoint 8 Byte Count L BC7/SKIP BC6 BC5 BC4 BC3 BC2 BC1 BC0 xxxxxxxx RW
E69E 2reserved
E6A0 1EP0CS Endpoint 0 Control and
Status HSNAK 0 0 0 0 0 BUSY STALL 10000000 bbbbbbrb
E6A1 1EP1OUTCS Endpoint 1 OUT Control
and Status 0 0 0 0 0 0 BUSY STALL 00000000 bbbbbbrb
E6A2 1EP1INCS Endpoint 1 IN Contr ol and
Status 0 0 0 0 0 0 BUSY STALL 00000000 bbbbbbrb
E6A3 1EP2CS Endpoint 2 Control and
Status 0NPAK2 NPAK1 NPAK0 FULL EMPTY 0STALL 00101000 rrrrrrrb
E6A4 1EP4CS Endpoint 4 Control and
Status 0 0 NPAK1 NPAK0 FULL EMPTY 0STALL 00101000 rrrrrrrb
E6A5 1EP6CS Endpoint 6 Control and
Status 0NPAK2 NPAK1 NPAK0 FULL EMPTY 0STALL 00000100 rrrrrrrb
E6A6 1EP8CS Endpoint 8 Control and
Status 0 0 NPAK1 NPAK0 FULL EMPTY 0STALL 00000100 rrrrrrrb
E6A7 1EP2FIFOFLGS Endpoint 2 slave FIFO
Flags 0 0 0 0 0 PF EF FF 00000010 R
E6A8 1EP4FIFOFLGS Endpoint 4 slave FIFO
Flags 0 0 0 0 0 PF EF FF 00000010 R
E6A9 1EP6FIFOFLGS Endpoint 6 slave FIFO
Flags 0 0 0 0 0 PF EF FF 00000110 R
E6AA 1EP8FIFOFLGS Endpoint 8 slave FIFO
Flags 0 0 0 0 0 PF EF FF 00000110 R
E6AB 1EP2FIFOBCH Endpoint 2 slave FIFO
total byte count H 0 0 0 BC12 BC11 BC10 BC9 BC8 00000000 R
E6AC 1EP2FIFOBCL Endpoint 2 slave FIFO
total byte count L BC7 BC6 BC5 BC4 BC3 BC2 BC1 BC0 00000000 R
E6AD 1EP4FIFOBCH Endpoint 4 slave FIFO
total byte count H 0 0 0 0 0 BC10 BC9 BC8 00000000 R
E6AE 1EP4FIFOBCL Endpoint 4 slave FIFO
total byte count L BC7 BC6 BC5 BC4 BC3 BC2 BC1 BC0 00000000 R
E6AF 1EP6FIFOBCH Endpoint 6 slave FIFO
total byte count H 0 0 0 0 BC11 BC10 BC9 BC8 00000000 R
E6B0 1EP6FIFOBCL Endpoint 6 slave FIFO
total byte count L BC7 BC6 BC5 BC4 BC3 BC2 BC1 BC0 00000000 R
E6B1 1EP8FIFOBCH Endpoint 8 slave FIFO
total byte count H 0 0 0 0 0 BC10 BC9 BC8 00000000 R
E6B2 1EP8FIFOBCL Endpoint 8 slave FIFO
total byte count L BC7 BC6 BC5 BC4 BC3 BC2 BC1 BC0 00000000 R
E6B3 1SUDPTRH Setup Data Pointer high
address byte A15 A14 A13 A12 A11 A10 A9 A8 xxxxxxxx RW
E6B4 1SUDPTRL Setup Data Pointer low ad-
dress byte A7 A6 A5 A4 A3 A2 A1 0 xxxxxxx0 bbbbbbbr
E6B5 1SUDPTRCTL Setup Data Pointer Auto
Mode 0 0 0 0 0 0 0 SDPAUTO 00000001 RW
2reserved
E6B8 8SETUPDAT 8 bytes of setup data D7 D6 D5 D4 D3 D2 D1 D0 xxxxxxxx R
SETUPDAT[0] =
bmRequestType
SETUPDAT[1] =
bmRequest
SETUPDAT[2:3] = wValue
SETUPDAT[4:5] = wIndex
SETUPDAT[6:7] =
wLength
GPIF
E6C0 1GPIFWFSELECT Waveform Selector SINGLEWR1 SINGLEWR0SINGLERD1 SINGLERD0 FIFOWR1 FIFOWR0 FIFORD1 FIFORD0 11100100 RW
E6C1 1GPIFIDLECS GPIF Done, GPIF IDLE
drive mode DONE 0 0 0 0 0 0 IDLEDRV 10000000 RW
E6C2 1GPIFIDLECTL Inactive Bus, CTL states 0 0 CTL5 CTL4 CTL3 CTL2 CTL1 CTL0 11111111 RW
E6C3 1GPIFCTLCFG CTL Drive Type TRICTL 0CTL5 CTL4 CTL3 CTL2 CTL1 CTL0 00000000 RW
E6C4 1GPIFADRH[9] GPIF Address H 0 0 0 0 0 0 0 GPIFA8 00000000 RW
E6C5 1GPIFADRL[9] GPIF Address L GPIFA7 GPIFA6 GPIFA5 GPIFA4 GPIFA3 GPIFA2 GPIFA1 GPIFA0 00000000 RW
FLOWSTATE
E6C6 1 FLOWSTATE Flowstate Enable and
Selector FSE 0 0 0 0 FS2 FS1 FS0 00000000 brrrrbbb
E6C7 1FLOWLOGIC Flowstate Logic LFUNC1 LFUNC0 TERMA2 TERMA1 TERMA0 TERMB2 TERMB1 TERMB0 00000000 RW
E6C8 1FLOWEQ0CTL CTL-Pin Sta tes in
Flowstate
(when Logic = 0)
CTL0E3 CTL0E2 CTL0E1/
CTL5 CTL0E0/
CTL4 CTL3 CTL2 CTL1 CTL0 00000000 RW
E6C9 1FLOWEQ1CTL CTL-Pin States in Flow-
state (when Logic = 1) CTL0E3 CTL0E2 CTL0E1/
CTL5 CTL0E0/
CTL4 CTL3 CTL2 CTL1 CTL0 00000000 RW
E6CA 1FLOWHOLDOFF Holdoff Configuration HOPERIOD3 HOPERIOD2HOPERIOD1 HOPERIOD
0HOSTATE HOCTL2 HOCTL1 HOCTL0 00000000 RW
Table 6-1. FX1 Register Summary (continued)
Hex Size Name Description b7 b6 b5 b4 b3 b2 b1 b0 Default Access
CY7C64713/14
Document #: 38-08039 Rev. *B Page 27 of 50
E6CB 1FLOWSTB Flowstate Strobe
Configuration SLAVE RDYASYNC CTLTOGL SUSTAIN 0MSTB2 MSTB1 MSTB0 00100000 RW
E6CC 1FLOWSTBEDGE Flowstate Rising/Falling
Edge Configuration 0 0 0 0 0 0 FALLING RISING 00000001 rrrrrrbb
E6CD 1FLOWSTBPERIOD Master-S t robe Half-PeriodD7 D6 D5 D4 D3 D2 D1 D0 00000010 RW
E6CE 1GPIFTCB3[9] GPIF Transaction Count
Byte 3 TC31 TC30 TC29 TC28 TC27 TC26 TC25 TC24 00000000 RW
E6CF 1GPIFTCB2[9] GPIF Transaction Count
Byte 2 TC23 TC22 TC21 TC20 TC19 TC18 TC17 TC16 00000000 RW
E6D0 1GPIFTCB1[9] GPIF Transaction Count
Byte 1 TC15 TC14 TC13 TC12 TC11 TC10 TC9 TC8 00000000 RW
E6D1 1GPIFTCB0[9] GPIF Transaction Count
Byte 0 TC7 TC6 TC5 TC4 TC3 TC2 TC1 TC0 00000001 RW
2reserved 00000000 RW
reserved
reserved
E6D2 1EP2GPIFFLGSEL[9] Endpoint 2 GPIF Flag
select 0 0 0 0 0 0 FS1 FS0 00000000 RW
E6D3 1EP2GPIFPFSTOP E ndpoint 2 GPIF stop
transaction on prog. flag 0 0 0 0 0 0 0 FIFO2FLAG 00000000 RW
E6D4 1EP2GPIFTRIG[9] Endpoint 2 GPIF Trigger x x x x x x x x xxxxxxxx W
3reserved
reserved
reserved
E6DA 1EP4GPIFFLGSEL[9] Endpoint 4 GPIF Flag
select 0 0 0 0 0 0 FS1 FS0 00000000 RW
E6DB 1EP4GPIFPFSTOP E ndpoint 4 GPIF stop
transaction on GPIF Flag 0 0 0 0 0 0 0 FIFO4FLAG 00000000 RW
E6DC 1EP4GPIFTRIG[9] Endpoint 4 GPIF Trigger x x x x x x x x xxxxxxxx W
3reserved
reserved
reserved
E6E2 1EP6GPIFFLGSEL[9] Endpoint 6 GPIF Flag
select 0 0 0 0 0 0 FS1 FS0 00000000 RW
E6E3 1EP6GPIFPFSTOP Endpoint 6 GPIF stop
transaction on prog. flag 0 0 0 0 0 0 0 FIFO6FLAG 00000000 RW
E6E4 1EP6GPIFTRIG[9] Endpoint 6 GPIF Trigger x x x x x x x x xxxxxxxx W
3reserved
reserved
reserved
E6EA 1EP8GPIFFLGSEL[9] Endpoint 8 GPIF Flag
select 0 0 0 0 0 0 FS1 FS0 00000000 RW
E6EB 1EP8GPIFPFSTOP Endpoint 8 GPIF stop
transaction on prog. flag 0 0 0 0 0 0 0 FIFO8FLAG 00000000 RW
E6EC 1EP8GPIFTRIG[9] Endpoint 8 GPIF Trigger x x x x x x x x xxxxxxxx W
3reserved
E6F0 1 XGPIFSGLDATH GPIF Data H
(16-bit mode only) D15 D14 D13 D12 D11 D10 D9 D8 xxxxxxxx RW
E6F1 1XGPIFSGLDATLX Read/Write GPIF Data L &
trigger transaction D7 D6 D5 D4 D3 D2 D1 D0 xxxxxxxx RW
E6F2 1XGPIFSGLDATL-
NOX Read GPIF Data L, no
transaction trigger D7 D6 D5 D4 D3 D2 D1 D0 xxxxxxxx R
E6F3 1GPIFREADYCFG Internal RDY , Sync/Async,
RDY pin states INTRDY SAS TCXRDY5 0 0 0 0 0 00000000 bbbrrrrr
E6F4 1GPIFREADYSTAT GPIF Ready Status 0 0 RDY5 RDY4 RDY3 RDY2 RDY1 RDY0 00xxxxxx R
E6F5 1GPIFABORT Abort GPIF Waveforms x x x x x x x x xxxxxxxx W
E6F6 2reserved
ENDPOINT BUFFERS
E740 64 EP0BUF EP0-IN/-OUT buffer D7 D6 D5 D4 D3 D2 D1 D0 xxxxxxxx RW
E780 64 EP10UTBUF EP1-OUT buffer D7 D6 D5 D4 D3 D2 D1 D0 xxxxxxxx RW
E7C0 64 EP1INBUF EP1-IN buffer D7 D6 D5 D4 D3 D2 D1 D0 xxxxxxxx RW
2048 reserved RW
F000 1023 EP2FIFOBUF 64/1023-byte E P 2 / slave
FIFO buffer (IN or OUT) D7 D6 D5 D4 D3 D2 D1 D0 xxxxxxxx RW
F400 64 EP4FIFOBUF 64 byte EP 4 / slave FIFO
buffer (IN or OUT) D7 D6 D5 D4 D3 D2 D1 D0 xxxxxxxx RW
F600 64 reserved
F800 1023 EP6FIFOBUF 64/1023-byte E P 6 / slave
FIFO buffer (IN or OUT) D7 D6 D5 D4 D3 D2 D1 D0 xxxxxxxx RW
FC00 64 EP8FIFOBUF 64 byte EP 8 / slave FIFO
buffer (IN or OUT) D7 D6 D5 D4 D3 D2 D1 D0 xxxxxxxx RW
FE00 64 reserved
xxxx I²C Configuration Byte 0DISCON 0 0 0 0 0 400KHZ xxxxxxxx
[[11]] n/a
Special Function Registers (SFRs)
80 1IOA[10] Port A (bit addressable) D7 D6 D5 D4 D3 D2 D1 D0 xxxxxxxx RW
Table 6-1. FX1 Register Summary (continued)
Hex Size Name Description b7 b6 b5 b4 b3 b2 b1 b0 Default Access
CY7C64713/14
Document #: 38-08039 Rev. *B Page 28 of 50
81 1SP Stack Pointer D7 D6 D5 D4 D3 D2 D1 D0 00000111 RW
82 1DPL0 Data Pointer 0 L A7 A6 A5 A4 A3 A2 A1 A0 00000000 RW
83 1DPH0 Data Pointer 0 H A15 A14 A13 A12 A11 A10 A9 A8 00000000 RW
84 1DPL1[10] Data Pointer 1 L A7 A6 A5 A4 A3 A2 A1 A0 00000000 RW
85 1DPH1[10] Data Pointer 1 H A15 A14 A13 A12 A11 A10 A9 A8 00000000 RW
86 1DPS[10] Data Pointer 0/1 select 0 0 0 0 0 0 0 SEL 00000000 RW
87 1PCON Power Control SMOD0 x 1 1 x x x IDLE 00110000 RW
88 1TCON Timer/Counter Control
(bit addressable) TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0 00000000 RW
89 1TMOD Timer/Counter Mode
Control GATE CT M1 M0 GATE CT M1 M0 00000000 RW
8A 1TL0 Timer 0 reload L D7 D6 D5 D4 D3 D2 D1 D0 00000000 RW
8B 1TL1 Timer 1 reload L D7 D6 D5 D4 D3 D2 D1 D0 00000000 RW
8C 1TH0 Timer 0 reload H D15 D14 D13 D12 D11 D10 D9 D8 00000000 RW
8D 1TH1 Timer 1 reload H D15 D14 D13 D12 D11 D10 D9 D8 00000000 RW
8E 1CKCON[10] Clock Control x x T2M T1M T0M MD2 MD1 MD0 00000001 RW
8F 1reserved
90 1IOB[10] Port B (bit addressable) D7 D6 D5 D4 D3 D2 D1 D0 xxxxxxxx RW
91 1EXIF[10] External Interrupt Flag(s) IE5 IE4 I²CINT USBNT 1 0 0 0 00001000 RW
92 1MPAGE[10] Upper Add r Byte of MOVX
using @R0 / @R1 A15 A14 A13 A12 A11 A10 A9 A8 00000000 RW
93 5reserved
98 1SCON0 Serial Port 0 Control
(bit addressable) SM0_0 SM1_0 SM2_0 REN_0 TB8_0 RB8_0 TI_0 RI_0 00000000 RW
99 1SBUF0 Serial Port 0 Data Buffer D7 D6 D5 D4 D3 D2 D1 D0 00000000 RW
9A 1AUTOPTRH1[10] Autopointer 1 Address H A15 A14 A13 A12 A11 A10 A9 A8 00000000 RW
9B 1AUTOPTRL1[10] Autopointer 1 Address L A7 A6 A5 A4 A3 A2 A1 A0 00000000 RW
9C 1reserved
9D 1AUTOPTRH2[10] Autopointer 2 Address H A15 A14 A13 A12 A11 A10 A9 A8 00000000 RW
9E 1AUTOPTRL2[10] Autopointer 2 Address L A7 A6 A5 A4 A3 A2 A1 A0 00000000 RW
9F 1reserved
A0 1IOC[10] Port C (bit addressable) D7 D6 D5 D4 D3 D2 D1 D0 xxxxxxxx RW
A1 1INT2CLR[10] Interrupt 2 clear x x x x x x x x xxxxxxxx W
A2 1INT4CLR[10] Interrupt 4 clear x x x x x x x x xxxxxxxx W
A3 5reserved
A8 1IE Interrupt Enable
(bit addressable) EA ES1 ET2 ES0 ET1 EX1 ET0 EX0 00000000 RW
A9 1reserved
AA 1EP2468STAT[10] Endpoint 2,4,6,8 status
flags EP8F EP8E EP6F EP6E EP4F EP4E EP2F EP2E 01011010 R
AB 1EP24FIFOFLGS
[10] Endpoint 2,4 slave FIFO
status flags 0EP4PF EP4EF EP4FF 0EP2PF EP2EF EP2FF 00100010 R
AC 1EP68FIFOFLGS
[10] Endpoint 6,8 slave FIFO
status flags 0EP8PF EP8EF EP8FF 0EP6PF EP6EF EP6FF 01100110 R
AD 2reserved
AF 1AUTOPTRSETUP[10] Autopointer 1&2 setup 0 0 0 0 0 APTR2INC APTR1INC APTREN 00000110 RW
B0 1IOD[10] Port D (bit addressable) D7 D6 D5 D4 D3 D2 D1 D0 xxxxxxxx RW
B1 1IOE[10] Port E
(NOT bit addressable) D7 D6 D5 D4 D3 D2 D1 D0 xxxxxxxx RW
B2 1OEA[10] Port A Output Enable D7 D6 D5 D4 D3 D2 D1 D0 00000000 RW
B3 1OEB[10] Port B Output Enable D7 D6 D5 D4 D3 D2 D1 D0 00000000 RW
B4 1OEC[10] Port C Output Enable D7 D6 D5 D4 D3 D2 D1 D0 00000000 RW
B5 1OED[10] Port D Output Enable D7 D6 D5 D4 D3 D2 D1 D0 00000000 RW
B6 1OEE[10] Port E Output Enable D7 D6 D5 D4 D3 D2 D1 D0 00000000 RW
B7 1reserved
B8 1IP Interrupt Priority (bit ad-
dressable) 1PS1 PT2 PS0 PT1 PX1 PT0 PX0 10000000 RW
B9 1reserved
BA 1EP01STAT[10] Endpoint 0&1 Status 0 0 0 0 0 EP1INBSY EP1OUTBS
YEP0BSY 00000000 R
BB 1GPIFTRIG[10] [9] Endpoint 2,4,6,8 GPIF
slave FIFO Trigger DONE 0 0 0 0 RW EP1 EP0 10000xxx brrrrbbb
BC 1reserved
BD 1GPIFSGLDATH[10] GPIF Data H (16-bit mode
only) D15 D14 D13 D12 D11 D10 D9 D8 xxxxxxxx RW
BE 1GPIFSGLDATLX[10] GPIF Data L w/ Trigger D7 D6 D5 D4 D3 D2 D1 D0 xxxxxxxx RW
BF 1GPIFSGLDAT
LNOX[10] GPIF Data L w/ No TriggerD7 D6 D5 D4 D3 D2 D1 D0 xxxxxxxx R
C0 1SCON1[10] Serial Port 1 Control (bit
addressable) SM0_1 SM1_1 SM2_1 REN_1 TB8_1 RB8_1 TI_1 RI_1 00000000 RW
C1 1SBUF1[10] Serial Port 1 Data Buffer D7 D6 D5 D4 D3 D2 D1 D0 00000000 RW
C2 6reserved
Notes:
11. If no EEPROM is detected by the SIE then the default is 00000000.
Table 6-1. FX1 Register Summary (continued)
Hex Size Name Description b7 b6 b5 b4 b3 b2 b1 b0 Default Access
CY7C64713/14
Document #: 38-08039 Rev. *B Page 29 of 50
C8 1T2CON Timer/Counter 2 Control
(bit addressable) TF2 EXF2 RCLK TCLK EXEN2 TR2 CT2 CPRL2 00000000 RW
C9 1reserved
CA 1RCAP2L Capture for Timer 2, auto-
reload, up-counter D7 D6 D5 D4 D3 D2 D1 D0 00000000 RW
CB 1RCAP2H Capture for Timer 2, auto-
reload, up-counter D7 D6 D5 D4 D3 D2 D1 D0 00000000 RW
CC 1TL2 Timer 2 reload L D7 D6 D5 D4 D3 D2 D1 D0 00000000 RW
CD 1TH2 Timer 2 reload H D15 D14 D13 D12 D11 D10 D9 D8 00000000 RW
CE 2reserved
D0 1PSW Program Status Word (bit
addressable) CY AC F0 RS1 RS0 OV F1 P00000000 RW
D1 7reserved
D8 1EICON[10] Externa l Interrupt Co ntro l SMOD1 1ERESI RESI INT6 0 0 0 01000000 RW
D9 7reserved
E0 1ACC Accumulator (bit address-
able) D7 D6 D5 D4 D3 D2 D1 D0 00000000 RW
E1 7reserved
E8 1EIE[10] External Interrupt En-
able(s) 1 1 1 EX6 EX5 EX4 EI²CEUSB 11100000 RW
E9 7reserved
F0 1 B B (bit addressable) D7 D6 D5 D4 D3 D2 D1 D0 00000000 RW
F1 7reserved
F8 1EIP[10] External Interrupt Priority
Control 1 1 1 PX6 PX5 PX4 PI²CPUSB 11100000 RW
F9 7reserved
Table 6-1. FX1 Register Summary (continued)
Hex Size Name Description b7 b6 b5 b4 b3 b2 b1 b0 Default Access
r = read-only bit
w = write-only bit
b = both read/write bit
R = all bits read-only
W = all bits write-only
CY7C64713/14
Document #: 38-08039 Rev. *B Page 30 of 50
7.0 Absolute Maximum Ratings
Storage Temperature ..................................–65°C to +150°C
Ambient Temperature with Power Supplied......0°C to +70°C
Supply Voltage to Ground Potential...............–0.5V to +4.0V
DC Input Voltage to Any Input Pin .......................... 5.25V[12]
DC Voltage Applied to Outputs
in High-Z State..................................... –0.5V to VCC + 0.5V
Power Dissipation.................................................... 235 mW
Static Discharge Voltage.......................................... > 2000V
Max Output Current, per I/O port................................ 10 mA
Max Output Current, all five I/O ports
(128- and 100-pin packages) ..................................... 50 mA
8.0 Operating Conditions
TA (Ambient Temperature Under Bias)............. 0°C to +70°C
Supply Voltage ...........................................+3.15V to +3.45V
Ground Volt age .................. ...... ................. ..... ...... ..... ........0V
FOSC (Oscillator or Crystal Frequency) ...24 MHz ± 100 ppm
.......................... ...... ...... ..... ................. ......Parallel Resona nt
9.0 DC Characteristics
9.1 USB Transceiver
USB 2.0-compliant in full-speed mode.
Note:
12. It is recommended to not power I/O when chip power is off.
13. Mea sur ed at Max VCC, 25ºC.
Table 9-1. DC Characteristics
Parameter Description Conditions Min. Typ. Max. Unit
VCC Supply Voltage 3.15 3.3 3.45 V
VCC Ramp Up 0 to 3.3V 200 µs
VIH Input HIGH Vo ltage 2 5.25 V
VIL Input LOW Voltage –0.5 0.8 V
VIH_X Crystal input HIGH Voltage 2 5.25 V
VIL_X Crystal input LOW Voltage –0.05 0.8 V
IIInput Leakage Current 0< VIN < VCC ±10 µA
VOH Output Voltage HIGH IOUT = 4 mA 2.4 V
VOL Output LOW Voltage IOUT = –4 mA 0.4 V
IOH Output Current HIGH 4mA
IOL Output Current LOW 4mA
CIN Input Pin Capacitance Except D+/D–3.29 10 pF
D+/D–12.96 15 pF
ISUSP Suspend Current
CY7C64714 Connected 300 380[13] µA
Disconnected 100 150[13] µA
Suspend Current
CY7C64713 Connected .5 1.2 mA
Disconnected .3 1.0 mA
ICC Supply Current 8051 running, connected to USB 35 65 mA
TRESET Reset Time after Valid Power VCC min = 3.0V 5.0 ms
Pin Reset after powered on 200 µs
CY7C64713/14
Document #: 38-08039 Rev. *B Page 31 of 50
10.0 AC Electrical Characteristics
10.1 USB Transceiver
USB 2.0-compliant in full-speed mode.
10.2 Program Memory Read
Notes:
14. CLKOUT is shown with positive polarity.
15. tACC1 is computed from the above parameters as follows:
tACC1(24 MHz) = 3*tCL – tAV –tDSU = 106 ns
tACC1(48 MHz) = 3*tCL – tAV – tDSU = 43 ns .
tCL
tDH
tSOEL
tSCSL
PSEN#
D[7..0]
OE#
A[15..0]
CS#
tSTBL
data in
tACC1
tAV
tSTBH
tAV
Figure 10-1. Program Memory Read Timing Diagram
CLKOUT[14]
[15]
Table 10-1. Program Memory Read Par amet ers
Parameter Description Min. Typ. Max. Unit Notes
tCL 1/CLKOUT Frequency 20.83 ns 48 MHz
41.66 ns 24 MHz
83.2 ns 12 MHz
tAV Delay from Clock to Va lid Address 0 10.7 ns
tSTBL Clock to PSEN Low 0 8 ns
tSTBH Clock to PSEN High 0 8 ns
tSOEL Clock to OE Low 11.1 ns
tSCSL Clock to CS Low 13 ns
tDSU Data Setup to Clock 9.6 ns
tDH Data Hold Time 0 ns
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Document #: 38-08039 Rev. *B Page 32 of 50
10.3 Data Memory Read
data in
tCL
A[15..0]
tAV tAV
RD# tSTBL tSTBH
tDH
D[7..0] data in
tACC1
[16 tDSU
Stre tch = 0
Stretch = 1
tCL
A[15..0]
tAV
RD#
tDH
D[7..0] tACC1[16] tDSU
CS#
CS# tSCSL
OE# tSOEL
Figure 10-2. Data Memory Read Timing Diagram
CLKOUT[14]
CLKOUT[14]
Table 10-2. Data Memory Read Parameters
Parameter Description Min. Typ. Max. Unit Notes
tCL 1/CLKOUT Frequency 20.83 ns 48 MHz
41.66 ns 24 MHz
83.2 ns 12 MHz
tAV Delay from Clock to Va lid Address 10.7 ns
tSTBL Clock to RD LOW 11 ns
tSTBH Clock to RD HIGH 11 ns
tSCSL Clock to CS LOW 13 ns
tSOEL Clock to OE LOW 11.1 ns
tDSU Data Setup to Clock 9.6 ns
tDH Data Hold Time 0 ns
Note:
16. tACC2 and tACC3 are computed from the above parameters as follows:
tACC2(24 MHz) = 3*tCL – tAV –tDSU = 106 ns
tACC2(48 MHz) = 3*tCL – tAV – tDSU = 43 ns
tACC3(24 MHz) = 5*tCL – tAV –tDSU = 190 ns
tACC3(48 MHz) = 5*tCL – tAV – tDSU = 86 ns.
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10.4 Data Memory Write
tOFF1
CLKOUT
A[15..0]
WR#
tAV
D[7..0]
tCL
tSTBL tSTBH
data out
tOFF1
CLKOUT
A[15..0]
WR#
tAV
D[7..0]
tCL
data out
Stretch = 1
tON1
tSCSL
tAV
CS#
tON1
CS#
Figure 10-3. Data Memory Write Timing Diagram
Tabl e 10-3. Data Memor y Write Parameters
Parameter Description Min. Max. Unit Notes
tAV Delay from Clock to Valid Address 0 10.7 ns
tSTBL Clock to WR Pulse LOW 0 11.2 ns
tSTBH Clock to WR Pulse HIGH 0 11.2 ns
tSCSL Clock to CS Pulse LOW 13.0 ns
tON1 Clock to Data Turn-on 0 13.1 ns
tOFF1 Clock to Data Hold Time 0 13.1 ns
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10.5 GPIF Synchronous Signals
Notes:
17. Dashed lines denote signals with programmable polarity.
18. GPIF asyn chrono us RDYx signals have a minimum Setup time of 50 ns when using internal 48-MHz IFCLK.
19. IFCLK must n ot exceed 48 MHz.
DATA(output)
tXGD
IFCLK
RDYX
DATA(input) valid
tSRY
tRYH
tIFCLK
tSGD
CTL
X
tXCTL
tDAH
NN+1
GPIFADR[8:0]
tSGA
Figure 10-4. GPIF Synchronous Signals Timing Diagram[17]
Table 10-4. GPIF Synchronous Signals Parameters with Internally Sourced IFCLK[18, 19]
Parameter Description Min. Max. Unit
tIFCLK IFCLK Period 20.83 ns
tSRY RDYX to Clock Setup Time 8.9 ns
tRYH Clock to RDYX 0ns
tSGD GPIF Data to Clock Setup Time 9.2 ns
tDAH GPIF Data Hold Time 0 ns
tSGA Clock to GPIF Address Propagation Delay 7.5 ns
tXGD Clock to GPIF Data Output Propagation Delay 11 ns
tXCTL Clock to CTLX Output Propagation Delay 6.7 ns
Table 10-5. GPIF Synchronous Signals Parameters with Externally Sourced IFCLK[19]
Parameter Description Min. Max. Unit
tIFCLK IFCLK Period 20.83 200 ns
tSRY RDYX to Clock Setup Time 2.9 ns
tRYH Clock to RDYX 3.7 ns
tSGD GPIF Data to Clock Setup Time 3.2 ns
tDAH GPIF Data Hold Time 4.5 ns
tSGA Clock to GPIF Address Propagation Delay 11.5 ns
tXGD Clock to GPIF Data Output Propagation Delay 15 ns
tXCTL Clock to CTLX Outpu t Propagation Del ay 10.7 ns
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10.6 Slave FIFO Synchronous Read
IFCLK
SLRD
FLAGS
SLOE
tSRD tRDH
tOEon tXFD
tXFLG
DATA
tIFCLK
N+1
tOEoff
N
Figure 10-5. Slave FIFO Synchronous Read Timing Diagram[17]
Table 10-6. Slave FIFO Synchronous Read Parameters with Internally Sourced IFCLK[19]
Parameter Description Min. Max. Unit
tIFCLK IFCLK Period 20.83 ns
tSRD SLRD to Clock Setu p Time 18.7 ns
tRDH Clock to SLRD Hold Time 0 ns
tOEon SLOE Turn-on to FIFO Data Valid 10.5 ns
tOEoff SLOE Turn-off to FIFO Data Hold 10.5 ns
tXFLG Clock to FLAGS Output Propagation Delay 9.5 ns
tXFD Clock to FIFO Data Output Propagation Delay TBD 11 ns
Table 10-7. Slave FIFO Synchronous Read Parameters with Externally Sourced IFCLK[19]
Parameter Description Min. Max. Unit
tIFCLK IFCLK Period 20.83 200 ns
tSRD SLRD to Clock Setu p Time 12.7 ns
tRDH Clock to SLRD Hold Time 3.7 ns
tOEon SLOE Turn-on to FIFO Data Valid 10.5 ns
tOEoff SLOE Turn-off to FIFO Data Hold 10.5 ns
tXFLG Clock to FLAGS Output Propagation Delay 13.5 ns
tXFD Clock to FIFO Data Output Propagation Delay TBD 15 ns
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Document #: 38-08039 Rev. *B Page 36 of 50
10.7 Slave FIFO Asynchronous Read
SLRD
FLAGS
tRDpwl
tRDpwh
SLOE
tXFLG
tXFD
DATA
tOEon tOEoff
N+1
N
Figure 10-6. Slave FIFO Asynchronous Read Timing Diagram[17]
Table 10-8. Slave FIFO Asynchronous Read Parameters[20]
Parameter Description Min. Max. Unit
tRDpwl SLRD Pulse Width LOW 50 ns
tRDpwh SLRD Pulse Width HIGH 50 ns
tXFLG SLRD to FLAGS Output Propagation Delay 70 ns
tXFD SLRD to FIFO Data Output Propagation Delay 15 ns
tOEon SLOE Turn-on to FIFO Data Valid 10.5 ns
tOEoff SLOE Turn-off to FIFO Data Hold 10.5 ns
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10.8 Slave FIFO Synchronous Writ e
Z
Z
tSFD tFDH
DATA
IFCLK
SLWR
FLAGS
tWRH
tXFLG
tIFCLK
tSWR
N
Figure 10-7. Slave FIFO Synchronous Write Timing Diagram[17]
Table 10-9. Slave FIFO Synchronous Write Parameters with Internally Sourced IFCLK [19]
Parameter Description Min. Max. Unit
tIFCLK IFCLK Period 20.83 ns
tSWR SLWR to Clock Setup Time 18.1 ns
tWRH Clock to SLWR Hold Time 0 ns
tSFD FIFO Data to Clock Setup Time 9.2 n s
tFDH Clock to FIFO Data Hold Time 0 ns
tXFLG Clock to FLAGS Output Propagation Time 9.5 ns
Table 10-10. Slave FIFO Synchronous Write Parameters with Externally Sourced IFCLK [19]
Parameter Description Min. Max. Unit
tIFCLK IFCLK Period 20.83 200 ns
tSWR SLWR to Clock Setup Time 12.1 ns
tWRH Clock to SLWR Hold Time 3.6 ns
tSFD FIFO Data to Clock Setup Time 3.2 n s
tFDH Clock to FIFO Data Hold Time 4.5 ns
tXFLG Clock to FLAGS Output Propagation Time 13.5 ns
Note:
20. Slave FIFO asynchronous parameter values use internal IFCLK setting at 48 MHz.
CY7C64713/14
Document #: 38-08039 Rev. *B Page 38 of 50
10.9 Slave FIFO Asynchronous Write
10.10 Slave FIFO Sy nchronous Packet End St robe
There is no specific timing requirement that needs to be met
for asserting PKTEND pin with regards to asserting SLWR.
PKTEND ca n be ass erted wit h the last data v alue cl ocked into
the FIFOs or there afte r. The only consi deratio n is th at the se t-
up t ime t SPE and the hol d time tPEH for PKTEND m ust be met.
Although typically there are no spec ific timing requ irements for
asserti ng PKTEND in relatio n to SLWR, there ex ist s a specifi c
DATA
tSFD tFDH
FLAGS tXFD
SLWR/SLCS#
tWRpwh
tWRpwl
Figure 10-8. Slave FIFO Asynchronous Write Timing Diagram[17]
Table 10-11. Slave FIFO Asynchronous Write Parameters with Internally Sourced IFCLK [20]
Parameter Description Min. Max. Unit
tWRpwl SLWR Pulse LOW 50 ns
tWRpwh SLWR Pulse HIGH 70 ns
tSFD SLWR to FIFO DATA Setup Time 10 ns
tFDH FIFO DATA to SLWR Hold Time 10 ns
tXFD SLWR to FLAGS Output Propagation Delay 70 ns
FLAGS
tXFLG
IFCLK
PKTEND tSPE
tPEH
Figure 10-9. Slave FIFO Synchronous Packet End Strobe Timing Diagram[17]
Table 10-12. Slave FIFO Synchronous Packet End Strobe Parameters with Internally Sourced IFCLK [19]
Parameter Description Min. Max. Unit
tIFCLK IFCLK Period 20.83 ns
tSPE PKTEND to Clock Setu p Time 14 .6 ns
tPEH Clock to PKTEND Hold Time 0 ns
tXFLG Clock to FLAGS Output Propagation Delay 9.5 ns
Table 10-13. Slave FIFO Synchronous Packet End Strobe Parameters with Externally Sourced IFCLK [19]
Parameter Description Min. Max. Unit
tIFCLK IFCLK Period 20.83 200 ns
tSPE PKTEND to Clock Setup T im e 8.6 ns
tPEH Clock to PKTEND Hold Time 2.5 ns
tXFLG Clock to FLAGS Output Propagation Delay 13.5 ns
CY7C64713/14
Document #: 38-08039 Rev. *B Page 39 of 50
corner case condition that needs attention. While using the
PKTEND to commit a one byte/word packet, an additional
timing requirement needs to be met when the FIFO is
configured to operate in auto mode and it is desired to send
two packets back to back:
•A full packet (full defined as the number of bytes in the FIFO
meeting the level set in AUTOINLEN register) committed
automatically followed by
•A short one byte/word packet committed manually using the
PKTEND pin.
In this particular scenario, the developer must make sure to
assert PKTEND at least one clock cycle after the rising edge
that caus ed the last by te/w o rd to be clocked into the pr ev iou s
auto committed packet. Figure 10-10 below shows this
scenario. X is the value the AUTOINLEN register is set to
when the IN endpoint is configured to be in auto mode.
Figure 10-10 shows a sc enario whe re two packets are be ing
committed. The first packet gets comitted automatically when
the number of bytes in the FIFO reaches X (value set in
AUTOINLEN register) and the second one byte/word short
packet being committed manually using PKTEND. Note that
there is atleast one IFCLK cycle timing between asserting
PKTEND and clocking of the last byte of the previous packet
(causin g the p ac k et to b e co mm itted automatically). F ailing to
adhere to this timing, will result in the FX2 failing to send the
one byte/word short packet.
10.11 Slave FIFO Asynchronous Packet End Strobe
Table 10-14. Slave FIFO Asynchronous Packet End Strobe Parameters[20]
Parameter Description Min. Max. Unit
tPEpwl PKTEND Pulse Width LOW 50 ns
tPWpwh PKTEND Pulse Width HIGH 50 ns
tXFLG PKTEND to FLAGS Output Propagation Delay 115 ns
IFCLK
SLWR
DATA
Figure 10-10. Slave FIFO Synchronous Write Sequence and Timing Diagram
tIFCLK
>= tSWR >= tWRH
X-2
PKTEND
X-3
tFAH
tSPE tPEH
FIFOADR
tSFD tSFD tSFD
X-4
tFDH
tFDH
tFDH
tSFA
1
X
tSFD tSFD tSFD
X-1
tFDH
tFDH
tFDH
Atleast one IFCLK cycle
FLAGS tXFLG
PKTEND tPEpwl
tPEpwh
Figure 10-11. Slave FIFO Asynchronous Packet End Strobe Timing Diagram[17]
CY7C64713/14
Document #: 38-08039 Rev. *B Page 40 of 50
10.12 Slave FIF O Outp ut Enab le
10.13 Slave FIFO Address to Flags/Data
Table 10-15. Slave FIFO Output Enable Parameters
Parameter Description Min. Max. Unit
tOEon SLOE Assert to FIFO DATA Output 10.5 ns
tOEoff SLOE Deassert to FIFO DATA Hold 10.5 ns
SLOE
DATA tOEon tOEoff
Figure 10-12. Slave FIFO Output Enable Timing Diagram[17]
Table 10-16. Slave FIFO Address to Flags/Data Parameters
Parameter Description Min. Max. Unit
tXFLG FIFOADR[1:0] to FLAGS Output Propagation Delay 10.7 ns
tXFD FIFOADR[1:0] to FIFODATA Output Propagation Delay 14.3 ns
FIFOADR [1.0]
DATA
tXFLG
tXFD
FLAGS
NN+1
Figure 10-13. Slave FIFO Address to Flags/Data Timing Diagram[17]
CY7C64713/14
Document #: 38-08039 Rev. *B Page 41 of 50
10.14 Slave FIFO Synchronous Address
10.15 Slave FIFO Asynchronous Address
Table 10-17. Slave FIFO Synchronous Address Parameters [19]
Parameter Description Min. Max. Unit
tIFCLK Interface Clock Period 20.83 200 ns
tSFA FIFOADR[1:0] to Clock Setup Time 25 ns
tFAH Clock to FIFOADR[1:0] Hold Time 10 ns
IFCLK
SLCS/FIFOADR [1:0]
tSFA tFAH
Figure 10-14. Slave FIFO Synchronous Address Timing Diagram
Table 10-18. Slave FIFO Asynchronous Address Parameters[20]
Parameter Description Min. Max. Unit
tSFA FIFOADR[1:0] to RD/WR/PKTEND Setup Time 10 ns
tFAH RD/WR/PKTEND to FIFOADR[1:0] Hold Time 10 ns
RD/WR/PKTEND
SLCS/FIFOADR [1:0]
tSFA tFAH
Figure 10-15. Slave FIFO Asynchronous Address Timing Diagram[17]
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Document #: 38-08039 Rev. *B Page 42 of 50
10.16 Sequence Diagram
10.16.1 Single and Burst Synchronous Read Example
Figure 10-16 shows the timing relationship o f the SLA VE FIFO
signals during a synchronous FIFO read using IFCLK as the
synchronizing clock. The diagram illustrates a single read
followed by a burst read.
•At t = 0 t he FI FO add res s is s t ab le a nd the s ig nal SLC S i s
asse rted (SLCS may be tied low in some applications).
Note: tSFA has a minimum of 25 nsec. This means when
IFCLK is runn ing at 48 MHz, th e FIFO ad dres s setu p time
is more than one IFCLK cycle.
•At = 1, SLOE is asserted. SLOE is an output enable only,
whose so le fu nc tio n is to drive the dat a bus . Th e da ta that
is driven on the bus is the data that the internal FIFO pointer
is currently pointing to. In this example it is the first data
value in the FIFO. Note: the data is pre-fetched and is driven
on the bus when SL OE is asserted.
•At t = 2, SLRD is asserted. SLRD must meet the setup time
of tSRD (time from asserting the SLRD signal to the rising
edge of the IFCLK) and main t ain a minim um hold tim e of
tRDH (time from the IFCLK edge to the de-assertion of the
SLRD signal). If the SLCS signal is used, it must be asserted
with SLRD, or bef ore SLRD is ass erted (i.e. the SLCS and
SLRD signals mu st both be asse r ted to st a rt a valid read
condition).
•The FIFO pointer is updated on the rising edge of the IFCLK,
while SLRD is asserted. This starts the propagation of data
from the newly addressed location to the data bus. After a
propagation delay of tXFD (measured from the rising edge
of IFCL K) the ne w data value is pres ent . N is th e fi rst data
value read from the FIFO. In order to have data on the FIFO
data bus , SLOE MU ST also be ass erte d.
The same se quence of even ts a re show n for a bur st read an d
are marked with the time indicators of T=0 through 5. Note:
For the burst mode, the SLRD and SLOE are left asserted
during the entire duratio n of the rea d. In the burst read mode,
when SLOE is asserted, data indexed by the FIFO pointer is
on the dat a bu s. Dur ing the first rea d cycl e, on the ris ing edg e
of the clock the FIFO pointer is updated and increments to
point to address N+1. For each subsequent rising edge of
IFCLK, while the SLRD is asserted, the FIFO pointer is incre-
mented and the next data value is placed on the data bus.
IFCLK
SLRD
FLAGS
SLOE
DATA
Figure 10-16. Slave FIFO Synchronous Read Sequence and Timing Diagram
tSRD tRDH
tOEon
tXFD
tXFLG
tIFCLK
N+1
Data Driven: N
>= tSRD
tOEon
tXFD
N+2
tXFD tXFD
>= tRDH
tOEoff
N+4
N+3
tOEoff
tSFA tFAH
FIFOADR
SLCS
t=0
N+1
t=1
t=2 t=3
t=4
tFAH
T=0
tSFA
T=1
T=2 T=3
T=4
NNN+1 N+2
FIFO POINT ER N+3
FIFO DATA BUS
N+4
Not Driven Driven: N
SLOE SLRD
N+1 N+2 N+3 Not Driven
SLRD
SLOE
IFCLK
Figure 10-17. Slave FIFO Synchronous Sequence of Events Diagram
IFCLK IFCLK IFCLK IFCLK N+4
N+4
IFCLK IFCLKIFCLK IFCLK
SLRD
N+1
SLRD
N+1
N+1
SLOE
Not Driven
N+4
N+4
IFCLK
SLOE
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Document #: 38-08039 Rev. *B Page 43 of 50
10.16.2 Single and Burst Synchronous Write
The Figure 10-18 shows the timing relationship of the SLAVE
FIFO signals during a synchronous write using IFCLK as the
synchronizing clock. The diagram illustrates a single write
follow ed by burst wr ite of 3 by tes and commi tting all 4 by tes as
a short packet using the PKTEND pin.
•At t = 0 t he FI FO add res s is s t ab le a nd the s ig nal SLC S i s
asserted. (SLCS may be tied low in some applications)
Note: tSFA has a minimum of 25 ns. This means when IFCLK
is running at 48 MHz , the FIFO add ress setup time is more
than one IFCLK cycle.
•At t = 1, the external master/peripheral must outputs the
data value onto the data bus with a minimum set up time of
tSFD before the rising edge of IFCLK.
•At t = 2, SL WR is asserted. The SL WR must meet the setup
time of tSWR (time from asserting the S LWR si gnal to the
rising edg e of IFCLK) and maintain a minimum hold time of
tWRH (time from th e IF CLK e dge to the de-assertio n o f th e
SLWR signal). If SLCS signal is used, it must be asserted
with SLWR or before SL WR is asserted. (i.e. the SLCS and
SLWR sig na ls must both be asser ted to start a valid write
condition).
•While the SL WR is asserted, data is written to the FIFO and
on the rising edge of the IFCLK, the FIFO pointer is incre-
mented. The FIFO flag will al so be updated af ter a dela y of
tXFLG from the rising edge of the clock.
The same sequence of events are a lso shown for a burst writ e
and are marked with the time indicators of T=0 through 5.
Note: For the burst mode, SLWR and SLCS are left asserted
for the enti re durat ion of writ ing all the required dat a valu es. In
this bu rst w rite m ode, once the SLWR is asse rted, t he data on
the FIFO data bus is written to the FIFO on every rising edge
of IFCLK. Th e FIFO pointer is upd ated on ea ch rising edge of
IFCLK. In Figure 10-18, once the four bytes are written to the
FIFO, SLWR is de-asserted. The short 4-byte packet can be
committed to the host by asserting the PKTEND signal.
There is no specific timing requirement that needs to be met
for asserting PKTEND signal with regards to asserting the
SLWR signal. PKTEND can be asserted with the last data
value or thereafter. The only consideration is the setup time
tSPE and the hold time tPEH must be met. In the scenario of
Figure 10-18, the number of data values committed includes
the last value written to the FIFO. In this example, both the
data value and the PKTEND signal are clocked on the same
rising edge of IFCLK. PKTEND can be asserted in subsequent
clock cycles. The FIFOADDR lines should be held constant
during the PKTEND assertion.
Although there are no specific timi ng requirement for asserting
PKTEND, there is a spec ifi c corn er ca se co nd ition that need s
attention while using the PKTEND to commit a one byte/word
packet. Additional timing requirements exists when the FIFO
is conf igured to o perate i n auto mode a nd it i s des ired to sen d
two packets: a full packet (ful l defined as the number of b y tes
in the FIFO meeting the level set in AUTOINLEN register)
committed automatically followed by a short one byte/word
packet committed manually using the PKTEND pin. In this
case, the external master must make sure to assert the
PKTEND pin atleast one clock cycle after the rising edge that
caused the last byte/w ord t o be clock ed i nto the pr eviou s auto
committed pack et ( the pa cket with the number of bytes equal
to what is set in the AUTOINLEN register). Refer to section 10-
10 for further details on this timing.
IFCLK
SLWR
FLAGS
DATA
Figure 10-18. Slave FIFO Synchronous Write Sequence and Timing Diagram[17]
tSWR tWRH
tSFD
tXFLG
tIFCLK
N
>= tSWR >= tWRH
N+3
PKTEND
N+2
tXFLG
tSFA tFAH
tSPE tPEH
FIFOADR
SLCS
tSFD tSFD tSFD
N+1
tFDH
tFDH
tFDH tFDH
t=0
t=1
t=2 t=3
tSFA
tFAH
T=1
T=0
T=2 T=5
T=3 T=4
CY7C64713/14
Document #: 38-08039 Rev. *B Page 44 of 50
10.16.3 Sequence Diagram of a Single and Burst Asynchronous Read
Figure 10-19 diagrams the timing relationship of the SLAVE
FIFO signals during an asynchronous FIFO read. It shows a
single read followed by a burst read.
•At t = 0 t he FI FO add res s is s t ab le and the SLC S si gna l is
asserted.
•At t = 1, SLOE is asserted. This results in the data bus being
driven. The data that is driven on to the bus is previous data,
it data that was in the FIFO from a prior read cycle.
•At t = 2, SLRD is asserted. The SLRD must meet the
minimum active pulse of tRDpwl and minimum de-active
pulse width of tRDpwh. If SLCS is used then, SLCS mu st be
in asserted with SLRD or before SL RD is asserted. (i.e. the
SLCS and SLRD signals must both be asserted to start a
valid read condition.)
•The data that will be driven, after asserting SLRD, is the
updated data from the FIFO. This data is valid after a propa-
gation delay of tXFD from the activating edge of SLRD. In
Figure 10-19, data N is the first valid data read from the
FIFO. For data to appear on the data bus during the read
cycle (i.e. SLRD is asserted), SLOE MUST be in an asserted
state. SLRD and SLOE can also be tied together.
The same sequence of events is also shown for a burst read
marked with T = 0 throu gh 5. Note: In burst rea d mode, during
SLOE is assertion, the dat a bus is in a driven state and out puts
the pr ev ious data. On ce S LRD is as ser ted, the data fr om t he
FIFO is driven on the data bus (SLOE must also be asserted)
and then the FIFO pointer is incremented.
SLRD
FLAGS
SLOE
DATA
Figure 10-19. Slave FIFO Asynchronous Read Sequence and Timing Diagram
tRDpwh
tRDpwl
tOEon
tXFD
tXFLG
N
Data (X)
tXFD
N+1
tXFD
tOEoff
N+3
N+2
tOEoff
tXFLG
tSFA tFAH
FIFOADR
SLCS
Driven
tXFD
tOEon
tRDpwh
tRDpwl tRDpwh
tRDpwl tRDpwh
tRDpwl
tFAH tSFA
N
t=0 T=0
T=1 T=7
T=2 T=3 T=4 T=5 T=6
t=1
t=2 t=3
t=4
NN
SLOE SLRD
FIFO POINTER
N+3
FIFO DATA BUS Not Driven Driven: X N Not Driven
SLOE
N
N+2
N+3
Figure 10-20. Slave FIFO Asynchronous Read Sequence of Events Diagram
SLRD
N
N+1
SLRD
N+1
SLRD
N+1
N+2
SLRD
N+2
SLRD
N+2
N+1
SLOE
Not Driven
SLOE
N
N+1
N+1
CY7C64713/14
Document #: 38-08039 Rev. *B Page 45 of 50
10.16.4 Sequence Diagram of a Single and Burst Asynchronous Write
Figure 10-21 diagrams the timing relationship of the SLAVE FIFO write in an asynchronous mode. The diagram shows a single
write followed by a burst write of 3 bytes and committing the 4-byte-short packet using PKTEND.
·At t = 0 the FIFO addre ss is applie d, insuring t hat it meet s the setu p time of tSFA. If SLCS is used, it must also be asserted (SLCS
may be tied low in some applications).
·At t = 1 SLWR is asserted. SLWR m ust me et the mi nimum ac tive pu lse of tWRpwl and minimum de-active pulse width of tWRpwh.
If the SLCS is used, it must be in asserted with SLWR or before SLWR is asserted.
·At t = 2, data must be present on the bus tSFD before the de-asserting edge of SLWR.
·At t = 3, deasse rting SL WR will c ause the data to be w ritten from the dat a bus to the FIFO and then increments the FIFO pointer.
The FIFO flag is also updated after tXFLG from the de-asserting edge of SLWR.
The same sequence of events are shown for a burst write and is indicated by the timing marks of T = 0 through 5. Note: In the
burst wr ite mode, o nce SLWR is deasserte d, the da ta is writt en to the FIFO and then the FIFO pointe r is inc remen ted to the next
byte in the FIFO. The FIFO pointer is post incremented.
In Figure 10-21 once the four bytes are written to the FIFO and SLWR is deasserted, the short 4-byte packet can be committed
to the host us ing the PKTEND. Th e external dev ice shoul d be designe d to not assert SLWR and the PKTEND signa l at the same
time. It s ho uld be des ig ned to assert t he PKTEND after SLWR is deasser ted a nd me t the mi nim um de as se rted pul se w id t h. Th e
FIFOADDR lines are to be held constant during the PKTEND assertion.
11.0 Ordering Information
PKTEND
SLWR
FLAGS
DATA
Figure 10-21. Slave FIFO Asynchronous Write Sequence and Timing Diagram[17]
tWRpwh
tWRpwl
tXFLG
N
tSFD
N+1
tXFLG
tSFA tFAH
FIFOADR
SLCS
tWRpwh
tWRpwl tWRpwh
tWRpwl tWRpwh
tWRpwl
tFAH tSFA
tFDH tSFD
N+2
tFDH tSFD
N+3
tFDH
tSFD tFDH
tPEpwh
tPEpwl
t=0
t=2
t =1 t=3
T=0
T=2
T=1 T=3 T=6 T=9
T=5 T=8
T=4 T=7
Table 11-1. Ordering Information
Ordering Code Package Type RAM Size # Prog I/Os
8051
Address
/Data Busses
Ideal for battery powered applications
CY7C64714-128AXC 128 TQFP – Lead-Free 16K 40 16/8 bit
CY7C64714-100AXC 100 TQFP – Lead-Free 16K 40 –
CY7C64714-56LFXC 56 QFN – Lead-Free 16K 24 –
Ideal for non-battery powered applications
CY7C64713-128AXC 128 TQFP - Lead-Free 16K 40 16/8 bit
CY7C64713-100AXC 100 TQFP - Lead-Free 16K 40 -
CY7C64713-56LFXC 56 QFN - Lead-Free 16K 24 -
CY3674 EZ-USB FX1 Development Kit
CY7C64713/14
Document #: 38-08039 Rev. *B Page 46 of 50
12.0 Package Diagrams
The FX1 is available in three packages:
•56-pin QFN
•100-pin TQ FP
•128-pin TQ FP
Package Diagrams
0.80[0.031]
7.70[0.303]
7.90[0.311]
A
C
1.00[0.039] MAX.
N
SEATING
PLANE
N
2
0.18[0.007]
0.50[0.020]
11
0.08[0.003]
0.50[0.020]
0.05[0.002] MAX.
2
(4X)
C
0.24[0.009]
0.20[0.008] REF.
0.80[0.031] MAX.
PIN1 ID
0°-12°
6.45[0.254]
8.10[0.319]
7.80[0.307]
6.55[0.258]
0.45[0.018]
0.20[0.008] R.
8.10[0.319]
7.90[0.311]
7.80[0.307]
7.70[0.303]
DIA.
0.28[0.011]
0.30[0.012]
6.55[0.258]
6.45[0.254]
0.60[0.024]
TOP VIEW BOTTOM VIEW
SIDE VIEW
E-PAD
(PAD SIZE VARY
BY DEVICE TYPE)
51-85144-*D
Figure 12-1. 56-Lead QFN 8 x 8 mm LF56A
CY7C64713/14
Document #: 38-08039 Rev. *B Page 47 of 50
Package Diagrams (continued)
51-85050-*A
Figure 12-2. 100-Pin Thin Plastic Quad Flatpack (14 x 20 x 1.4 mm) A101
CY7C64713/14
Document #: 38-08039 Rev. *B Page 48 of 50
13.0 Quad Flat Package No Leads (QFN)
Package Design Notes
Electrical contact of the part to the Printed Circuit Board (PCB)
is made by soldering the leads on the bottom surface of the
package to the PCB. Hence, special attention is required to the
heat transfer area below the package to provide a good
thermal bond to the circuit board. A Copper (Cu) fill is to be
designed into the PCB as a thermal pad under the package.
Heat is transferred from the FX1 through the device’s metal
paddle on the bottom side of the package. Heat from here, is
conducted to the PCB at the thermal pad. It is then conducted
from the thermal pad to t he PCB in ner ground plane by a 5 x 5
array of via. A via is a plated through hole in the PCB with a
finishe d diameter of 13 mil. The QFN’s metal die paddl e mus t
be soldered to the PCB’s thermal pad. Sol d er ma sk is pla c ed
on the board top side over each via to resist solder flow into
the via. The mask on the top side also minimizes outgassing
during the solder reflow process.
For further information on this package design please refer to
the application note Surface Mount Assembly of AMKOR’s
MicroLeadFrame (MLF) T echnology. This application note can
be downloaded from AMKOR’s website from the following
URL
http://www.amkor.com/products/notes_papers/MLF_AppNote
_0902.pdf. The application note provides detailed information
on board mounti ng guidel ines, s oldering flow , re work pr ocess,
etc.
Figure 13-1 below disp lays a cross-se ctional area undern eath
the package. The cross section is of only one via. The solder
paste template needs to be designed to allow at least 50%
solder coverage. The thickness of the solder paste template
should be 5 mil. It is recommended that “No Clean” type 3
solde r paste is us ed for moun ting th e part . Nitroge n purge is
recomm end ed duri ng reflow.
Package Diagrams (continued)
51-85101-*B
Figure 12-3. 128-Lead Thin Plastic Quad Flatpack (14 x 20 x 1.4 mm) A128
CY7C64713/14
Document #: 38-08039 Rev. *B Page 49 of 50
© Cypress Semiconducto r Corpor ati on, 2005. The informat i on cont ained her ein i s subject to change with out notice. Cy press Sem iconducto r Corporation assum es no respo nsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Figure 13-2 is a plot of t he sol der mas k patte rn and Figure 13-3 d ispla ys an X-R ay ima ge of th e asse mbly (darker a rea s indi cate
solder).
Purchase of I2C co mponent s from Cypres s, or one of it s sublicens ed Associate d Companie s, conveys a licen se under the Philips
I2C Patent Rights to use these components in an I2C system, provided that the system confo rms to the I2C S tandard S pecificatio n
as defined by Philips. EZ-USB FX1, EZ-USB FX2LP, EZ-USB FX2, and ReNumeration are trademarks, and EZ-USB is a registered
trademark, of Cypress Semiconductor. All product and company names mentioned in this document are the trademarks of their
respective holders.
0.017” dia
Solder Mask Cu Fill
Cu Fill
PCB Material
PCB Material 0.013” dia
Via hole for thermally connecting the
QFN to the circuit board ground plane. This figure only shows the top three layers of the
circuit board: Top Solder, PCB Dielectric, and
the Ground Plane
Figure 13-1. Cross-section of the Area Underneath the QFN Package
Figure 13-2. Plot of the Solder Mask (White Area)
Figure 13-3. X-ray Image of the Assembly
CY7C64713/14
Document #: 38-08039 Rev. *B Page 50 of 50
© Cypress Semiconducto r Corpor ati on, 2005. The informat i on cont ained her ein i s subject to change with out notice. Cy press Sem iconducto r Corporation assum es no respo nsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Document History Page
Document Title: CY7C64713/4 EZ-USB FX1™ USB Microcontroller Full-Speed USB Peripheral Controller
Document Numbe r: 38-080 39
REV. ECN NO. Issue Date Orig. of
Change Description of Change
** 132091 02/10/04 KKU New Data Sheet
*A 230709 SEE ECN KKU Changed Lead free Marketing part numbers in Table 11-1 according to spec
change in 28-00054.
*B 307474 SEE ECN BHA Changed default PID in Table 4-2.
Updat ed regi ste r ta ble .
Removed word compatible where associated with I2C.
Changed Set-up to Setup.
Added Power Dissipation.
Changed Vcc from ± 10% to ± 5%
Added values for VIH_X, VIL_X
Added values for ICC
Added values for ISUSP
Removed IUNCONFIGURED from table 9-1
Changed PKTEND to FLAGS output propagation delay (asynchronous
interface) in Table 10-14 from a maximum value of 70 ns to 115 ns.
Removed 56 SSOP and added 56 QFN package
Provided additional timing restrictions and requirement regarding the use of
PKTEND pin to commit a short one byte/word packet subsequent to committing
a packet automatically (when in auto mode).
Added part number CY7C64714 ideal for battery powered applications.
Changed Supply Voltage in section 8 to read +3.15V to +3.45V
Added Min Vcc Ramp Up time (0 to 3.3v)
Removed Preliminary
