A428316 Series
Preliminary 256K X 16 CMOS DYNAMIC RAM WITH EDO PAGE MODE
PRELIMINARY (August, 2002, Version 0.3) AMIC Technology, Inc.
Document Title
256K X 16 CMOS DYNAMIC RAM WITH EDO PAGE MODE
Revision History
Rev. No. History Issue Date Remark
0.0 Initial issue June 13, 2001 Preliminary
0.1 Modify AC data April 26, 2002
0.2 Modify DC data and all parts guarantee self-refresh mode June 10, 2002
0.3 Delete -30,-40 grade and add -25 grade August 20, 2002
A428316 Series
Preliminary 256K X 16 CMOS DYNAMIC RAM WITH EDO PAGE MODE
PRELIMINARY (August, 2002, Version 0.3) 1 AMIC Technology, Inc.
Features
n Organization: 262,144 words X 16 bits
n Part Identification
- A428316 (512 Ref.)
n Single 5.0V power supply/built-in VBB generator
n Low power consumption
- Operating: 110mA (-25 max)
- Standby: 2.5mA (TTL), 1.0mA (CMOS)
1.0mA (Self-refresh current)
n High speed
- 25/35 ns RAS access time
- 12/17 ns column address access time
- 8/10 ns CAS access time
- 12/16 ns EDO Page Mode Cycle Time
n Industrial operating temperature range: -40°C to 85°C
for -U
n Fast Page Mode with Extended Data Out
n Separate CAS (UCAS,LCAS ) for byte selection
n 512 Refresh Cycle in 8ms
n Read-modify-write, RAS -only, CAS -before-RAS ,
Hidden refresh capability
n TTL-compatible, three-state I/O
n JEDEC standard packages
- 400mil, 40-pin SOJ
- 400mil, 40/44 TSOP type II package
General Description
The A428316 is a new generation randomly accessed
memory for graphics, organized in a 262,144-word by 16-
bit configuration. This product can execute Byte Write
and Byte Read operation via two CAS pins.
The A428316 offers an accelerated Fast Page Mode
Pin Configuration
nnSOJ nn TSOP
VCC
I/O0
I/O1
NC
A1
A2
A3
VCC A4
A5
A6
A7
A8
I/O13
I/O14
I/O15
VSS
A428316S
21
WE
RAS
I/O12
OE
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
A0
NC
NC
VCC
VSS
UCAS
LCAS
NC
I/O8
I/O9
I/O10
I/O11
VSS
20
19
18
12
16
17
13
14
15
11
10
9
8
7
6
5
4
3
2
1
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40 VCC
I/O0
I/O1
NC
A1
A2
A3 A4
A5
A6
A7
A8
I/O13
I/O14
I/O15
VSS
A428316V
23
WE
RAS
I/O12
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
A0
NC
NC
VCC
VSS
UCAS
LCAS
NC
I/O8
I/O9
I/O10
I/O11
VSS
22
21
20
14
18
19
15
16
17
13
10
9
8
7
6
5
4
3
2
1
24
25
26
27
28
29
30
31
32
35
36
37
38
39
40
41
42
43
44
VCC
OE
cycle with a feature called Extended Data Out (EDO).
This allow random access of up to 512 words within a row
at a 83/62 MHz EDO cycle, making the A428316 ideally
suited for graphics, digital signal processing and high
performance computing systems.
Pin Descriptions
Symbol Description
A0 – A8 Address Inputs
I/O0 - I/O15 Data Input/Output
RAS Row Address Strobe
LCAS Column Address Strobe for Lower Byte
(I/O0 – I/O7)
UCAS Column Address Strobe for Upper Byte
(I/O8 – I/O15)
WE Write Enable
OE Output Enable
VCC 5.0V Power Supply
VSS Ground
NC No Connection
A428316 Series
PRELIMINARY (August, 2002, Version 0.3) 2 AMIC Technology, Inc.
Selection Guide
Symbol Description -25 -35 Unit
tRAC Maximum RAS Access Time 25 35 ns
tAA Maximum Column Address Access Time 12 17 ns
tCAC Maximum CAS Access Time 8 10 ns
tOEA Maximum Output Enable (OE) Access Time 8 10 ns
tRC Minimum Read or Write Cycle Time 44 62 ns
tPC Minimum EDO Cycle Time 12 16 ns
Functional Description
The A428316 reads and writes data by multiplexing an 18-
bit address into a 9-bit row and 9-bit column address.
RASand CAS are used to strobe the row address and the
column address, respectively.
The A428316 has two CAS inputs: LCAS controls I/O0-
I/O7, and UCAS controls I/O8 - I/O15, UCAS and LCAS
function in an identical manner to CAS in that either will
generate an internal CAS signal. The CAS function and
timing are determined by the first CAS ( UCAS or
LCAS ) to transition low and by the last to transition high.
Byte Read and Byte Write are controlled by using LCAS
and UCAS separately.
A Read cycle is performed by holding the WE signal high
during RAS/CAS operation. A Write cycle is executed by
holding the WE signal low during RAS /CAS operation;
the input data is latched by the falling edge of WE or
CAS, whichever occurs later. The data inputs and outputs
are routed through 16 common I/O pins, with RAS, CAS,
WE and OE controlling the in direction.
EDO Page Mode operation all 512 columns within a
selected row to be randomly accessed at a high data rate.
A EDO Page Mode cycle is initiated with a row address
latched by RAS followed by a column address latched by
CAS . While holding RAS low, CAS can be toggled to
strobe changing column addresses, thus achieving shorter
cycle times.
The A428316 offers an accelerated Fast Page Mode cycle
through a feature called Extended Data Out, which keeps
the output drivers on during the CAS precharge time (tcp).
Since data can be output after CAS goes high, the user is
not required to wait for valid data to appear before starting
the next access cycle. Data-out will remain valid as long as
RAS and OE are low, and WE is high; this is the only
characteristic which differentiates Extended Data Out
operation from a standard Read or Fast Page Read.
A memory cycle is terminated by returning both RAS and
CAS high. Memory cell data will retain its correct state by
maintaining power and accessing all 512 combinations of
the 9-bit row addresses, regardless of sequence, at least
once every 8ms through any RAS cycle (Read, Write) or
RAS Refresh cycle (RAS-only, CBR, or Hidden). The CBR
Refresh cycle automatically controls the row addresses by
invoking the refresh counter and controller.
Power-On
The initial application of the VCC supply requires a 200 µs
wait followed by a minimum of any eight initialization cycles
containing a RAS clock. During Power-On, the VCC
current is dependent on the input levels of RAS and CAS.
It is recommended that RAS and CAStrack with VCC or
be held at a valid VIH during Power-On to avoid current
surges.
A428316 Series
PRELIMINARY (August, 2002, Version 0.3) 3 AMIC Technology, Inc.
Block Diagram
Recommended Operating Conditions (Ta = 0°C to +70°C or -40°C to +85°C)
Symbol Description Min. Typ. Max. Unit Notes
VCC Power Supply 4.5 5.0 5.5 V 1
VSS Input High Voltage 0.0 0.0 0.0 V 1
VIH Input High Voltage 2.4 - VCC + 1.0 V 1
VIL Input Low Voltage -0.5 - 0.8 V 1
VSS
VCC
CAS Clock
Generator
Column
Address
Buffers
Refresh
Counter &
Controller
Row
Address
Buffers
RAS Clock
Generator
WE Clock
Generator
ROW DECODER
OE Clock
Generator
AY0 - AY8
AX0 - AX8
Sense Amplifiers
Column Decoders Data I/O
Buffers
Memory Array
512 x 512 x 16
.
.
.
512
.
.
.
. . 512 x 16 . .
I/O0
to
I/O15
OE
WE
UCAS
LCAS
A0 - A8
RAS
A428316 Series
PRELIMINARY (August, 2002, Version 0.3) 4 AMIC Technology, Inc.
Truth Table
Function RAS UCAS LCAS WE OE Address I/Os Notes
Standby H H H X X X High-Z
Read: Word L L L H L Row/Col. Data Out
Read: Lower Byte L H L H L Row/Col. I/O0-7 = Data Out
I/O8-15 = High-Z
Read: Upper Byte L L H H L Row/Col. I/O0-7 = High-Z
I/O8-15 = Data Out
Write: Word L L L L H Row/Col. Data In
Write: Lower Byte L H L L H Row/Col. I/O0-7 = Data In
I/O8-15 = X
Write: Upper Byte L L H L H Row/Col. I/O0-7 = X
I/O8-15 = Data In
Read-Write L L L H→L L→H Row/Col. Data Out → Data In 1,2
EDO-Page-Mode Read: Hi-Z
-First cycle
-Subsequent Cycles
L
L
H→L
H→L
H→L
H→L
H
H
H→L
H→L
Row/Col.
Col.
Data Out
Data Out
2
2
EDO-Page-Mode Write
-First cycle
-Subsequent Cycles
L
L
H→L
H→L
H→L
H→L
L
L
H
H
Row/Col.
Col.
Data In
Data In
1
1
EDO-Page-Mode Read-Write
-First cycle
-Subsequent Cycles
L
L
H→L
H→L
H→L
H→L
H→L
H→L
L→H
L→H
Row/Col.
Col.
Data Out → Data In
Data Out → Data In
1, 2
1, 2
Hidden Refresh Read L→H→L
L L H L Row/Col. Data Out 2
Hidden Refresh Write L→H→L
L L L X Row/Col. Data In → High-Z 1
RAS-Only Refresh L H H X X Row High-Z
CBR Refresh H→L L L X X X High-Z 3
Self Refresh H→L L L H X X High-Z
Note: 1. Byte Write may be executed with either UCAS or LCAS active.
2. Byte Read may be executed with either UCAS or LCAS active.
3. Only one CAS signal (UCAS or LCAS ) must be active.
A428316 Series
PRELIMINARY (August, 2002, Version 0.3) 5 AMIC Technology, Inc.
Absolute Maximum Ratings*
Input Voltage (Vin) . . . . . . . . . . . . . . . . . . . . -1.0V to +7.0V
Output Voltage (Vout) . . . . . . . . . . . . . . . . . -1.0V to +7.0V
Power Supply Voltage (VCC) . . . . . . . . . . . -1.0V to +7.0V
Operating Temperature (TOPR) . . . . . . . . . . . . 0°C to +70°C
Storage Temperature (TSTG) . . . . . . . . . . . -55°C to +150°C
Soldering Temperature X Time (TSOLDER) . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C X 10sec
Power Dissipation (PD) . . . . . . . . . . . . . . . . . . . . . . . . . . 1W
Short Circuit Output Current (Iout) . . . . . . . . . . . . . . . 50mA
Latch-up Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200mA
*Comments
Stresses above those listed under "Absolute Maximum
Ratings" may cause permanent damage to this device.
These are stress ratings only. Functional operation of
this device at these or any other conditions above
those indicated in the operational sections of these
specification is not implied or intended. Exposure to
the absolute maximum rating conditions for extended
periods may affect device reliability.
DC Electrical Characteristics (VCC = 5.0V ± 10%, VSS = 0V, Ta = 0°C to +70°C or -40°C to +85°C)
-25 -35 Unit Test Conditions Notes Symbol Parameter
Min. Max. Min. Max.
IIL Input Leakage Current -5 +5 -5 +5 µA 0V ≤ Vin ≤ VCC
Pins not under
Test = 0V
IOL Output Leakage Current -5 +5 -5 +5 µA DOUT disabled,
0V ≤ Vout ≤ VCC
ICC1 Operating Power Supply
Current - 115 - 105 mA RAS,UCAS,LCAS and
Address cycling;
tRC = min.
1, 2
ICC2 TTL Supply Current Supply
Current - 2.5 - 2.5 mA RAS=UCAS=LCAS= VIH
ICC3 Average Power Supply
Current, RAS Refresh
Mode
- 115 - 105 mA RAS and Address cycling,
UCAS=LCAS = VIH,
tRC = min.
1
ICC4 EDO Page Mode Average
Power Supply Current - 115 - 105 mA RAS and address = VIL,
UCAS,LCAS and
Address cycling;
tPC = min.
1, 2
ICC5 CAS-before-RAS Refresh
Power Supply Current - 115 - 105 mA RAS and UCAS or
LCAS cycling;
tRC = min.
1
ICC6 CMOS Standby Power
Supply Current - 1.0 - 1.0 mA RAS=UCAS=LCAS =
VCC - 0.2V
ICC7 Self Refresh Mode Current - 1.0 - 1.0 mA RAS=CAS≤VSS+0.2V
All other input high levels
are VCC-0.2V or input low
levels are VSS +0.2V
VOH 2.4 - 2.4 - V IOUT = -5.0mA
VOL Output Voltage - 0.4 - 0.4 V IOUT = 4.2mA
A428316 Series
PRELIMINARY (August, 2002, Version 0.3) 6 AMIC Technology, Inc.
AC Characteristics (VCC = 5.0V ± 10%, VSS = 0V, Ta = 0°C to +70°C or -40°C to +85°C)
Test Conditions:
Input timing reference level: VIH/VIL=2.4V/0.8V
Output reference level: VOH/VOL=2.0V/0.8V
Output Load: 2TTL gate + CL (50pF)
Assumed tT=2ns
-25 -35
# Std
Symbol
Parameter Min. Max. Min. Max.
Unit
Notes
tT Transition Time (Rise and Fall) 1 50 1 50 ns 4, 5
1 tRC Random Read or Write Cycle Time 44 - 62 - ns
2 tRP RAS Precharge Time 15 - 23 - ns
3 tRAS RAS Pulse Width 25 10K 35 10K ns
4 tCAS CAS Pulse Width 4 10K 6 10K ns
5 tRCD RAS to CAS Delay Time 10 21 10 25 ns 6
6 tRAD RAS to Column Address Delay Time 8 14 8 18 ns 7
7 tRSH CAS to RAS Hold Time 5 - 6 - ns
8 tCSH CAS Hold Time 25 - 31 - ns
9 tCRP CAS to RAS Precharge Time 5 - 5 - ns
10 tASR Row Address Setup Time 0 - 0 - ns
11 tRAH Row Address Hold Time 5 - 6 - ns
12 tCLZ CAS to Output in Low Z 3 - 3 - ns 8
13 tRAC Access Time from RAS - 25 - 35 ns 6,7
14 tCAC Access Time from CAS - 8 - 10 ns 6, 13
15 tAA Access Time from Column Address - 12 - 17 ns 7, 13
16 tOEA OE Access Time - 8 - 10 ns
17 tAR Column Address Hold Time from RAS 22 - 31 - ns
18 tRCS Read Command Setup Time 0 - 0 - ns
19 tRCH Read Command Hold Time 0 - 0 - ns 9
A428316 Series
PRELIMINARY (August, 2002, Version 0.3) 7 AMIC Technology, Inc.
AC Characteristics (continued) (VCC = 5.0V ± 10%, VSS = 0V, Ta = 0°C to +70°C or -40°C to +85°C)
Test Conditions:
Input timing reference level: VIH/VIL=2.4V/0.8V
Output reference level: VOH/VOL=2.0V/0.8V
Output Load: 2TTL gate + CL (50pF)
Assumed tT=2ns
-25 -35
# Std
Symbol
Parameter Min. Max. Min. Max.
Unit
Notes
20 tRRH Read Command Hold Time Reference to RAS 0 - 0 - ns 9
21 tRAL Column Address to RAS Lead Time 12 - 17 - ns
22 tCOH Output Hold After CAS Low 3 - 3 - ns
23 tOFF Output Buffer Turn-Off Delay Time - 3 - 3 ns 8, 10
24 tASC Column Address Setup Time 0 - 0 - ns
25 tCAH Column Address Hold Time 5 - 6 - ns
26 tOES OE Low to CAS High Set Up 5 - 7 - ns
27 tWCS Write Command Setup Time 0 - 0 - ns 11
28 tWCH Write Command Hold Time 5 - 6 - ns 11
29 tWCR Write Command Hold Time to RAS 22 - 31 - ns
30 tWP Write Command Pulse Width 5 - 6 - ns
31 tRWL Write Command to RAS Lead Time 7 - 10 - ns
32 tCWL Write Command to CAS Lead Time 5 - 7 - ns
33 tDS Data-in setup Time 0 - 0 - ns 12
34 tDH Data-in Hold Time 5 - 6 - ns 12
35 tDHR Data-in Hold Time to RAS 22 - 31 - ns
36 tRWC Read-Modify-Write Cycle Time 62 - 85 - ns
37 tRWD RAS to WE Delay Time (Read-Modify-Write) 34 - 46 - ns 11
38 tCWD CAS to WE Delay Time (Read-Modify-Write) 17 - 21 - ns 11
A428316 Series
PRELIMINARY (August, 2002, Version 0.3) 8 AMIC Technology, Inc.
AC Characteristics (continued) (VCC = 5.0V ± 10%, VSS = 0V, Ta = 0°C to +70°C or -40°C to +85°C)
Test Conditions:
Input timing reference level: VIH/VIL=2.4V/0.8V
Output reference level: VOH/VOL=2.0V/0.8V
Output Load: 2TTL gate + CL (50pF)
Assumed tT=2ns
-30 -35
# Std
Symbol
Parameter Min. Max. Min. Max.
Unit
Notes
39 tAWD Column Address to WE Delay Time
(Read-Modify-Write) 21 - 28 - ns 11
40 tOEH OE Hold Time from WE 5 - 6 - ns
41 tOEP OE High Pulse Width 5 - 5 - ns
42 tPC Read or Write Cycle Time (EDO Page) 12 - 16 - ns 14
43 tCPA Access Time from CAS Precharge (EDO Page) - 14 - 18 ns 13
44 tCP CAS Precharge Time 4 - 6 - ns
45 tPCM EDO Page Mode RMW Cycle Time 32 - 40 - ns
46 tCRW EDO Page Mode CAS Pulse Width (RMW) 24 - 30 - ns
47 tRASP RAS Pulse Width (EDO Page) 30 200K 35 200K ns
48 tCSR CAS Setup Time (CAS -before-RAS) 5 - 5 - ns 3
49 tCHR CAS Hold Time (CAS -before-RAS) 7 - 10 - ns 3
50 tRPC RAS to CAS Precharge Time 10 - 10 - ns 3
51 tOEZ Output Buffer Turn-off Delay from OE - 3 - 3 ns 8
52 tRASS RAS pulse width (C-B-
R
self refresh) 100 - 100 - µs
53 tRPS RAS precharge time (C-B-
R
self refresh)
44 - 62 - ns
54 tCHS CAShold time (C-B-
R
self refresh) -50 - -50 - ns
A428316 Series
PRELIMINARY (August, 2002, Version 0.3) 9 AMIC Technology, Inc.
Notes:
1. ICC1, ICC3, ICC4, and ICC5 depend on cycle rate.
2. ICC1 and ICC4 depend on output loading. Specified values are obtained with the outputs open.
3. An initial pause of 200µs is required after power-up followed by any 8 RAS cycles before proper device operation is
achieved. In the case of an internal refresh counter, a minimum of 8 CAS-before-RAS initialization cycles instead of 8
RAS cycles are required. 8 initialization cycles are required after extended periods of bias without clocks.
4. AC Characteristics assume tT = 2ns. All AC parameters are measured with a load equivalent to two TTL loads and
50pF, VIL (min.) ≥ GND and VIH (max.) ≤ VCC.
5. VIH (min.) and VIL (max.) are reference levels for measuring timing of input signals. Transition times are measured
between VIH and VIL.
6. Operation within the tRCD (max.) limit insures that tRAC (max.) can be met. tRCD (max.) is specified as a reference
point only. If tRCD is greater than the specified tRCD (max.) limit, then access time is controlled exclusively by tCAC.
7. Operation within the tRAD (max.) limit insures that tRAC (max.) can be met. tRAD (max.) is specified as a reference
point only. If tRAD is greater than the specified tRAD (max.) limit, then access time is controlled exclusively by tAA.
8. Assumes three state test load (5pF and a 500Ω Thevenin equivalent).
9. Either tRCH or tRRH must be satisfied for a read cycle.
10. tOFF (max.) defines the time at which the output achieves the open circuit condition; it is not referenced to output
voltage levels.
11. tWCS, tWCH, tRWD, tCWD and tAWD are not restrictive operating parameters. They are included in the data sheet
as electrical characteristics only. If tWCS ≥ tWCS (min.) and tWCH ≥ tWCH (min.), the cycle is an early write cycle
and data-out pins will remain open circuit, high impedance, throughout the entire cycle. If tRWD ≥ tRWD (min.) , tCWD ≥
tCWD (min.) and tAWD ≥ tAWD (min.), the cycle is a read-modify-write cycle and the data out will contain data read from
the selected cell. If neither of the above conditions is satisfied, the condition of the data out at access time is
indeterminate.
12. These parameters are referenced to UCAS and LCAS leading edge in early write cycles and to WE leading edge in
read-modify-write cycles.
13. Access time is determined by the longer of tAA or tCAC or tCPA.
14. tASC ≥ tCP to achieve tPC (min.) and tCPA (max.) values.
A428316 Series
PRELIMINARY (August, 2002, Version 0.3) 10 AMIC Technology, Inc.
Word Read Cycle
t
RAS(3)
t
RP(2)
t
RC(1)
t
CRP(9)
t
CSH(8)
t
RCD(5)
t
RSH(7)
t
CAS(4)
t
ASR(10)
t
CRP(9)
t
RAH(11)
t
ASC(24)
t
CAH(25)
t
RAD(6)
t
RAL(21)
t
RCH(19)
t
RRH(20)
t
AR(17)
t
RCS(18)
t
OEA(16)
t
RAC(13)
t
AA(15)
t
CAC(14)
t
CLZ(12)
t
OEZ(51)
t
OFF(23)
High-Z
: High or Low
Valid Data-out
Row Address Column Address
I/O
0
~
I/O
15
OE
WE
A0~A8
UCAS
LCAS
RAS
A428316 Series
PRELIMINARY (August, 2002, Version 0.3) 11 AMIC Technology, Inc.
Word Write Cycle (Early Write)
t
RAS(3)
t
RP(2)
t
RC(1)
t
CRP(9)
t
CSH(8)
t
RCD(5)
t
RSH(7)
t
CAS(4)
t
ASR(10)
t
CRP(9)
t
RAH(11)
t
ASC(24)
t
CAH(25)
t
RAD(6)
t
RAL(21)
t
WCH(28)
: High or Low
Row Address Column Address
I/O
0
~
I/O
15
OE
A0~A8
UCAS
LCAS
RAS
t
AR(17)
t
CWL(32)
t
RWL(31)
t
WP(30)
t
WCS(27)
Valid Data-in
t
DS(33)
t
DH(34)
WE
t
WCR(29)
t
DHR(35)
A428316 Series
PRELIMINARY (August, 2002, Version 0.3) 12 AMIC Technology, Inc.
Word Write Cycle (Late Write)
t
RAS(3)
t
RP(2)
t
RC(1)
t
CRP(9)
t
CSH(8)
t
RCD(5)
t
RSH(7)
t
CAS(4)
t
ASR(10)
t
CRP(9)
t
ASC(24)
t
CAH(25)
t
RAD(6)
t
RAL(21)
Row Address Column Address
A0~A8
UCAS
LCAS
RAS
t
AR(17)
t
CWL(32)
t
RWL(31)
t
WP(30)
t
RAH(11)
t
OEH(40)
t
DS(33)
t
DH(34)
I/O
0
~
I/O
15
: High or Low
OE
WE
High-Z Vaild Data-in
t
WCR(29)
t
DHR(35)
A428316 Series
PRELIMINARY (August, 2002, Version 0.3) 13 AMIC Technology, Inc.
Word Read-Modify-Write Cycle
t
RAS(3)
t
RP(2)
t
RWC(36)
t
CRP(9)
t
CSH(8)
t
RCD(5)
t
RSH(7)
t
ASR(10)
t
CRP(9)
t
RAH(11)
t
CAH(25)
t
RAD(6)
Row Address Column AddressA0~A8
UCAS
LCAS
RAS
t
AR(17)
t
RWL(31)
t
ASC(24)
t
CWL(32)
t
AWD(39)
t
CWD(38)
t
RWD(37)
t
WP(30)
t
OEA(16)
t
OEZ(51)
t
CLZ(12)
t
CAC(14)
t
AA(15)
t
RAC(13)
t
DS(33)
t
DH(34)
High-Z Data-out Data-in
: High or Low
I/O
0
~
I/O
15
OE
WE
t
OEH(40)
t
RCS(18)
A428316 Series
PRELIMINARY (August, 2002, Version 0.3) 14 AMIC Technology, Inc.
EDO Page Mode Word Read Cycle
t
RASP(47)
t
RP(2)
RAS
UCAS
LCAS
t
CAS(4)
t
CAS(4)
t
CAS(4)
t
RCD(5)
t
CSH(8)
t
CRP(9)
t
CRP(9)
t
PC(42)
t
RSH(7)
t
ASR(10)
t
RAH(11)
t
RAD(6)
t
AR(16)
t
RAL(21)
A0~A8
OE
WE
I/O
0
~
I/O
15
: High or Low
t
ASC(24)
t
CP(44)
t
CSH(8)
t
ASC(24)
t
CAH(25)
t
CAH(25)
Row Column Column Column
t
RCH(19)
t
RCS(18)
t
RCS(18)
t
RCH(25)
t
RCS(18)
t
CAH(25)
t
RRH(20)
t
OFF(23)
t
OEZ(51)
t
AA(15)
t
OEA(16)
t
OEP(41)
t
CAC(14)
t
CLZ(12)
t
OEZ(51)
t
CPA(43)
t
OES(26)
t
AA(15)
t
OEA(16)
t
COH(22)
t
CAC(14)
t
RAC(13)
t
CAC(14)
t
CLZ(12)
Data-out Data-out Data-out
A428316 Series
PRELIMINARY (August, 2002, Version 0.3) 15 AMIC Technology, Inc.
EDO Page Mode Early Word Write Cycle
t
RASP(47)
t
RP(2)
RAS
UCAS
LCAS
t
CAS(4)
t
CP(44)
t
CAS(4)
t
CP(44)
t
CAS(4)
t
RCD(5)
t
CSH(8)
t
CRP(9)
t
CRP(9)
t
PC(42)
t
RSH(7)
t
ASR(10)
t
RAH(11)
t
RAD(6)
t
ASC(24)
t
CAH(25)
t
ASC(24)
t
CAH(25)
t
CAH(25)
t
ASC(24)
t
RAL(21)
Row Column ColumnA0~A8
WE
t
CWL(32)
t
WCH(28)
t
WCS(27)
t
WCS(27)
Column
t
CWL(32)
t
WCH(28)
t
WCS(27)
t
WCH(28)
t
CWL(32)
t
RWL(31)
t
WP(30)
t
WP(30)
t
WP(30)
t
DH(34)
t
DS(33)
t
DH(34)
t
DS(33)
t
DS(33)
t
DH(34)
Data-in Data-in Data-in
I/O
0
~
I/O
15
OE
: High or Low
A428316 Series
PRELIMINARY (August, 2002, Version 0.3) 16 AMIC Technology, Inc.
EDO Page Mode Word Read-Modify-Write Cycle
t
RASP(47)
RAS
t
CRW(46)
t
CP(44)
t
CRW(46)
t
CP(44)
t
CRW(46)
t
RCD(5)
t
CSH(8)
t
CRP(9)
t
CRP(9)
t
PCM(45)
t
RSH(7)
t
RP(2)
t
ASR(10)
t
RAH(11)
t
RAD(6)
t
ASC(24)
t
CAH(25)
t
ASC(24)
t
CAH(25)
t
ASC(24)
t
CAH(25)
t
RAL(21)
t
RCS(18)
t
CWD(38)
t
RWD(37)
t
CWL(32)
t
CWD(38)
t
CWL(32)
t
CWD(38)
t
CWL(32)
t
RWL(31)
t
OEA(16)
t
OEA(16)
t
OEA(16)
t
WP(30)
t
WP(30)
t
WP(30)
t
AWD(39)
t
AWD(39)
t
AWD(39)
t
CAC(14)
t
AA(15)
t
RAC(13)
t
OEZ(51)
t
DS(33)
t
AA(15)
t
CPA(43)
t
DH(34)
t
OEZ(51)
t
DS(33)
t
DH(34)
t
OEZ(51)
t
DS(33)
t
DH(34)
t
AA(15)
t
CPA(43)
t
CLZ(12)
t
CLZ(12)
t
CLZ(12)
High-Z
: High or Low
I/O
0
~
I/O
15
OE
WE
A0~A8
UCAS
LCAS
Data-out Data-in Data-out Data-in Data-out Data-in
Row Column Column Column
t
OEH(40)
A428316 Series
PRELIMINARY (August, 2002, Version 0.3) 17 AMIC Technology, Inc.
RAS Only Refresh Cycle
CAS Before RAS Refresh Cycle
t
RAS(3)
t
RP(2)
t
RC(1)
RAS
t
CRP(9)
t
RPC(50)
t
ASR(10)
t
RAH(11)
A0~A8
UCAS
: High or Low
Row
Note: WE, OE = Don't care.
LCAS
t
RAS(3)
t
RP(2)
t
RC(1)
RAS
t
RP(2)
t
RPC(50)
t
CP(44)
t
CSR(48)
t
CHR(49)
t
OFF(23)
I/O
0
~
I/O
15
UCAS
High-Z
: High or LowNote: WE, OE, Address = Don't care.
LCAS
A428316 Series
PRELIMINARY (August, 2002, Version 0.3) 18 AMIC Technology, Inc.
Hidden Refresh Cycle (Word Read)
tRAS(3) tRP(2)
tRC(1)
tCRP(9)
tAR(17)
tRCD(5)
tASR(10)
tCRP(9)
tASC(24)
tCAH(25)
tRAD(6)
A0~A8
UCAS
RAS
tRAH(11)
tRRH(20)tRCS(18)
I/O
0
~
I/O
15
: High or Low
OE
High-Z
tRAS(3) tRP(2)
tCHR(49)
tRC(1)
tRSH(7)
tRAL(21)
tCAC(14) tOFF(23)
tAA(15)
tCLZ(12)
tRAC(13)
WE
Row Column
Valid Data-out
LCAS
tOEZ(51)
tOEA(16)
A428316 Series
PRELIMINARY (August, 2002, Version 0.3) 19 AMIC Technology, Inc.
Hidden Refresh Cycle (Early Word Write)
t
RAS(3)
t
RP(2)
t
RC(1)
t
CRP(9)
t
AR(17)
t
RCD(5)
t
ASR(10)
t
CRP(9)
t
ASC(24)
t
CAH(25)
t
RAD(6)
A0~A8
RAS
t
RAH(11)
: High or Low
OE
t
RAS(3)
t
RP(2)
t
CHR(49)
t
RC(1)
t
RSH(7)
t
RAL(21)
WE
Row Column
t
WCS(27)
t
WCH(28)
t
WP(30)
t
DS(33)
t
DH(34)
Valid Data-in
I/O
0
~
I/O
15
UCAS
LCAS
A428316 Series
PRELIMINARY (August, 2002, Version 0.3) 20 AMIC Technology, Inc.
EDO Page Mode Read-Early-Write Cycle (Pseudo Read-Modify-Write)
RAS
: High or Low
I/O
0
~
I/O
15
OE
WE
A0~A8
UCAS
t
RP(2)
t
RASP(47)
t
CRP(9)
t
CSH(8)
t
RCD(5)
t
CAS(4)
t
CP(44)
t
CAS(4)
t
CP(44)
t
CAS(4)
t
CPR(9)
t
RSH(7)
t
PC(42)
t
PC(42)
Row Column Column
t
RAL(21)
t
CAH(25)
t
ASC(24)
t
CAH(25)
t
ASC(24)
t
CAH(25)
t
ASC(24)
t
ASR(10)
t
RAH(11)
t
RAD(6)
Column
t
RCS(18)
t
RCH(19)
t
WCS(27)
t
WCH(28)
Data-out Data-out Data-in
t
DH(34)
t
DS(33)
t
AA(15)
t
CAP(43)
t
CAC(14)
t
COH(22)
t
AA(15)
t
RAC(13)
t
CAC(14)
t
OEA(16)
LCAS
A428316 Series
PRELIMINARY (August, 2002, Version 0.3) 21 AMIC Technology, Inc.
Self Refresh Mode
n Self Refresh Mode.
a. Entering the Self Refresh Mode:
The A428316 Self Refresh Mode is entered by using CAS before RAScycle and holding RAS and CAS signal “low”
longer than 100µs.
b. Continuing the Self Refresh Mode:
The Self Refresh Mode is continued by holding RAS “low” after entering the Self Refresh Mode.
It does not depend on CAS being “high” or “low” after entering the Self Refresh Mode continue the Self Refresh Mode.
c. Exiting the Self Refresh Mode:
The A428316 exits the Self Refresh Mode when the RAS signal is brought “high”.
t
RASS(52)
t
RP(2)
t
CRP(9)
t
CSR(48)
t
RPC(50)
RAS
t
RPS(53)
t
CHS(54)
t
ASR(10)
t
CP(44)
t
OFF(23)
A0~A8
: High or Low
High-Z
I/O
0
~
I/O
15
UCAS
LCAS
ROW COL
Note: WE, OE = Don't care.
A428316 Series
PRELIMINARY (August, 2002, Version 0.3) 22 AMIC Technology, Inc.
Capacitance (f = 1MHz, Ta = Room Temperature, VCC = 5.0V ± 10%)
Symbol Signals Parameter Max. Unit Test Conditions
CIN1 A0 - A8 5 pF Vin = 0V
CIN2 RAS ,UCAS ,
LCAS ,WE ,
OE
Input Capacitance 7 pF Vin = 0V
CI/O I/O0 - I/O15 I/O Capacitance 7 pF Vin = Vout = 0V
Ordering Codes
Package
RAS
Access Time 25ns 35ns Self-Refresh
SOJ 40L (400mil) A428316S-25 A428316S-35 Yes
TSOP 40/44 L type II (400mil) A428316V-25 A428316V-35 Yes
TSOP 40/44 L type II (400mil) A428316V-25U A428316V-35U Yes
Note: -U is for industrial operating temperature range.
A428316 Series
PRELIMINARY (August, 2002, Version 0.3) 23 AMIC Technology, Inc.
Package Information
SOJ 40L (400mil) Outline Dimensions unit: inches/mm
Dimensions in inches Dimensions in mm
Symbol Min Nom Max Min Nom Max
A - - 0.144 - - 3.66
A1 0.025 - - 0.64 - -
A2 0.105 0.110 0.115 2.67 2.79 2.92
b1 0.026 0.028 0.032 0.66 0.71 0.81
b 0.016 0.018 0.022 0.41 0.46 0.56
C 0.008 0.010 0.014 0.20 0.25 0.36
D 1.020 1.025 1.030 25.91 26.04 26.16
E 0.395 0.400 0.405 10.03 10.16 10.29
e 0.044 0.050 0.056 1.12 1.27 1.42
e1 0.355 0.366 0.376 9.114 9.383 9.652
HE 0.430 0.440 0.450 10.92 11.18 11.43
L 0.081 0.093 0.105 2.083 2.39 2.70
S - - 0.050 - - 1.27
y - - 0.004 - - 0.10
θ 0° - 10° 0° - 10°
Notes:
1. The maximum value of dimension D includes end flash.
2. Dimension E does not include resin fins.
3. Dimension e1 is for PC Board surface mount pad pitch design
reference only.
4. Dimension S includes end flash.
1
E
HE
20
2140
A1A2
ee1
C
S
D
Seating Plane
D
y
L
1
A
b
b
θ
A428316 Series
PRELIMINARY (August, 2002, Version 0.3) 24 AMIC Technology, Inc.
Package Information
TSOP 40/44L (Type II) (400mil) Outline Dimensions unit: inches/mm
1
E
HE
L
1
L1
c
44
A1A2
A
S
D
y
e
D
B
L
L
θ
Dimensions in inches Dimensions in mm
Symbol Min Nom Max Min Nom Max
A - - 0.047 - - 1.20
A1 0.002 - 0.006 0.05 - 0.15
A2 0.037 0.039 0.041 0.95 1.00 1.05
B 0.013 0.015 0.017 0.32 0.37 0.42
c 0.003 0.005 0.009 0.08 0.13 0.23
D 0.720 0.725 0.730 18.28 18.41 18.54
E 0.395 0.400 0.405 10.03 10.16 10.29
e 0.031 BSC 0.80 BSC
HE 0.455 0.463 0.471 11.56 11.76 11.96
L 0.016 0.020 0.024 0.40 0.50 0.60
L1 - 0.031 - - 0.80 -
S - - 0.035 - - 0.90
y - - 0.004 - - 0.10
θ 1° 3° 5° 1° 3° 5°
Notes:
1. The maximum value of dimension D includes end flash.
2. Dimension E does not include resin fins.
3. Dimension S includes end flash.
