1CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 |Copyright Intersil Americas Inc. 1989, 2012. All Rights Reserved
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
Single 16/Differential 8-Channel CMOS Analog
Multiplexers with Active Overvoltage Protection
HI-546/883, HI-547/883
The HI-546/883 and HI-547/883 are analog multiplexers with
active overvoltage protection and guaranteed rON matching.
Analog input levels may greatly exceed either power supply
without damaging the device or disturbing the signal path of
other channels. Active protection circuitry assures that signal
fidelity is maintained even under fault conditions that would
destroy other multiplexers.
Analog inputs can withstand constant 70VP-P levels with ±15V
supplies. Digital inputs will also sustain continuous faults up to
4V greater than either supply. In addition, signal sources are
protected from short circuiting should multiplexer supply loss
occur. Each input presents 1kΩ of resistance under this
condition. These features make the HI-546/883 and
HI-547/883 ideal for use in systems where the analog inputs
originate from external equipment or separately powered
circuitry. Both devices are fabricated with 44V Dielectrically
Isolated CMOS technology. The HI-546/883 is a single
16-channel, and the HI-547/883 is an 8-channel differential
version. If input overvoltage protection is not needed, the
HI-506/883 and HI-507/883 multiplexers are recommended.
For further information see Application Note AN520.
Features
• This Circuit is Processed in Accordance to MIL-STD-883 and
is Fully Conformant Under the Provisions of Paragraph 1.2.1.
• No Channel Interaction During Overvoltage
•Guaranteed r
ON Matching
• 44V Maximum Power Supply
• Break-Before-Make Switching
• Analog Signal Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±15V
• Access Time (Max) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0µs
• Power Dissipation (Max) . . . . . . . . . . . . . . . . . . . . . . . . . 45mW
Applications
• Data Acquisition Systems
• Control Systems
• Telemetry
Ordering Information
PART #
PART
MARKING
TEMP. RANGE
(°C) PACKAGE
PKG.
DWG. #
HI1-0546/883 HI1-546/883 -55 to 125 28 Ld CerDIP F28.6
HI4-0546/883 HI4-0546 /883 -55 to 125 28 Ld CLCC J28.A
HI1-0547/883 HI4-0547 /883 -55 to 125 28 Ld CerDIP F28.6
HI4-0547/883 HI1-547/883 -55 to 125 28 Ld CLCC J28.A
April 9, 2012
FN7994.0
HI-546/883, HI-547/883
2FN7994.0
April 9, 2012
Pin Configurations
HI-546/883
(28 LD CERDIP)
TOP VIEW
HI-547/883
(28 LD CERDIP)
TOP VIEW
HI-546/883
(28 LD CLCC)
TOP VIEW
HI-547/883
(28 LD CLCC)
TOP VIEW
+VSUPPLY
NC
NC
IN 16
IN 15
IN 14
IN 13
IN 12
IN 11
IN 10
IN 9
GND
VREF
ADDRESS A3
OUT
IN 8
IN 7
IN 6
IN 5
IN 3
IN 1
ENABLE
ADDRESS A0
ADDRESS A1
ADDRESS A2
-VSUPPLY
IN 4
IN 2
28
27
26
25
24
23
22
21
20
19
18
17
16
15
1
2
3
4
5
6
7
8
9
10
11
12
13
14
+VSUPPLY
OUT B
NC
IN 8B
IN 7B
IN 6B
IN 5B
IN 4B
IN 3B
IN 2B
IN 1B
GND
VREF
NC
OUT A
IN 8A
IN 7A
IN 6A
IN 5A
IN 3A
IN 1A
ENABLE
ADDRESS A0
ADDRESS A1
ADDRESS A2
-VSUPPLY
IN 4A
IN 2A
28
27
26
25
24
23
22
21
20
19
18
17
16
15
1
2
3
4
5
6
7
8
9
10
11
12
13
14
IN 15
IN 14
IN 13
IN 12
IN 11
IN 10
IN 9
IN 16
NC
NC
+VSUPPLY
OUT
-VSUPPLY
IN 8
GND
VREF
A3
A2
A1
ENABLE
A0
IN 7
IN 6
IN 5
IN 4
IN 3
IN 2
IN 1
1234
5
6
7
8
9
10
11
12 13 14 15 16 17 18
19
20
21
22
23
24
25
262728
IN 7B
IN 6B
IN 5B
IN 4B
IN 3B
IN 2B
IN 1B
IN 8B
NC
OUT B
+VSUPPLY
OUT A
-VSUPPLY
IN 8A
GND
VREF
NC
A2
A1
ENABLE
A0
IN 7A
IN 6A
IN 5A
IN 4A
IN 3A
IN 2A
IN 1A
1234
5
6
7
8
9
10
11
12 13 14 15 16 17 18
19
20
21
22
23
24
25
262728
HI-546/883, HI-547/883
3FN7994.0
April 9, 2012
Functional Diagrams
HI-546/883
HI-547/883
DECODER/
DRIVER
† † † †
OUT
IN 1
IN 2
IN 16
† DIGITAL INPUT
VREF A0A1A2
†
EN
LEVEL
SHIFT
5V
REF
OVERVOLTAGE
CLAMP AND
SIGNAL
ISOLATION
PROTECTION
A3
1k
1k
1k
TRUTH TABLE HI-546/883
A3A2A1A0EN “ON” CHANNEL
XXXXL None
LLLLH 1
LLLHH 2
LLHLH 3
L LHHH 4
LHLLH 5
LHLHH 6
LHHLH 7
LHHHH 8
HLLLH 9
HLLHH 10
HLHLH 11
HLHHH 12
HHL LH 13
HHLHH 14
HHHLH 15
HHHHH 16
DECODER/
DRIVER
† † †
IN 1A
IN 8A
IN 8B
† DIGITAL INPUT
VREF A0A1A2
†
EN
LEVEL
SHIFT
5V
REF
OVERVOLTAGE
CLAMP AND
SIGNAL
ISOLATION
PROTECTION
1k
1k
1k
1k
OUT A
OUT B
IN 1B
TRUTH TABLE HI-547/883
A2A1A0EN “ON” CHANNEL PAIR
XXXL None
LLLH 1
LLHH 2
LHLH 3
LHHH 4
HLLH 5
HLHH 6
HHLH 7
HHHH 8
HI-546/883, HI-547/883
4FN7994.0
April 9, 2012
Absolute Maximum Ratings Thermal Information
Voltage Between Supply Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44V
+VSUPPLY to Ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22V
-VSUPPLY to Ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25V
Analog Input Voltage, +VS. . . . . . . . . . . . . . . . . . . . . . . . . . . +VSUPPLY +20V
Analog Input Voltage, -VS . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-VSUPPLY -20V
Digital Input Voltage, +VEN, +VA. . . . . . . . . . . . . . . . . . . . . . . +VSUPPLY +4V
Digital Input Voltage, -V
EN, -VA. . . . . . . . . . . . . . . . . . . . . . . . . -VSUPPLY +4V
or 20mA, whichever occurs first
Continuous Current, S or D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20mA
Peak Current, S or D (Pulsed at 1ms, 10% Duty Cycle Max). . . . . . . . 40mA
ESD Classification. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .≤2000V
Recommended Operating Conditions
Operating Temperature Range . . . . . . . . . . . . . . . . . . . . . .-55°C to +125°C
Operating Supply Voltage (±VSUPPLY) . . . . . . . . . . . . . . . . . . . . . . . . . . ±15V
Analog Input Voltage (VS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±VSUPPLY
Logic Low Level (VAL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0V to 0.8V
Logic High Level (VAH) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +4V to +VSUPPLY
Max RMS Current, S or D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8mA
Thermal Resistance θJA (°C/W) θJC (°C/W)
CerDIP Package . . . . . . . . . . . . . . . . . . . . . . 50 18
CLCC Package. . . . . . . . . . . . . . . . . . . . . . . . 81 20
Power Dissipation
CerDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.0W
CLCC Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.23W
Power Dissipation Derating Factor (Above +75°C)
CerDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20.0mW/°C
CLCC Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12.3mW/°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+175°C
Storage Temperature Range. . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Lead Temperature (Soldering 10s). . . . . . . . . . . . . . . . . . . . . . . . . . .+275°C
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
TABLE 1. D.C. ELECTRICAL PERFORMANCE SPECIFICATIONS
Device Tested at: +VSUPPLY = +15V, −VSUPPLY = −15V, VEN = 4.0V, VREF (Pin 13) = OPEN, unless otherwise specified.
D.C. PARAMETERS SYMBOL CONDITIONS
GROUP A
SUBGROUPS
TEMPERATURE
(°C) MIN MAX UNITS
Input Leakage Current IIH Measure inputs sequentially,
connect all unused inputs to GND
1, 2, 3 +25, +125, -55 -1.0 1.0 µA
IIL 1, 2, 3 +25, +125, -55 -1.0 1.0 µA
Source “OFF”
Leakage Current
+IS(OFF) VS = +10V, VD = -10V, VEN = 0.8V,
All unused inputs = -10V
1 +25 -10 10 nA
2, 3 +125, -55 -50 50 nA
-IS(OFF) VS = -10V, VD = +10V, VEN = 0.8V,
All unused inputs = +10V
1 +25 -10 10 nA
2, 3 +125, -55 -50 50 nA
Drain “OFF”
Leakage Current
+ID(OFF) VD = +10V, VEN = 0.8V,
All unused inputs = -10V
1 +25 -10 10 nA
HI-546/883 2, 3 +125, -55 -300 300 nA
HI-547/883 2, 3 +125, -55 -200 200 nA
-ID(OFF) VD = -10V, VEN = 0.8V,
All unused inputs = +10V
1 +25 -10 10 nA
HI-546/883 2, 3 +25 to +125 -300 300 nA
HI-547/883 2, 3 +125, -55 -200 200 nA
Channel “ON”
Leakage Current
+ID(ON) VIN (selected channels) = VD = +10V
VS = unused inputs = -10V
1 +25 -10 10 nA
HI-546/883 2, 3 +125, -55 -300 300 nA
HI-547/883 2, 3 +125, -55 -200 200 nA
-ID(ON) VIN (selected channels) = VD = -10V
VS = unused inputs = +10V
1 +25 -10 10 nA
HI-546/883 2, 3 +125, -55 -300 300 nA
HI-547/883 2, 3 +125, -55 -200 200 nA
HI-546/883, HI-547/883
5FN7994.0
April 9, 2012
Overvoltage Protected,
Leakage Current Into the
Drain Terminal of an “OFF”
Switch
ID(OFF)
Overvoltage
VS = 33V, VD = 0V, VEN = 0.8V
VS applied at ≤25% duty cycle
1, 2, 3 +25, +125, -55 -2.0 2.0 µA
VS = -33V, VD = 0V, VEN = 0.8V
VS applied at ≤25% duty cycle
1, 2, 3 +25, +125, -55 -2.0 2.0 µA
Positive Supply Current +I VA = 0V, VEN = 4.0V 1, 2, 3 +25, +125, -55 - 2.0 mA
Negative Supply Current -I VA = 0V, VEN = 4.0V 1, 2, 3 +25, +125, -55 -1.0 - mA
Standby Positive Supply
Current
+ISBY VA = 0V, VEN = 0V 1, 2, 3 +25, +125, -55 2.0 mA
Standby Negative Supply
Current
-ISBY VA = 0V, VEN = 0V 1, 2, 3 +25, +125, -55 --1.0 - mA
Switch “ON” Resistance +rDS1 VS = 10V, ID = 100µA 1 +25 - 1500 Ω
2, 3 +125, -55 - 1800 Ω
-rDS1 VS = -10V, ID = -100µA 1 +25 - 1500 Ω
2, 3 +125, -55 - 1800 Ω
Logic Level Voltage VAL1 Notes 1, 2 1, 2, 3 +25, +125, -55 - 0.8 V
VAH1 Notes 1, 2 1, 2, 3 +25, +125, -55 4.0 - V
VAL2 Note 3 1, 2, 3 +25, +125, -55 - 0.8 V
VAH2 Note 3 1, 2, 3 +25, +125, -55 6.0 - V
Difference in Switch “ON”
Resistance Between
Channels
+ΔrDS1 1 +25 - 7 %
-ΔrDS1 1 +25 - 7 %
TABLE 1. D.C. ELECTRICAL PERFORMANCE SPECIFICATIONS (Continued)
Device Tested at: +VSUPPLY = +15V, −VSUPPLY = −15V, VEN = 4.0V, VREF (Pin 13) = OPEN, unless otherwise specified.
D.C. PARAMETERS SYMBOL CONDITIONS
GROUP A
SUBGROUPS
TEMPERATURE
(°C) MIN MAX UNITS
+rDS1MAX()+rDS1MIN()100×–
+rDS1AVE
--------------------------------------------------------------------------------------------
-rDS1MAX()-rDS1MIN()100×–
-rDS1AVE
-----------------------------------------------------------------------------------------
TABLE 2. A.C. ELECTRICAL PERFORMANCE SPECIFICATIONS
Device Tested at: +VSUPPLY = +15V, −VSUPPLY = −15V, VEN = 4.0V, VREF (Pin 13) = OPEN, unless otherwise specified.
PARAMETERS SYMBOL CONDITIONS
GROUP A
SUBGROUPS
TEMPERATURE
(°C) MIN MAX UNITS
Break-Before-Make Time
Delay
tDRL = 1kΩ, CL = 12.5pF 9 +25 25 ns
Propagation Delay Times:
Address Inputs to I/O
Channel Times
tARL = 10MΩ, CL = 14pF 9 +25 500 ns
10, 11 +125, -55 1000 ns
Enable to I/O tON(EN) RL = 1kΩ, CL = 12.5pF 9 +25 500 ns
10, 11 +125, -55 1000 ns
tOFF(EN) RL = 1kΩ, CL = 12.5pF 9 +25 500 ns
10, 11 +125, -55 1000 ns
HI-546/883, HI-547/883
6FN7994.0
April 9, 2012
TABLE 3. ELECTRICAL PERFORMANCE SPECIFICATIONS
Device Tested at: +VSUPPLY = +15V, −VSUPPLY = −15V, VEN = 4.0V, VREF (Pin 13) = OPEN, unless otherwise specified.
PARAMETERS SYMBOL CONDITIONS NOTE
TEMPERATURE
(°C) MIN MAX UNITS
Capacitance Address Input CAV+ = V- = 0V, f = 1MHz 4 +25 12 pF
Capacitance Output Switch COS V+ = V- = 0V HI-546/883 4 +25 85 pF
f = 1MHz HI-547/883 4 +25 50 pF
Capacitance Input Switch CIS V+ = V- = 0V, f = 1MHz 4 +25 15 pF
Charge Transfer Error VCTE VS = GND, VGEN = 0V to 5V 4 +25 10 mV
Off Isolation VISO VEN = 0.8V, RL = 1kΩ, CL = 15pF,
VS=7V
RMS, f = 100kHz
4, 5 +25 -50 dB
NOTES:
1. Used for forcing conditions for all DC Tests, unless otherwise specified.
2. To drive from DTL/TTL circuits, 1kΩ pull-up resistors to +5.0V supply are recommended.
3. VREF = +10V.
4. The parameters listed in this table are controlled via design or process parameters and are not directly tested. These parameters are characterized
upon initial design release and upon design changes which would affect these characteristics.
5. Worst case isolation occurs on channel 8B due to proximity of the output pins.
TABLE 4. ELECTRICAL TEST REQUIREMENTS
MIL-STD-883 TEST REQUIREMENTS SUBGROUPS (See Tables 1, 2, 3)
Interim Electrical Parameters (Pre Burn-in) 1
Final Electrical Test Parameters 1 (Note 6), 2, 3, 9, 10, 11
Group A Test Requirements 1, 2, 3, 9, 10, 11
Groups C & D Endpoints 1
NOTE:
6. PDA applies to Subgroup 1 only. No other subgroups are included in PDA.
HI-546/883, HI-547/883
7FN7994.0
April 9, 2012
Test Circuits
INPUT LEAKAGE CURRENT ID(OFF) IS(OFF)
ID(ON) ID(OFF) OVERVOLTAGE RDS
SUPPLY CURRENTS CHARGE TRANSFER ERROR OFF CHANNEL ISOLATION
HI-546/883, HI-547/883
8FN7994.0
April 9, 2012
Switching Waveforms
BREAK-BEFORE-MAKE DELAY (tOPEN) BREAK-BEFORE-MAKE DELAY (tOPEN)
ACCESS TIME vs LOGIC LEVEL (HIGH) ACCESS TIME
ENABLE DELAY
tON(EN), tOFF(EN)
ENABLE DELAY
tON(EN), tOFF(EN)
*SIMILAR CONNECTION FOR HI-547/883
*SIMILAR CONNECTION FOR HI-547/883
*SIMILAR CONNECTION FOR HI-547/883
HI-546/883, HI-547/883
9FN7994.0
April 9, 2012
Burn-In Circuits
HI-546/883, HI-547/883 CERDIP
NOTES:
R1, R2 = 10kΩ ± 5% 1/2W or 1/4W (per socket)
C1, C2 = 0.01µF (per socket) or 0.1µF (per row)
D1, D2 = 1N4002 (or equivalent) (per board)
HI-546/883, HI-547/883 CLCC
NOTES:
R1, R2 = 10kΩ ± 5% 1/2W or 1/4W (per socket)
C1, C2 = 0.01µF (per socket) or 0.1µF (per row)
D1, D2 = 1N4002 (or equivalent) (per board)
HI-546/883, HI-547/883
10 FN7994.0
April 9, 2012
Schematic Diagrams
ADDRESS INPUT BUFFER AND LEVEL SHIFTER
LEVEL SHIFTER
P
N
P
N
N
P
N
P
VREF
ADD
IN
N
P
N
P P
N
P
NN
P
N
P
LEVEL
SHIFTED
ADDRESS
TO
TTL REFERENCE
CIRCUIT
V+
R10
R9
Q1
Q4
D3
GND
OVERVOLTAGE
PROTECTION
D2
R1
200Ω
V-
D1
V+
R2
R3
GND
V+
V-
DECODE
R4
R5 R7
R8
R6
HI-546/883, HI-547/883
11 FN7994.0
April 9, 2012
ADDRESS DECODER
MULTIPLEX SWITCH
Schematic Diagrams (Continued)
P
N
A0 OR A0
TO N-CHANNEL
DEVICE OF
THE SWITCH
A1 OR A1
A2 OR A2
A3 OR A3
ENABLE
PP PP P P
V+
V-
N
N
N
N
NN
TO P-CHANNEL
DEVICE OF
THE SWITCH
DELETE A3 OR A3 INPUT FOR HI-547/883
IN
FROM
DECODE
R11
1k
V+
P
D6 D7
Q6
FROM
DECODE
OVERVOLTAGE PROTECTION
V-
Q5
D4 D5
N
N
N
P
OUT
HI-546/883, HI-547/883
12 FN7994.0
April 9, 2012
Die Characteristics
DIE DIMENSIONS:
83.9 mils x 159 mils x 19 mils
METALLIZATION:
Type: Al
Thickness: 16kÅ ±2kÅ
GLASSIVATION:
Type: Nitride
Thickness: 7kÅ ± 0.7kÅ
WORST CASE CURRENT DENSITY:
1.4 x 105 A/cm2
TRANSISTOR COUNT:
485
PROCESS:
CMOS-DI
Metallization Mask Layouts
HI-546/883 HI-547/883
IN 9
IN 10
IN 11
IN 12
IN 13
IN 14
IN 15
IN 16
V- (27) +V (1) NC (2)
IN 1
IN 2
IN 3
IN 4
IN 5
IN 6
IN 7
IN 8
EN A0A1A2VREF GND
(18) (17) (16) (15) (13) (12)
(19)
(20)
(21)
(22)
(23)
(24)
(25)
(26) (4)
(5)
(6)
(7)
(8)
(9)
(10)
(11)
OUT (28)
A3
(14)
IN 1B
IN 2B
IN 3B
IN 4B
IN 5B
IN 6B
IN 7B
IN 8B
V- (27) +V (1) OUT B(2)
IN 1A
IN 2A
IN 3A
IN 4A
IN 5A
IN 6A
IN 7A
IN 8A
EN A0A1A2NC VREF GND
(18) (17) (16) (15) (14) (13) (12)
(19)
(20)
(21)
(22)
(23)
(24)
(25)
(26) (4)
(5)
(6)
(7)
(8)
(9)
(10)
(11)
OUT A (28)
HI-546/883, HI-547/883
13
Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems as noted
in the quality certifications found at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time
without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be
accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third
parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN7994.0
April 9, 2012
For additional products, see www.intersil.com/product_tree
Ceramic Dual-In-Line Frit Seal Packages (CERDIP)
NOTES:
1. Index area: A notch or a pin one identification mark shall be locat-
ed adjacent to pin one and shall be located within the shaded
area shown. The manufacturer’s identification shall not be used
as a pin one identification mark.
2. The maximum limits of lead dimensions b and c or M shall be
measured at the centroid of the finished lead surfaces, when
solder dip or tin plate lead finish is applied.
3. Dimensions b1 and c1 apply to lead base metal only. Dimension
M applies to lead plating and finish thickness.
4. Corner leads (1, N, N/2, and N/2+1) may be configured with a
partial lead paddle. For this configuration dimension b3 replaces
dimension b2.
5. This dimension allows for off-center lid, meniscus, and glass
overrun.
6. Dimension Q shall be measured from the seating plane to the
base plane.
7. Measure dimension S1 at all four corners.
8. N is the maximum number of terminal positions.
9. Dimensioning and tolerancing per ANSI Y14.5M - 1982.
10. Controlling dimension: INCH.
bbb C A - B
S
c
Q
L
A
SEATING
BASE
D
PLANE
PLANE
-D-
-A-
-C-
-B-
α
D
E
S1
b2
b
A
e
M
c1
b1
(c)
(b)
SECTION A-A
BASE
LEAD FINISH
METAL
eA/2
A
M
SS
ccc C A - B
MD
SSaaa CA - B
MD
SS
eA
F28.6 MIL-STD-1835 GDIP1-T28 (D-10, CONFIGURATION A)
28 LEAD CERAMIC DUAL-IN-LINE FRIT SEAL PACKAGE
SYMBOL
INCHES MILLIMETERS
NOTESMIN MAX MIN MAX
A - 0.232 - 5.92 -
b 0.014 0.026 0.36 0.66 2
b1 0.014 0.023 0.36 0.58 3
b2 0.045 0.065 1.14 1.65 -
b3 0.023 0.045 0.58 1.14 4
c 0.008 0.018 0.20 0.46 2
c1 0.008 0.015 0.20 0.38 3
D - 1.490 - 37.85 5
E 0.500 0.610 12.70 15.49 5
e 0.100 BSC 2.54 BSC -
eA 0.600 BSC 15.24 BSC -
eA/2 0.300 BSC 7.62 BSC -
L 0.125 0.200 3.18 5.08 -
Q 0.015 0.060 0.38 1.52 6
S1 0.005 - 0.13 - 7
α90o105o90o105o-
aaa - 0.015 - 0.38 -
bbb - 0.030 - 0.76 -
ccc - 0.010 - 0.25 -
M - 0.0015 - 0.038 2, 3
N28 288
Rev. 0 4/94
HI-546/883, HI-547/883
14 FN7994.0
April 9, 2012
Ceramic Leadless Chip Carrier Packages (CLCC)
D
j x 45o
D3
B
h x 45o
AA1
E
LL3
e
B3
L1
D2
D1
e1
E2
E1
L2
PLANE 2
PLANE 1
E3
B2
0.010 E HS S
0.010 E F
SS
-E-
0.007 E FM S HS
B1
-H-
-F-
J28.A MIL-STD-1835 CQCC1-N28 (C-4)
28 PAD CERAMIC LEADLESS CHIP CARRIER PACKAGE
SYMBOL
INCHES MILLIMETERS
NOTESMIN MAX MIN MAX
A 0.060 0.100 1.52 2.54 6, 7
A1 0.050 0.088 1.27 2.23 -
B-----
B1 0.022 0.028 0.56 0.71 2 , 4
B2 0.072 REF 1.83 REF -
B3 0.006 0.022 0.15 0.56 -
D 0.442 0.460 11.23 11.68 -
D1 0.300 BSC 7.62 BSC -
D2 0.150 BSC 3.81 BSC -
D3 - 0.460 - 11.68 2
E 0.442 0.460 11.23 11.68 -
E1 0.300 BSC 7.62 BSC -
E2 0.150 BSC 3.81 BSC -
E3 - 0.460 - 11.68 2
e 0.050 BSC 1.27 BSC -
e1 0.015 - 0.38 - 2
h 0.040 REF 1.02 REF 5
j 0.020 REF 0.51 REF 5
L 0.045 0.055 1.14 1.40 -
L1 0.045 0.055 1.14 1.40 -
L2 0.075 0.095 1.90 2.41 -
L3 0.003 0.015 0.08 0.038 -
ND 7 7 3
NE 7 7 3
N28 283
Rev. 0 5/18/94
NOTES:
1. Metallized castellations shall be connected to plane 1 terminals
and extend toward plane 2 across at least two layers of ceramic
or completely across all of the ceramic layers to make electrical
connection with the optional plane 2 terminals.
2. Unless otherwise specified, a minimum clearance of 0.015 inch
(0.38mm) shall be maintained between all metallized features
(e.g., lid, castellations, terminals, thermal pads, etc.)
3. Symbol “N” is the maximum number of terminals. Symbols “ND”
and “NE” are the number of terminals along the sides of length
“D” and “E”, respectively.
4. The required plane 1 terminals and optional plane 2 terminals (if
used) shall be electrically connected.
5. The corner shape (square, notch, radius, etc.) may vary at the
manufacturer’s option, from that shown on the drawing.
6. Chip carriers shall be constructed of a minimum of two ceramic
layers.
7. Dimension “A” controls the overall package thickness. The maxi-
mum “A” dimension is p ackage height before being solder dipped.
8. Dimensioning and tolerancing per ANSI Y14.5M-1982.
9. Controlling dimension: INCH.
