ispLSI
® 1024
In-System Programmable High Density PLD
1
1024_06
Features
• HIGH-DENSITY PROGRAMMABLE LOGIC
— High-Speed Global Interconnect
— 4000 PLD Gates
— 48 I/O Pins, Six Dedicated Inputs
— 144 Registers
— Wide Input Gating for Fast Counters, State
Machines, Address Decoders, etc.
— Small Logic Block Size for Fast Random Logic
— Security Cell Prevents Unauthorized Copying
• HIGH PERFORMANCE E2CMOS® TECHNOLOGY
— fmax = 90 MHz Maximum Operating Frequency
— fmax = 60 MHz for Industrial and Military/883 Devices
— tpd = 12 ns Propagation Delay
— TTL Compatible Inputs and Outputs
— Electrically Erasable and Reprogrammable
— Non-Volatile E2CMOS Technology
— 100% Tested
• IN-SYSTEM PROGRAMMABLE
— In-System Programmable™ (ISP™) 5-Volt Only
— Increased Manufacturing Yields, Reduced Time-to-
Market, and Improved Product Quality
— Reprogram Soldered Devices for Faster Debugging
• COMBINES EASE OF USE AND THE FAST SYSTEM
SPEED OF PLDs WITH THE DENSITY AND FLEX-
IBILITY OF FIELD PROGRAMMABLE GATE ARRAYS
— Complete Programmable Device Can Combine Glue
Logic and Structured Designs
— Four Dedicated Clock Input Pins
— Synchronous and Asynchronous Clocks
— Flexible Pin Placement
— Optimized Global Routing Pool Provides Global
Interconnectivity
• ispDesignEXPERT™ – LOGIC COMPILER AND COM-
PLETE ISP DEVICE DESIGN SYSTEMS FROM HDL
SYNTHESIS THROUGH IN-SYSTEM PROGRAMMING
— Superior Quality of Results
— Tightly Integrated with Leading CAE Vendor Tools
— Productivity Enhancing Timing Analyzer, Explore
Tools, Timing Simulator and ispANALYZER™
— PC and UNIX Platforms
unctional Block Diagram
Output Routing Pool
CLK
B0 B1 B2 B3 B4 B5 B6 B7
A0
A1
A2
A3
A4
A5
A6
A7
C7
C6
C5
C4
C3
C2
C1
C0
Output Routing Pool
Output Routing Pool
Global Routing Pool (GRP)
Logic
Array
DQ
DQ
DQ
DQ
GLB
0139-A-isp
Description
The ispLSI 1024 is a High-Density Programmable Logic
Device containing 144 Registers, 48 Universal I/O pins,
six Dedicated Input pins, four Dedicated Clock Input pins
and a Global Routing Pool (GRP). The GRP provides
complete interconnectivity between all of these elements.
The ispLSI 1024 features 5-Volt in-system programma-
bility and in-system diagnostic capabilities. It is the first
device which offers non-volatile reprogrammability of the
logic, as well as the interconnect to provide truly
reconfigurable systems.
The basic unit of logic on the ispLSI 1024 device is the
Generic Logic Block (GLB). The GLBs are labeled A0, A1
.. C7 (see figure 1). There are a total of 24 GLBs in the
ispLSI 1024 device. Each GLB has 18 inputs, a program-
mable AND/OR/XOR array, and four outputs which can
be configured to be either combinatorial or registered.
Inputs to the GLB come from the GRP and dedicated
inputs. All of the GLB outputs are brought back into the
GRP so that they can be connected to the inputs of any
other GLB on the device.
Copyright © 1999 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject
to change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A. February 1999
Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com
Functional Block Diagram
Specifications ispLSI 1024
2
The device also has 48 I/O cells, each of which is directly
connected to an I/O pin. Each I/O cell can be individually
programmed to be a combinatorial input, registered in-
put, latched input, output or bi-directional
I/O pin with 3-state control. Additionally, all outputs are
polarity selectable, active high or active low. The signal
levels are TTL compatible voltages and the output drivers
can source 4 mA or sink 8 mA.
Eight GLBs, 16 I/O cells, two dedicated inputs and one
ORP are connected together to make a Megablock (see
figure 1). The outputs of the eight GLBs are connected
to a set of 16 universal I/O cells by the ORP. The I/O cells
within the Megablock also share a common Output
Enable (OE) signal. The ispLSI 1024 device contains
three of these Megablocks.
Functional Block Diagram
Figure 1.ispLSI 1024 Functional Block Diagram
Y
0Y
1Y
2Y
3
I/O 0
I/O 1
I/O 2
I/O 3
IN 5
IN 4
I/O 6
I/O 7
I/O 8
I/O 9
I/O 10
I/O 11
I/O 12
I/O 13
I/O 14
I/O 15
I/O 47
I/O 46
I/O 45
I/O 44
I/O 43
I/O 42
I/O 41
I/O 40
I/O 39
I/O 38
I/O 37
I/O 36
I/O 35
I/O 34
I/O 33
I/O 32
I/O
17
I/O
16 I/O
18 I/O
19 I/O
20 I/O
21 I/O
22 I/O
23 I/O
24 I/O
25 I/O
26 I/O
27 I/O
28 I/O
29 I/O
30 I/O
31
I/O 4
I/O 5
RESET
Global
Routing
Pool
(GRP)
Output Routing Pool (ORP)
CLK 0
CLK 1
CLK 2
IOCLK 0
IOCLK 1
Clock
Distribution
Network
B0 B1 B2 B3 B4 B5 B6 B7
A0
A1
A2
A3
A4
A5
A6
A7
C7
C6
C5
C4
C3
C2
C1
C0
Output Routing Pool (ORP)
Generic
Logic Blocks
(GLBs)
Megablock
Output Routing Pool (ORP)
lnput Bus
Input Bus
ispEN
Input Bus
0139D_1024.eps
SDI/IN 0
SDO/IN 1
SCLK/IN 2
MODE/IN 3
The GRP has as its inputs the outputs from all of the GLBs
and all of the inputs from the bi-directional I/O cells. All of
these signals are made available to the inputs of the
GLBs. Delays through the GRP have been equalized to
minimize timing skew.
Clocks in the ispLSI 1024 device are selected using the
Clock Distribution Network. Four dedicated clock pins
(Y0, Y1, Y2 and Y3) are brought into the distribution
network, and five clock outputs (CLK 0, CLK 1, CLK 2,
IOCLK 0 and IOCLK 1) are provided to route clocks to the
GLBs and I/O cells. The Clock Distribution Network can
also be driven from a special clock GLB (B4 on the ispLSI
1024 device). The logic of this GLB allows the user to
create an internal clock from a combination of internal
signals within the device.
Specifications ispLSI 1024
3
Absolute Maximum Ratings 1
Supply Voltage Vcc .................................. -0.5 to +7.0V
Input Voltage Applied........................-2.5 to VCC +1.0V
Off-State Output Voltage Applied .....-2.5 to VCC +1.0V
Storage Temperature................................ -65 to 150°C
Case Temp. with Power Applied ..............-55 to 125°C
Max. Junction Temp. (TJ) with Power Applied ... 150°C
1. Stresses above those listed under the “Absolute Maximum Ratings” may cause permanent damage to the device. Functional
operation of the device at these or at any other conditions above those indicated in the operational sections of this specification
is not implied (while programming, follow the programming specifications).
DC Recommended Operating Conditions
V
V
PARAMETERSYMBOL MIN. MAX. UNITS
5.25
5.5
5.5
0.8
Vcc + 1
Supply Voltage
V
CC
V
IL
V
IH
Table 2- 0005Aisp w/mil.eps
4.75
4.5
4.5
0
2.0
Commercial T
A
=
0°C to +70°C
Industrial T
A
= -40°C to +85°C
Military/883 T
C
= -55°C to +125°C
Input Low Voltage
Input High Voltage
V
Capacitance (TA=25oC, f=1.0 MHz)
SYMBOL PARAMETER MAXIMUM1UNITS TEST CONDITIONS
C
1
Commercial/Industrial 8 pf VCC=5.0V, VIN=2.0V
Military 10 pf VCC=5.0V, VIN=2.0V
C
2
I/O and Clock Capacitance 10 pf VCC=5.0V, VI/O, VY=2.0V
1. Guaranteed but not 100% tested. Table 2- 0006
Dedicated Input Capacitance
Data Retention Specifications
Table 2- 0008B
PARAMETER
Data Retention MINIMUM MAXIMUM UNITS
Erase/Reprogram Cycles 20
10000 —
—Years
Cycles
Specifications ispLSI 1024
4
Switching Test Conditions
Input Pulse Levels GND to 3.0V
Input Rise and Fall Time ≤ 3ns 10% to 90%
Input Timing Reference Levels 1.5V
Output Timing Reference Levels 1.5V
Output Load See figure 2
3-state levels are measured 0.5V from steady-state
active level. Table 2- 0003
DC Electrical Characteristics
Over Recommended Operating Conditions
V
OL
V
OH
I
IL
I
IH
I
IL-isp
I
IL-PU
I
OS
1
I
CC
2,4
1. One output at a time for a maximum duration of one second. V
out
= 0.5V was selected to avoid test problems by tester ground
degradation. Characterized but not 100% tested.
2. Measured using six 16-bit counters.
3. T ypical values are at V
CC
= 5V and T
A
= 25
o
C.
4. Maximum I
CC
varies widely with specific device configuration and operating frequency. Refer to the Power Consumption sec-
tion of this datasheet and Thermal Management section of the Lattice Semiconductor Data Book and CD-ROM to estimate maximum
I
CC
.
I
OL
=8 mA
I
OH
=-4 mA
0V ≤ V
IN
≤ V
IL
(MAX.)
3.5V ≤ V
IN
≤ V
CC
0V ≤ V
IN
≤ V
IL
(MAX.)
0V ≤ V
IN
≤ V
IL
V
CC
= 5V, V
OUT
= 0.5V
V
IL
= 0.5V, V
IH
= 3.0V Commercial
f
TOGGLE
= 1 MHz Industrial/Military
0.4
–
-10
10
-150
-150
-200
190
215
V
V
µA
µA
µA
µA
mA
mA
mA
SYMBOL
Output Low Voltage
Output High Voltage
Input or I/O Low Leakage Current
Input or I/O High Leakage Current
isp Input Low Leakage Current
I/O Active Pull-Up Current
Output Short Circuit Current
Operating Power Supply Current
CONDITION MIN. UNITS
MAX.
TYP.
3
–
–
–
–
–
–
–
130
135
–
2.4
–
–
–
–
–
–
–
PARAMETER
Table 2-0007A-24 w/mil
Figure 2. Test Load
+ 5V
R1
R2CL*
Device
Output Test
Point
*CL includes Test Fixture and Probe Capacitance.
Output Load Conditions (see figure 2)
T est Condition R1 R2 CL
A 470Ω390Ω35pF
B Active High 390Ω35pF
Active Low 470Ω390Ω35pF
Active High to Z 390Ω5pF
Cat V
OH
- 0.5V
Active Low to Z 470Ω390Ω5pF
at V
OL
+ 0.5V
∞
∞
Table 2- 0004A
Specifications ispLSI 1024
5
External Timing Parameters
Over Recommended Operating Conditions
MIN. MAX.
Data Propagation Delay, 4PT bypass, ORP bypass
Data Propagation Delay, Worst Case Path
Clock Frequency with Internal Feedback
3
Clock Frequency with External Feedback
Clock Frequency, Max Toggle
4
GLB Reg. Setup Time before Clock, 4PT bypass
GLB Reg. Clock to Output Delay, ORP bypass
GLB Reg.
Hold Time after Clock, 4 PT bypass
GLB Reg. Setup Time before Clock
GLB Reg. Clock to Output Delay
GLB Reg. Hold Time after Clock
Ext. Reset Pin to Output Delay
Ext. Reset Pulse Duration
Input to Output Enable
Input to Output Disable
Ext. Sync. Clock Pulse Duration, High
Ext. Sync. Clock Pulse Duration, Low
I/O Reg. Setup Time before Ext. Sync. Clock (Y2, Y3)
I/O Reg. Hold Time after Ext. Sync. Clock (Y2, Y3)
ns
ns
MHz
MHz
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
pd1
t
pd2
f
max (Int.)
f
max (Ext.)
f
max (Tog.)
t
su1
t
co1
t
h1
t
su2
t
co2
t
h2
t
r1
t
rw1
t
en
t
dis
t
wh
t
wl
t
su5
t
h5
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
A
A
A
–
–
–
A
–
–
–
–
A
–
B
C
–
–
–
–
DESCRIPTION
1
PARAMETER #
2
UNITS
TEST
5
COND.
1
tsu2 + tco1
( )
MIN. MAX.
–
–
80
50
100
7
–
0
10
–
0
–
10
–
–
5
5
2
6.5
15
20
–
–
–
–
10
–
–
12
–
17
–
18
18
–
–
–
–
–
–
60
38
83
9
–
0
13
–
0
–
13
–
–
6
6
2.5
8.5
20
25
–
–
–
–
13
–
–
16
–
22.5
–
24
24
–
–
–
–
-80 -60
MIN. MAX.
–
–
90.9
58.8
125
6
–
0
9
–
0
–
10
–
–
4
4
2
6.5
12
17
–
–
–
–
8
–
–
10
–
15
–
15
15
–
–
–
–
-90
Table 2-0030-24/90,80,60C
1. Unless noted otherwise, all parameters use a GRP load of 4 GLBs, 20 PTXOR path, ORP and Y0 clock.
2. Refer to Timing Model in this data sheet for further details.
3. Standard 16-Bit loadable counter using GRP feedback.
4. fmax (Toggle) may be less than 1/(twh + twl). This is to allow for a clock duty cycle of other than 50%.
5. Reference Switching Test Conditions Section.
Specifications ispLSI 1024
6
Internal Timing Parameters1
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
–
–
7.3
1.3
–
–
–
–
–
–
–
–
–
–
–
–
–
–
1.3
6.0
–
–
–
–
4.6
–
–
2.7
4.0
–
–
4.0
3.3
5.3
2.0
2.7
4.0
5.0
6.0
8.3
8.6
9.3
10.6
12.7
1.3
–
–
2.7
3.3
13.3
12.0
9.9
3.3
0.7
MIN. MAX.
DESCRIPTIONPARAMETER UNITS
-60
Inputs
tiobp
tiolat
tiosu
tioh
tioco
tior
tdin
GRP
tgrp1
tgrp4
tgrp8
tgrp12
tgrp16
tgrp24
GLB
t4ptbp
t1ptxor
t20ptxor
txoradj
tgbp
tgsu
tgh
tgco
tgr
tptre
tptoe
tptck
ORP
torp
torpbp
#
2
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
I/O Register Bypass
I/O Latch Delay
I/O Register Setup Time before Clock
I/O Register Hold Time after Clock
I/O Register Clock to Out Delay
I/O Register Reset to Out Delay
Dedicated Input Delay
GRP Delay, 1 GLB Load
GRP Delay, 4 GLB Loads
GRP Delay, 8 GLB Loads
GRP Delay, 12 GLB Loads
GRP Delay, 16 GLB Loads
GRP Delay, 24 GLB Loads
4 Product Term Bypass Path Delay
1 Product Term/XOR Path Delay
20 Product Term/XOR Path Delay
XOR Adjacent Path Delay
3
GLB Register Bypass Delay
GLB Register Setup Time before Clock
GLB Register Hold Time after Clock
GLB Register Clock to Output Delay
GLB Register Reset to Output Delay
GLB Product Term Reset to Register Delay
GLB Product Term Output Enable to I/O Cell Delay
GLB Product Term Clock Delay
ORP Delay
ORP Bypass Delay
–
–
5.5
1.0
–
–
–
–
–
–
–
–
–
–
–
–
–
–
1.0
4.5
–
–
–
–
3.5
–
–
2.0
3.0
–
–
3.0
2.5
4.0
1.5
2.0
3.0
3.8
4.5
6.3
6.5
7.0
8.0
9.5
1.0
–
–
2.0
2.5
10.0
9.0
7.5
2.5
0.5
MIN. MAX.
-80
–
–
4.8
2.1
–
–
–
–
–
–
–
–
–
–
–
–
–
–
1.2
3.6
–
–
–
–
2.8
–
–
1.6
2.4
–
–
2.4
2.8
3.2
1.2
1.6
2.4
3.0
3.6
5.0
5.2
5.7
7.0
8.2
0.8
–
–
1.6
2.0
8.0
7.8
6.0
2.4
0.4
MIN. MAX.
-90
1. Internal Timing Parameters are not tested and are for reference only.
2. Refer to Timing Model in this data sheet for further details.
3. The XOR Adjacent path can only be used by Hard Macros.
Specifications ispLSI 1024
7
Internal Timing Parameters1
ns
ns
ns
ns
ns
ns
ns
ns
ns
–
–
–
6.0
4.6
1.3
4.6
1.3
–
4.0
6.7
6.7
6.0
7.3
6.6
7.3
6.6
12.0
Outputs
tob
toen
todis
Clocks
tgy0
tgy1/2
tgcp
tioy2/3
tiocp
Global Reset
tgr
47
48
49
50
51
52
53
54
55
Output Buffer Delay
I/O Cell OE to Output Enabled
I/O Cell OE to Output Disabled
Clock Delay, Y0 to Global GLB Clock Line (Ref. clock)
Clock Delay, Y1 or Y2 to Global GLB Clock Line
Clock Delay, Clock GLB to Global GLB Clock Line
Clock Delay, Y2 or Y3 to I/O Cell Global Clock Line
Clock Delay, Clock GLB to I/O Cell Global Clock Line
Global Reset to GLB and I/O Registers
MIN. MAX.
DESCRIPTIONPARAMETER UNITS
-60
#2
–
–
–
4.5
3.5
1.0
3.5
1.0
–
3.0
5.0
5.0
4.5
5.5
5.0
5.5
5.0
9.0
MIN. MAX.
-80
1. Internal Timing Parameters are not tested and are for reference only.
2. Refer to Timing Model in this data sheet for further details.
–
–
–
3.6
2.8
0.8
2.8
0.8
–
2.4
4.0
4.0
3.6
4.4
4.0
4.4
4.0
8.2
MIN. MAX.
-90
Specifications ispLSI 1024
8
ispLSI Timing Model
GLB Reg
Delay
I/O Pin
(Output)
ORP
Delay
Feedback
4 PT Bypass
20 PT
XOR Delays
Control
PTs
GRP
Loading
Delay
Input
Register
Clock
Distribution
I/O Pin
(Input)
Y0
Y1,2,3
DQ
GRP 4 GLB Reg Bypass ORP Bypass
DQ
RST
RE
OE
CK
I/O Reg Bypass
I/O CellORPGLBGRPI/O Cell
#21 - 25 #27, 29,
30, 31, 32
#28 #33
#34, 35, 36
#51, 52,
53, 54 #42, 43,
44
#50
#45
#46
Reset
Ded. In #26
#20
RST
#55
#55
#37
#38, 39,
40, 41
#48, 49
#47
Derivations of
t
su,
t
h and
t
co from the Product Term Clock
1
tsu = Logic + Reg su - Clock (min)
= (tiobp + tgrp4 + t20ptxor) + (tgsu) - ( tiobp + tgrp4 + tptck(min))
= (#20 + #28 + #35) + (#38) - (#20 + #28 + #44)
5.5 ns = (2.0 + 2.0 + 8.0) + (1.0) - (2.0 + 2.0 + 3.5)
th = Clock (max) + Reg h - Logic
= (tiobp + tgrp4 + tptck(max)) + (tgh) - (tiobp + tgrp4 + t20ptxor)
= (#20 + #28 + #44) + (#39) - (#20 + #28 + #35)
4.0 ns = (2.0 + 2.0 + 7.5) + (4.5) - (2.0 + 2.0 + 8.0)
tco = Clock (max) + Reg co + Output
= (tiobp + tgrp4 + tptck(max)) + (tgco) + (torp + tob)
= (#20 + #28 + #44 ) + (#40) + (#45 + #47)
19.0 ns = (2.0+ 2.0 +7.5) + (2.0) + (2.5 + 3.0)
Derivations of tsu, th and tco from the Clock GLB
1
tsu = Logic + Reg su - Clock (min)
= (tiobp + tgrp4 + t20ptxor) + (tgsu) - (tgy0(min) + tgco + tgcp(min))
= (#20 + #28 + #35) + (#38) - (#50 + #40 + #52)
5.5 ns = (2.0 + 2.0 + 8.0) + (1.0) - (4.5 + 2.0 + 1.0)
th = Clock (max) + Reg h - Logic
= (tgy0(max) + tgco + tgcp(max)) + (tgh) - (tiobp + tgrp4 + t20ptxor)
= (#50 + #40 + #52) + (#39) - (#20 + #28 + #35)
4.0 ns = (4.5 + 2.0 + 5.0) + (4.5) - (2.0 + 2.0 + 8.0)
tco = Clock (max) + Reg co + Output
= (tgy0(max) + tgco + tgcp(max)) + (tgco) + (torp + tob)
= (#50 + #40 + #52 ) + (#40) + (#45 + #47)
19.0 ns = (4.5 + 2.0 + 5.0) + (2.0) + (2.5 + 3.0)
1. Calculations are based upon timing specifications for the ispLSI 1024-80.
Specifications ispLSI 1024
9
Maximum GRP Delay vs GLB Loads
ispLSI 1024-60
ispLSI 1024-80
ispLSI 1024-90
1
2
3
4 8 12 16
GLB Loads
GRP Delay (ns)
4
5
6
0
0126A-80-24-isp.eps
Power Consumption
Figure 3. Typical Device Power Consumption vs fmax
ICC can be estimated for the ispLSI 1024 using the following equation:
ICC = 42 + (# of PTs * 0.45) + (# of nets * Max. freq * 0.008) where:
# of PTs = Number of Product Terms used in design
# of nets = Number of Signals used in device
Max. freq = Highest Clock Frequency to the device
The ICC estimate is based on typical conditions (VCC = 5.0V, room temperature) and an assumption of 2 GLB loads on
average exists. These values are for estimates only. Since the value of ICC is sensitive to operating conditions and the
program in the device, the actual ICC should be verified.
50
100
150
0 10203040506070
fmax (MHz)
ICC (mA)
80
200
Notes: Configuration of Six 16-bit Counters
Typical Current at 5V, 25˚C
ispLSI 1024
0127A-24-80-isp
Power consumption in the ispLSI 1024 device depends
on two primary factors: the speed at which the device is
operating, and the number of Product Terms used. Fig-
ure 3 shows the relationship between power and operat-
ing speed.
Specifications ispLSI 1024
10
Dedicated Clock input. This clock input is brought into the clock
distribution network, and can optionally be routed to any GLB on the
device.
Dedicated Clock input. This clock input is connected to one of the clock
inputs of all of the GLBs on the device.
Input/Output Pins - These are the general purpose I/O pins used by the
logic array.
NAME
Table 2 - 0002C-24
PLCC and JLCC
PIN NUMBERS DESCRIPTION
22,
26,
30,
37,
41,
45,
56,
60,
64,
3,
7,
11,
23,
27,
31,
38,
42,
46,
57,
61,
65,
4,
8,
12,
24,
28,
32,
39,
43,
47,
58,
62,
66,
5,
9,
13,
I/O 0 - I/O 3
I/O 4 - I/O 7
I/O 8 - I/O 11
I/O 12 - I/O 15
I/O 16 - I/O 19
I/O 20 - I/O 23
I/O 24 - I/O 27
I/O 28 - I/O 31
I/O 32 - I/O 35
I/O 36 - I/O 39
I/O 40 - I/O 43
I/O 44 - I/O 47
25,
29,
33,
40,
44,
48,
59,
63,
67,
6,
10,
14
54Y1
16Y0
55MODE/IN 31Input - This pin performs two functions. When ispEN is logic low, it
functions as pin to control the operation of the isp state machine. It is a
dedicated input pin when ispEN is logic high.
Ground (GND)
GND
V
VCC
CC
IN 4 - IN 5 2, 15 Input - These pins are dedicated input pins to the device.
Input - Dedicated in-system programming enable input pin. This pin is
brought low to enable the programming mode. The MODE, SDI, SDO
and SCLK options become active.
19ispEN
Input - This pin performs two functions. When ispEN is logic low, it
functions as an input pin to load programming data into the device.
SDI/IN 0 is also used as one of the two control pins for the isp state
machine. It is a dedicated input pin when ispEN is logic high.
21SDI/IN 01
34SDO/IN 11Output/Input - This pin performs two functions. When ispEN is logic low,
it functions as an output pin to read serial shift register data. It is a
dedicated input pin when ispEN is logic high.
49SCLK/IN 21Input - This pin performs two functions. When ispEN is logic low, it
functions as a clock pin for the Serial Shift Register. It is a dedicated
input pin when ispEN is logic high.
Active Low (0) Reset pin which resets all of the GLB and I/O registers in
the device.
20RESET
Dedicated Clock input. This clock input is brought into the clock
distribution network, and can optionally be routed to any GLB and/or
any I/O cell on the device.
51Y2
Dedicated Clock input. This clock input is brought into the clock
distribution network, and can optionally be routed to any I/O cell on the
device.
50Y3
1, 18, 35, 52
17, 36, 53, 68
19,
23,
31,
42,
46,
54,
69,
73,
81,
92,
96,
4,
20,
28,
32,
43,
47,
55,
70,
78,
82,
93,
97,
5,
21,
29,
33,
44,
48,
56,
71,
79,
83,
94,
98,
6,
22,
30,
34,
45,
53,
57,
72,
80,
84,
95,
3,
7
67
9
68
91, 8
16
18
35
58
17
60
59
14, 15, 36, 37,
10, 11, 40, 41,
61, 62, 89, 90
65, 66, 85, 86
TQFP PIN NUMBERS
1. Pins have dual function capability.
2. NC pins are not to be connected to any active signals, Vcc or GND.
No Connect
NC2—1, 2, 12, 13,
24, 25, 26, 27,
38, 39, 49, 50,
51, 52, 63 64,
74, 75, 76, 77
87, 88, 99, 100
Pin Description
Specifications ispLSI 1024
11
1NC
1NC
I/O 43
I/O 44
I/O 45
I/O 46
I/O 47
IN5
Y0
VCC
VCC
1NC
1NC
GND
GND
ispEN
RESET
2SDI/1N0
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
1NC
1NC
NC1
NC1
I/O 28
I/O 27
I/O 26
I/O 25
I/O 24
IN3/MODE2
Y1
VCC
VCC
NC1
NC1
GND
GND
Y2
Y3
IN2/SCLK2
I/O 23
I/O 22
I/O 21
I/O 20
I/O 19
NC1
NC1
NC1
NC1
I/O 42
I/O 41
I/O 40
I/O 39
I/O 38
I/O 37
I/O 36
IN4
GND
GND
NC1
NC1
VCC
VCC
I/O 35
I/O 34
I/O 33
I/O 32
I/O 31
I/O 30
I/O 29
NC1
NC1
1NC
1NC
I/O 5
I/O 6
I/O 7
I/O 8
I/O 9
I/O 10
I/O 11
2SDO/IN1
GND
GND
1NC
1NC
VCC
VCC
I/O 12
I/O 13
I/O 14
I/O 15
I/O 16
I/O 17
I/O 18
1NC
1NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
57
56
55
54
53
52
51
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
58
ispLSI 1024
Top View
0766A-24-isp
1. NC pins are not to be connected to any active signal, Vcc or GND.
2. Pins have dual function capability.
ispLSI 1024 100-Pin TQFP Pinout Diagram
I/O 28
I/O 27
I/O 26
I/O 25
I/O 24
IN3/MODE1
Y1
VCC
GND
Y2
Y3
IN2/SCLK1
I/O 23
I/O 22
I/O 21
I/O 20
I/O 19
I/O 43
I/O 44
I/O 45
I/O 46
I/O 47
IN 5
Y0
VCC
GND
ispEN
1SDI/IN 0
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 42
I/O 41
I/O 40
I/O 39
I/O 38
I/O 37
I/O 36
IN 4
GND
VCC
I/O 35
I/O 34
I/O 33
I/O 32
I/O 31
I/O 30
I/O 29
I/O 5
I/O 6
I/O 7
I/O 8
I/O 9
I/O 10
I/O 11
1SDO/IN 1
GND
VCC
I/O 12
I/O 13
I/O 14
I/O 15
I/O 16
I/O 17
I/O 18
10 60
61
43
11 59
12 58
13 57
14 56
15 55
16 54
17 53
18 52
19 51
20 50
21 49
22 48
23 47
24 46
25 45
26 44
62
42
63
41
64
40
65
39
66
38
67
37
68
36
1
35
2
34
3
33
4
32
5
31
6
30
7
29
8
28
9
27
RESET
ispLSI 1024
Top View
0123C-isp.eps
1. Pins have dual function capability.
Pin Configuration
ispLSI 1024 68-Pin PLCC Pinout Diagram
Specifications ispLSI 1024
12
Pin Configuration
ispLSI 1024 68-Pin JLCC Pinout Diagram
I/O 28
I/O 27
I/O 26
I/O 25
I/O 24
IN 3/MODE1
Y1
VCC
GND
Y2
Y3
IN 2/SCLK1
I/O 23
I/O 22
I/O 21
I/O 20
I/O 19
I/O 43
I/O 44
I/O 45
I/O 46
I/O 47
IN 5
Y0
VCC
GND
ispEN
1SDI/IN 0
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 42
I/O 41
I/O 40
I/O 39
I/O 38
I/O 37
I/O 36
IN 4
GND
VCC
I/O 35
I/O 34
I/O 33
I/O 32
I/O 31
I/O 30
I/O 29
I/O 5
I/O 6
I/O 7
I/O 8
I/O 9
I/O 10
I/O 11
1SDO/IN 1
GND
VCC
I/O 12
I/O 13
I/O 14
I/O 15
I/O 16
I/O 17
I/O 18
10 60
61
43
11 59
12 58
13 57
14 56
15 55
16 54
17 53
18 52
19 51
20 50
21 49
22 48
23 47
24 46
25 45
26 44
62
42
63
41
64
40
65
39
66
38
67
37
68
36
1
35
2
34
3
33
4
32
5
31
6
30
7
29
8
28
9
27
RESET
ispLSI 1024/883
Top View
0123-24-isp/JLCC
1. Pins have dual function capability.
Specifications ispLSI 1024
13
Part Number Description
tpd (ns)fmax (MHz) Ordering Number Package
COMMERCIAL
tpd (ns)fmax (MHz) Ordering Number Package
60 20 ispLSI 1024-60LJI 68-Pin PLCC
INDUSTRIAL
Family
ispLSI 80 15 ispLSI 1024-80LT 100-Pin TQFP
60 20
60 20
ispLSI 1024-60LJ
ispLSI 1024-60LT
68-Pin PLCC
100-Pin TQFP
ispLSI
Family
Table 2-0041A-24-isp
MILITARY/883
90 12 ispLSI 1024-90LJ 68-Pin PLCC
90 12
80 15
ispLSI 1024-90LT
ispLSI 1024-80LJ
100-Pin TQFP
68-Pin PLCC
Note: Lattice Semiconductor recognizes the trend in military device procurement towards
using SMD compliant devices, as such, ordering by this number is recommended.
tpd (ns)fmax (MHz) Ordering Number Package
60 20 ispLSI 1024-60LH/883 68-Pin JLCC
ispLSI
Family SMD #
5962-9476101MXC
60 20 ispLSI 1024-60LTI 100-Pin TQFP
Ordering Information
Device Number
Grade
Blank = Commercial
I = Industrial
/883 = 883 Military Process
1024 XX X X X
Speed
90 = 90 MHz
f
max
80 = 80 MHz
f
max
60 = 60 MHz
f
max Power
L = Low
Package
J = PLCC
T = TQFP
H = JLCC
–
Device Family
ispLSI
00212-80B-isp1024
ispLSI
