LTC3114-1
1
Rev. D
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TYPICAL APPLICATION
FEATURES DESCRIPTION
40V, 1A Synchronous
Buck-Boost DC/DC Converter with
Programmable Output Current
The LT C
®
3114-1 is a versatile, wide operating voltage
range synchronous monolithic buck-boost DC/DC con-
verter with programmable average output current. The
LTC3114-1’s proprietary buck-boost PWM control cir-
cuitry delivers low noise operation across the entire
operating voltage range. Current mode control ensures
exceptional line and load transient responses.
Synchronous, internal MOSFET switches and pin select-
able Burst Mode operation maintain high efficiency across
the entire range of load current. Average output current
is programmed with a standard resistor and provides
the basis for wide input range, high efficiency charging
systems or constant current, high efficiency LED drive.
Regulator turn-on is programmable through the accu-
rate RUN pin. Quiescent current is just 3µA in shutdown.
Overtemperature protection, short-circuit protection and
soft-start are integrated. The LTC3114-1 is offered in
16-lead 3mm × 5mm × 0.75mm DFN and 16 lead TSSOP
(FE) packages.
Efficiency vs Input Voltage
APPLICATIONS
n Regulates VOUT Above, Below or Equal to VIN
n Single Inductor
n Wide VIN Range: 2.2V to 40V
n Wide VOUT Range: 2.7V to 40V
n 1A Output Current in Buck Mode
n 0.5A Output Current, VIN = 3.6V, VOUT = 5V
n Programmable Average Output Current
n Up to 96% Efficiency
n Burst Mode
®
Operation, 30µA No-Load IQ
n Current Mode Control
n 1.2MHz Ultralow Noise PWM
n Accurate RUN Pin Threshold
n Thermally Enhanced, 16-lead 3mm × 5mm DFN and
TSSOP Packages
n AEC-Q100 Qualified for Automotive Applications
n 24V/28V Industrial Power Supply
n 12V Lead-Acid to 12V Regulator
n High Power LED Driver
n 12V/24V Solar Panel Battery Charging Systems
n Automotive Power Systems
All registered trademarks and trademarks are the property of their respective owners. Protected
by U.S. patents, including 6404251, 6166527.
6.8µH
SW1 SW2
GND PGND
BST1
68nF
4.7µF
4700pF
27.4k
499k
31141 TA01a
2M
20k33nF
68nF
BST2
VIN PVOUT
PVIN LDO
PLDO
FB
RUN
10µF
VIN
2.7V TO 40V
VCPROG
MODE
30µF
VOUT
5V
1A
VIN
> 5V
LTC3114-1
INPUT VOLTAGE (V)
EFFICIENCY (%)
95
90
85
31141 TA01b
70
80
75
1 10 40
ILOAD = 300mA
ILOAD = 600mA
LTC3114-1
2
Rev. D
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ABSOLUTE MAXIMUM RATINGS
VIN, PVIN, PVOUT ........................................ –0.3V to 45V
VBST1 .....................................VSW1 – 0.3V to VSW1 + 6V
VBST2 .....................................VSW2 – 0.3V to VSW2 + 6V
VRUN ............................................. –0.3V to (VIN + 0.3V)
Voltage, All Other Pins ................................. –0.3V to 6V
Operating Junction Temperature Range (Notes 2, 4)
LTC3114E-1/LTC3114I-1 ..................... –40°C to 125°C
LTC3114H-1 ....................................... –40°C to 150°C
LTC3114MP-1 ..................................... –55°C to 150°C
(Note 1)
16
15
14
13
12
11
10
9
17
PGND
1
2
3
4
5
6
7
8
MODE
SW1
PVIN
BST1
BST2
PLDO
VIN
LDO
PGND
SW2
PV
OUT
RUN
PROG
VC
FB
GND
TOP VIEW
DHC PACKAGE
16-LEAD (5mm × 3mm) PLASTIC DFN
TJMAX = 150°C, θJA = 43°C/W (4-LAYER BOARD), θJC = 4°C/W
EXPOSED PAD (PIN 17) IS PGND, MUST BE SOLDERED TO PCB
FOR RATED THERMAL PERFORMANCE
FE PACKAGE
16-LEAD PLASTIC TSSOP
1
2
3
4
5
6
7
8
TOP VIEW
16
15
14
13
12
11
10
9
PGND
SW2
PV
OUT
RUN
PROG
VC
FB
GND
MODE
SW1
PVIN
BST1
BST2
PLDO
VIN
LDO
17
PGND
TJMAX = 150°C, θJA = 38°C/W
EXPOSED PAD (PIN 17) IS PGND, MUST BE SOLDERED TO PCB
FOR RATED THERMAL PERFORMANCE
PIN CONFIGURATION
ORDER INFORMATION
LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE
LTC3114EDHC-1#PBF LTC3114EDHC-1#TRPBF 31141 16-Lead (5mm × 3mm) Plastic DFN –40°C to 125°C
LTC3114IDHC-1#PBF LTC3114IDHC-1#TRPBF 31141 16-Lead (5mm × 3mm) Plastic DFN –40°C to 125°C
LTC3114HDHC-1#PBF LTC3114HDHC-1#TRPBF 31141 16-Lead (5mm × 3mm) Plastic DFN –40°C to 150°C
LTC3114MPDHC-1#PBF LTC3114MPDHC-1#TRPBF 31141 16-Lead (5mm × 3mm) Plastic DFN –55°C to 150°C
LTC3114EFE-1#PBF LTC3114EFE-1#TRPBF 3114FE-1 16-Lead Plastic TSSOP –40°C to 125°C
LTC3114IFE-1#PBF LTC3114IFE-1#TRPBF 3114FE-1 16-Lead Plastic TSSOP –40°C to 125°C
LTC3114HFE-1#PBF LTC3114HFE-1#TRPBF 3114FE-1 16-Lead Plastic TSSOP –40°C to 150°C
LTC3114MPFE-1#PBF LTC3114MPFE-1#TRPBF 3114FE-1 16-Lead Plastic TSSOP –55°C to 150°C
Storage Temperature Range....................–65°C to 150°C
Lead Temperature (Soldering, 10 Sec)
FE Package .......................................................300°C
LTC3114-1
3
Rev. D
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ORDER INFORMATION
LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE
AUTOMOTIVE PRODUCTS**
LTC3114EDHC-1#WPBF LTC3114EDHC-1#WTRPBF 31141 16-Lead (5mm × 3mm) Plastic DFN –40°C to 125°C
LTC3114IDHC-1#WPBF LTC3114IDHC-1#WTRPBF 31141 16-Lead (5mm × 3mm) Plastic DFN –40°C to 125°C
LTC3114IFE-1#WPBF LTC3114IFE-1#WTRPBF 3114FE-1 16-Lead Plastic TSSOP –40°C to 125°C
LTC3114EFE-1#WPBF LTC3114EFE-1#WTRPBF 3114FE-1 16-Lead Plastic TSSOP –40°C to 125°C
Contact the factory for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
Tape and reel specifications. Some packages are available in 500 unit reels through designated sales channels with #TRMPBF suffix.
**Versions of this part are available with controlled manufacturing to support the quality and reliability requirements of automotive applications. These
models are designated with a #W suffix. Only the automotive grade products shown are available for use in automotive applications. Contact your
local Analog Devices account representative for specific product ordering information and to obtain the specific Automotive Reliability reports for
thesemodels.
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the specified operating
junction temperature range, otherwise specifications are at TA = 25°C (Note 2). VIN = 24V, VOUT = 5V, unless otherwise noted.
PARAMETER CONDITIONS MIN TYP MAX UNITS
VIN Operating Voltage VLDO ≥ 2.7V, –55°C to 0°C
VLDO ≥ 2.7V, 0°C to 150°C
l
l
2.3
2.2
40
40
V
V
Output Operating Voltage (Note 5) l2.7 40 V
Undervoltage Lockout Threshold on LDO VLDO Rising l2.3 2.5 2.7 V
VIN Quiescent Current in Shutdown 3 µA
VIN Quiescent Current in Burst Mode Operation FB = 1.4V, Non-Bootstrapped (Note 6) 50 µA
Oscillator Frequency l1000 1200 1400 kHz
Oscillator Frequency Variation VIN = 12V to 36V 0.1 %/V
Feedback Voltage Measured on FB l0.98 1.0 1.02 V
Feedback Voltage Line Regulation VIN = 2.7V to 40V, Measured on FB 0.2 %
Error Amplifier Transconductance VC Current = ±5µA 120 µS
FB Pin Input Current FB = 1V 1 50 nA
VC Source Current VC = 0.6V –12 µA
VC Sink Current VC = 0.6V 12 µA
RUN Pin Threshold—Accurate RUN Pin Rising l1.185 1.205 1.29 V
RUN Pin Hysteresis 140 mV
Run Pin Threshold—Logic l0.3 0.7 1.1 V
PROG Current Switch D Current = 1A
Switch D Current = 500mA
Switch D Current = 100mA (Note 3)
38
18
2
40
20
4
42
22
6
µA
µA
µA
PROG Current Gain Ratio of PROG Current to SWD Current 40 µA/A
PROG Voltage Threshold 0.90 0.925 0.95 V
Inductor Current Limit (Note 3) l1.3 1.7 2.3 A
Overload Current Limit VOUT = 0V (Note 3) 2.6 A
IZERO Inductor Current Limit (Note 3) 100 mA
Maximum Duty Cycle Percentage of Period SW2 is Low in Boost Mode
Percentage of Period SW1 is High in Boost Mode
l
l
90
85
95
88
%
%
Minimum Duty Cycle Percentage of Period SW1 is High in Buck Mode l0 %
LTC3114-1
4
Rev. D
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ELECTRICAL CHARACTERISTICS
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: The LTC3114-1 is tested under pulsed load conditions such that
TJ ≈TA. The LTC3114E-1 is guaranteed to meet performance specifications
from 0°C to 85°C junction temperature. Specifications over the –40°C
to 125°C operating junction temperature range are assured by design,
characterization and correlation with statistical process controls. The
LTC3114I-1 specifications are guaranteed over the –40°C to 125°C
operating junction temperature range. The LTC3114H-1 specifications are
guaranteed over the –40°C to 150°C operating junction temperature range.
The LTC3114MP-1 specifications are guaranteed over the –55°C to 150°C
operating junction temperature range. High junction temperatures degrade
operating lifetime; operating lifetime is derated for junction temperatures
greater than 125°C. The maximum ambient temperature consistent with
these specifications is determined by specific operating conditions in
conjunction with board layout, the rated package thermal resistance and
other environmental factors.
The junction temperature (TJ in degrees Celsius) is calculated from the
ambient temperature (TA in degrees Celsius) and the power dissipation
(PD in Watts) according to the following formula:
TJ = TA + (PD • θJA)
where θJA is the thermal impedance of the package.
The l denotes the specifications which apply over the specified operating
junction temperature range, otherwise specifications are at TA = 25°C (Note 2). VIN = 24V, VOUT = 5V, unless otherwise noted.
Note 3: Current measurements are performed when the LTC3114-1 is
not switching. The current limit values measured in operation will be
somewhat higher due to the propagation delay of the comparators. The
LTC3114-1 is tested in a proprietary non-switching test mode.
Note 4: This IC includes overtemperature protection that is intended to
protect the device during momentary overload conditions. The maximum
rated junction temperature will be exceeded when this protection is active.
Continuous operation above the specified absolute maximum operating
junction temperature may impair device reliability or permanently damage
the device.
Note 5: Operating output voltage can be programmed as low as 1.0V
nominal if the accurate programmable output current limit feature is not
required.
Note 6: Connecting LDO/PLDO to the regulated 5V output (bootstrapping),
reduces quiescent current substantially. Typical no-load quiescent current
for 12V VIN to 5V VOUT is 30µA, if boostrapped.
N-Channel Switch Resistance Switch A (from PVIN to SW1)
Switch B (from SW1 to PGND)
Switch C (from SW2 to PGND)
Switch D (from PVOUT to SW2)
250
250
250
250
mΩ
mΩ
mΩ
mΩ
N-Channel Switch Leakage 0.1 10 µA
LDO Output Voltage ILDO = 10mA l4.2 4.4 4.6 V
LDO Load Regulation ILDO = 1mA to 10mA 0.8 %
LDO Line Regulation ILDO = 1mA, VIN = 10V to 40V 0.2 %
LDO Current Limit VLDO = 2.5V 40 65 mA
Soft-Start Time 2 ms
SW1 and SW2 Forced Low Time 100 ns
MODE Pin Logic Threshold H = PWM Mode, L = Burst Mode Operation l0.5 0.9 1.3 V
LTC3114-1
5
Rev. D
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TYPICAL PERFORMANCE CHARACTERISTICS
No-Load Input Current
vs VIN, Burst Mode Enabled
12V Output Efficiency vs VIN
24V Output Efficiency
vs Load Maximum Load Current vs VIN
5V Output Efficiency vs Load 12V Output Efficiency vs Load
(TA = 25°C unless otherwise specified)
LOAD CURRENT (A)
60
EFFICIENCY (%)
65
70
75
80
0.001 0.01 0.1 1
31141 G01
55
50
45
40
85
95
90
VIN = 3.6V
VIN = 12V
VIN = 24V
VIN = 36V
LOAD CURRENT (A)
60
EFFICIENCY (%)
65
70
75
80
0.001 0.01 0.1 1
31141 G02
55
50
45
40
85
95
90
VIN = 5V
VIN = 12V
VIN = 24V
VIN = 36V
INPUT VOLTAGE (V)
EFFICIENCY (%)
95
90
85
31141 G03
70
80
75
1 10 40
ILOAD = 200mA
ILOAD = 400mA
ILOAD = 600mA
ILOAD = 1A
LOAD CURRENT (A)
0.0001
EFFICIENCY (%)
65
70
75
80
0.001 0.01 0.1 1
31141 G04
60
85
95
90
VIN = 5V
VIN = 12V
VIN = 24V
VIN = 36V
INPUT VOLTAGE (V)
1
0.55
OUTPUT CURRENT (A)
0.75
0.95
10 40
31141 G05
0.35
0.05
0.15
1.35
1.15
0.45
0.65
0.85
0.25
1.25
1.05
VOUT = 5V
VOUT = 12V
VOUT = 24V
INPUT VOLTAGE (V)
1
INPUT CURRENT (µA)
40
80
10 40
31141 G06
20
160
120
60
140
100
VOUT = 5V
VOUT = 12V
Average Output Current
vs VIN, RPROG
Burst Mode Operation Threshold
vs VIN
No-Load Input Current
vs VIN, PWM Mode
INPUT VOLTAGE (V)
1
LOAD CURRENT (mA)
110
130
10 40
31141 G07
50
80
70
60
90
100
170
150
120
160
140
LOAD INCREASING
LOAD DECREASING
INPUT VOLTAGE (V)
1
INPUT CURRENT (mA)
10
15
10 40
31141 G08
5
20
VOUT = 5V
VOUT = 12V
INPUT VOLTAGE (V)
1
OUTPUT CURRENT (mA)
520
600
10 40
31141 G09
240
440
400
360
320
280
480
760
680
560
720
640
R = 25k
R = 50k
R = 100k
LTC3114-1
6
Rev. D
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TYPICAL PERFORMANCE CHARACTERISTICS
Average Output Current vs VOUT
PROG Regulation Voltage
vs Temperature Output Voltage Load Regulation
Output Voltage Line Regulation
Combined LDO, PLDO Supply
Current vs VIN
(TA = 25°C unless otherwise specified)
OUTPUT VOLTAGE (V)
0
AVERAGE OUTPUT CURRENT (mA)
320
360
420
400
440
380
340
300
10 20
240
280
160
200
220
260
140
120
180
100
31141 G10
VIN = 12V
RPROG = 64.7k
TEMPERATURE (°C)
–55
PROG REGULATION VOLTAGE
NORMALIZED TO 1V (%)
–0.50
0
0.50
1.00
125
31141 G11
–1.00
–1.50
–2.00
–0.25
0.25
0.75
–0.75
–1.25
–1.75
–15 25 45 85 105
–35 565 145
VIN = 12V
LOAD CURRENT (mA)
–0.2
CHANGE IN VOUT NORMALIZED TO 100µA (%)
0
0.2
–0.3
–0.1
0.1
0.1 10 100 1000
31141 G12
–0.4
1
VOUT = 5V
VOUT = 12V
INPUT VOLTAGE (V)
1
–0.1
CHANGE IN VOUT NORMALIZED TO VIN = 2.7V (%)
0
0.1
0.3
10 40
31141 G13
0.2
VOUT = 5V
VOUT = 12V
INPUT VOLTAGE (V)
1
6.00
COMBINED LDO, PLDO CURRENT (mA)
6.50
7.00
8.00
10 40
31141 G14
7.50
6.25
6.75
7.75
7.25
VOUT = 12V
Combined LDO, PLDO Supply
Current vs LDO
LDO, PLDO VOLTAGE (V)
2.7
3.50
COMBINED LDO, PLDO CURRENT (mA)
4.00
5.00
5.50
6.00
8.50
7.00
3.4 4.1
4.50
7.50
8.00
6.50
4.8 5.5
VOUT = 5V
LDO Dropout Voltage
vs Temperature
Oscillator Frequency
vs TemperatureLDO Voltage vs Temperature
TEMPERATURE (°C)
–60
4.400
LDO VOLTAGE (V)
4.410
4.430
4.440
4.450
30 60 90 120
4.490
31141 G16
4.420
–30 0 150
4.460
4.470
4.480 VIN = 40V
VIN = 5V
TEMPERATURE (°C)
–60
30
LDO DROPOUT VOLTAGE (mV)
50
40
60
30 60 90 120
80
31141 G17
–30 0 150
70
ILDO = 5mA
TEMPERATURE (°C)
–60
1.060
OSCILLATOR FREQUENCY (MHz)
1.100
1.080
1.120
30 60 90 120
1.160
31141 G18
–30 0 150
1.140
VIN = 3V
VIN = 24V
VIN = 40V
LTC3114-1
7
Rev. D
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Inductor Overload Current Limit
Threshold vs Temperature
RUN Pin Threshold
vs Temperature
RUN Pin Current vs RUN Pin
Voltage FB Voltage vs Temperature
Power Switch Resistance
vs Temperature
Inductor Current Limit Threshold
vs Temperature
TYPICAL PERFORMANCE CHARACTERISTICS
(TA = 25°C unless otherwise specified)
TEMPERATURE (°C)
–60
1.216
RUN PIN THRESHOLD (V)
1.220
1.218
1.222
30 60 90 120
1.230
31141 G19
–30 0 150
1.226
1.224
1.228
VIN = 24V
RUN PIN VOLTAGE (V)
0
RUN PIN CURRENT (µA)
4
6
40
31141 G20
2
010 20 30
515 25 35
8
3
5
1
7
VIN = 12V
TEMPERATURE (°C)
–60
–0.40
NORMAIZED FB VOLTAGE (% CHANGE FROM 25°C)
–0.24
–0.32
–0.16
30 60 90 120
0.24
31141 G21
–30 0 150
0
–0.08
0.08
0.16
VIN = 24V
TEMPERATURE (°C)
–60
0.19
POWER SWITCH RESISTANCE A/D (Ω)
0.23
0.21
0.25
30 60 90 120
0.41
31141 G22
–30 0 150
0.31
0.27
0.35
0.39
0.29
0.33
0.37
VIN = 24V
TEMPERATURE (°C)
–60
1.650
INDUCTOR CURRENT LIMIT THRESHOLD (A)
1.700
1.675
1.725
30 60 90 120
1.800
31141 G23
–30 0 150
1.750
1.775
VIN = 24V
TEMPERATURE (°C)
–60
2.40
INDUCTOR OVERLOAD CURRENT
LIMIT THRESHOLD (A)
2.50
2.45
2.55
30 60 90 120
2.70
31141 G24
–30 0 150
2.60
2.65
VIN = 24V
Inductor Zero Current Threshold
vs Temperature
SW1/SW2 Minimum Low Times
vs Temperature
SW1/SW2 Minimum Low Times
vs LDO
TEMPERATURE (°C)
–60
100
INDUCTOR ZERO CURRENT THRESHOLD (mA)
106
103
109
30 60 90 120
115
31141 G25
–30 0 150
112
VIN = 24V
TEMPERATURE (°C)
–60
90
MINIMUM LOW TIME (ns)
102
96
108
30 60 90 120
120
31141 G26
–30 0 150
114
VIN = 24V
LDO VOLTAGE (V)
2.7
MINIMUM LOW TIME (ns)
130
140
150
5.5
31141 G27
120
110
90 3.4 4.1 4.8
100
170
160
IN APPLICATION
LTC3114-1
8
Rev. D
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Load Transient in Buck Mode,
100mA to 600mA
Burst Mode Operation to PWM
Mode Output Voltage Response
Load Transient in Boost Mode,
100mA to 600mA
5V Output Voltage Response
to Fast Line Transient
(4V to 28V in 10µs)
Output Voltage Ripple in Burst
Mode Operation
Output Voltage Ripple in
PWM Mode
TYPICAL PERFORMANCE CHARACTERISTICS
(TA = 25°C unless otherwise specified)
LOAD
CURRENT
500mA/DIV
VOUT
200mV/DIV
1ms/DIVVIN = 14V
VOUT = 5V
31141 G28
LOAD
CURRENT
500mA/DIV
VOUT
200mV/DIV
1ms/DIVVIN = 3.6V
VOUT = 5V
31141 G29
VOUT
50mV/DIV
200µs/DIVVIN = 14V
LOAD = 10mA
FRONT PAGE CIRCUIT
31141 G30
VOUT
50mV/DIV
LOAD
CURRENT
500mA/DIV
1ms/DIV 31141 G31
VOUT
20mV/DIV
500ns/DIV 31141 G33
VOUT
100mV/DIV
VIN
10V/DIV
50µs/DIV 31141 G32
LTC3114-1
9
Rev. D
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BLOCK DIAGRAM
+
–
BIAS GENERATOR
1.2MHz OSCILLATOR
RUN
LDO 4.4V
PLDO
MODE
PGND
1.2V
VIN
2.1V
LDO
2.5V
LTC3114-1
GATE DRIVERS
PWM
AVERAGE
CURRENT
AMP
VOLTAGE
ERROR
AMP
SOFT-START
1V
IOUT
25k
BANDGAP REFERENCE POR
OVERTEMPERATURE PROTECTION
+
–
+
–
+
–
BST2
BST1
0.1A
PGND
PGND 10µA
OUTPUT
CURRENT
SENSE
MB
MA
MC
MD
SW1 SW2 PVOUT
VIN PVIN
INDUCTOR
ISENSE
IZERO
+
–
REVERSE
BLOCKING
LDO
1V
1V
PROG
FB
VC
GND
31141 BD
+
–
+
–
LTC3114-1
10
Rev. D
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PIN FUNCTIONS
PGND (Pin 1, Exposed Pad Pin 17): Power Ground
Connections. The PGND pin must be electrically con-
nected to a power ground plane in the application. The
exposed pad is an additional power ground connection in
parallel with Pin 1. Optimal thermal performance requires
that the exposed pad be soldered to the PC board and
preferably to a ground plane.
SW2 (Pin 2): Buck-Boost Converter Power Switch Pin.
This pin is connected to one side of the buck-boost
inductor.
PVOUT (Pin 3): Buck-Boost Converter Power Output. This
pin should be connected to a low ESR capacitor of at least
10µF. The capacitor should be placed as close to the IC as
possible and should have a short return path to PGND. In
applications subject to output short circuits through an
inductive load, it is recommended that a Schottky diode
be installed from ground (anode) to PVOUT (cathode) to
limit the extent that PVOUT is driven below ground during
the short-circuit transient.
RUN (Pin 4): Input to Enable and Disable the IC and Set
Custom Input Undervoltage Lockout (UVLO) Thresholds.
The RUN pin can be driven by an external logic signal to
enable and disable the IC. In addition, the voltage on this
pin can be set by a resistive voltage divider connected
to the input voltage in order to provide accurate turn-on
and turn-off (UVLO) thresholds. The IC is enabled if RUN
exceeds 1.2V nominally. Once enabled, the UVLO thresh-
old has built-in hysteresis of approximately 100mV, so
turn-off will occur when the voltage on RUN drops to
below 1.1V nominally. To continuously enable the IC, RUN
can be tied directly to the input voltage up to the absolute
maximum rating.
PROG (Pin 5): Output Current Programming Pin and
Output of the Switch D Current Sense Amplifier. A current
proportional to the current in switch D, the buck-boost
converter output current, is delivered from PROG. The
PROG current magnitude is approximately ISWD/25000.
Connect a parallel resistor and capacitor from PROG to
GND to generate a voltage proportional to output current.
In applications where this voltage is used to control aver-
age output current, the resistor value should be set such
that the desired average output current produces 1V on
PROG and is given by:
RPROG(Ω)=
1V • 25000
IOUT A
( )
Alternatively, the voltage on PROG can be connected
to an A/D converter and used for system diagnostic
functions. Refer to the Applications Information section
for complete details on how to select the proper values
for RPROG and CPROG.
VC (Pin 6): Error Amplifier Output. A frequency com-
pensation network must be connected between VC and
GND to stabilize the buck-boost converter. Refer to the
Applications Information section for details.
FB (Pin 7): Feedback Voltage Input. A resistor divider
connected to this pin sets the output voltage for the buck-
boost converter. The nominal FB voltage is 1V. Care should
be taken in the routing of the connection to this pin to
minimize the possibility of stray coupling from the SW
pins. VOUT is determined by the following relationship:
VOUT (V)=1+RTOP/RBOT where RTOP is connected from
PVOUT to FB and RBOT is connected from FB to GND
GND (Pin 8): Signal Ground. This pin is the ground con-
nection for the control circuitry of the IC and must be tied
to ground in the application.
LDO (Pin 9): Low Voltage Supply Input for the IC Control
Circuitry. This pin powers internal IC control circuitry
and must be connected to the LDO pin in the application.
A 4.7µF or larger bypass capacitor must be connected
between this pin and ground. Pins LDO and PLDO must
be connected together in the application.
VIN (Pin 10): LDO Supply Connection. This pin provides
power to the internal VCC regulator. Pins VIN and PVIN
must be connected together in the application. If the
trace connecting VIN and PVIN is of substantial length, a
1µF capacitor should be connected from VIN to GND as
close to the IC pins as possible.
LTC3114-1
11
Rev. D
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PIN FUNCTIONS
PLDO (Pin 11): Internal LDO Regulator Output. PLDO is
the output of the internal linear regulator that generates
the LDO rail from VIN. PLDO is also used as the supply
connection to the power switch gate drivers. Pins PLDO
and LDO must be connected together in the application.
BST2 (Pin 12): Flying Capacitor Pin for SW2. This pin
must be connected to SW2 through a 68nF capacitor.
BST2 is used to generate the gate driver rail for power
switch D. Make the PCB trace from BST2 to the boost
capacitor as short and direct as possible.
BST1 (Pin 13): Flying Capacitor Pin for SW1. This pin
must be connected to SW1 through a 68nF capacitor.
BST1 is used to generate the gate driver rail for power
switch A. Make the PCB trace from BST2 to the boost
capacitor as short and direct as possible.
PVIN (Pin 14): Power Input for the Buck-Boost Converter.
A 10µF or larger capacitor must be connected between
PVIN and GND as close to the IC as possible. The bypass
capacitor ground connection should via directly down to
the PCB ground plane. Pins PVIN and VIN must be con-
nected together in the application.
SW1 (Pin 15): Buck-Boost Power Converter Switch
Pin. This pin is connected to one side of the buck-boost
inductor.
MODE (Pin 16): Burst Mode/PWM Mode Control Pin.
Forcing MODE high causes the IC to operate in continu-
ous fixed frequency PWM mode. The nominal switching
frequency in PWM mode is 1.2MHz. Forcing MODE low
enables Burst Mode operation. Burst Mode operation
improves efficiency at light loads by only activating the
buck-boost converter as needed to maintain the nominal
regulated output voltage. If MODE is low, the converter
will automatically transition to PWM mode if the load cur-
rent increases.
OPERATION
INTRODUCTION
The LTC3114-1 is a monolithic, current mode, buck-boost
DC/DC converter that can operate over a wide voltage
range of 2.2V to 40V and provide up to 1A to the load.
Internal, low RDS(ON) N-channel DMOS power switches
reduce solution complexity and maximize efficiency. A
proprietary switch control algorithm allows the buck-
boost converter to maintain output voltage regulation with
input voltages that are above, below or equal to the output
voltage. Transitions between the step-up or step-down
operating modes are seamless and free of transients and
subharmonic switching, making this product ideal for
noise sensitive applications. The LTC3114-1 operates at a
fixed nominal switching frequency of 1.2MHz, which pro-
vides an ideal trade-off between small solution size and
high efficiency. Current mode control provides inherent
input line voltage rejection, simplified compensation and
rapid response to load transients. Burst Mode capability
is also included in the LTC3114-1 and is user selected
via the MODE input pin. In Burst Mode operation, the
LTC3114-1 provides exceptional efficiency at light output
loading conditions by operating the converter only when
necessary to maintain voltage regulation. At higher loads,
the LTC3114-1 automatically switches to fixed frequency
PWM mode when Burst Mode operation is selected. For
5V VOUT applications, the quiescent current in Burst Mode
operation can be as low as 20µA with the internal LDO
regulator bootstrapped to the output voltage. If the appli-
cation requires extremely low noise, continuous PWM
operation can also be selected via the MODE pin. The
LTC3114-1 also features an accurate RUN comparator
threshold with hysteresis. This allows the buck-boost
DC/DC converter to turn on and off at user-selected VIN
voltage thresholds. With a wide voltage range and pro-
grammable output current or monitoring capabilities,
the LTC3114-1 is well suited for many demanding power
conversion needs.
PROGRAMMABLE AVERAGE OUTPUT CURRENT
The LTC3114-1 includes the ability to program an accu-
rate average output current from the buck-boost DC/DC
converter. Whether the application is driving high power
LTC3114-1
12
Rev. D
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OPERATION
LEDs, charging batteries, a wide compliance range cur-
rent source or just providing a well controlled current
limit, the LTC3114-1 programmable average output
current capability delivers high efficiency and maximum
flexibility. The output current limit level is independent of
operating mode, (buck or boost), and is active down to
approximately 2V on VOUT. Below 2V on VOUT, a secondary
foldback current limit circuit is activated to reduce power
dissipation. The desired average output current level is
programmed with a standard low wattage resistor from
PROG to ground. A low loss current sense resistor and
accurate current sense amplifier are integrated within the
IC, greatly simplifying the PCB layout and design. Factory
trimming of the output current limit offset and gain pro-
vide a high degree of accuracy, typically within ±5% of
the setpoint. The applications section provides details on
how to select the programming resistor, RPROG, for the
desired average output current level from the LTC3114-1.
PWM Mode Operation
If the MODE pin is high or if the load current on the con-
verter is high enough to command PWM mode opera-
tion with MODE low, the LTC3114-1 operates in a fixed
1.2MHz PWM mode using a current mode control loop.
PWM mode minimizes output voltage ripple and yields
a low noise switching frequency spectrum. A propri-
etary switching algorithm provides seamless transitions
between operating modes and eliminates discontinuities
in the average inductor current, inductor ripple current
and loop transfer function throughout all modes of oper-
ation. These advantages result in increased efficiency,
A
PLDO
BST1
C
BST1
C
BST2
L
BST2PVIN PVOUT
SW1 SW2
PLDO
PLDO PLDO
LTC3114-1
PGND PGND
31141 F01
B
D
C
Figure1. Power Stage Schematic
improved loop stability and lower output voltage ripple
in comparison to the traditional buck-boost converter.
Figure1 shows the topology of the LTC3114-1 power stage
which is comprised of four N-channel DMOS switches and
their associated gate drivers. In PWM mode operation
both switch pins transition on every cycle independent of
the input and output voltages. In response to the internal
control loop command, an internal pulse width modulator
generates the appropriate switch duty cycle to maintain
regulation of the output voltage.
When stepping down from a high input voltage to a lower
output voltage, the converter operates in buck mode and
switch D remains on for the entire switching cycle except
for the minimum switch low duration (typically 50ns).
During the switch low duration, switch C is turned on
which forces SW2 low and charges the flying capacitor,
CBST2. This ensures that the switch D gate driver power
supply rail on BST2 is maintained. The duty cycle of
switches A and B are adjusted by the PWM to maintain
output voltage regulation in buck mode.
If the input voltage is lower than the output voltage, the
converter operates in boost mode. Switch A remains on
for the entire switching cycle except for the minimum
switch low duration (typically 100ns). During the switch
low duration, switch B is turned on which forces SW1
low and charges the flying capacitor, CBST1. This ensures
that the switch A gate driver power supply rail on BST1
is maintained. The duty cycle of switches C and D are
adjusted by the PWM to maintain output voltage regula-
tion in boost mode.
LTC3114-1
13
Rev. D
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OPERATION
Oscillator
The LTC3114-1 operates from an internal oscillator with
a nominal fixed frequency of 1.2MHz. This allows the
DC/DC converter efficiency to be maximized while still
using small external components.
Current Mode Control
The LTC3114-1 utilizes average current mode control for
the pulse width modulator as shown in Figure2. Current
mode control, both average and the better known peak
method, enjoy some benefits compared to other control
methods including: simplified loop compensation, rapid
response to load transients and improved rejection of line
voltage transients.
Referring to Figure2, an internal high gain transconduc-
tance error amplifier monitors VOUT through a voltage
divider connected to the FB pin and provides an output,
VC, that is used by the current mode control loop to com-
mand the appropriate inductor current level. To ensure
stability, external frequency compensation components
(CP1, CP2 and RZ) must be installed between VC and
ground. The procedure for determining these components
is provided in the Applications Information section of this
data sheet. VC is internally connected to the noninvert-
ing input of a high gain, integrating, operational amplifier,
referred to in Figure2, as the average current amp. The
inverting input of the average current amplifier is con-
nected to the inductor current sense circuit through a gain
setting resistor (R
CS1
) and to its output (VIA) through
an internal frequency compensation network comprised
of RCS2, CCS1 and CCS2. The average current amplifier’s
output provides the cycle-by-cycle duty cycle command
into the buck-boost PWM circuitry.
PWM
A B C D
CONTROL
LOGIC
VIA
AVERAGE
CURRENT
AMP
VOLTAGE
ERROR
AMP
ACTIVE RANGE OF
VC = 135mV TO 1V
SOFT-START
1V
RCS1
CCS2
RCS2
CCS1
RZ
RBOT
RTOP
CP1
+
–
CP2
RCOESR
RLOAD
V
OUT
COUT
RX
gm = 111µA/V
VIN
SWB
SWC
SWD PVOUT
SWA
R
A
250mΩ
VDS
SENSE
L1
VDS
SENSE
1V
gm = 120µS
RO = 3.6M
FB
VC
GND
31141 F02
+
–
gm
INDUCTOR
ISENSE
Figure2. Average Current Mode Control Loop
LTC3114-1
14
Rev. D
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OPERATION
The noninverting reference level input to the average cur-
rent amplifier is VC and the feedback or inverting input
is driven from the inductor current sensing circuitry. The
inductor current sensing circuitry alternately measures the
current through switches A and B. The output of the sens-
ing circuitry produces a voltage across resistor RX that
resembles the inductor current waveform transformed to
a voltage. If there is an increase in the power converter
load on VOUT, the instantaneous level of VOUT will drop
slightly, which will increase the voltage level on VC by
the inverting action of the voltage error amplifier. When
the increase on VC first occurs, the output of the current
averaging amplifier, VIA, will also increase momentarily
to command a larger duty cycle. This duty cycle increase
will result in a higher inductor current level, ultimately
raising the average voltage across RX. Once the average
value of the voltage on RX is equivalent to the VC level,
the voltage on VIA will revert very closely to its previous
level into the PWM and force the correct duty cycle to
maintain voltage regulation at this new higher inductor
current level. The average current amplifier is configured
as an integrator, so in steady state, the average value of
the voltage applied to its inverting input (voltage across
RX) will be equivalent to the voltage on its noninverting,
VC. As a result, the average value of the inductor current
is controlled in order to maintain voltage regulation. The
entire current amplifier and PWM can be simplified as a
voltage controlled current source, with the driving voltage
coming from VC. VC is commonly referred to as the cur-
rent command for this reason and the voltage on VC is
directly proportional to average inductor current, which
can prove useful for many applications.
The voltage error amplifier monitors the output voltage,
V
OUT
through a voltage divider and makes adjustments to
the current command as necessary to maintain regulation.
The voltage error amplifier therefore controls the outer
voltage regulation loop. The average current amplifier
makes adjustments to the inductor current as directed by
the voltage error amplifier output via VC and is commonly
referred to as the inner current-loop amplifier.
The average current mode control technique is similar to
peak current mode control except that the average current
amplifier, by virtue of its configuration as an integrator,
controls average current instead of the peak current.
This difference eliminates the peak to average current
error inherent to peak current mode control, while main-
taining most of the advantages inherent to peak current
modecontrol.
Average current mode control requires appropriate com-
pensation for the inner current loop unlike peak current
mode control. The compensation network must have high
DC gain to minimize errors between the commanded aver-
age current level and actual, high bandwidth to quickly
change the commanded current level following transient
load steps and a controlled mid-band gain to provide a
form of slope compensation unique to average current
mode control. Fortunately, the compensation components
required to ensure these sometimes conflicting require-
ments have been carefully selected and are integrated
within the LTC3114-1. With the inner loop compensation
fixed internally, compensation of the outer voltage loop
as is detailed in the applications section, is similar to well
known techniques used with peak current mode control.
Inductor Current Sense and Maximum Output Current
As part of the current control loop required for current
mode control, the LTC3114-1 includes a pair of current
sensing circuits that directly measure the buck-boost
converter inductor current as shown in Figure2. These
circuits measure the voltage dropped across switches A
and B separately and produce output currents propor-
tional to the switches’ voltage drop. By sensing current
in this manner, there is no additional power loss incurred,
which improves converter efficiency. The amplifier output
terminals are summed together into a common resistor,
RX connected to ground. Since switches A and B are never
conducting at the same time, the resultant waveform on
RX resembles the inductor current. This replica of the
inductor current is used as one input to the current aver-
aging amplifier as described in the previous section.
The voltage error amplifier output, VC, is internally
clamped to a nominal level of 1V. Since the average induc-
tor current is proportional to VC, the 1V clamp level sets
the maximum average inductor current that can be pro-
grammed by the inner current loop. Taking into account
the current sense amplifier’s gain and the value of R
X
, the
LTC3114-1
15
Rev. D
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OPERATION
maximum average inductor current is approximately 1.7A
(typical). In buck mode, the output current is approxi-
mately equal to the inductor current, IL.
IOUT(BUCK) ≈ IL • 0.9
The SW1/SW2 forced low time on each switching cycle
briefly disconnects the inductor from VOUT and VIN result
-
ing in slightly less output current in either buck or boost
mode for a given inductor current. In boost mode, the
output current is related to average inductor current and
duty cycle by:
IOUT(BOOST) ≈ IL • (1 – D)
where D is the converter duty cycle.
Since the output current in boost mode is reduced by the
duty cycle (D), the output current rating in buck mode
is always greater than in boost mode. Also, because
boost mode operation requires a higher inductor cur-
rent for a given output current compared to buck mode,
the efficiency in boost mode will be lower due to higher
IINDUCTOR2 • RDS(ON) losses in the power switches. This
will further reduce the output current capability in boost
mode. In either operating mode, however, the inductor
peak-to-peak ripple current does not play a major role
in determining the output current capability, unlike peak
current mode control.
With peak current mode control, the maximum output
current capability is reduced by the magnitude of inductor
ripple current because the peak inductor current level is the
control variable, but the average inductor current is what
determines the output current. The LTC3114 -1 measures
and controls average inductor current, and therefore, the
inductor ripple current magnitude has little effect on the
maximum current capability in contrast to an equivalent
peak current mode converter. Under most conditions in
buck mode, the LTC3114 -1 is capable of providing 1A to
the load. Under certain conditions, more output current is
possible, refer to the Typical Performance Characteristics
section for more details. In boost mode, as described
previously, the output current capability is related to the
boost ratio or duty cycle (D). For a 3.6V VIN to 5V output
application, the LTC3114-1 can provide up to 500mA to
the load. Refer to the Typical Performance Characteristics
section for more detail on output current capability.
At VC levels below 135mV, the LTC3114-1 will not com-
mand any current because the internal current sense sig-
nal has a built-in 135mV offset. Therefore, the active range
of VC is between approximately 135mV (zero current) and
1V (full current). In some applications, an external circuit
may be used to control the VC voltage level. Any such
circuit needs to have the capability to sink or source the
approximate 12µA provided by the internal error amplifier
and to pull below 135mV to disable the current command,
if necessary.
OVERLOAD CURRENT LIMIT AND ZERO CURRENT
COMPARATOR
The internal current sense waveform is also used by the
peak overload current (IPEAK) and zero current (IZERO)
comparators. The IPEAK current comparator monitors
ISENSE and halts converter operation if the inductor cur-
rent level exceeds its maximum internal threshold, which
is approximately 50% above the normal maximum current
level commanded by the current control loop. An inductor
current level of this magnitude will only occur during a
fault, such as an output short circuit or a fast VIN (line)
transient. If the IPEAK comparator is engaged, the PWM
is halted for the remainder of the switching cycle with
SW1 and SW2 held low. If V
OUT
is less than approximately
1.8V when the peak limit occurs, then a soft-start cycle
is initiated. In the event that the current overload is the
result of an output short-circuit condition, the LTC3114-1
will remain in a low frequency restart mode, keeping the
on-chip power dissipation to very low levels. If the short
circuit is removed, the LTC3114-1 will restart in the normal
fashion.
The LTC3114-1 exhibits discontinuous inductor current
operation at light output loads by virtue of the I
ZERO
com-
parator circuit under most operating conditions. This
improves efficiency at light output loads if PWM mode
operation compared to continuous conduction mode. If
the internal current sense waveform transitions below the
internally set zero current threshold, the LTC3114-1 will
disconnect the inductor from VOUT, by shutting off switch
D, to prevent discharge of the output capacitor. The IZERO
circuitry is reset by the oscillator clock at the end of the
switching cycle. The I
ZERO
comparator threshold is set
LTC3114-1
16
Rev. D
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OPERATION
slightly above zero current to compensate for comparator
propagation delay. In some cases, the inductor current
may reverse slightly if there is a very high voltage output
or small inductor resulting in a small amount of resid-
ual energy left in the inductor following a zero current
event. In this case the LTC3114-1 SW1 waveform will
display a characteristic half sine wave between the time
at which Izero is detected and when the next switching
cycle commences. This is because SWC is the only active
(on) switch following an IZERO event and this behavior is
not harmful to the LTC3114-1.
Burst Mode Operation
When the MODE pin is held low, the LTC3114-1 is config-
ured for Burst Mode operation. As a result, the buck-boost
DC/DC converter will operate with normal continuous
PWM switching above a predetermined minimum out-
put load and will automatically transition to power saving
Burst Mode operation below this output load level. Refer
to the Typical Performance Characteristics section of this
data sheet to determine the Burst Mode transition thresh-
old for various combinations of VIN and VOUT. If MODE
is low, at light output loads, the LTC3114-1 will go into a
standby or sleep state when the output voltage achieves
its nominal regulation level. The sleep state halts PWM
switching and powers down all non-essential functions
of the IC, significantly reducing the quiescent current of
the LTC3114-1. This greatly improves overall power con-
version efficiency when the output load is light. Since the
converter is not operating in sleep, the output voltage will
slowly decay at a rate determined by the output load resis-
tance and the output capacitor value. When the output
voltage has decayed by a small amount, typically 1%, the
LTC3114-1 will wake and resume normal PWM switch-
ing operation until the voltage on VOUT is restored to the
previous level. If the load is very light, the LTC3114-1
may only need to switch for a few cycles to restore VOUT
and may sleep for extended periods of time, significantly
improving efficiency.
Soft-Start
The LTC3114-1 soft-start circuit minimizes input current
transients and output voltage overshoot on initial power
up. The required timing components for soft-start are
internal to the LTC3114-1 and produce a nominal soft-
start duration of approximately 2ms. The internal soft-
start circuit slowly ramps the error amplifier output, VC.
In doing so, the current command of the IC is also slowly
increased, starting from zero. It is unaffected by output
loading or output capacitor value. Soft-start is reset by
undervoltage lockout on both VIN and LDO, the accurate
RUN pin comparator, thermal shutdown and the overload
current limit as described previously.
LDO REGULATOR
An internal low dropout regulator generates a nominal
4.4V rail from VIN. The LDO rail powers the internal control
circuitry and power device gate drivers of the LTC3114-1.
The LDO regulator is disabled in shutdown to reduce qui-
escent current and is enabled by forcing the RUN pin
above its logic threshold. The LDO regulator includes
current-limit protection to safeguard against accidental
short-circuiting of the LDO rail. In 5V VOUT applications,
the LDO can be driven by VOUT through a Schottky diode,
commonly referred to as bootstrapping. Bootstrapping
can provide a significant efficiency improvement, partic-
ularly when VIN is very high and also allows operation to
the minimum rated input voltage of 2.2V.
UNDERVOLTAGE LOCKOUT
The LTC3114-1 undervoltage lockout (UVLO) circuit dis-
ables operation of the internal power switches and keeps
other IC functions in a reset state if either the input voltage
applied to VIN or the LDO output voltage are below their
respective UVLO thresholds. There are two UVLO circuits,
one that monitors VIN and another that monitors LDO. The
VIN UVLO comparator has a falling voltage threshold of
2.1V (typical). If VIN falls below this level, IC operation is
disabled until VIN rises above 2.2V (typical), as long as
the LDO voltage is above its UVLO threshold. The LDO
UVLO has a falling voltage threshold of 2.4V (typical). If
the LDO voltage falls below this threshold, IC operation
is disabled until LDO rises above 2.5V (typical) as long as
VIN is above its nominal UVLO threshold level.
LTC3114-1
17
Rev. D
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OPERATION
Depending on the particular application, either of these
UVLO thresholds could be the limiting factor affecting
the minimum input voltage required for operation. The
LTC3114-1 LDO regulator uses VIN for its power input. If
LDO is not bootstrapped, then there exists a voltage drop
or dropout voltage between V
IN
and LDO. The dropout
voltage is proportional to the loading on LDO, which is
primarily due to the gate charge and capacitive charging
currents inherent to the internal power switches. The
loading on LDO and the LDO dropout voltage, therefore,
are proportional to VIN and VOUT. For this reason, the min-
imum input voltage required for operation is limited by the
LDO minimum voltage as input voltage (VIN) will always
be higher than LDO in the normal (non-bootstrapped)
configuration. The Typical Performance Characteristics
section of this data sheet provides guidance on the drop-
out voltage between VIN and LDO over the range of VIN
and VOUT.
In applications where LDO is bootstrapped (powered by
VOUT through a Schottky diode or auxiliary power rail),
the minimum input voltage for operation (after start-up)
will be limited only by the VIN UVLO threshold (2.1V typ-
ical). Please note that if the bootstrap voltage is derived
from the LTC3114-1 VOUT and not an independent power
rail, then the minimum input voltage required for initial
start-up is still limited by the minimum LDO voltage (2.6V
typical).
RUN PIN COMPARATOR
In addition to serving as a logic-level input to enable cer-
tain functions of the IC, the RUN pin includes an accurate
internal comparator that allows it to be used to set custom
rising and falling on/off thresholds with the addition of
an external resistor divider. When RUN is driven above
its logic threshold (0.7V typical), the LDO regulator is
enabled, which provides power to the internal control
circuitry of the IC. If the voltage on RUN is increased
further so that it exceeds the RUN comparator accurate
analog threshold (1.2V nominal), all functions of the buck-
boost converter will be enabled and a startup sequence
will ensue.
If RUN is brought below the accurate comparator thresh-
old, the buck-boost converter will inhibit switching, but
the LDO regulator and control circuitry will remain pow-
ered unless RUN is brought below its logic threshold.
Therefore, in order to completely shut down the IC and
reduce the VIN current to 3µA (typical), it is necessary to
ensure that RUN is brought below its worst-case low-
logic threshold of 0.3V. RUN is a high voltage input and
can be tied directly to VIN to continuously enable the IC
when the input supply is present. Also note that RUN can
be driven above VIN or VOUT as long as it stays within the
operating range of the IC, that is, less than 40V. If RUN
is forced above 5V, it will sink a small current as given by
the following equation:
IRUN ≈
V
RUN
– 5V
5MΩ
With the addition of an optional resistor divider as shown
in Figure 3, the RUN pin can be used to establish a
user-programmable turn on and turn off threshold.
The buck-boost converter is enabled when the voltage on
RUN reaches 1.205V (nominal). Therefore, the turn-on
voltage threshold on VIN is given by:
VTURNON =1.205V 1+
R1
R2
⎛
⎝
⎜⎞
⎠
⎟
Once the converter is enabled, the RUN comparator
includes a built-in hysteresis of approximately 140mV,
so that the turn-off threshold will be approximately 8.33%
lower than the turn-on threshold. Put another way, the
internal threshold level for the RUN comparator looks like
1.1V after the IC is enabled.
Figure3. Accurate RUN Pin Comparator
+
–
+
–
ENABLE SWITCHING
ENABLE LDO AND
CONTROL CIRCUITS
1.2V
ACCURATE THRESHOLD
LTC3114-1
LOGIC THRESHOLD
0.7V
31141 F03
RUN
R1
R2
V
IN
LTC3114-1
18
Rev. D
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OPERATION
The RUN comparator is relatively noise insensitive, but
there may be cases dues to PCB layout, very large value
resistors for R1 and R2 or proximity to noisy components
where noise pickup is unavoidable and may cause the
turn on or turn off of the IC to be intermittent. In these
cases, a filter capacitor can be added across R2 to ensure
proper operation.
THERMAL CONSIDERATIONS
The power switches of the LTC3114-1 are designed to
operate continuously with currents up to the internal cur-
rent limit thresholds. However, when operating at high
current levels, there may be significant heat generated
within the IC. In addition, the LDO regulator can generate
a significant amount of heat when VIN is very high. This
adds to the total power dissipation of the IC. As described
elsewhere in this data sheet, bootstrapping of the LDO
for 5V output applications can essentially eliminate the
LDO power dissipation term and significantly improve
efficiency. As a result, careful consideration must be given
to the thermal environment of the IC in order to provide
a means to remove heat from the IC and ensure that the
LTC3114-1 is able to provide its full rated output current.
Specifically, the exposed die attach pad of both the DHC
and FE packages must be soldered to a copper layer on
the PCB to maximize the conduction of heat out of the IC
package. This can be accomplished by utilizing multiple
vias from the die attach pad connection underneath the IC
package to other PCB layer(s) containing a large copper
plane. A typical board layout incorporating these concepts
is shown in Figure4.
If the IC die temperature exceeds approximately 165°C,
overtemperature shutdown will be invoked and all switch-
ing will be inhibited. The part will remain disabled until the
die temperature cools by approximately 10°C. The soft-
start circuit is re-initialized in overtemperature shutdown
to provide a smooth recovery when the IC die temperature
cools enough to resume operation.
Start-Up Into a Pre-Biased VOUT
Some applications require the LTC3114-1 to start up into
an output voltage (VOUT), that is pre-biased by an external
source to some level. It is desirable at LTC3114-1 start-up
to minimize current taken from the pre-bias voltage source
and VOUT storage capacitor to prevent VOUT glitches and
currents fed backwards into the VIN power source of the
LTC3114-1.
If the LTC3114-1 V
IN
voltage is higher than the pre-bi-
ased VOUT, indicating buck mode operation, then there
will be minimal reverse current at start-up. However, if
the LTC3114-1 VIN voltage is lower than the pre-biased
VOUT, indicating boost mode operation, then it is possible
for a brief, but substantial reverse current to be taken by
the LTC3114-1 from VOUT. The duration of this reverse
current is approximately 100µs to 200µs. The magnitude
is inversely proportional to the VIN voltage and dependent
upon external component values.
Prevention of pre-biased V
OUT
reverse current in boost
mode can be achieved in two ways. The preferred method
is to ensure that the pre-biased VOUT voltage level is set
higher than the nominal VOUT regulation level. For exam-
ple, if VOUT is pre-biased to 13V, then setting the VOUT
regulation voltage of the LTC3114-1 to less than 13V,
taking into account error margins, will result in negligible
or zero reverse current at start-up. If this is not possible,
then a Schottky diode can be connected in series between
VOUT of the LTC3114-1 and the converter output to block
reverse current .
LTC3114-1
19
Rev. D
For more information www.analog.com
OPERATION
Figure4. Typical 4 Layer PC Board Layout
Top Layer
Bottom Layer
2nd Layer
3rd Layer
LTC3114-1
20
Rev. D
For more information www.analog.com
APPLICATIONS INFORMATION
A standard application circuit for the LTC3114-1 is shown
on the front page of this data sheet. The appropriate
selection of external components is dependent upon the
required performance of the IC in each particular appli-
cation given considerations and trade-offs such as PCB
area, input and output voltage range, output voltage rip-
ple, required efficiency, thermal considerations and cost.
This section of the data sheet provides some basic guide-
lines and considerations to aid in the selection of external
components and the design of the applications circuit.
LDO Capacitor Selection
The LDO output of the LTC3114-1 is generated from VIN
by a low dropout linear regulator. The LDO regulator has
been designed for stable operation with a wide range
of output capacitors. For most applications, a low ESR
capacitor of at least 4.7µF should be used. The capacitor
should be located as close to the PLDO pin as possible
and connected to the LDO pin and ground through the
shortest traces possible. PLDO is the regulator output
and is also the internal supply pin for the gate drivers
and boost rail charging diodes. The LDO pin is the supply
connection for the remainder of the control circuitry. The
LDO and PLDO pins must be connected together on the
PCB. If the connecting trace cannot be made short, an
additional 0.1µF bypass capacitor should be connected
between the LDO pin and ground as close to the package
pins as possible.
Inductor Selection
The choice of inductor used in LTC3114-1 application circuits
influences the maximum deliverable output current, the con-
verter bandwidth, the magnitude of the inductor current ripple
and the overall converter efficiency. The inductor must have a
low DC series resistance or output current capability and effi-
ciency will be compromised. Larger inductor values reduce
inductor current ripple but will not increase output current
capability as is the case with peak current mode control as
described in the Maximum Output Current section of this data
sheet. Larger value inductors also tend to have a higher DC
series resistance for a given case size, which will have a nega-
tive impact on efficiency. Larger values of inductance will also
lower the right half plane (RHP) zero frequency when operat-
ing in boost mode, which requires the converter bandwidth to
be set lower in frequency, slowing the converter’s response
to load transients. Nearly all LTC3114-1 application circuits
deliver the best performance with an inductor value between
4.7µH and 15µH. Buck mode-only applications can use the
larger inductor values as they are unaffected by the RHP zero,
while mostly boost applications generally require inductance
on the low end of this range depending on how deep they will
operate in boost mode.
Regardless of inductor value, the saturation current rat-
ing should be selected such that it is greater than the
worst-case average inductor current plus half of the ripple
current. The peak-to-peak inductor current ripple for each
operational mode can be calculated from the following
formula, where f is the switching frequency (1.2MHz), L
is the inductance in µH and tLOW is the switch pin mini-
mum low time in µs. The switch pin minimum low time
is typically 0.05µs.
ΔIL(P-P)(BUCK) =VOUT
L
V
IN – VOUT
V
IN
⎛
⎝
⎜⎞
⎠
⎟1
f– tLOW
⎛
⎝
⎜⎞
⎠
⎟Amps
ΔIL(P-P)(BOOST) =V
IN
L
VOUT – V
IN
VOUT
⎛
⎝
⎜⎞
⎠
⎟1
f– tLOW
⎛
⎝
⎜⎞
⎠
⎟Amps
It should be noted that the worst-case inductor peak-to-
peak inductor ripple current occurs when the duty cycle
in buck mode is maximum (highest VIN) and in boost
mode when the duty cycle is 50% (VOUT = 2 • VIN). As an
example, if VIN (minimum) = 3.6V and VIN (maximum) =
40V, VOUT = 5V and L = 6.8µH, the peak-to-peak inductor
ripples at the voltage extremes (40V V
IN
for buck and 3.6V
VIN for boost) are:
Buck = 504mA peak-to-peak
Boost = 116mA peak-to-peak
One-half of this inductor ripple current must be added to
the highest expected average inductor current in order to
select the proper saturation current rating for the inductor.
In addition to its influence on power conversion efficiency,
the inductor DC resistance can also impact the maximum
output current capability of the buck-boost converter par-
ticularly at low input voltages. In buck mode, the output
current of the buck-boost converter is primarily limited
by the inductor current reaching the average current limit
LTC3114-1
21
Rev. D
For more information www.analog.com
APPLICATIONS INFORMATION
threshold defined by VC. However, in boost mode, espe-
cially at large step-up ratios, the output current capability
can also be limited by the total resistive losses in the
power stage. These losses include, switch resistances,
inductor DC resistance and PCB trace resistance. Avoid
inductors with a high DC resistance (DCR) as they can
degrade the maximum output current capability from
what is shown in the Typical Performance Characteristics
section and from the Typical Application circuits. As a
guideline, the inductor DCR should be significantly less
than the typical power switch resistance of 250mΩ. The
only exceptions are applications that have a maximum
output current much less than what the LTC3114-1 is
capable of delivering.
Different inductor core materials and styles have an impact
on the size and price of an inductor at any given current
rating. Shielded construction is generally preferred as it
minimizes the chances of interference with other circuitry.
The choice of inductor style depends upon the price, siz-
ing, and EMI requirements of a particular application.
Table1 provides a small sampling of inductors that are
well suited to many LTC3114-1 applications.
Output Capacitor Selection
A low effective series resistance (ESR) output capacitor
should be connected at the output of the buck-boost con-
verter in order to minimize output voltage ripple. Multilayer
ceramic capacitors are an excellent option as they have low
ESR and are available in small footprints. The capacitor value
should be chosen large enough to reduce the output voltage
ripple to acceptable levels. Neglecting the capacitor’s ESR
and ESL (effect series inductance), the peak-to-peak output
voltage ripple can be calculated by the following formula,
where f is the frequency in MHz (1.2MHz for the LTC3114
-1), COUT is the capacitance in µF, tLOW is the switch pin min-
imum low time in us (0.1µs for the LTC3114-1) and ILOAD is
the output current in Amps.
ΔV
P-P(BUCK) =
I
LOAD
t
LOW
COUT
Volts
ΔV
P-P(BOOST) =ILOAD
fCOUT
VOUT – V
IN +tLOWfV
IN
VOUT
⎛
⎝
⎜⎞
⎠
⎟Volts
Examining the previous equations reveal that the output
voltage ripple increases with load current and is gener-
ally higher in boost mode than in buck mode. Note that
these equations only take into account the voltage ripple
that occurs from the inductor current to the output being
discontinuous. They provide a good approximation to the
ripple at any significant load current but underestimate the
output voltage ripple at very light loads where the output
voltage ripple is dominated by the inductor current ripple.
In addition to the output voltage ripple generated across
the output capacitance, there is also output voltage rip-
ple produced across the internal resistance of the output
capacitor. The ESR-generated output voltage ripple is pro-
portional to the series resistance of the output capacitor
and is given by the following expressions where RESR is
Table1. Representative Surface Mount Inductors
PART NUMBER
VALUE
(µH)
DCR
(mΩ)
MAX DC
CURRENT (A)
SIZE (mm)
W × L × H
Coilcraft
LPS6225
LPS6235
MSS1038
D03316P
4.7
6.8
22
15
65
75
70
50
3.2
2.8
3.3
3.0
6.2 × 6.2 × 2.5
6.2 × 6.2 × 3.5
10.2 × 10.5 × 3.8
12.9 × 9.4 × 5.2
Cooper-Bussmann
CD1-150-R
DR1030-100-R
FP3-8R2-R
DR1040-220-R
15
10
8.2
22
50
40
74
54
3.6
3.18
3.4
2.9
10.5 × 10.4 × 4.0
10.3 × 10.5 × 3.0
7.3 × 6.7 × 3.0
10.3 × 10.5 × 4.0
Panasonic
ELLCTV180M
ELLATV100M
18
10
30
23
3.0
3.3
12 × 12 × 4.2
10 × 10 × 4.2
Sumida
CDRH8D28/HP
CDR10D48MNNP
CDRH8D28NP
10
39
4.7
78
105
24.7
3.0
3.0
3.4
8.3 × 8.3 × 3
10.3 × 10.3 × 5
8.3 × 8.3 × 3
Taiyo-Yuden
NR10050T150M
15
46
3.6
9.8 × 9.8 × 5
TOKO
B1047AS-6R8N
B1179BS-150M
892NAS-180M
6.8
15
18
36
56
42
2.9
3.3
3.0
7.6 × 7.6 × 5
10.3 × 10.3 × 4
12.3 × 12.3 × 4.5
Wurth
7447789004
7440650068
744771133
744066150
4.7
6.8
33
15
33
33
49
40
2.9
3.6
2.7
3.2
7.3 × 7.3 × 3.2
10 × 10 × 3
12 × 12 × 6
10 × 10 × 3.8
LTC3114-1
22
Rev. D
For more information www.analog.com
APPLICATIONS INFORMATION
the series resistance of the output capacitor and all other
terms as previously defined.
ΔV
P-P(BUCK) =
I
LOAD
R
ESR
1– tLOWf≅ILOADRESRVolts
ΔV
P-P(BOOST) =ILOADRESRVOUT
V
IN 1– tLOWf
( )
≅ILOADRESR
VOUT
V
IN
⎛
⎝
⎜⎞
⎠
⎟Volts
In most LTC3114-1 applications, an output capacitor
between 10µF and 22µF will work well.
Input Capacitor Selection
The PVIN pin carries the full inductor current and provides
power to internal control circuits in the IC. To minimize
input voltage ripple and ensure proper operation of the IC,
a low ESR bypass capacitor with a value of at least 6.8µF
should be located as close to the pin as possible. The
traces connecting this capacitor to PVIN and the ground
plane should be made as short as possible. The VIN pin
provides power to the LDO regulator and other internal
circuitry. If the PCB trace connecting PVIN to VIN is long, it
is recommended to add an additional small 0.1µF bypass
capacitor near the VIN pin.
When powered through long leads or from a high ESR
power source, a larger value bulk input capacitor may
be required. In such applications, a 47µF to 100µF elec-
trolytic capacitor in parallel with a 1µF ceramic capacitor
generally yields a high performance, low cost solution.
Recommended Input and Output Capacitors
The capacitors used to filter the input and output of the
LTC3114-1 must have low ESR and must be rated to han-
dle the large AC currents generated by the switching con-
verters. This is important to maintain proper functioning of
the IC and to reduce output voltage ripple. There are many
capacitor types that are well suited to these applications
including multilayer ceramic, low ESR tantalum, OS-CON
and POSCAP technologies. In addition, there are certain
types of electrolytic capacitors such as solid aluminum
organic polymer capacitors that are designed for low ESR
and high AC currents and these are also well suited to some
LTC3114-1 applications. Table2 provides a partial listing
of appropriate capacitors to use with the LTC3114-1. The
choice of capacitor technology is primarily dictated by a
trade-off between size, leakage current and cost. In backup
power applications, the input or output capacitor might be
a super or ultra capacitor with a capacitance value mea-
suring in the Farad range. The selection criteria in these
Table2. Representative Bypass and Output Capacitors
MANUFACTURER,
PART NUMBER
VALUE
(µF)
VOLTAGE
(V)
SIZE L × W × H (mm),
TYPE, ESR
AVX
12103D226MAT2A 22 25 3.2 × 2.5 × 2.79
X5R Ceramic
TPME226K050R0075 22 50 7.3 × 4.3 × 4.1
Tantalum, 75mΩ
Kemet
C2220X226K3RACTU 22 25 5.7 × 5.0 × 2.4
X7R Ceramic
A700D226M016ATE030 22 16 7.3 × 4.3 × 2.8
Alum. Polymer, 30mΩ
Murata
GRM32ER71E226KE15L
22 25 3.2 × 2.5 × 2.5
X7R Ceramic
Nichicon
PLV1E121MDL1 82 25 8 × 8 × 12
Alum. Polymer, 25mΩ
Panasonic
ECJ-4YB1E226M 22 25 3.2 × 2.5 × 2.5
X5R Ceramic
Sanyo
25TQC22MV 22 25 7.3 × 4.3 × 3.1
POSCAP, 50mΩ
16TQC100M 100 16 7.3 × 4.3 × 1.9
POSCAP, 45mΩ
25SVPF47M 47 25 6.6 × 6.6 × 5.9
OS-CON, 30mΩ
Taiyo Yuden
UMK325BJ106MM-T 10 50 3.2 × 2.5 × 2.5
X5R Ceramic
TMK325BJ226MM-T 22 25 3.2 × 2.5 × 2.5
X5R Ceramic
TDK
KTJ500B226M55BFT00 22 50 6.0 × 5.3 × 5.5
X7R Ceramic
C5750X7R1H106M 10 50 5.7 × 5.0 × 2.0
X7R Ceramic
CKG57NX5R1E476M 47 25 6.5 × 5.5 × 5.5
X5R Ceramic
Vishay
94SVPD476X0035F12 47 35 10.3 × 10.3 × 12.6
OS-CON, 30mΩ
LTC3114-1
23
Rev. D
For more information www.analog.com
APPLICATIONS INFORMATION
applications are generally similar except that voltage ripple
is generally not a concern. Some capacitors exhibit a high
DC leakage current which may preclude their consideration
for applications that require a very low quiescent current in
Burst Mode operation.
Ceramic capacitors are often utilized in switching con-
verter applications due to their small size, low ESR and
low leakage currents. However, many ceramic capacitors
intended for power applications experience a significant
loss in capacitance from their rated value as the DC bias
voltage on the capacitor increases. It is not uncommon for
a small surface mount capacitor to lose more than 50%
of its rated capacitance when operated near its maximum
rated voltage. This effect is generally reduced as the case
size is increased for the same nominal value capacitor. As
a result, it is often necessary to use a larger value capaci-
tance or a higher voltage rated capacitor than would ordi-
narily be required to actually realize the intended capaci-
tance at the operating voltage of the application. X5R and
X7R dielectric types are recommended as they exhibit
the best performance over the wide operating range and
temperature of the LTC3114-1. To verify that the intended
capacitance is achieved in the application circuit, be sure
to consult the capacitor vendor’s curve of capacitance
versus DC bias voltage.
Programming Custom VIN Turn-On and Turn-Off
Thresholds
With the addition of an external resistor divider connected
to the input voltage as shown in Figure3, the RUN pin
can be used to program the input voltage at which the
LTC3114-1 is enabled and disabled.
For a rising input voltage, the LTC3114-1 is enabled when
V
IN
reaches the threshold given by the following equation,
where R1 and R2 are the values of the resistor divider
resistors specified in kΩ:
VTH(RISING) =1.2 R1+R2
R2
⎛
⎝
⎜⎞
⎠
⎟Volts
Once the IC is enabled, it will remain so until the input
voltage drops below the comparator threshold by the
hysteresis voltage of approximately 100mV, measured
on the RUN pin. Therefore, the amount of hysteresis is
approximately 8.33% of the programmed turn-on thresh-
old level given in the previous equation.
Bootstrapping the LDO Regulator
The high and low side gate drivers are powered through
the PLDO rail, which is generated from the input voltage,
VIN, through an internal linear regulator. In some applica-
tions, especially at high input voltages, the power dissipa-
tion in the linear regulator can become a major contributor
to thermal heating of the IC. The Typical Performance
Characteristics section of this data sheet provides data on
the LDO/PLDO current and resulting power loss versus
VIN and VOUT. A significant performance advantage can
be attained in applications where converter output voltage
(VOUT) is programmed to 5V, if VOUT is used to power
the LDO/PLDO rails. Powering the LDO/PLDO rails in this
manner is referred to as bootstrapping. This can be done
by connecting a Schottky diode from VOUT to LDO/PLDO
as shown in Figure5. With the bootstrap diode installed,
the gate driver currents are supplied by the buck-boost
converter at high efficiency rather than through the inter-
nal linear regulator. The internal linear regulator contains
reverse blocking circuitry that allows LDO/PLDO pins to
be driven slightly above their nominal regulation level with
only a very slight amount of reverse current. Please note
that the bootstrapping supply (either VOUT or a separate
regulator) must be limited to less than 5.7V.
V
OUT
4.7µF
31141 F05
PVOUT
LTC3114-1
LDO
PLDO
Figure5. Bootstrapping PLDO and LDO
Average Output Current Limit Programming
The LTC3114-1 includes an average output current pro-
gramming feature that transforms the LTC3114-1 into
a wide voltage compliance range, high efficiency, con-
stant current source. A resistor from PROG to ground
programs the desired level of average output current up
to 1A. Potential uses include high brightness LED driving
and constant current battery or capacitor charging.
LTC3114-1
24
Rev. D
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APPLICATIONS INFORMATION
A simplified diagram of the average output current pro-
gramming circuitry is shown in the Block Diagram. An
internal sense resistor, RS, and low offset amplifier directly
measure current in the VOUT path and produce a small
fraction of this current out of the PROG pin. Accordingly,
a resistor and filtering capacitor connected from PROG to
ground produce a voltage proportional to average output
current on PROG. An internal transconductance amplifier
compares the PROG voltage to the fixed 1V internal refer-
ence. If the PROG voltage tries to exceed the 1V reference
level, this amplifier will pull down on VC and take com-
mand of the PWM. As described earlier, VC is the current
command voltage, so limiting VC in this manner will also
limit output current. The resulting average output current
is given by the following equation:
IOUT(AVG) ≅25,000 •
1V
RPROG
where: RPROG = 24.9k to 100k.
The largest recommended PROG pin resistor is 100k. Values
of RPROG larger than 100k may latch-off the LTC3114-1 if
VOUT is forced to less than 2V by an external load. This is
generally not an issue for battery charging applications, but
may prevent the charging of very large capacitors. In some
general purpose power supply applications, this latch-off
behavior may be desirable and in these cases, values of
RPROG > 100k are acceptable to use.
The gain of 25,000 is generated internal to the LTC3114-1
and is factory trimmed to provide the best accuracy
at 500mA of output current. The accuracy of the pro-
grammed output current is best at the high end of the
range as the residual internal current sense amplifier off-
set becomes a smaller percentage of the total current
sense signal amplitude with increasing current. The pro-
vided electrical specifications define the PROG pin current
accuracy over a range of output currents.
Selecting the capacitor, CPROG, to put in parallel with
RPROG is a trade-off between response time, output cur-
rent ripple and interaction with the normal output voltage
control loop. In general, if speed is not a concern as is the
case for most current sourcing applications, then CPROG
should be made at least 3 times higher than the voltage
error amplifier compensation capacitor, C
P1
, described
in the Compensation section of this data sheet. This will
ensure minimal to no interaction when the transition
occurs between voltage regulation mode and output cur-
rent regulation mode.
In current sourcing applications, the maximum output
compliance voltage of the LTC3114-1 is set by the voltage
error amplifier dividers resistors as it is for standard
voltage regulation applications. For LED drivIng appli-
cations, select the VOUT divider resistors for a clamping
level 1V to 2V higher than the expected forward voltage
drop of the LED string.
The average output current cir-
cuitry can also be used to monitor, rather than control the
output current. To do this, select an RPROG value that will
limit the voltage on the PROG pin to 0.8V or less at the
highest output current expected in the application.
Connect a 20k resistor and 33nF capacitor from PROG to
ground if the function is not going to be used to provide a
higher level of protection against inadvertent short-circuit
conditions on VOUT.
Compensation of the Buck-Boost Converter
The LTC3114-1 utilizes average current mode control to
regulate the output voltage. Average current mode control
has two loops that require frequency compensation, the
inner average current loop and the outer voltage loop.
The compensation for the inner average current loop is
fixed within the LTC3114-1 in order to provide the highest
possible bandwidth over the wide operating range of the
LTC3114-1. Therefore, the only control loop that requires
compensation design is the outer voltage loop. As will be
shown, compensation design of the outer loop is similar
to the techniques used in well known peak current mode
control devices.
The LTC3114-1 utilizing average current mode control can
be conceptualized in its simplest form as a voltage-con-
trolled current source (VCCS), driving the output load
formed primarily by RLOAD and COUT, as shown in Figure6.
The error amplifier output (VC), provides the command
input to the V
CCS
. The full-scale range of VC is 0.865V
(135mV to 1V). With a full-scale command on VC, the
LTC3114-1 buck-boost converter will generate an average
1.7A of inductor current (typical) from the converterfor a
LTC3114-1
25
Rev. D
For more information www.analog.com
APPLICATIONS INFORMATION
transconductance gain of 1.97A/V. Similar to peak current
mode control, the inner average current mode control
loop effectively turns the inductor into a current source
over the frequency range of interest, resulting in a fre-
quency response from the power stage that exhibits a
single pole (–20dB/decade) roll off. The output capacitor
(C
OUT
) and load resistance (R
LOAD
) form the normally
dominant low frequency pole and the effective series
resistance of the output capacitor and its capacitance
form a zero, usually at a high enough frequency to be
ignored. A potentially troublesome right half plane zero
(RHPZ) is also encountered if the LTC3114-1 is operated
in boost mode. The RHPZ causes an increase in gain, like
a zero, but a decrease in phase, like a pole. This will ulti-
mately limit the maximum converter bandwidth that can
be achieved with the LTC3114-1. The RHPZ is not present
when operating in buck mode. The overall open loop gain
at DC is the product of the following terms:
Voltage Error Amp Gain:
gm • RO = 120µs • 3.6M = 432V/V (not adjustable)
Voltage Divider Gain:
V
FB
VOUT
=
1V
VOUT
(determined by the application, VFB is the reference
voltage for the voltage error amplifier)
Current Loop Transconductance:
GC=
1.7A
0.865V
=1.97A/V
(not adjustable)
Load Resistance (RLOAD) (determined by the application)
The frequency dependent terms that affect the loop gain
include:
Output Load Pole(P1):
1
2π•R
LOAD
• C
OUT
(application dependent)
Error Amplifier Compensation (2 Poles and 1 Zero):
These are the design variables available
Right Half Plane Zero (RHPZ): boost mode only (deter-
mined by maximum load, VIN, VOUT and inductor)
Current Amplifier Compensation Components (Fixed
Internal to the LTC3114-1)
The internal current amplifier and inner current loop
have a much higher bandwidth than the overall loop,
however, unlike an ideal VCCS with a flat gain versus
frequency characteristic, the inner loop exhibits gain
peaking in the range of approximately 2kHz to 20kHz
that is an artifact of the fixed current amplifier compen
-
sation. This gain peaking has the effect of pushing out
the overall loop crossover frequency, while
providing some phase margin boost as well. As long as
there is sufficient margin between the loop crossover
frequency and the worst-case RHPZ frequency, then
stable operation over all conditions is relatively easy
to achieve.
The design parameters for compensation design will
focus on the series resistor and capacitors connected
from VC to ground (RZ, CP1 and CP2). The general goal
is to provide a phase boost using the compensation net-
work zero in order to maximize the bandwidth and phase
margin of the converter. Being a buck-boost converter,
the target loop crossover frequency for the compensation
design will be dictated by the highest boost ratio and load
current that is expected as this will result in the lowest
RHPZ frequency. An illustrative example is provided next
that will derive the compensation components for a typical
LTC3114-1 application.
Compensation Example
This section will demonstrate how to derive and select the
compensation components for a typical LTC3114-1 appli-
cation. Designing compensation for other applications
+
–
gm1V
1V
g
m = 1.7A/0.865V
+
–
FB
VOLTAGE
ERROR
AMP
VOLTAGE
CONTROLLED
CURRENT
SOURCE
VC
GND RZ
RTOP
1.7M
RBOT
100k
RCOSER
0.01Ω
RLOAD
18Ω
CP1
COUT
22µF
VOUT
CP2
31141 F06
Figure6. Simplified Representation of Average
Current Mode Control Loop
LTC3114-1
26
Rev. D
For more information www.analog.com
APPLICATIONS INFORMATION
is simply a matter of substituting different values in the
equations provided and reviewing the Bode plots, mak-
ing minor adjustments as needed. Since the compen-
sation design procedure uses a simplified model of the
LTC3114-1, the results from the following compensation
design should always be verified with time domain step
load response tests to validate the effectiveness of the
compensation design. It is assumed that the value and
type of output capacitor will be selected based on the
guidelines provided elsewhere in this data sheet. Particular
attention needs to be paid to the voltage bias effect on
ceramic capacitors typically used for output bypassing.
Similarly, it is assumed that the inductor value and current
rating has been selected as well based on the application
requirements.
Example Application Details:
VIN = 9V to 36V
VOUT = 12V
Maximum IOUT (boost mode) = 700mA, RLOAD (min)
= 12V/0.7A = 17.1Ω
Maximum IOUT (buck mode) = 1A, RLOAD (min) = 12Ω
COUT = 44µF
L = 10µH
Since this application includes boost mode operation, the
first step is to calculate the worst-case RHPZ frequency
as this will dictate the maximum loop bandwidth for the
converter:
RHPZ(f) =
V
IN2
•R
LOAD
V
OUT
2• 2π•L(Hz)
substituting the values mentioned earlier yields:
RHPZ(f) =9V2• 17.1Ω
12V2• 2π• 10µH
=153.1kHz
In order to account for internal IC component variations, it
is good practice to set the converter bandwidth or cross-
over frequency at least three times lower than the RHPZ
frequency to avoid excessive phase loss from the RHPZ
when operating in boost mode. In some instances such
as higher output voltage applications, an even greater
separation between the loop crossover frequency and
the RHPZ frequency may be necessary. In this example
design, we’ll plan to achieve a loop bandwidth (fCC) of
29kHz or approximately one-fifth the RHPZ frequency.
The system poles and zeros are as follows:
Output Load Pole (P1) =
1
2π•R
LOAD
• C
OUT
;
buck mode, where RLOAD = output resistance.
In boost mode this equation is slightly different:
2
2π•RLOAD • COUT
( )
′,
but with the reduced output current capability in boost
(higher RLOAD), the load pole location is about the
same.
Error Amp Pole (P2) =
1
2π•REA • CC
( )
;
this pole is very close to DC, REA = error amp output
resistance, which is approximately 3.6MΩ. It has no
impact on the compensation design, but is included
here for completeness.
Compensation Zero (Z1) =
1
2π•RZ• CP1
( )
;
RZ and CP1 are the error amp compensation compo-
nents that will be selected.
Ignoring very high frequency output capacitor ESR zero
and secondary high frequency error amp pole, the system
has two poles and one zero. The error amp pole (P2) is
always near DC and we have little influence on it. The
output load pole (P1) will move depending on buck-boost
converter load resistance. The highest frequency for P1,
the output load pole, is at maximum load current (min-
imum RLOAD). If we design the error amp zero (Z1) fre-
quency so that it coincides with P1(max), then we will get
the maximum phase benefit from the compensation net-
work at full load and enough phase boost at lighter loads
for stable operation and a single pole response where the
loop crosses zero dB.
LTC3114-1
27
Rev. D
For more information www.analog.com
APPLICATIONS INFORMATION
Assuming the error amp zero is designed as just described,
at frequencies above P2 (and Z1), the closed-loop gain of
our system simplifies to:
GCL =
G
CS
•R
LOAD
• g
m
•R
Z
VOUT
where:
GCS is the inner current loop closed-loop transconduc-
tance = 1.97A/V
RLOAD is the minimum load resistance in ohms
gm is the transconductance of the error amplifier, 120µS
R
Z
is the compensation zero setting resistor (one of
our design variables)
VOUT is the output voltage
Our desired closed-loop frequency (fCC) defined earlier is
29kHz. Assuming that we have a single pole response in
our system, we can express the ratio of the closed-loop
crossover frequency to fP1 in the buck mode of operation
as follows:
f
CC
fP1
=
G
CS
•R
LOAD
• g
m
•R
z
VO
We can now calculate RZ by rearranging the previous
equation:
RZ=
f
CC
• V
OUT
• 2π• C
OUT
GCS • gm
It’s important to note that the value of RZ is proportional
to the overall crossover frequency, fCC. If we later want to
adjust fCC lower, for example, RZ can be lowered in value
and CP1 increased proportionally to keep the compensa-
tion zero at the same frequency.
As mentioned previously, we will place the zero at fre-
quency P1, yielding:
CP1 =
1
2π•R
Z
• f
P1
or more simply,
R
LOAD
• C
OUT
R
Z
where Rl is the minimum load resistance in buck mode,
12Ω in this example.
Quickly substituting our values in the above equations
yields:
RZ = 407k, CP1 = 1.3nF,
but please continue reading as this is not the final answer.
If the inner current loop were an ideal VCCS, then the pre-
viously derived compensation would be sufficient to stabi-
lize the converter. However, the inner current loop utilizes
an operational amplifier with an integral compensation
network, which contributes an additional zero and pole in
the power stage response, the gain peaking, as described
previously. The effect of the additional zero/pole pair
pushes out fCC, our crossover frequency, beyond what
was predicted by the previous calculations. A simplified
approach to calculating our compensation components
then is to re-use the previous equations but scale fCC, the
cross over frequency, by a scaling factor (α), which will
account for the gain boost present in the system:
fCC′=
f
CC
3
•α
( )
, where α = 0.42
So, in our example, this results in:
fCC′=
29kHz
3
• 0.42
( )
= 4.06kHz
Using the new value of fCC′ in the previous equations for
RZ and CC yields:
RZ=
4.06kHz • 12V • 2π• 44µF
1.97A
V•120µA
V
RZ=56.9kΩ, use 56.2kΩ
CP1 =12Ω• 44µF
56.2k
C
P1
=9.4nF, use 10nF
CP2 is usually chosen to be a small value around 10pF as
it is meant to filter out high frequency switching frequency
related components.
Keep in mind that this analysis assumes that the zero pro-
vided by the output capacitor and its ESR is at a frequency
much higher than fCC.
LTC3114-1
28
Rev. D
For more information www.analog.com
TYPICAL APPLICATIONS
9V to 36V VIN to 12V VOUT Regulator
10µH
SW1 SW2
GND PGND
BST1
68nF
4.7µF
10nF
10pF
33nF 56.2k
20k 182k
INDUCTOR: WURTH 744 065 100
31141 TA02a
2M
68nF
BST2
VIN PVOUT
PVIN LDO
PLDO
FB
RUN
10µF
VIN
9V TO 36V
VCPROG
MODE
44µF
VOUT
12V AT 1A, VIN > 12V
12V AT 0.7A, VIN
> 9V
LTC3114-1
Efficiency vs Input Voltage Load Step Response
INPUT VOLTAGE (V)
8
EFFICIENCY (%)
87
93
94
95
16 24 28 32
31141 TA02b
91
89
86
92
85
90
88
12 20 36 40
ILOAD = 350mA
LOAD CURRENT
500mA/DIV
VOUT
200mV/DIV
1ms/DIV 31141 TA02c
VIN = 15V
100mA to 700mA
LTC3114-1
29
Rev. D
For more information www.analog.com
TYPICAL APPLICATIONS
6V to 40V VIN to 24V VOUT Regulator
Efficiency vs Load Current 12V VIN Synchronous Boost Operation with Inrush Current
Limiting at Start-Up and Output Disconnect in Shutdown
15µH
SW1 SW2
GND PGND
BST1
68nF
4.7µF
10nF
10pF
33nF
INDUCTOR: WURTH 744 066 150
39.2k
20k 86.6k
31141 TA03a
2M
68nF
BST2
VIN PVOUT
PVIN LDO
PLDO
FB
RUN
10µF
VIN
6V TO 40V
VCPROG
MODE
22µF
VOUT
24V AT 1A, VIN > 24V
24V AT 0.2A, VIN
= 6V
LTC3114-1
LOAD CURRENT (mA)
0.1
60
EFFICIENCY (%)
65
70
75
80
1 10 1000100
31141 TA03b
55
50
45
40
85
95
90 VIN = 12V
INPUT CURRENT
1A/DIV
RUN PIN
2V/DIV
VOUT
10V/DIV
10ms/DIV 31141 TA03c
LTC3114-1
30
Rev. D
For more information www.analog.com
Constant Current/Constant Voltage Lead-Acid Battery Charger
6.8µH
SW1 SW2
GND PGND
BST1
68nF
D1
4.7µF
10nF
56.2k 164k
NTC: VISHAY NTCS0603E3683 HT 68k NOMINAL AT 25°C
INDUCTOR: COILCRAFT MSS1048-682NL
D1: ON SEMI MBRS260T3G
TEMPERATURE
COMPENSATION
1A CONSTANT CHARGING
CURRENT WHEN BELOW
FLOAT LEVEL
220k
NTC
68k
31141 TA04a
2M
24.9k33nF
68nF
BST2
VIN PVOUT
PVIN LDO
PLDO
FB
RUN
10µF
VIN
2.7V TO 40V
VCPROG
MODE
44µF
6-CELL
LEAD-ACID
BATTERY
LTC3114-1
+
–30°C
0°C
25°C
50°C
14.5V
14.03V
13.8V
13.48V
VBATT FLOAT LEVEL
TYPICAL APPLICATIONS
Constant Current High Brightness LED Driver
Efficiency vs Input Voltage, 350mA Drive Current
15µH
SW1 SW2
GND PGND
BST1
68nF
D1
4.7µF
0.47µF
31.6k
71.5k
31141 TA05a
1M
R1
71.5k
3.3nF
68nF
BST2
VIN PVOUT
PVIN LDO
PLDO
FB
RUN
10µF
VIN
9V TO 40V
500mA: R1 = 49.9k
350mA: R1 = 71.5k
ADJUST R1 FOR DIMMING
VCPROG
MODE
44µF
CONSTANT CURRENT DOWN
TO 2V
VOLTAGE DIVIDER LIMITS VOUT
TO 15V IN CASE OF OPEN LED
500mA CONSTANT CURRENT, VIN > 11V
350mA CONSTANT CURRENT, VIN > 9V
LTC3114-1
INDUCTOR: WURTH 744 066 150
D1: ON SEMI MBRS260T3G
INPUT VOLTAGE (V)
8
85
EFFICIENCY (%)
86
88
89
90
95
92
16 24 28
31141 TA05b
87
93
94
91
12 20 32 36 40
LTC3114-1
31
Rev. D
For more information www.analog.com
PACKAGE DESCRIPTION
3.00 ±0.10
(2 SIDES)
5.00 ±0.10
(2 SIDES)
NOTE:
1. DRAWING PROPOSED TO BE MADE VARIATION OF VERSION (WJED-1) IN JEDEC
PACKAGE OUTLINE MO-229
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE
TOP AND BOTTOM OF PACKAGE
0.40 ±0.10
BOTTOM VIEW—EXPOSED PAD
1.65 ±0.10
(2 SIDES)
0.75 ±0.05
R = 0.115
TYP
R = 0.20
TYP
4.40 ±0.10
(2 SIDES)
18
169
PIN 1
TOP MARK
(SEE NOTE 6)
0.200 REF
0.00 – 0.05
(DHC16) DFN 1103
0.25 ±0.05
PIN 1
NOTCH
0.50 BSC
4.40 ±0.05
(2 SIDES)
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
1.65 ±0.05
(2 SIDES)2.20 ±0.05
0.50 BSC
0.65 ±0.05
3.50 ±0.05
PACKAGE
OUTLINE
0.25 ± 0.05
DHC Package
16-Lead Plastic DFN (5mm × 3mm)
(Reference LTC DWG # 05-08-1706 Rev Ø)
LTC3114-1
32
Rev. D
For more information www.analog.com
PACKAGE DESCRIPTION
FE16 (BB) TSSOP REV L 1216
0.09 – 0.20
(.0035 – .0079)
0° – 8°
0.25
REF
0.50 – 0.75
(.020 – .030)
4.30 – 4.50*
(.169 – .177)
1 3 4 5678
10 9
4.90 – 5.10*
(.193 – .201)
16 1514 13 12 11
1.10
(.0433)
MAX
0.05 – 0.15
(.002 – .006)
0.65
(.0256)
BSC
2.94 ±0.15
(.116 ±.006)
0.195 – 0.30
(.0077 – .0118)
TYP
2
RECOMMENDED SOLDER PAD LAYOUT
0.45 ±0.05
0.65 BSC
4.50 ±0.10
6.60 ±0.10
1.05 ±0.10
2.94
(.116)
3.05
(.120)
3.70 ±0.15
(.146 ±.006)
3.70
(.146)
4.70
(.185)
MILLIMETERS
(INCHES)
NOTE:
1. CONTROLLING DIMENSION: MILLIMETERS
2. DIMENSIONS ARE IN
3. DRAWING NOT TO SCALE
4. RECOMMENDED MINIMUM PCB METAL SIZE
FOR EXPOSED PAD ATTACHMENT
SEE NOTE 4
NOTE 5
NOTE 5
6.40 ±0.15
(.252 ±.006)
FE Package
16-Lead Plastic TSSOP (4.4mm)
(Reference LTC DWG # 05-08-1663 Rev L)
Exposed Pad Variation BB
5. BOTTOM EXPOSED PADDLE MAY HAVE METAL PROTRUSION
IN THIS AREA. THIS REGION MUST BE FREE OF ANY EXPOSED
TRACES OR VIAS ON PCB LAYOUT
*DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.150mm (.006") PER SIDE
DETAIL A
DETAIL A IS THE PART OF THE
LEAD FRAME FEATURE FOR
REFERENCE ONLY
NO MEASUREMENT PURPOSE
0.56
(.022)
REF
0.53
(.021)
REF
DETAIL A
LTC3114-1
33
Rev. D
For more information www.analog.com
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog
Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications
subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
REVISION HISTORY
REV DATE DESCRIPTION PAGE NUMBER
A 11/14 Corrected Part Marking Table for TSSOP Package Option. 2
B 03/16 Clarified Min VIN on Electrical Characteristics.
Clarified FB (Pin 7) description, BST2 (Pin 12) and BST1 (Pin 13) description.
Added High Transient Input Voltage Applications section.
Clarified Average Output Current Limit Programming section.
Added optional diode to Typical Applications.
Added LTC3118 to Related Parts.
3
9
17
23
17-30
34
C 07/19 Add AEC-Q100 Qualification and Orderable Part Numbers 1, 3
D 05/20 Added patent number to end of paragraph description.
Added #W_FE temp grades to part list (I, E).
Schottky diode recommendation to PVOUT.
Striked out “High transient Input Voltage Applications”.
Removed D1 from schematic.
Removed D1 part number description from schematic.
Removed D1 from schematic.
Removed D1 part number description from schematic.
Removed D2 from schematics.
Removed D2 part number description from schematics.
Removed D1 from schematic.
Removed D1 part number description from schematic.
1
3
10
18
28
28
29
29
30
30
34
34
LTC3114-1
34
Rev. D
For more information www.analog.com
ANALOG DEVICES, INC. 2020
www.analog.com
05/20
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27.4k
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31141 TA06
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INDUCTOR: WURTH 744 065 0068