DATA SHEET
ICS879S216AKI-02 REVISION A APRIL 8, 2011 1 ©2011 Integrated Device Technology, Inc.
2:2, Differential-to-LVPECL/LVDS Divider ICS879S216I-02
Q0
nQ0
Q1
nQ1
Pullup/Pulldown
Pulldown
Pulldown
Pullup/Pulldown
Pulldown
Pullup
Pullup
PCLK0
CLK_SEL
SEL_OUT
nPCLK0
PCLK1
nPCLK1
F_SEL[1:0] 2
0
1
00 ÷2,
01 ÷4,
10 ÷8,
11 ÷16 (default)
N
7 8 9 10 11 12
22 23 24 21 20 19
1
2
3
4
5
6
15
16
17
18
14
13
CLK_SEL
PCLK0
nPCLK0
PCLK1
nPCLK1
SEL_OUT
VCC
nc
nc
nc
nc
VEE
VCC
VEE
VCC_TAP
nc
F_SEL1
F_SEL0
nc
VEE
Q0
nQ0
Q1
nQ1
General Description
The ICS879S216I-02 is a Differential-to-LVPECL/ LVDS Clock
Divider which can operate up to 2.5GHz. ICS879S216I-02 has 2
selectable differential clock inputs. The fully differential architecture
and low propagation delay make it ideal for use in clock distribution
circuits. ICS879S216I-02 can divide the input clock by ÷2, ÷4, ÷8
and ÷16. Table 4A lists all the available output dividers.
Table 1A. VCC_TAP Function Table
Features
•High speed 2:2 differential divider
•Two differential LVPECL or LVDS output pairs
•Four selectable divide combinations
•PCLKx can accept the following input levels: LVPECL, LVDS, CML
•Maximum input frequency: 2.5GHz
•Propagation delay: 0.8ns (minimum), 1.6ns (maximum)
•Output Skew: 25ps (maximum)
•Full 3.3V or 2.5V supply modes
•-40°C to 85°C ambient operating temperature
•Available in lead-free (RoHS 5) package
Table 1B. SEL_OUT Function Table
Outputs
Output Level Supply VCC_TAP
Q[1:0], nQ[1:0]
LVPECL 2.5V VCC
LVPECL 3.3V VCC
LVDS 2.5V VCC
LVDS 3.3V Float
Input Outputs
SEL_OUT Q[1:0], nQ[1:0]
1 LVPECL (default)
0LVDS
ICS879S216I-02
24-Lead VFQFN
4mm x 4mm x 0.95mm package body
K Package
Top View
Pin Assignment
Block Diagram
ICS879S216I-02 Data Sheet 2:2, DIFFERENTIAL-TO-LVPECL/LVDS DIVIDER
ICS879S216AKI-02 REVISION A APRIL 8, 2011 2 ©2011 Integrated Device Technology, Inc.
Table 2. Pin Descriptions
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 3. Pin Characteristics
Function Tables
Table 4A. Clock Input Function Table Table 4B. CLK_SEL Function Table
NOTE: CLK_SEL is an asynchronous control.
Number Name Type Description
1 CLK_SEL Input Pulldown Clock select input. See Table 4B. LVCMOS/LVTTL interface levels.
2 PCLK0 Input Pulldown Non-inverting differential LVPECL clock input.
3 nPCLK0 Input Pullup/
Pulldown Inverting differential LVPECL clock input.
4 PCLK1 Input Pulldown Non-inverting differential LVPECL clock input.
5 nPCLK1 Input Pullup/
Pulldown Inverting differential LVPECL clock input.
6 SEL_OUT Input Pullup Select pin. See Table 1B. LVCMOS/LVTTL interface levels.
7, 18 VCC Power Power supply pins.
8V
CC_TAP Power Power supply pin. See Table 1A.
9, 13, 23 VEE Power Negative supply pins.
10, 14. 15,
16, 17, 24 nc Unused No connect.
11,
12
F_SEL1,
F_SEL0 Input Pullup Clock select inputs. See Table 4A. LVCMOS / LVTTL interface levels.
19, 20 nQ1, Q1 Output Differential output pair. LVPECL or LVDS interface levels.
21, 22 nQ0, Q0 Output Differential output pair. LVPECL or LVDS interface levels.
Symbol Parameter Test Conditions Minimum Typical Maximum Units
CIN Input Capacitance 2pF
RPULLUP Input Pullup Resistor 51 kΩ
RPULLDOWN Input Pulldown Resistor 51 kΩ
Input
DivideF_SEL1 F_SEL0
00 2
01 4
10 8
1 1 16 (default)
Inputs
CLK_SEL PCLK[0:1], nPCLK[0:1]
0 PCLK0, nPCLK0 (default)
1 PCLK1, nPCLK1
ICS879S216I-02 Data Sheet 2:2, DIFFERENTIAL-TO-LVPECL/LVDS DIVIDER
ICS879S216AKI-02 REVISION A APRIL 8, 2011 3 ©2011 Integrated Device Technology, Inc.
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device.
These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond
those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect product reliability.
DC Electrical Characteristics
Table 5A. LVPECL Power Supply DC Characteristics, VCC = VCC_TAP = 3.3V ± 5%, VEE = 0V, TA = -40°C to 85°C
Table 5B. LVPECL Power Supply DC Characteristics, VCC = VCC_TAP = 2.5V ± 5%, VEE = 0V, TA = -40°C to 85°C
Table 5C. LVDS Power Supply DC Characteristics, VCC = 3.3V ± 5%, VCC_TAP = Float, VEE = 0V, TA = -40°C to 85°C
Table 5D. LVDS Power Supply DC Characteristics, VCC = VCC_TAP = 2.5V ± 5%, VEE = 0V, TA = -40°C to 85°C
Item Rating
Supply Voltage, VCC 4.6V
Inputs, VI-0.5V to VCC + 0.5V
Outputs, IO (LVPECL)
Continuous Current
Surge Current
Outputs, IO (LVDS)
Continuos Current
Surge Current
50mA
100mA
10mA
15mA
Package Thermal Impedance, θJA 49.5°C/W (0 mps)
Storage Temperature, TSTG -65°C to 150°C
Symbol Parameter Test Conditions Minimum Typical Maximum Units
VCC Power Supply Voltage 3.135 3.3 3.465 V
VCC_TAP Power Supply Voltage 3.135 3.3 3.465 V
IEE Power Supply Current 65 mA
Symbol Parameter Test Conditions Minimum Typical Maximum Units
VCC Power Supply Voltage 2.375 2.5 2.625 V
VCC_TAP Power Supply Voltage 2.375 2.5 2.625 V
IEE Power Supply Current 60 mA
Symbol Parameter Test Conditions Minimum Typical Maximum Units
VCC Positive Supply Voltage 3.135 3.3 3.465 V
IEE Power Supply Current 95 mA
Symbol Parameter Test Conditions Minimum Typical Maximum Units
VCC Power Supply Voltage 2.375 2.5 2.625 V
VCC_TAP Power Supply Voltage 2.375 2.5 2.625 V
IEE Power Supply Current 90 mA
ICS879S216I-02 Data Sheet 2:2, DIFFERENTIAL-TO-LVPECL/LVDS DIVIDER
ICS879S216AKI-02 REVISION A APRIL 8, 2011 4 ©2011 Integrated Device Technology, Inc.
Table 5E. LVCMOS/LVTTL DC Characteristics, VCC = VCC_TAP = 3.3V ± 5% or 2.5V ± 5%, VEE = 0V, TA = -40°C to 85°C
Table 5F. LVPECL DC Characteristics, VCC = VCC_TAP = 3.3V ± 5% or 2.5V ± 5%, VEE = 0V, TA = -40°C to 85°C
NOTE 1: VIL should not be less than -0.3V.
NOTE 2: Common mode input voltage is defined as VIH.
NOTE 3: Outputs terminated with 50Ω to VCC – 2V.
Table 5G. LVDS DC Characteristics, VCC = 3.3V ± 5%, VCC_TAP = Float, VEE = 0V, TA = -40°C to 85°C
Table 5H. LVDS DC Characteristics, VCC = VCC_TAP = 2.5V ± 5%, VEE = 0V, TA = -40°C to 85°C
Symbol Parameter Test Conditions Minimum Typical Maximum Units
VIH Input High Voltage VCC = 3.465V 2.2 VCC + 0.3 V
VCC = 2.625V 1.7 VCC + 0.3 V
VIL Input Low Voltage VCC = 3.465V -0.3 0.8 V
VCC = 2.625V -0.3 0.7 V
IIH
Input
High Current
CLK_SEL VCC = VIN = 3.465V or 2.625V 150 µA
F_SEL[1:0],
SEL_OUT VCC = VIN = 3.465V or 2.625V 10 µA
IIL
Input
Low Current
CLK_SEL VCC = 3.465V or 2.625V, VIN = 0V -10 µA
F_SEL[1:0],
SEL_OUT VCC = 3.465V or 2.625V, VIN = 0V -150 µA
Symbol Parameter Test Conditions Minimum Typical Maximum Units
IIH Input High Current PCLK0, nPCLK0,
PCLK1, nPCLK1 VCC = VIN = 3.465V or 2.625V 150 µA
IIL Input Low Current
PCLK0, PCLK1 VCC = 3.465V or 2.625V -10 µA
nPCLK0, nPCLK1 VCC = 3.465V or 2.625V,
VIN = 0V -150 µA
VPP Peak-to-Peak Voltage; NOTE 1 0.15 1.3 V
VCMR Common Mode Input Voltage; NOTE 1, 2 VEE + 0.5 VCC – 0.85 V
VOH Output High Voltage; NOTE 3 VCC – 1.4 VCC – 0.8 V
VOL Output Low Voltage; NOTE 3 VCC – 2.0 VCC – 1.6 V
VSWING Peak-to-Peak Output Voltage Swing 0.6 1.0 V
Symbol Parameter Test Conditions Minimum Typical Maximum Units
VOD Differential Output Voltage SEL_OUT = 0 247 454 mV
∆VOD VOD Magnitude Change SEL_OUT = 0 50 mV
VOS Offset Voltage SEL_OUT = 0 1.125 1.375 V
∆VOS VOS Magnitude Change SEL_OUT = 0 50 mV
Symbol Parameter Test Conditions Minimum Typical Maximum Units
VOD Differential Output Voltage SEL_OUT = 0 247 454 mV
∆VOD VOD Magnitude Change SEL_OUT = 0 50 mV
VOS Offset Voltage SEL_OUT = 0 1.1 1.375 V
∆VOS VOS Magnitude Change SEL_OUT = 0 50 mV
ICS879S216I-02 Data Sheet 2:2, DIFFERENTIAL-TO-LVPECL/LVDS DIVIDER
ICS879S216AKI-02 REVISION A APRIL 8, 2011 5 ©2011 Integrated Device Technology, Inc.
AC Electrical Characteristics
Table 6A. LVPECL AC Characteristics, VCC = VCC_TAP = 3.3V ± 5%, VEE = 0V, TA = -40°C to 85°C
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium
has been reached under these conditions.
NOTE 1: Measured from the differential input crossing point to the differential output crossing point.
NOTE 2: This parameter is defined according with JEDEC Standard 65.
NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltage, same temperature, same frequency and
with equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points.
NOTE 4: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the differential output
crossing point.
NOTE 5: Q, nQ outputs measured differentially. See MUX Isolation diagram in the Parameter Measurement Information Section.
Table 6B. LVPECL AC Characteristics, VCC = VCC_TAP = 2.5V ± 5%, VEE = 0V, TA = -40°C to 85°C
For NOTES, see Table 6A above.
Symbol Parameter Test Conditions Minimum Typical Maximum Units
fIN Input Frequency 2.5 GHz
fOUT Output Frequency
F_SEL[1:0] = 00 1.25 GHz
F_SEL[1:0] = 01 625 MHz
F_SEL[1:0] = 10 312.5 MHz
F_SEL[1:0] = 11 156.25 MHz
tpLH
Propagation Delay, Low-to-High;
NOTE 1 0.8 1.6 ns
tsk(i) Input Skew 60 ps
tsk(o) Output Skew; NOTE 2, 3 25 ps
tsk(pp) Part-to-Part Skew; NOTE 2; 4 650 ps
tR / tFOutput Rise/Fall Time 20% to 80% 90 250 ps
odc Output Duty Cycle 47 53 %
MUXISOLATION MUX Isolation; NOTE 5 >100 dB
Symbol Parameter Test Conditions Minimum Typical Maximum Units
fIN Input Frequency 2.5 GHz
fOUT Output Frequency
F_SEL[1:0] = 00 1.25 GHz
F_SEL[1:0] = 01 625 MHz
F_SEL[1:0] = 10 312.5 MHz
F_SEL[1:0] = 11 156.25 MHz
tpLH
Propagation Delay, Low-to-High;
NOTE 1 0.8 1.6 ns
tsk(i) Input Skew 60 ps
tsk(o) Output Skew; NOTE 2, 3 25 ps
tsk(pp) Part-to-Part Skew; NOTE 2; 4 650 ps
tR / tFOutput Rise/Fall Time 20% to 80% 90 250 ps
odc Output Duty Cycle 47 53 %
MUXISOLATION MUX Isolation >100 dB
ICS879S216I-02 Data Sheet 2:2, DIFFERENTIAL-TO-LVPECL/LVDS DIVIDER
ICS879S216AKI-02 REVISION A APRIL 8, 2011 6 ©2011 Integrated Device Technology, Inc.
Table 6C. LVDS AC Characteristics, VCC = 3.3V ± 5%, VCC_TAP = Float, VEE = 0V, TA = -40°C to 85°C
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium
has been reached under these conditions.
NOTE 1: Measured from the differential input crossing point to the differential output crossing point.
NOTE 2: This parameter is defined according with JEDEC Standard 65.
NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltage, same temperature, same frequency and
with equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points.
NOTE 4: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the differential output
crossing point.
NOTE 5: Q, nQ outputs measured differentially. See MUX Isolation diagram in the Parameter Measurement Information Section..
Table 6D. LVDS AC Characteristics, VCC = VCC_TAP = 2.5V ± 5%, VEE = 0V, TA = -40°C to 85°C
For NOTES, see Table 6C above.
Symbol Parameter Test Conditions Minimum Typical Maximum Units
fIN Input Frequency 2.5 GHz
fOUT Output Frequency
F_SEL[1:0] = 00 1.25 GHz
F_SEL[1:0] = 01 625 MHz
F_SEL[1:0] = 10 312.5 MHz
F_SEL[1:0] = 11 156.25 MHz
tpLH
Propagation Delay, Low-to-High;
NOTE 1 0.8 1.6 ns
tsk(i) Input Skew 75 ps
tsk(o) Output Skew; NOTE 2, 3 25 ps
tsk(pp) Part-to-Part Skew; NOTE 2; 4 650 ps
tR / tFOutput Rise/Fall Time 20% to 80% 70 250 ps
odc Output Duty Cycle 46 54 %
MUXISOLATION MUX Isolation >100 dB
Symbol Parameter Test Conditions Minimum Typical Maximum Units
fIN Input Frequency 2.5 GHz
fOUT Output Frequency
F_SEL[1:0] = 00 1.25 GHz
F_SEL[1:0] = 01 625 MHz
F_SEL[1:0] = 10 312.5 MHz
F_SEL[1:0] = 11 156.25 MHz
tpLH
Propagation Delay, Low-to-High;
NOTE 1 0.8 1.6 ns
tsk(i) Input Skew 75 ps
tsk(o) Output Skew; NOTE 2, 3 25 ps
tsk(pp) Part-to-Part Skew; NOTE 2; 4 650 ps
tR / tFOutput Rise/Fall Time 20% to 80% 70 250 ps
odc Output Duty Cycle 46 54 %
MUXISOLATION MUX Isolation >100 dB
ICS879S216I-02 Data Sheet 2:2, DIFFERENTIAL-TO-LVPECL/LVDS DIVIDER
ICS879S216AKI-02 REVISION A APRIL 8, 2011 7 ©2011 Integrated Device Technology, Inc.
Parameter Measurement Information
3.3V LVPECL Output Load AC Test Circuit
3.3V LVDS Output Load AC Test Circuit
Differential Input Level
2.5V LVPECL Output Load AC Test Circuit
2.5V LVDS Output Load AC Test Circuit
Propagation Delay
SCOPE
Qx
nQx
LVPECL
VEE
VCC,
2V
-1.3V±0.165V
VCC_TAP
SCOPE
Qx
nQx
LVDS
3.3V±5%
POWER SUPPLY
+–
Float GND
VCC
VCC_TAP = Float
VCC
nPCLK[0:1]
PCLK[0:1]
VEE
VCMR
Cross Points
VPP
SCOPE
Qx
nQx
LVPECL
VEE
VCC,
2V
-0.5V±0.125V
VCC_TAP
SCOPE
Qx
nQx
LVDS
2.5V±5%
POWER SUPPLY
+–
Float GND
VCC,
VCC_TAP
tpLH
nQ[0:1]
Q[0:1]
PCLK0,
PCLK1
nPCLK0,
nPCLK1
ICS879S216I-02 Data Sheet 2:2, DIFFERENTIAL-TO-LVPECL/LVDS DIVIDER
ICS879S216AKI-02 REVISION A APRIL 8, 2011 8 ©2011 Integrated Device Technology, Inc.
Parameter Measurement Information, continued
MUX Isolation
Part-to-Part Skew
LVDS Output Rise/Fall Time
Input Skew
Output Skew
LVPECL Output Rise/Fall Time
Amplitude (dB)
A0
Spectrum of Output Signal Q
MUX_ISOL = A0 – A1
(fundamental) Frequency
ƒ
MUX selects static input
MUX selects active
input clock signal
A1
tsk(pp)
Part 1
Part 2
nQx
Qx
nQy
Qy
20%
80% 80%
20%
tRtF
VOD
nQ[0:1]
Q[0:1]
tPD2
tPD1
tsk(i) = |tPD1 - tPD2|
tsk(i)
nPCLK1
PCLK1
nQ
Q
nPCLK0
PCLK0
tsk(o)
nQx
Qx
nQy
Qy
20%
80% 80%
20%
tRtF
VSWING
nQ[0:1]
Q[0:1]
ICS879S216I-02 Data Sheet 2:2, DIFFERENTIAL-TO-LVPECL/LVDS DIVIDER
ICS879S216AKI-02 REVISION A APRIL 8, 2011 9 ©2011 Integrated Device Technology, Inc.
Parameter Measurement Information, continued
Offset Voltage Setup
Output Duty Cycle/Pulse Width/Period
Differential Output Voltage Setup
out
out
LVDS
DC Input
➤
➤
➤
VOS/∆ VOS
VDD
tPW
tPERIOD
tPW
tPERIOD
odc = x 100%
nQ[0:1]
Q[0:1]
➤
➤
➤
100
out
out
LVDS
DC Input VOD/∆ VOD
VDD
ICS879S216I-02 Data Sheet 2:2, DIFFERENTIAL-TO-LVPECL/LVDS DIVIDER
ICS879S216AKI-02 REVISION A APRIL 8, 2011 10 ©2011 Integrated Device Technology, Inc.
Applications Information
Recommendations for Unused Input and Output Pins
Inputs:
PCLK/nPCLK Inputs
For applications not requiring the use of a differential input, both the
PCLK and nPCLK pins can be left floating. Though not required, but
for additional protection, a 1kΩ resistor can be tied from PCLK to
ground.
LVCMOS Control Pins
All control pins have internal pullups or pulldowns; additional
resistance is not required but can be added for additional protection.
A 1kΩ resistor can be used.
Outputs:
LVPECL Outputs
All unused LVPECL outputs can be left floating. We recommend that
there is no trace attached. Both sides of the differential output pair
should either be left floating or terminated.
LVDS Outputs
All unused LVDS output pairs can be either left floating or terminated
with 100Ω across. If they are left floating, there should be no trace
attached.
Wiring the Differential Input to Accept Single-Ended Levels
Figure 1 shows how a differential input can be wired to accept single
ended levels. The reference voltage VREF = VCC/2 is generated by
the bias resistors R1 and R2. The bypass capacitor (C1) is used to
help filter noise on the DC bias. This bias circuit should be located as
close to the input pin as possible. The ratio of R1 and R2 might need
to be adjusted to position the VREF in the center of the input voltage
swing. For example, if the input clock swing is 2.5V and VCC = 3.3V,
R1 and R2 value should be adjusted to set VREF at 1.25V. The values
below are for when both the single ended swing and VCC are at the
same voltage. This configuration requires that the sum of the output
impedance of the driver (Ro) and the series resistance (Rs) equals
the transmission line impedance. In addition, matched termination at
the input will attenuate the signal in half. This can be done in one of
two ways. First, R3 and R4 in parallel should equal the transmission
line impedance. For most 50Ω applications, R3 and R4 can be 100Ω.
The values of the resistors can be increased to reduce the loading for
slower and weaker LVCMOS driver. When using single-ended
signaling, the noise rejection benefits of differential signaling are
reduced. Even though the differential input can handle full rail
LVCMOS signaling, it is recommended that the amplitude be
reduced. The datasheet specifies a lower differential amplitude,
however this only applies to differential signals. For single-ended
applications, the swing can be larger, however VIL cannot be less
than -0.3V and VIH cannot be more than VCC + 0.3V. Though some
of the recommended components might not be used, the pads
should be placed in the layout. They can be utilized for debugging
purposes. The datasheet specifications are characterized and
guaranteed by using a differential signal.
Figure 1. Recommended Schematic for Wiring a Differential Input to Accept Single-ended Levels
ICS879S216I-02 Data Sheet 2:2, DIFFERENTIAL-TO-LVPECL/LVDS DIVIDER
ICS879S216AKI-02 REVISION A APRIL 8, 2011 11 ©2011 Integrated Device Technology, Inc.
3.3V LVPECL Clock Input Interface
The PCLK /nPCLK accepts LVPECL, LVDS, CML and other
differential signals. The differential signals must meet the VPP and
VCMR input requirements. Figures 2A to 2E show interface examples
for the PCLK/ nPCLK input driven by the most common driver types.
The input interfaces suggested here are examples only. If the driver
is from another vendor, use their termination recommendation.
Please consult with the vendor of the driver component to confirm the
driver termination requirements.
Figure 2A. PCLK/nPCLK Input Driven by a CML Driver
Figure 2C. PCLK/nPCLK Input Driven by a
3.3V LVPECL Driver
Figure 2E. PCLK/nPCLK Input Driven by a
3.3V LVDS Driver
Figure 2B. PCLK/nPCLK Input Driven by a
Built-In Pullup CML Driver
Figure 2D. PCLK/nPCLK Input Driven by a
3.3V LVPECL Driver with AC Couple
PCLK
nPCLK
LVPECL
Input
CML
3.3V
Zo = 50Ω
Zo = 50Ω
3.3V
3.3V
R1
50Ω
R2
50Ω
R3
125Ω
R4
125Ω
R1
84Ω
R2
84Ω
3.3V
Zo = 50Ω
Zo = 50Ω
PCLK
nPCLK
3.3V
3.3V
LVPECL LVPECL
Input
3.3V
R1
100Ω
LVDS
PCLK
nPCLK
3.3V
LVPECL
Input
Zo = 50Ω
Zo = 50Ω
PCLK
nPCLK
3.3V
LVPECL
Input
3.3V
Zo = 50Ω
Zo = 50Ω
R1
100Ω
CML Built-In Pullup
R3
84
R4
84
R1
125
R2
125
R5
100 - 200
R6
100 - 200
PCLK
nPCLK
3.3V LVPECL
3.3V
Zo = 50Ω
Zo = 50Ω
3.3V
3.3V
LVPECL
Input
C1
C2
ICS879S216I-02 Data Sheet 2:2, DIFFERENTIAL-TO-LVPECL/LVDS DIVIDER
ICS879S216AKI-02 REVISION A APRIL 8, 2011 12 ©2011 Integrated Device Technology, Inc.
2.5V LVPECL Clock Input Interface
The PCLK /nPCLK accepts LVPECL, LVDS and other differential
signals. The differential signals must meet the VPP and VCMR input
requirements. Figures 3A to 3C show interface examples for the
PCLK/nPCLK input driven by the most common driver types. The
input interfaces suggested here are examples only. If the driver is
from another vendor, use their termination recommendation. Please
consult with the vendor of the driver component to confirm the driver
termination requirements.
Figure 3A. PCLK/nPCLK Input Driven by a 2.5V LVDS
Driver
Figure 3C. PCLK/nPCLK Input Driven by a 2.5V
LVPECL Driver
Figure 3B. PCLK/nPCLK Input Driven by a 3.3V
LVPECL Driver with AC Couple
2.5V
R1
100Ω
LVDS
PCLK
nPCLK
2.5V
LVPECL
Input
Zo = 50Ω
Zo = 50Ω
R3
250Ω
R4
250Ω
R1
62.5Ω
R2
62.5Ω
2.5V
Zo = 50Ω
Zo = 50Ω
PCLK
nPCLK
2.5V
2.5V
LVPECL LVPECL
Input
R6
100
Ω
-180
Ω
3.3V LVPEC L D riv er
R7
100
Ω
-180
Ω
Zo = 50
Ω
R2
100
Ω
C1
Zo = 50
Ω
R3
100
Ω
C2
R4
100
Ω
R1
100
Ω
2.5V
3.3V
PCLK
nPCLK
ICS879S216I-02 Data Sheet 2:2, DIFFERENTIAL-TO-LVPECL/LVDS DIVIDER
ICS879S216AKI-02 REVISION A APRIL 8, 2011 13 ©2011 Integrated Device Technology, Inc.
LVDS Driver Termination
A general LVDS interface is shown in Figure 4. Standard termination
for LVDS type output structure requires both a 100Ω parallel resistor
at the receiver and a 100Ω differential transmission line environment.
In order to avoid any transmission line reflection issues, the 100Ω
resistor must be placed as close to the receiver as possible. IDT
offers a full line of LVDS compliant devices with two types of output
structures: current source and voltage source. The standard
termination schematic as shown in Figure 4 can be used with either
type of output structure. If using a non-standard termination, it is
recommended to contact IDT and confirm if the output is a current
source or a voltage source type structure. In addition, since these
outputs are LVDS compatible, the amplitude and common mode
input range of the input receivers should be verified for compatibility
with the output.
Figure 4. Typical LVDS Driver Termination
Termination for 3.3V LVPECL Outputs
The clock layout topology shown below is a typical termination for
LVPECL outputs. The two different layouts mentioned are
recommended only as guidelines.
The differential outputs are low impedance follower outputs that
generate ECL/LVPECL compatible outputs. Therefore, terminating
resistors (DC current path to ground) or current sources must be
used for functionality. These outputs are designed to drive 50Ω
transmission lines. Matched impedance techniques should be used
to maximize operating frequency and minimize signal distortion.
Figures 5A and 5B show two different layouts which are
recommended only as guidelines. Other suitable clock layouts may
exist and it would be recommended that the board designers
simulate to guarantee compatibility across all printed circuit and clock
component process variations.
Figure 5A. 3.3V LVPECL Output Termination Figure 5B. 3.3V LVPECL Output Termination
100Ω
–
+
100Ω Differential Transmission Line
LVDS Driver LVDS
Receiver
3.3V
VCC - 2V
R1
50Ω
R2
50Ω
RTT
Zo = 50Ω
Zo = 50Ω
+
_
RTT = * Zo
1
((VOH + VOL) / (VCC – 2)) – 2
3.3V
LVPECL Input
R1
84Ω
R2
84Ω
3.3V
R3
125Ω
R4
125Ω
Zo = 50Ω
Zo = 50Ω
LVPECL Input
3.3V
3.3V
+
_
ICS879S216I-02 Data Sheet 2:2, DIFFERENTIAL-TO-LVPECL/LVDS DIVIDER
ICS879S216AKI-02 REVISION A APRIL 8, 2011 14 ©2011 Integrated Device Technology, Inc.
Termination for 2.5V LVPECL Outputs
Figure 6A and Figure 5B show examples of termination for 2.5V
LVPECL driver. These terminations are equivalent to terminating 50Ω
to VCC – 2V. For VCC = 2.5V, the VCC – 2V is very close to ground
level. The R3 in Figure 6B can be eliminated and the termination is
shown in Figure 6C.
Figure 6A. 2.5V LVPECL Driver Termination Example
Figure 6C. 2.5V LVPECL Driver Termination Example
Figure 6B. 2.5V LVPECL Driver Termination Example
2.5V LVPECL Driver
VCC = 2.5V
2.5V
2.5V
50Ω
50Ω
R1
250Ω
R3
250Ω
R2
62.5Ω
R4
62.5Ω
+
–
2.5V LVPECL Driver
VCC = 2.5V
2.5V
50Ω
50Ω
R1
50Ω
R2
50Ω
+
–
2.5V LVPECL Driver
VCC = 2.5V
2.5V
50Ω
50Ω
R1
50Ω
R2
50Ω
R3
18Ω
+
–
ICS879S216I-02 Data Sheet 2:2, DIFFERENTIAL-TO-LVPECL/LVDS DIVIDER
ICS879S216AKI-02 REVISION A APRIL 8, 2011 15 ©2011 Integrated Device Technology, Inc.
VFQFN EPAD Thermal Release Path
In order to maximize both the removal of heat from the package and
the electrical performance, a land pattern must be incorporated on
the Printed Circuit Board (PCB) within the footprint of the package
corresponding to the exposed metal pad or exposed heat slug on the
package, as shown in Figure 7. The solderable area on the PCB, as
defined by the solder mask, should be at least the same size/shape
as the exposed pad/slug area on the package to maximize the
thermal/electrical performance. Sufficient clearance should be
designed on the PCB between the outer edges of the land pattern
and the inner edges of pad pattern for the leads to avoid any shorts.
While the land pattern on the PCB provides a means of heat transfer
and electrical grounding from the package to the board through a
solder joint, thermal vias are necessary to effectively conduct from
the surface of the PCB to the ground plane(s). The land pattern must
be connected to ground through these vias. The vias act as “heat
pipes”. The number of vias (i.e. “heat pipes”) are application specific
and dependent upon the package power dissipation as well as
electrical conductivity requirements. Thus, thermal and electrical
analysis and/or testing are recommended to determine the minimum
number needed. Maximum thermal and electrical performance is
achieved when an array of vias is incorporated in the land pattern. It
is recommended to use as many vias connected to ground as
possible. It is also recommended that the via diameter should be 12
to 13mils (0.30 to 0.33mm) with 1oz copper via barrel plating. This is
desirable to avoid any solder wicking inside the via during the
soldering process which may result in voids in solder between the
exposed pad/slug and the thermal land. Precautions should be taken
to eliminate any solder voids between the exposed heat slug and the
land pattern. Note: These recommendations are to be used as a
guideline only. For further information, please refer to the Application
Note on the Surface Mount Assembly of Amkor’s Thermally/
Electrically Enhance Leadframe Base Package, Amkor Technology.
Figure 7. P.C. Assembly for Exposed Pad Thermal Release Path – Side View (drawing not to scale
SOLDERSOLDER PINPIN EXPOSED HEAT SLUG
PIN PAD PIN PADGROUND PLANE LAND PATTERN
(GROUND PAD)
THERMAL VIA
ICS879S216I-02 Data Sheet 2:2, DIFFERENTIAL-TO-LVPECL/LVDS DIVIDER
ICS879S216AKI-02 REVISION A APRIL 8, 2011 16 ©2011 Integrated Device Technology, Inc.
LVPECL Power Considerations
This section provides information on power dissipation and junction temperature for the ICS879S2162I-02.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS879S216I-02 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for VCC = 3.3V + 5% = 3.465V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
• Power (core)MAX = VCC_MAX * IEE_MAX = 3.465V * 65mA = 225.225mW
• Power (outputs)MAX = 32mW/Loaded Output pair
If all outputs are loaded, the total power is 2 * 32mW = 64mW
Total Power_MAX (3.465, with all outputs switching) = 225.225mW + 64mW = 289.225mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad directly affects the reliability of the device. The
maximum recommended junction temperature is 125°C. Limiting the internal transistor junction temperature, Tj, to 125°C ensures that the bond
wire and bond pad temperature remains below 125°C.
The equation for Tj is as follows: Tj = θJA * Pd_total + TA
Tj = Junction Temperature
θJA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming no air flow and
a multi-layer board, the appropriate value is 49.5°C/W per Table 7 below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 0.289W * 49.5°C/W = 99.3°C. This is below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of
board (multi-layer).
Table 7. Thermal Resistance θJA for 24 Lead VFQFN, Forced Convection
θJA by Velocity
Meters per Second 012.5
Multi-Layer PCB, JEDEC Standard Test Boards 49.5°C/W 43.3°C/W 38.8°C/W
ICS879S216I-02 Data Sheet 2:2, DIFFERENTIAL-TO-LVPECL/LVDS DIVIDER
ICS879S216AKI-02 REVISION A APRIL 8, 2011 17 ©2011 Integrated Device Technology, Inc.
3. Calculations and Equations.
The purpose of this section is to calculate the power dissipation for the LVPECL output pair.
LVPECL output driver circuit and termination are shown in Figure 8.
Figure 8. LVPECL Driver Circuit and Termination
To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a termination voltage of
VCC – 2V.
• For logic high, VOUT = VOH_MAX = VCC_MAX – 0.8V
(VCC_MAX – VOH_MAX) = 0.8V
• For logic low, VOUT = VOL_MAX = VCC_MAX – 1.6V
(VCC_MAX – VOL_MAX) = 1.6V
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low.
Pd_H = [(VOH_MAX – (VCC_MAX – 2V))/RL] * (VCC_MAX – VOH_MAX) = [(2V – (VCC_MAX – VOH_MAX))/RL] * (VCC_MAX – VOH_MAX) =
[(2V – 0.8V)/50Ω] * 0.8V = 19.2mW
Pd_L = [(VOL_MAX – (VCC_MAX – 2V))/RL] * (VCC_MAX – VOL_MAX) = [(2V – (VCC_MAX – VOL_MAX))/RL] * (VCC_MAX – VOL_MAX) =
[(2V – 1.6V)/50Ω] * 1.6V = 12.8mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 32mW
VOUT
VCCO
VCCO - 2V
Q1
RL
50Ω
ICS879S216I-02 Data Sheet 2:2, DIFFERENTIAL-TO-LVPECL/LVDS DIVIDER
ICS879S216AKI-02 REVISION A APRIL 8, 2011 18 ©2011 Integrated Device Technology, Inc.
LVDS Power Considerations
This section provides information on power dissipation and junction temperature for the ICS879S2162I-02.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS879S2162I-02 is the sum of the core power plus the analog power plus the power dissipated in the
load(s). The following is the power dissipation for VCC = 3.3V + 5% = 3.465V, which gives worst case results.
• Power (core)MAX = VCC_MAX * IEE_MAX = 3.465V * 95mA = 329.175mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad directly affects the reliability of the device. The
maximum recommended junction temperature is 125°C. Limiting the internal transistor junction temperature, Tj, to 125°C ensures that the bond
wire and bond pad temperature remains below 125°C.
The equation for Tj is as follows: Tj = θJA * Pd_total + TA
Tj = Junction Temperature
θJA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming no air flow and
a multi-layer board, the appropriate value is 49.5°C/W per Table 8 below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 0.329W * 49.5°C/W = 101.3°C. This is below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of
board (multi-layer).
Table 8. Thermal Resistance θJA for 24 Lead VFQFN, Forced Convection
θJA by Velocity
Meters per Second 012.5
Multi-Layer PCB, JEDEC Standard Test Boards 49.5°C/W 43.3°C/W 38.8°C/W
ICS879S216I-02 Data Sheet 2:2, DIFFERENTIAL-TO-LVPECL/LVDS DIVIDER
ICS879S216AKI-02 REVISION A APRIL 8, 2011 19 ©2011 Integrated Device Technology, Inc.
Reliability Information
Table 9. θJA vs. Air Flow Table for a 24 Lead VFQFN
Transistor Count
The transistor count for ICS879S216I-02 is: 1039
θJA vs. Air Flow
Meters per Second 012.5
Multi-Layer PCB, JEDEC Standard Test Boards 49.5°C/W 43.3°C/W 38.8°C/W
ICS879S216I-02 Data Sheet 2:2, DIFFERENTIAL-TO-LVPECL/LVDS DIVIDER
ICS879S216AKI-02 REVISION A APRIL 8, 2011 20 ©2011 Integrated Device Technology, Inc.
Package Outline and Package Dimensions
Package Outline - K Suffix for 24 Lead VFQFN
Table 10. Package Dimensions
Reference Document: JEDEC Publication 95, MO-220
NOTE: The following package mechanical drawing is a generic
drawing that applies to any pin count VFQFN package. This drawing
is not intended to convey the actual pin count or pin layout of this
device. The pin count and pinout are shown on the front page. The
package dimensions are in Table 10.
To p View
Index Area
D
Chamfer 4x
0.6 x 0.6 max
OPTIONAL
Anvil
Singula tion
A
0. 08 C
C
A3
A1
S eating Plan e
E2
E2
2
L
(N
-1)x e
(R ef.)
(Ref.)
N & N
Even
N
e
D2
2
D2
(Ref.)
N & N
Odd
1
2
e
2
(Ty p.)
If N & N
are Even
(N -1)x e
(Re f.)
b
Th er mal
Ba se
N
OR
Anvil
Singulation
or
Sawn
Singulation
N-1N
CHAMFER
1
2
N-1
1
2
N
RADIUS
4
4
Bottom View w/Type C IDBottom View w/Type A ID
There are 2 methods of indicating pin 1 corner at the back of the VFQFN package are:
1. Type A: Chamfer on the paddle (near pin 1)
2. Type C: Mouse bite on the paddle (near pin 1)
JEDEC Variation: VEED-2/-4
All Dimensions in Millimeters
Symbol Minimum Maximum
N24
A0.80 1.0
A1 00.05
A3 0.25 Reference
b0.18 0.30
e0.50 Basic
D, E 4
D2, E2 2.30 2.55
L0.30 0.50
ND NE6
ICS879S216I-02 Data Sheet 2:2, DIFFERENTIAL-TO-LVPECL/LVDS DIVIDER
ICS879S216AKI-02 REVISION A APRIL 8, 2011 21 ©2011 Integrated Device Technology, Inc.
Ordering Information
Table 11. Ordering Information
NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.
Part/Order Number Marking Package Shipping Packaging Temperature
879S216AKI-02LF 6AI02L “Lead-Free” 24 Lead VFQFN Tray -40°C to 85°C
879S216AKI-02LFT 6AI02L “Lead-Free” 24 Lead VFQFN 2500 Tape & Reel -40°C to 85°C
While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes no responsibility for either its use or for the
infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal
commercial and industrial applications. Any other applications, such as those requiring high reliability or other extraordinary environmental requirements are not recommended without
additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support
devices or critical medical instruments.
ICS879S216I-02 Data Sheet 2:2, DIFFERENTIAL-TO-LVPECL/LVDS DIVIDER
DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the right to modify the products and/or specifications described herein at any time and at IDT’s sole discretion. All information in this document,
including descriptions of product features and performance, is subject to change without notice. Performance specifications and the operating parameters of the described products are determined in the independent state and are not
guaranteed to perform the same way when installed in customer products. The information contained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the
suitability of IDT’s products for any particular purpose, an implied warranty of merchantability, or non-infringement of the intellectual property rights of others. This document is presented only as a guide and does not convey any
license under intellectual property rights of IDT or any third parties.
IDT’s products are not intended for use in life support systems or similar devices where the failure or malfunction of an IDT product can be reasonably expected to significantly affect the health or safety of users. Anyone using an IDT
product in such a manner does so at their own risk, absent an express, written agreement by IDT.
Integrated Device Technology, IDT and the IDT logo are registered trademarks of IDT. Other trademarks and service marks used herein, including protected names, logos and designs, are the property of IDT or their respective third
party owners.
Copyright 2011. All rights reserved.
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