LMK04000,LMK04001,LMK04002,LMK04010,
LMK04011,LMK04031,LMK04033
LMK04000 Family Low-Noise Clock Jitter Cleaner with Cascaded PLLs
Literature Number: SNOSAZ8J
LMK04000 Family
September 19, 2011
Low-Noise Clock Jitter Cleaner with Cascaded PLLs
1.0 General Description
The LMK04000 family of precision clock conditioners pro-
vides low-noise jitter cleaning, clock multiplication and distri-
bution without the need for high-performance voltage con-
trolled crystal oscillators (VCXO) module. Using a cascaded
PLLatinum™ architecture combined with an external crystal
and varactor diode, the LMK04000 family provides sub-200
femtosecond (fs) root mean square (RMS) jitter performance.
The cascaded architecture consists of two high-performance
phase-locked loops (PLL), a low-noise crystal oscillator cir-
cuit, and a high-performance voltage controlled oscillator
(VCO). The first PLL (PLL1) provides a low-noise jitter cleaner
function while the second PLL (PLL2) performs the clock gen-
eration. PLL1 can be configured to either work with an exter-
nal VCXO module or use the integrated crystal oscillator with
an external crystal and a varactor diode. When used with a
very narrow loop bandwidth, PLL1 uses the superior close-in
phase noise (offsets below 50 kHz) of the VCXO module or
the crystal to clean the input clock. The output of PLL1 is used
as the clean input reference to PLL2 where it locks the inte-
grated VCO. The loop bandwidth of PLL2 can be optimized
to clean the far-out phase noise (offsets above 50 kHz) where
the integrated VCO outperforms the VCXO module or crystal
used in PLL1.
The LMK04000 family features dual redundant inputs, five
differential outputs, and an optional default-clock upon power
up. The input block is equipped with loss of signal detection
and automatic or manual selection of the reference clock.
Each clock output consists of a programmable divider, a
phase synchronization circuit, a programmable delay, and an
LVDS, LVPECL, or LVCMOS output buffer. The default start-
up clock is available on CLKout2 and it can be used to provide
an initial clock for the field-programmable gate array (FPGA)
or microcontroller that programs the jitter cleaner during the
system power up sequence.
2.0 Features
■Cascaded PLLatinum PLL Architecture
—PLL1
■Phase detector rate of up to 40 MHz
■Integrated Low-Noise Crystal Oscillator Circuit
■Dual redundant input reference clock with LOS
—PLL2
■Normalized [1 Hz] PLL noise floor of -224 dBc/Hz
■Phase detector rate up to 100 MHz
■Input frequency-doubler
■Integrated Low-Noise VCO
■Ultra-Low RMS Jitter Performance
—150 fs RMS jitter (12 kHz – 20 MHz)
—200 fs RMS jitter (100 Hz – 20 MHz)
■LVPECL/2VPECL, LVDS, and LVCMOS outputs
■Support clock rates up to 1080 MHz
■Default Clock Output (CLKout2) at power up
■Five dedicated channel divider and delay blocks
■Pin compatible family of clocking devices
■Industrial Temperature Range: -40 to 85 °C
■3.15 V to 3.45 V operation
■Package: 48 pin LLP (7.0 x 7.0 x 0.8 mm)
3.0 Target Applications
■Data Converter Clocking
■Wireless Infrastructure
■Networking, SONET/SDH, DSLAM
■Medical
■Military / Aerospace
■Test and Measurement
■Video
30027140
PLLatinum™ is a trademark of National Semiconductor Corporation.
TRI-STATE® is a registered trademark of National Semiconductor Corporation.
© 2011 National Semiconductor Corporation 300271 www.national.com
LMK04000 Family Low-Noise Clock Jitter Cleaner with Cascaded PLLs
Device Configuration Information
NSID PROCESS 2VPECL / LVPECL
OUTPUTS LVDS OUTPUTS LVCMOS
OUTPUTS VCO
LMK04000BISQ BiCMOS 3 4 1185 to 1296 MHz
LMK04001BISQ BiCMOS 3 4 1430 to 1570 MHz
LMK04002BISQ BiCMOS 3 4 1600 to 1750 MHz
LMK04010BISQ BiCMOS 5 1185 to 1296 MHz
LMK04011BISQ BiCMOS 5 1430 to 1570 MHz
LMK04031BISQ BiCMOS 2 2 2 1430 to 1570 MHz
LMK04033BISQ BiCMOS 2 2 2 1840 to 2160 MHz
NSID CLKout0 CLKout1 CLKout2 CLKout3 CLKout4
LMK04000BISQ 2VPECL / LVPECL LVCMOS x 2 LVCMOS x 2 2VPECL / LVPECL 2VPECL / LVPECL
LMK04001BISQ 2VPECL / LVPECL LVCMOS x 2 LVCMOS x 2 2VPECL / LVPECL 2VPECL / LVPECL
LMK04002BISQ 2VPECL / LVPECL LVCMOS x 2 LVCMOS x 2 2VPECL / LVPECL 2VPECL / LVPECL
LMK04010BISQ 2VPECL / LVPECL 2VPECL / LVPECL 2VPECL / LVPECL 2VPECL / LVPECL 2VPECL / LVPECL
LMK04011BISQ 2VPECL / LVPECL 2VPECL / LVPECL 2VPECL / LVPECL 2VPECL / LVPECL 2VPECL / LVPECL
LMK04031BISQ LVDS 2VPECL / LVPECL LVCMOS x 2 2VPECL / LVPECL LVDS
LMK04033BISQ LVDS 2VPECL / LVPECL LVCMOS x 2 2VPECL / LVPECL LVDS
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LMK04000 Family
4.0 Functional Block Diagram
30027101
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LMK04000 Family
Table of Contents
1.0 General Description ......................................................................................................................... 1
2.0 Features ........................................................................................................................................ 1
3.0 Target Applications .......................................................................................................................... 1
4.0 Functional Block Diagram ................................................................................................................. 3
5.0 Connection Diagram ........................................................................................................................ 6
6.0 Pin Descriptions ............................................................................................................................. 7
7.0 Absolute Maximum Ratings .............................................................................................................. 9
8.0 Package Thermal Resistance ............................................................................................................ 9
9.0 Recommended Operating Conditions ................................................................................................ 9
10.0 Electrical Characteristics ............................................................................................................... 10
11.0 Serial Data Timing Diagram .......................................................................................................... 22
12.0 Charge Pump Current Specification Definitions ................................................................................ 22
12.1 CHARGE PUMP OUTPUT CURRENT MAGNITUDE VARIATION VS. CHARGE PUMP OUTPUT
VOLTAGE ................................................................................................................................ 23
12.2 CHARGE PUMP SINK CURRENT VS. CHARGE PUMP OUTPUT SOURCE CURRENT
MISMATCH .............................................................................................................................. 23
12.3 CHARGE PUMP OUTPUT CURRENT MAGNITUDE VARIATION VS. TEMPERATURE ................ 23
13.0 Typical Performance Characteristics .............................................................................................. 24
13.1 CLOCK OUTPUT AC CHARACTERISTICS ............................................................................. 24
14.0 Features ..................................................................................................................................... 26
14.1 SYSTEM ARCHITECTURE ................................................................................................... 26
14.2 REDUNDANT REFERENCE INPUTS (CLKin0/CLKin0*, CLKin1/CLKin1*) ................................... 26
14.3 PLL1 CLKinX (X=0,1) LOSS OF SIGNAL (LOS) ....................................................................... 26
14.4 INTEGRATED LOOP FILTER POLES ..................................................................................... 26
14.5 CLOCK DISTRIBUTION ....................................................................................................... 26
14.6 CLKout DIVIDE (CLKoutX_DIV, X = 0 to 4) .............................................................................. 26
14.7 CLKout DELAY (CLKoutX_DLY, X = 0 to 4) ............................................................................. 26
14.8 GLOBAL CLOCK OUTPUT SYNCHRONIZATION (SYNC*) ....................................................... 26
14.9 GLOBAL OUTPUT ENABLE AND LOCK DETECT .................................................................... 26
15.0 Functional Description .................................................................................................................. 27
15.1 ARCHITECTURAL OVERVIEW .............................................................................................. 27
15.2 PHASE DETECTOR 1 (PD1) ................................................................................................. 27
15.3 PHASE DETECTOR 2 (PD2) ................................................................................................. 27
15.4 PLL2 FREQUENCY DOUBLER .............................................................................................. 27
15.5 INPUTS / OUTPUTS ............................................................................................................. 27
15.5.1 PLL1 Reference Inputs (CLKin0 / CLKin0*, CLKin1 / CLKin1*) .......................................... 27
15.5.2 PLL2 OSCin / OSCin* Port ........................................................................................... 27
15.5.3 CPout1 / CPout2 ........................................................................................................ 27
15.5.4 Fout .......................................................................................................................... 27
15.5.5 Digital Lock Detect 1 Bypass ........................................................................................ 28
15.5.6 Bias .......................................................................................................................... 28
16.0 General Programming Information ................................................................................................. 29
16.1 RECOMMENDED PROGRAMMING SEQUENCE .................................................................... 29
16.2 DEFAULT DEVICE REGISTER SETTINGS AFTER POWER ON/RESET .................................... 32
16.3 REGISTER R0 TO R4 ........................................................................................................... 33
16.3.1 CLKoutX_DIV: Clock Channel Divide Registers .............................................................. 33
16.3.2 EN_CLKoutX: Clock Channel Output Enable .................................................................. 33
16.3.3 CLKoutX_DLY: Clock Channel Phase Delay Adjustment .................................................. 33
16.3.4 CLKoutX/CLKoutX* LVCMOS Mode Control ................................................................... 33
16.3.5 CLKoutX/CLKoutX* LVPECL Mode Control .................................................................... 34
16.3.6 CLKoutX_MUX: Clock Output Mux ................................................................................ 34
16.4 REGISTERS 5, 6 .................................................................................................................. 34
16.5 REGISTER 7 ....................................................................................................................... 34
16.5.1 RESET bit ................................................................................................................. 34
16.6 REGISTERS 8, 9 .................................................................................................................. 34
16.7 REGISTER 10 ..................................................................................................................... 34
16.7.1 RC_DLD1_Start: PLL1 Digital Lock Detect Run Control bit ............................................... 34
16.8 REGISTER 11 ..................................................................................................................... 34
16.8.1 CLKinX_BUFTYPE: PLL1 CLKinX/CLKinX* Buffer Mode Control ...................................... 34
16.8.2 CLKin_SEL: PLL1 Reference Clock Selection and Revertive Mode Control Bits .................. 35
16.8.3 CLKinX_LOS ............................................................................................................. 35
16.8.4 PLL1 Reference Clock LOS Timeout Control .................................................................. 35
16.8.5 LOS Output Type Control ............................................................................................ 35
16.9 REGISTER 12 ..................................................................................................................... 35
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LMK04000 Family
16.9.1 PLL1_N: PLL1_N Counter ........................................................................................... 35
16.9.2 PLL1_R: PLL1_R Counter ........................................................................................... 36
16.9.3 PLL1 Charge Pump Current Gain (PLL1_CP_GAIN) and Polarity Control
(PLL1_CP_POL) ................................................................................................................ 36
16.10 REGISTER 13 .................................................................................................................... 36
16.10.1 EN_PLL2_XTAL: Crystal Oscillator Option Enable ......................................................... 36
16.10.2 EN_Fout: Fout Power Down Bit .................................................................................. 36
16.10.3 CLK Global Enable: Clock Global enable bit ................................................................. 36
16.10.4 POWERDOWN Bit -- Device Power Down .................................................................... 36
16.10.5 EN_PLL2 REF2X: PLL2 Frequency Doubler control bit .................................................. 36
16.10.6 PLL2 Internal Loop Filter Component Values ................................................................ 36
16.10.7 PLL1 CP TRI-STATE and PLL2 CP TRI-STATE ............................................................ 37
16.11 REGISTER 14 .................................................................................................................... 37
16.11.1 OSCin_FREQ: PLL2 Oscillator Input Frequency Register ............................................... 37
16.11.2 PLL2_R: PLL2_R Counter .......................................................................................... 37
16.11.3 PLL_MUX: LD Pin Selectable Output ........................................................................... 37
16.12 REGISTER 15 .................................................................................................................... 38
16.12.1 PLL2_N: PLL2_N Counter .......................................................................................... 38
16.12.2 PLL2_CP_GAIN: PLL2 Charge Pump Current and Output Control ................................... 38
16.12.3 VCO_DIV: PLL2 VCO Divide Register ......................................................................... 38
17.0 Application Information ................................................................................................................. 39
17.1 SYSTEM LEVEL DIAGRAM ................................................................................................... 39
17.2 LDO BYPASS AND BIAS PIN ................................................................................................ 40
17.3 LOOP FILTER ..................................................................................................................... 40
17.4 CURRENT CONSUMPTION / POWER DISSIPATION CALCULATIONS ..................................... 43
17.5 POWER SUPPLY CONDITIONING ........................................................................................ 43
17.6 THERMAL MANAGEMENT ................................................................................................... 43
17.7 OPTIONAL CRYSTAL OSCILLATOR IMPLEMENTATION (OSCin/OSCin*) ................................. 44
17.8 TERMINATION AND USE OF CLOCK OUTPUT (DRIVERS) ..................................................... 47
17.8.1 Termination for DC Coupled Differential Operation .......................................................... 47
17.8.2 Termination for AC Coupled Differential Operation .......................................................... 47
17.8.3 Termination for Single-Ended Operation ........................................................................ 48
17.9 DRIVING CLKin AND OSCin INPUTS ..................................................................................... 49
17.9.1 Driving CLKin Pins with a Differential Source .................................................................. 49
17.9.2 Driving CLKin Pins with a Single-Ended Source .............................................................. 49
17.10 ADDITIONAL OUTPUTS WITH AN LMK04000 FAMILY DEVICE .............................................. 49
17.11 OUTPUT CLOCK PHASE NOISE PERFORMANCE VS. VCXO PHASE NOISE .......................... 49
18.0 Physical Dimensions .................................................................................................................... 53
19.0 Ordering Information .................................................................................................................... 53
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LMK04000 Family
5.0 Connection Diagram
48-Pin LLP Package
30027102
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LMK04000 Family
6.0 Pin Descriptions
Pin Number Name(s) I/O Type Description
1 GND GND Ground (For Fout Buffer)
2 Fout O ANLG VCO Frequency Output Port
3 VCC1 PWR Power Supply for VCO Output Buffer
4 CLKuWire I CMOS Microwire Clock Input
5 DATAuWire I CMOS Microwire Data Input
6 LEuWire I CMOS Microwire Latch Enable Input
7 NC No Connection
8 VCC2 PWR Power Supply for VCO
9 LDObyp1 ANLG LDO Bypass, bypassed to ground with a 10 µF
capacitor
10 LDObyp2 ANLG LDO Bypass, bypassed to ground with a 0.1 µF
capacitor
11 GOE I CMOS Global Output Enable
12 LD O CMOS Lock Detect and PLL multiplexer Output
13 VCC3 PWR Power Supply for CLKout0
14 CLKout0 O LVDS/LVPECL Clock Channel 0 Output
15 CLKout0* O LVDS/LVPECL Clock Channel 0* Output
16 DLD_BYP ANLG DLD Bypass, bypassed to ground with a 0.47 µF
capacitor
17 GND GND Ground (Digital)
18 VCC4 PWR Power Supply for Digital
19 VCC5 PWR Power Supply for CLKin buffers and PLL1 R-divider
20 CLKin0 I ANLG Reference Clock Input Port for PLL1 - AC or DC
Coupled (Note 1)
21 CLKin0* I ANLG Reference Clock Input Port for PLL1 (complimentary)
- AC or DC Coupled (Note 1)
22 VCC6 PWR Power Supply for PLL1 Phase Detector and Charge
Pump
23 CPout1 O ANLG Charge Pump1 Output
24 VCC7 PWR Power Supply for PLL1 N-Divider
25 CLKin1 I ANLG Reference Clock Input Port for PLL1 - AC or DC
Coupled (Note 1)
26 CLKin1* I ANLG Reference Clock Input Port for PLL1 (complimentary)
- AC or DC Coupled (Note 1)
27 SYNC* I CMOS Global Clock Output Synchronization
28 OSCin I ANLG Reference oscillator Input for PLL2 - AC Coupled
29 OSCin* I ANLG Reference oscillator Input for PLL2 - AC Coupled
30 VCC8 PWR Power Supply for OSCin Buffer and PLL2 R-Divider
31 VCC9 PWR Power Supply for PLL2 Phase Detector and Charge
Pump
32 CPout2 O ANLG Charge Pump2 Output
33 VCC10 PWR Power Supply for VCO Divider and PLL2 N-Divider
34 CLKin0_LOS O LVCMOS Status of CLKin0 reference clock input
35 CLKin1_LOS O LVCMOS Status of CLKin1 reference clock input
36 Bias I ANLG Bias Bypass. AC coupled with 1 µF capacitor to Vcc1
37 VCC11 PWR Power Supply for CLKout1
38 CLKout1 O LVPECL/LVCMOS Clock Channel 1 Output
39 CLKout1* O LVPECL/LVCMOS Clock Channel 1* Output
40 VCC12 PWR Power Supply for CLKout2
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LMK04000 Family
Pin Number Name(s) I/O Type Description
41 CLKout2 O LVPECL/LVCMOS Clock Channel 2 Output
42 CLKout2* O LVPECL/LVCMOS Clock Channel 2* Output
43 VCC13 PWR Power Supply for CLKout3
44 CLKout3 O LVPECL Clock Channel 3 Output
45 CLKout3* O LVPECL Clock Channel 3* Output
46 VCC14 PWR Power Supply for CLKout4
47 CLKout4 O LVDS/LVPECL Clock Channel 4 Output
48 CLKout4* O LVDS/LVPECL Clock Channel 4* Output
DAP DAP DIE ATTACH PAD, connect to GND
Note 1: The reference clock inputs may be either AC or DC coupled.
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LMK04000 Family
7.0 Absolute Maximum Ratings (Note 2, Note 3, Note 4)
If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors
for availability and specifications.
Parameter Symbol Ratings Units
Supply Voltage (Note 5)VCC -0.3 to 3.6 V
Input Voltage VIN -0.3 to (VCC + 0.3) V
Storage Temperature Range TSTG -65 to 150 °C
Lead Temperature (solder 4 sec) TL+260 °C
Differential Input Current (CLKinX/X*, OSCin/
OSCin*) IIN ± 5 mA
Note 2: "Absolute Maximum Ratings" indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device
is intended to be functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics.
The guaranteed specifications apply only to the test conditions listed.
Note 3: This device is a high performance RF integrated circuit with an ESD rating up to 8 KV Human Body Model, up to 300 V Machine Model and up to 1,250
V Charged Device Model and is ESD sensitive. Handling and assembly of this device should only be done at ESD-free workstations.
Note 4: Stresses in excess of the absolute maximum ratings can cause permanent or latent damage to the device. These are absolute stress ratings only.
Functional operation of the device is only implied at these or any other conditions in excess of those given in the operation sections of the data sheet. Exposure
to absolute maximum ratings for extended periods can adversely affect device reliability.
Note 5: Never to exceed 3.6 V.
8.0 Package Thermal Resistance
Package θJA θJ-PAD (Thermal Pad)
48-Lead LLP (Note 6) 27.4° C/W 5.8° C/W
Note 6: Specification assumes 16 thermal vias connect the die attach pad to the embedded copper plane on the 4-layer JEDEC board. These vias play a key
role in improving the thermal performance of the LLP. It is recommended that the maximum number of vias be used in the board layout.
9.0 Recommended Operating Conditions
Parameter Symbol Condition Min Typical Max Unit
Ambient
Temperature TAVCC = 3.3 V -40 25 85 °C
Supply Voltage VCC 3.15 3.3 3.45 V
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LMK04000 Family
10.0 Electrical Characteristics
(3.15 V ≤ VCC ≤ 3.45 V, -40 °C ≤ TA ≤ 85 °C. Typical values represent most likely parametric norms at VCC = 3.3 V, TA = 25 °C,
at the Recommended Operating Conditions at the time of product characterization and are not guaranteed.)
Symbol Parameter Conditions Min Typ Max Units
Current Consumption
ICC_PD Power Down Supply Current 1 mA
ICC_CLKS
Supply Current with all clocks
enabled, all delay bypassed,
Fout disabled. (Note 7)
LMK04000, LMK04001,
LMK04002
(Note 8)
380 435
mALMK04010, LMK04011
(Note 8) 378 435
LMK04031, LMK04033
(Note 8) 335 385
CLKin0/0* and CLKin1/1* Input Clock Specifications
fCLKin
Clock Input Frequency
(Note 9)
Manual Select mode 0.001 400 MHz
Auto-Switching mode 1 400
SLEWCLKin
Slew Rate on CLKin
(Note 10)20% to 80% 0.15 0.5 V/ns
VCLKin (Bipolar input buffer
mode)
Input Voltage Swing,
single-ended input
AC coupled to CLKinX;
CLKinX* AC coupled to Ground
(CLKinX_TYPE=0)
0.25 2.0 Vpp
Input Voltage Swing,
differential input
CLKinX and CLKinX* are both
driven, AC coupled.
(CLKinX_TYPE=0)
0.5 3.1 Vpp
VCLKin-offset (Bipolar input
buffer mode)
DC offset voltage between
CLKinX/CLKinX*
|CLKinX-CLKinX*|
Each pin AC coupled
(CLKinX_TYPE=0) 44 mV
VCLKin (MOS input buffer
mode)
Input Voltage Swing, single-
ended input
AC coupled to CLKinX;
CLKinX* AC coupled to Ground
(CLKinX_TYPE=1)
0.25 2.0 Vpp
Input Voltage Swing,
differential input
CLKinX and CLKinX* are both
driven, AC coupled.
(CLKinX_TYPE=1)
0.5 3.1 Vpp
VCLKin- VIH (MOS input buffer
mode) Maximum input voltage
DC coupled to CLKinX;
CLKinX* AC coupled to Ground
(CLKinX_TYPE=1)
2.0 VCC V
VCLKin- VIL (MOS input buffer
mode)
DC coupled to CLKinX;
CLKinX* AC coupled to Ground
(CLKinX_TYPE=1)
0.0 0.4 V
VCLKin-offset (MOS input
buffer mode)
DC offset voltage between
CLKinX/CLKinX*
|CLKinX-CLKinX*|
Each pin AC coupled
(CLKinX_TYPE=1) 294 mV
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LMK04000 Family
Symbol Parameter Conditions Min Typ Max Units
PLL1 Specifications
fPD
PLL1 Phase Detector
Frequency 40 MHz
ICPout1 SOURCE PLL1 Charge Pump Source
Current (Note 11)
VCPout1 = VCC/2,
PLL1_CP_GAIN = 100b 25
µA
VCPout1 = VCC/2,
PLL1_CP_GAIN = 101b 50
VCPout1 = VCC/2,
PLL1_CP_GAIN = 110b 100
VCPout1 = VCC/2,
PLL1_CP_GAIN = 111b 400
PLL1_CP_GAIN = 000b NA
PLL1_CP_GAIN = 001b NA
VCPout1=VCC/2,
PLL1_CP_GAIN = 010b 20
VCPout1=VCC/2,
PLL1_CP_GAIN = 011b 80
ICPout1 SINK PLL1 Charge Pump Sink
Current (Note 11)
VCPout1=VCC/2,
PLL1_CP_GAIN = 100b -25
µA
VCPout1=VCC/2,
PLL1_CP_GAIN = 101b -50
VCPout1=VCC/2,
PLL1_CP_GAIN = 110b -100
VCPout1=VCC/2,
PLL1_CP_GAIN = 111b -400
PLL1_CP_GAIN = 000b NA
PLL1_CP_GAIN = 001b NA
VCPout1=VCC/2,
PLL1_CP_GAIN = 010b -20
VCPout1=VCC/2,
PLL1_CP_GAIN = 011b -80
ICPout1 %MIS Charge Pump Sink / Source
Mismatch VCPout1 = VCC/2, T = 25 °C 3 10 %
ICPout1VTUNE
Magnitude of Charge Pump
Current vs. Charge Pump
Voltage Variation
0.5 V < VCPout1 < VCC - 0.5 V
TA = 25 °C 4 %
ICPout1 %TEMP Charge Pump Current vs.
Temperature Variation 4 %
PLL1 ICPout1 TRI Charge Pump TRI-
STATE®Leakage Current 0.5 V < VCPout < VCC - 0.5 V 5 nA
PLL2 Reference Input (OSCin) Specifications
fOSCin
PLL2 Reference Input
(Note 12)
EN_PLL2_REF 2X = 0
(Note 13) 250 MHz
EN_PLL2_REF 2X = 1 50
SLEWOSCin
PLL2 Reference Clock
minimum slew rate on OSCin 20% to 80% 0.15 0.5 V/ns
VOSCin (Single-ended) Input Voltage for OSCin or
OSCin*
AC coupled; Single-ended
(Unused pin AC coupled to
GND)
0.2 2.0 Vpp
VOSCin (Differential) Differential voltage swing AC coupled 0.4 3.1 Vpp
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LMK04000 Family
Symbol Parameter Conditions Min Typ Max Units
Crystal Oscillator Mode Specifications
fXTAL Crystal Frequency Range 6 20 MHz
ESR Crystal Effective Series
Resistance 6 MHz < FXTAL < 20 MHz 100 Ohms
PXTAL
Crystal Power Dissipation
(Note 14)
Vectron VXB1 crystal, 12.288
MHz, RESR < 40 Ω 200 µW
CIN
Input Capacitance of
LMK040xx OSCin port -40 to +85 °C 6 pF
PLL2 Phase Detector and Charge Pump Specifications
fPD Phase Detector Frequency 100 MHz
ICPoutSOURCE PLL2 Charge Pump Source
Current (Note 11)
VCPout2=VCC/2,
PLL2_CP_GAIN = 00b 100
µA
VCPout2=VCC/2,
PLL2_CP_GAIN = 01b 400
VCPout2=VCC/2,
PLL2_CP_GAIN = 10b 1600
VCPout2=VCC/2,
PLL2_CP_GAIN = 11b 3200
ICPoutSINK PLL2 Charge Pump Sink
Current (Note 11)
VCPout2=VCC/2,
PLL2_CP_GAIN = 00b -100
µA
VCPout2=VCC/2,
PLL2_CP_GAIN = 01b -400
VCPout2=VCC/2,
PLL2_CP_GAIN = 10b -1600
VCPout2=VCC/2,
PLL2_CP_GAIN = 11b -3200
ICPout2%MIS Charge Pump Sink/Source
Mismatch VCPout2=VCC/2, TA = 25 °C 3 10 %
ICPout2VTUNE
Magnitude of Charge Pump
Current vs. Charge Pump
Voltage Variation
0.5 V < VCPout2 < VCC - 0.5 V
TA = 25 °C 4 %
ICPout2%TEMP Charge Pump Current vs.
Temperature Variation 4 %
ICPout2TRI Charge Pump Leakage 0.5 V < VCPout2 < VCC - 0.5 V 10 nA
PN10kHz
PLL 1/f Noise at 10 kHz offset
(Note 15). Normalized to
1 GHz Output Frequency
PLL2_CP_GAIN = 400 µA -117
dBc/Hz
PLL2_CP_GAIN = 3200 µA -122
PN1Hz Normalized Phase Noise
Contribution (Note 16)
PLL2_CP_GAIN = 400 µA -219 dBc/Hz
PLL2_CP_GAIN = 3200 µA -224
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LMK04000 Family
Symbol Parameter Conditions Min Typ Max Units
Internal VCO Specifications
fVCO VCO Tuning Range
LMK040x0 1185 1296
MHz
LMK040x1 1430 1570
LMK040x2 1600 1750
LMK040x3 1840 2160
PVCO
VCO Output power to a
50 Ω load driven by Fout
LMK040x0, TA = 25 °C, single-
ended 3
dBm
LMK040x1, TA = 25 °C, single-
ended 3
LMK040x2, TA = 25 °C, single-
ended 2
LMK040x3, TA = 25 °C, single-
ended 1840 MHz 0
LMK040x3, TA = 25 °C, single-
ended 2160 MHz -5
KVCO
Fine Tuning Sensitivity
(The range displayed in the
typical column indicates the
lower sensitivity is typical at
the lower end of the tuning
range, and the higher tuning
sensitivity is typical at the
higher end of the tuning
range).
LMK040x0 7 to 9
MHz/V
LMK040x1 8 to 11
LMK040x2 9 to 14
LMK040x3 14 to 26
|ΔTCL|
Allowable Temperature Drift
for Continuous Lock
(Note 17)
After programming R15 for
lock, no changes to output
configuration are permitted to
guarantee continuous lock
125 °C
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LMK04000 Family
Symbol Parameter Conditions Min Typ Max Units
Internal VCO Open Loop Phase Noise and Jitter
L(f)Fout
LMK040x0
fVCO = 1185 MHz
SSB Phase Noise
PLL2 = Open Loop
Measured at Fout
Offset = 1 kHz -66
dBc/Hz
Offset = 10 kHz -94
Offset = 100 kHz -119
Offset = 1 MHz -139
Offset = 10 MHz -158
Offset = 20 MHz -163
LMK040x0
fVCO = 1296 MHz
SSB Phase Noise
PLL2 = Open Loop
Measured at Fout
Offset = 1 kHz -64
dBc/Hz
Offset = 10 kHz -91
Offset = 100 kHz -117
Offset = 1 MHz -138
Offset = 10 MHz -157
Offset = 20 MHz -161
LMK040x1
fVCO = 1440 MHz
SSB Phase Noise
PLL2 = Open Loop
Measured at Fout
Offset = 1 kHz -61
dBc/Hz
Offset = 10 kHz -91
Offset = 100 kHz -117
Offset = 1 MHz -138
Offset = 10 MHz -158
Offset = 20 MHz -160
LMK040x1
fVCO = 1560 MHz
SSB Phase Noise
PLL2 = Open Loop
Measured at Fout
Offset = 1 kHz -58
dBc/Hz
Offset = 10 kHz -89
Offset = 100 kHz -115
Offset = 1 MHz -137
Offset = 10 MHz -157
Offset = 20 MHz -162
LMK040x2
fVCO = 1600 MHz
SSB Phase Noise
PLL2 = Open Loop
Measured at Fout
Offset = 1 kHz -63
dBc/Hz
Offset = 10 kHz -91
Offset = 100 kHz -115
Offset = 1 MHz -137
Offset = 10 MHz -156
Offset = 20 MHz -161
LMK040x2
fVCO = 1750 MHz
SSB Phase Noise
PLL2 = Open Loop
Measured at Fout
Offset = 1 kHz -61
dBc/Hz
Offset = 10 kHz -90
Offset = 100 kHz -114
Offset = 1 MHz -136
Offset = 10 MHz -155
Offset = 20 MHz -160
LMK040x3
fVCO = 1840 MHz
SSB Phase Noise
PLL2 = Open Loop
Measured at Fout
Offset = 1 kHz -58
dBc/Hz
Offset = 10 kHz -88
Offset = 100 kHz -113
Offset = 1 MHz -135
Offset = 10 MHz -155
Offset = 20 MHz -158
LMK040x3
fVCO = 2160 MHz
SSB Phase Noise
PLL2 = Open Loop
Measured at Fout
Offset = 1 kHz -54
dBc/Hz
Offset = 10 kHz -84
Offset = 100 kHz -110
Offset = 1 MHz -132
Offset = 10 MHz -154
Offset = 20 MHz -157
www.national.com 14
LMK04000 Family
Symbol Parameter Conditions Min Typ Max Units
Internal VCO Closed Loop Phase Noise and Jitter Specifications using an Instrumentation Quality VCXO
L(f)Fout
LMK040x0 (Note 18)
fVCO = 1200 MHz
SSB Phase Noise
PLL2 = Closed Loop
Measured at Fout
Offset = 1 kHz -111
dBc/Hz
Offset = 10kHz -119
Offset = 100 kHz -121
Offset = 1 MHz -133
Offset = 10 MHz -157
Offset = 20 MHz -162
Offset = 40 MHz -165
LMK040x1 (Note 19)
fVCO = 1500 MHz
SSB Phase Noise
PLL2 = Closed Loop
Measured at Fout
Offset = 1 kHz -110
dBc/Hz
Offset = 10 kHz -117
Offset = 100 kHz -120
Offset = 1 MHz -132
Offset = 10 MHz -156
Offset = 20 MHz -160
Offset = 40 MHz -163
LMK040x2 (Note 20)
fVCO = 1600 MHz
SSB Phase Noise
PLL2 = Closed Loop
Measured at Fout
Offset = 1 kHz -111
dBc/Hz
Offset = 10 kHz -118
Offset = 100 kHz -120
Offset = 1 MHz -132
Offset = 10 MHz -156
Offset = 20 MHz -162
Offset = 40 MHz -165
LMK040x3 (Note 21)
fVCO = 2000 MHz
SSB Phase Noise
PLL2 = Closed Loop
Measured at Fout
Offset = 1 kHz -107
dBc/Hz
Offset = 10 kHz -114
Offset = 100 kHz -117
Offset = 1 MHz -126
Offset = 10 MHz -152
Offset = 20 MHz -156
Offset = 40 MHz -160
JFout
LMK040x0 (Note 18)
fVCO = 1200 MHz
Integrated RMS Jitter
BW = 12 kHz to 20 MHz 105
fs
BW = 100 Hz to 20 MHz 110
LMK040x1 (Note 19)
fVCO = 1500 MHz
Integrated RMS Jitter
BW = 12 kHz to 20 MHz 100
BW = 100 Hz to 20 MHz 105
LMK040x2 (Note 20)
fVCO = 1600 MHz
Integrated RMS Jitter
BW = 12 kHz to 20 MHz 95
BW = 100 Hz to 20 MHz 100
LMK040x3 (Note 21)
fVCO = 2000 MHz
Integrated RMS Jitter
BW = 12 kHz to 20 MHz 105
BW = 100 Hz to 20 MHz 110
15 www.national.com
LMK04000 Family
Symbol Parameter Conditions Min Typ Max Units
CLKout's Internal VCO Closed Loop Phase Noise and Jitter Specifications using an Instrumentation Quality VCXO
L(f)CLKout
LMK040x0 (Note 22)
fCLKout = 250 MHz
SSB Phase Noise
Measured at Clock Outputs
Value is average for all output
types
Offset = 1 kHz -125
dBc/Hz
Offset = 10 kHz -130
Offset = 100 kHz -132
Offset = 1 MHz -148
Offset = 10 MHz -157
LMK040x1 (Note 23)
fCLKout = 250 MHz
SSB Phase Noise
Measured at Clock Outputs
Value is average for all output
types
Offset = 1 kHz -126
Offset = 10 kHz -133
Offset = 100 kHz -136
Offset = 1 MHz -147
Offset = 10 MHz -156
LMK040x2 (Note 24)
fCLKout = 250 MHz
SSB Phase Noise
Measured at Clock Outputs
Value is average for all output
types
Offset = 1 kHz -127
Offset = 10 kHz -133
Offset = 100 kHz -134
Offset = 1 MHz -145
Offset = 10 MHz -157
LMK040x3 (Note 25)
fCLKout = 250 MHz
SSB Phase Noise
Measured at Clock Outputs
Value Is average for all output
types
Offset = 1 kHz -125
Offset = 10 kHz -132
Offset = 100 kHz -135
Offset = 1 MHz -145
Offset = 10 MHz -156
JCLKout
LVPECL/2VPECL/LVDS
LMK040x0 (Note 22)
fCLKout = 250 MHz
Integrated RMS Jitter
BW = 12 kHz to 20 MHz 130
fs
BW = 100 Hz to 20 MHz 135
LMK040x1 (Note 23)
fCLKout = 250 MHz
Integrated RMS Jitter
BW = 12 kHz to 20 MHz 115
BW = 100 Hz to 20 MHz 120
LMK040x2 (Note 24)
fCLKout = 250 MHz
Integrated RMS Jitter
BW = 12 kHz to 20 MHz 130
BW = 100 Hz to 20 MHz 135
LMK040x3 (Note 25)
fCLKout = 250 MHz
Integrated RMS Jitter
BW = 12 kHz to 20 MHz 125
BW = 100 Hz to 20 MHz 130
JCLKout
LVCMOS
LMK040x0 (Note 22)
fCLKout = 250 MHz
Integrated RMS Jitter
BW = 12 kHz to 20 MHz 140
fs
BW = 100 Hz to 20 MHz 145
LMK040x1 (Note 23)
fCLKout = 250 MHz
Integrated RMS Jitter
BW = 12 kHz to 20 MHz 110
BW = 100 Hz to 20 MHz 115
LMK040x2 (Note 24)
fCLKout = 250 MHz
Integrated RMS Jitter
BW = 12 kHz to 20 MHz 130
BW = 100 Hz to 20 MHz 135
LMK040x3 (Note 25)
fCLKout = 250 MHz
Integrated RMS Jitter
BW = 12 kHz to 20 MHz 120
BW = 100 Hz to 20 MHz 125
www.national.com 16
LMK04000 Family
Symbol Parameter Conditions Min Typ Max Units
CLKout's Internal VCO Closed Loop Jitter Specifications using a Commercial Quality VCXO
JCLKout
LVPECL/2VPECL
LMK040x0 (Note 26, Note 30)
fCLKout = 250 MHz
Integrated RMS Jitter
BW = 12 kHz to 20 MHz 140 200
fs
BW = 100 Hz to 20 MHz 185
LMK040x1 (Note 27, Note 30)
fCLKout = 250 MHz
Integrated RMS Jitter
BW = 12 kHz to 20 MHz 130 200
BW = 100 Hz to 20 MHz 190
LMK040x2 (Note 28, Note 30)
fCLKout = 250 MHz
Integrated RMS Jitter
BW = 12 kHz to 20 MHz 150 200
BW = 100 Hz to 20 MHz 190
LMK040x3 (Note 29, Note 30)
fCLKout = 250 MHz
Integrated RMS Jitter
BW = 12 kHz to 20 MHz 145 200
BW = 100 Hz to 20 MHz 200
JCLKout
LVDS
LMK040x1 (Note 27)
fCLKout = 250 MHz
Integrated RMS Jitter
BW = 12 kHz to 20 MHz 130
fs
BW = 100 Hz to 20 MHz 190
LMK040x3 (Note 29)
fCLKout = 250 MHz
Integrated RMS Jitter
BW = 12 kHz to 20 MHz 145
BW = 100 Hz to 20 MHz 200
JCLKout
LVCMOS
LMK040x0 (Note 26)
fCLKout = 250 MHz
Integrated RMS Jitter
BW = 12 kHz to 20 MHz 150
fs
BW = 100 Hz to 20 MHz 190
LMK040x1 (Note 27)
fCLKout = 250 MHz
Integrated RMS Jitter
BW = 12 kHz to 20 MHz 125
BW = 100 Hz to 20 MHz 185
LMK040x2 (Note 28)
fCLKout = 250 MHz
Integrated RMS Jitter
BW = 12 kHz to 20 MHz 150
BW = 100 Hz to 20 MHz 190
LMK040x3 (Note 29)
fCLKout = 250 MHz
Integrated RMS Jitter
BW = 12 kHz to 20 MHz 145
BW = 100 Hz to 20 MHz 195
17 www.national.com
LMK04000 Family
Symbol Parameter Conditions Min Typ Max Units
CLKout's Internal VCO Closed Loop Jitter Specifications using the Integrated Low Noise Crystal Oscillator Circuit
JCLKout
LVPECL/2VPECL/LVDS
LMK040x0 (Note 31)
fCLKout = 245.76 MHz
Integrated RMS Jitter
BW = 12 kHz to 20 MHz 190
fs
BW = 100 Hz to 20 MHz 230
LMK040x1 (Note 32)
fCLKout = 245.76 MHz
Integrated RMS Jitter
BW = 12 kHz to 20 MHz 200
BW = 100 Hz to 20 MHz 230
LMK040x2 (Note 33)
fCLKout = 245.76 MHz
Integrated RMS Jitter
BW = 12 kHz to 20 MHz 195
BW = 100 Hz to 20 MHz 230
LMK040x3 (Note 34)
fCLKout = 245.76 MHz
Integrated RMS Jitter
BW = 12 kHz to 20 MHz 245
BW = 100 Hz to 20 MHz 260
JCLKout
LVCMOS
LMK040x0 (Note 31)
fCLKout = 245.76 MHz
Integrated RMS Jitter
BW = 12 kHz to 20 MHz 195
fs
BW = 100 Hz to 20 MHz 230
LMK040x1 (Note 32)
fCLKout = 245.76 MHz
Integrated RMS Jitter
BW = 12 kHz to 20 MHz 195
BW = 100 Hz to 20 MHz 220
LMK040x2 (Note 33)
fCLKout = 245.76 MHz
Integrated RMS Jitter
BW = 12 kHz to 20 MHz 195
BW = 100 Hz to 20 MHz 230
LMK040x3 (Note 34)
fCLKout = 245.76 MHz
Integrated RMS Jitter
BW = 12 kHz to 20 MHz 240
BW = 100 Hz to 20 MHz 260
Symbol Parameter Conditions Min Typ Max Units
Digital Inputs (CLKuWire, DATAuWire, LEuWire)
VIH High-Level Input Voltage 1.6 VCC V
VIL Low-Level Input Voltage 0.4 V
IIH High-Level Input Current VIH = VCC -5 25 µA
IIL Low-Level Input Current VIL = 0 -5.0 5.0 µA
Digital Inputs (GOE, SYNC*)
VIH High-Level Input Voltage 1.6 VCC V
VIL Low-Level Input Voltage 0.4 V
IIH High-Level Input Current VIH = VCC -5.0 5.0 µA
IIL Low-Level Input Current VIL = 0 -40.0 5.0 µA
Digital Outputs (CLKinX_LOS, LD)
VOH High-Level Output Voltage IOH = -500 µA VCC - 0.4 V
VOL Low-Level Output Voltage IOL = 500 µA 0.4 V
www.national.com 18
LMK04000 Family
Symbol Parameter Conditions Min Typ Max Units
Default Power On Reset Clock Output Frequency
fCLKout-startup
Default output clock frequency
at device power on
CLKout2, LM040x0 50
MHz
CLKout2, LM040x1 62
CLKout2, LM040x2 68
CLKout2, LM040x3 81
LVDS Clock Outputs (CLKoutX)
fCLKout
Maximum Frequency
(Note 35)RL = 100 Ω 1080 MHz
TSKEW
CLKoutX to CLKoutY
(Note 36)
LVDS-LVDS, T = 25 °C,
FCLK = 800 MHz, RL= 100 Ω 30 ps
VOD Differential Output Voltage
R = 100 Ω differential
termination, AC coupled to
receiver input,
FCLK = 800 MHz,
T = 25 °C
250 350 450 mV
ΔVOD
Change in Magnitude of VOD
for complementary output
states
-50 50 mV
VOS Output Offset Voltage 1.125 1.25 1.375 V
ΔVOS
Change in VOS for
complementary output states 35 |mV|
ISA
ISB
Output short circuit current -
single ended
Single-ended output shorted to
GND, T = 25 °C -24 24 mA
ISAB
Output short circuit current -
differential
Complimentary outputs tied
together -12 12 mA
LVPECL Clock Outputs (CLKoutX) (Note 37)
fCLKout
Maximum Frequency
(Note 35) 1080 MHz
TSKEW
CLKoutX to CLKoutY
(Note 36)
LVPECL-to-LVPECL,
T = 25 °C, FCLK = 800 MHz,
each output terminated with
120 Ω to GND.
40 ps
VOH Output High Voltage FCLK = 100 MHz, T = 25 °C
Termination = 50 Ω to
VCC - 2 V
VCC -
0.93 V
VOL Output Low Voltage VCC -
1.82 V
VOD Output Voltage 660 890 965 mV
2VPECL Clock Outputs (CLKoutX)
fCLKout
Maximum Frequency
(Note 35) 1080 MHz
TSKEW
CLKoutX to CLKoutY
(Note 36)
2VPECL-2VPECL, T=25 °C,
FCLK = 800 MHz, each output
terminated with 120 Ω to GND.
40 ps
VOH Output High Voltage FCLK = 100 MHz, T = 25 °C
Termination = 50 Ω to
VCC - 2 V
VCC -
0.95 V
VOL Output Low Voltage VCC -
1.98 V
VOD Output Voltage 800 1030 1200 mV
19 www.national.com
LMK04000 Family
Symbol Parameter Conditions Min Typ Max Units
LVCMOS Clock Outputs (CLKoutX)
fCLKout Maximum Frequency 5 pF Load 250 MHz
VOH Output High Voltage 1 mA Load VCC - 0.1 V
VOL Output Low Voltage 1 mA Load 0.1 V
IOH Output High Current (Source) VCC = 3.3 V, VO = 1.65 V 28 mA
IOL Output Low Current (Sink) VCC = 3.3 V, VO = 1.65 V 28 mA
TSKEW
Skew between any two
LVCMOS outputs, same
channel or different channel
RL = 50 Ω, CL = 10 pF,
T = 25 °C, FCLK = 100 MHz.
(Note 36)
100 ps
DUTYCLK Output Duty Cycle VCC/2 to VCC/2, FCLK = 100
MHz, T = 25 °C (Note 38)45 50 55 %
TROutput Rise Time 20% to 80%, RL = 50 Ω,
CL = 5 pF 400 ps
TFOutput Fall Time 80% to 20%, RL = 50 Ω,
CL = 5 pF 400 ps
Mixed Clock Skew
TSKEW ChanX - ChanY
LVPECL to LVDS skew Same device, T = 25 °C,
250 MHz -230 ps
LVDS to LVCMOS skew Same device, T = 25 °C,
250 MHz 770 ps
LVCMOS to LVPECL skew Same device, T = 25 °C,
250 MHz -540 ps
Microwire Interface Timing
TCS Data to Clock Set Up Time See Microwire Input Timing 25 ns
TCH Data to Clock Hold Time See Microwire Input Timing 8 ns
TCWH Clock Pulse Width High See Microwire Input Timing 25 ns
TCWL Clock Pulse Width Low See Microwire Input Timing 25 ns
TES
Clock to Latch Enable
Set Up Time See Microwire Input Timing 25 ns
TCES Clock to Enable Setup Time See Microwire Input Timing 25 ns
TEW Load Enable Pulse Width See Microwire Input Timing 25 ns
Note 7: Load conditions for output clocks: LVPECL: 50 Ω to VCC-2 V. 2VPECL: 50 Ω to VCC-2.36 V. LVDS: 100 Ω differential. LVCMOS: 10 pF.
Note 8: Additional test conditions for ICC limits: All clock delays disabled, CLKoutX_DIV = 510, PLL1 and PLL2 locked. (See Table 31 for more information)
Note 9: CLKin0 and CLKin1 maximum of 400 MHz is guaranteed by characterization, production tested at 200 MHz.
Note 10: In order to meet the jitter performance listed in the subsequent sections of this data sheet, the minimum recommended slew rate for all input clocks is
0.5 V/ns. This is especially true for single-ended clocks. Phase noise performance will begin to degrade as the clock input slew rate is reduced. However, the
device will function at slew rates down to the minimum listed. When compared to single-ended clocks, differential clocks (LVDS, LVPECL) will be less susceptible
to degradation in phase noise performance at lower slew rates due to their common mode noise rejection. However, it is also recommended to use the highest
possible slew rate for differential clocks to achieve optimal phase noise performance at the device outputs.
Note 11: This parameter is programmable
Note 12: FOSCin maximum frequency guaranteed by characterization. Production tested at 200 MHz.
Note 13: The EN_PLL2_REF2X bit (Register 13) enables/disables a frequency doubler mode for the PLL2 OSCin path.
Note 14: See Application Section discussion of Crystal Power Dissipation.
Note 15: A specification in modeling PLL in-band phase noise is the 1/f flicker noise, LPLL_flicker(f), which is dominant close to the carrier. Flicker noise has a 10
dB/decade slope. PN10kHz is normalized to a 10 kHz offset and a 1 GHz carrier frequency. PN10kHz = LPLL_flicker(10 kHz) - 20log(Fout / 1 GHz), where LPLL_flicker
(f) is the single side band phase noise of only the flicker noise's contribution to total noise, L(f). To measure LPLL_flicker(f) it is important to be on the 10 dB/decade
slope close to the carrier. A high compare frequency and a clean crystal are important to isolating this noise source from the total phase noise, L(f). LPLL_flicker(f)
can be masked by the reference oscillator performance if a low power or noisy source is used. The total PLL inband phase noise performance is the sum of
LPLL_flicker(f) and LPLL_flat(f).
Note 16: A specification modeling PLL in-band phase noise. The normalized phase noise contribution of the PLL, LPLL_flat(f), is defined as: PN1HZ=LPLL_flat
(f)-20log(N)-10log(fCOMP). LPLL_flat(f) is the single side band phase noise measured at an offset frequency, f, in a 1 Hz bandwidth and fCOMP is the phase detector
frequency of the synthesizer. LPLL_flat(f) contributes to the total noise, L(f).
Note 17: Maximum Allowable Temperature Drift for Continuous Lock is how far the temperature can drift in either direction from the value it was at the time that
the R0 register was last programmed, and still have the part stay in lock. The action of programming the R0 register, even to the same value, activates a frequency
calibration routine. This implies the part will work over the entire frequency range, but if the temperature drifts more than the maximum allowable drift for continuous
lock, then it will be necessary to reload the R0 register to ensure it stays in lock. Regardless of what temperature the part was initially programmed at, the
temperature can never drift outside the frequency range of -40 °C to 85 °C without violating specifications.
www.national.com 20
LMK04000 Family
Note 18: For LMK040x0, fVCO = 1200 MHz. PLL1 is powered down. A 100 MHz Wenzel XO (model: 501-04623G) drives the OSCin input of PLL2. PLL2 parameters:
VCO_DIV = 3, N2 = 5, R2 = 1, FDET = 100 MHz, ICP2 = 1.6 mA, C1 = 22 pF, C2 = 5.6 nF, R2 = 1.8 kΩ, LBW = 268 kHz, PM = 75°. Wenzel XO phase noise: 100
Hz: -132 dBc/Hz; 1 kHz: -147 dBc/Hz; 10 kHz: -159 dBc/Hz; 100 kHz: -167 dBc/Hz.
Note 19: For LMK040x1, fVCO = 1500 MHz. PLL1 is powered down. A 100 MHz Wenzel XO (model: 501-04623G) drives the OSCin input of PLL2. PLL2 parameters:
VCO_DIV = 3, N2 = 5, R2 = 1, FDET = 100 MHz, ICP2 = 1.6 mA, C1 = 22 pF, C2 = 5.6 nF, R2 = 1.8 kΩ, LBW = 268 kHz, PM = 75°. Wenzel XO phase noise: 100
Hz: -132 dBc/Hz; 1 kHz: -147 dBc/Hz; 10 kHz: -159 dBc/Hz; 100 kHz: -167 dBc/Hz.
Note 20: For LMK040x2, fVCO = 1600 MHz. PLL1 is powered down. A 100 MHz Wenzel XO (model: 501-04623G) drives the OSCin input of PLL2. PLL2 parameters:
VCO_DIV = 2, N2 = 8, R2 = 1, FDET = 100 MHz, ICP2 = 1.6 mA, C1 = 22 pF, C2 = 5.6 nF, R2 = 1.8 kΩ, LBW = 252 kHz, PM = 76°. Wenzel XO phase noise: 100
Hz: -132 dBc/Hz; 1 kHz: -147 dBc/Hz; 10 kHz: -159 dBc/Hz; 100 kHz: -167 dBc/Hz.
Note 21: For LMK040x3, fVCO = 2000 MHz. PLL1 is powered down. A 100 MHz Wenzel XO (model: 501-04623G) drives the OSCin input of PLL2. PLL2 parameters:
VCO_DIV = 2, N2 = 10, R2 = 1, FDET = 100 MHz, ICP2 = 1.6 mA, C1 = 22 pF, C2 = 5.6 nF, R2 = 1.8 kΩ, LBW = 434 kHz, PM = 69°. Wenzel XO phase noise:
100 Hz: -132 dBc/Hz; 1 kHz: -147 dBc/Hz; 10 kHz: -159 dBc/Hz; 100 kHz: -167 dBc/Hz.
Note 22: For LMK040x0, fVCO = 1250 MHz. PLL1 is powered down. A 100 MHz Wenzel XO (model: 501-04623G) drives the OSCin input of PLL2. PLL2 parameters:
VCO_DIV = 5, N2 = 5, R2 = 2, FDET = 50 MHz, ICP2 = 3.2 mA, C1 = 22 pF, C2 = 5.6 nF, R2 = 1.8 kΩ, LBW = 251 kHz, PM = 76°. Wenzel XO phase noise: 100
Hz: -132 dBc/Hz; 1 kHz: -147 dBc/Hz; 10 kHz: -159 dBc/Hz; 100 kHz: -167 dBc/Hz. CLKoutX_DIV = Bypass. CLKout_DLY = OFF.
Note 23: For LMK040x1, fVCO = 1500 MHz. PLL1 is powered down. A 100 MHz Wenzel XO (model: 501-04623G) drives the OSCin input of PLL2. PLL2 parameters:
VCO_DIV = 3, N2 = 5, R2 = 1, FDET = 100 MHz, ICP2 = 1.6 mA, C1 = 22 pF, C2 = 5.6 nF, R2 = 1.8 kΩ, LBW = 268 kHz, PM = 75°. Wenzel XO phase noise: 100
Hz: -132 dBc/Hz; 1 kHz: -147 dBc/Hz; 10 kHz: -159 dBc/Hz; 100 kHz: -167 dBc/Hz. CLKoutX_DIV = 2. CLKout_DLY = OFF.
Note 24: For LMK040x2, fVCO = 1750 MHz. PLL1 is powered down. A 100 MHz Wenzel XO (model: 501-04623G) drives the OSCin input of PLL2. PLL2 parameters:
VCO_DIV = 7, N2 = 5, R2 = 2, FDET = 50 MHz, ICP2 = 1.6 mA, C1 = 22 pF, C2 = 5.6 nF, R2 = 1.8 kΩ, LBW = 354 kHz, PM = 73°. Wenzel XO phase noise: 100
Hz: -132 dBc/Hz; 1 kHz: -147 dBc/Hz; 10 kHz: -159 dBc/Hz; 100 kHz: -167 dBc/Hz. CLKoutX_DIV = Bypass. CLKout_DLY = OFF.
Note 25: For LMK040x3, fVCO = 2000 MHz. PLL1 is powered down. A 100 MHz Wenzel XO (model: 501-04623G) drives the OSCin input of PLL2. PLL2 parameters:
VCO_DIV = 2, N2 = 10, R2 = 1, FDET = 100 MHz, ICP2 = 1.6 mA, C1 = 22 pF, C2 = 5.6 nF, R2 = 1.8 kΩ, LBW = 434 kHz, PM = 69°. Wenzel XO phase noise:
100 Hz: -132 dBc/Hz; 1 kHz: -147 dBc/Hz; 10 kHz: -159 dBc/Hz; 100 kHz: -167 dBc/Hz. CLKoutX_DIV = 4. CLKout_DLY = OFF.
Note 26: For LMK040x0, FVCO = 1250 MHz. PLL1 parameters: FDET = 1 MHz, ICP1 = 100 µA, loop bandwidth = 20 Hz. A 100 MHz VCXO drives the OSCin input
of PLL2. PLL2 parameters: VCO_DIV = 5, N2 = 5, R2 = 2, FDET = 50 MHz, ICP2 = 3.2 mA, C1 = 0 pF, C2 = 12 nF, R2 = 1.8 kΩ, LBW = 254 kHz, PM = 81°.
CLKDIST parameters: CLKoutX_DIV = Bypass, CLKout_DLY = OFF. VCXO phase noise: 100 Hz: -100 dBc/Hz; 1 kHz: -128 dBc/Hz; 10 kHz: -144 dBc/Hz; 100
kHz: -147 dBc/Hz.
Note 27: For LMK040x1, FVCO = 1500 MHz. PLL1 parameters: FDET = 1 MHz, ICP1 = 100 µA, loop bandwidth = 20 Hz. A 100 MHz VCXO drives the OSCin input
of PLL2. PLL2 parameters: VCO_DIV = 3, N2 = 5, R2 = 1, FDET = 100 MHz, ICP2 = 1.6 mA, C1 = 0 pF, C2 = 12 nF, R2 = 1.8 kΩ, LBW = 271 kHz, PM = 80°.
CLKDIST parameters: CLKoutX_DIV = 2, CLKout_DLY = OFF. VCXO phase noise: 100 Hz: -100 dBc/Hz; 1 kHz: -128 dBc/Hz; 10 kHz: -144 dBc/Hz; 100 kHz:
-147 dBc/Hz.
Note 28: For LMK040x2, FVCO = 1750 MHz. PLL1 parameters: FDET = 1 MHz, ICP1 = 100 µA, loop bandwidth = 20 Hz. A 100 MHz VCXO drives the OSCin input
of PLL2. PLL2 parameters: VCO_DIV = 7, N2 = 5, R2 = 2, FDET = 50 MHz, ICP2 = 3.2 mA, C1 = 0 pF, C2 = 12 nF, R2 = 1.8 kΩ, LBW = 360 kHz, PM = 79°.
CLKDIST parameters: CLKoutX_DIV = Bypass, CLKout_DLY = OFF. VCXO phase noise: 100 Hz: -100 dBc/Hz; 1 kHz: -128 dBc/Hz; 10 kHz: -144 dBc/Hz; 100
kHz: -147 dBc/Hz.
Note 29: For LMK040x3, FVCO = 2000 MHz. PLL1 parameters: FDET = 1 MHz, ICP1 = 100 µA, loop bandwidth = 20 Hz. A 100 MHz VCXO drives the OSCin input
of PLL2. PLL2 parameters: VCO_DIV = 2, N2 = 10, R2 = 1, FDET = 100 MHz, ICP2 = 1.6 mA, C1 = 0 pF, C2 = 12 nF, R2 = 1.8 kΩ, LBW = 445 kHz, PM = 76°.
CLKDIST parameters: CLKoutX_DIV = 4, CLKout_DLY = OFF. VCXO phase noise: 100 Hz: -100 dBc/Hz; 1 kHz: -128 dBc/Hz; 10 kHz: -144 dBc/Hz; 100 kHz:
-147 dBc/Hz.
Note 30: Max jitter specification applies to CH3 (LVPECL) output and guaranteed by test in production.
Note 31: For LMK040x0, FVCO = 1228.8 MHz. PLL1 parameters: FDET = 1.024 MHz, ICP1 = 100 µA, loop bandwidth = 20 Hz. A 12.288 MHz Vectron crystal
(model: VXB1-1127-12M288000) and tuning circuitry is used with on-chip XO circuitry. PLL2 parameters: VCO_DIV = 5, N2 = 10, EN_PLL2_REF2X = 1, FDET =
24.576 MHz, ICP2 = 3.2 mA, C1 = 0 pF, C2 = 12 nF, R2 = 1.8 kΩ, R3 = 600 Ω, R4 = 10 kΩ, C3 = 150 pF, C4 = 60 pF, LBW = 109 kHz, PM = 43°, CLKoutX_DIV
= 2, CLKout_DLY = OFF.
Note 32: For LMK040x1, FVCO = 1474.56 MHz. PLL1 parameters: FDET = 1.024 MHz, ICP1 = 100 µA, loop bandwidth = 20 Hz. A 12.288 MHz Ecliptek crystal
(model: ECX-6465) and tuning circuitry is used with on-chip XO circuitry. PLL2 parameters: VCO_DIV = 3, N2 = 20, EN_PLL2_REF2X = 1, FDET = 24.576 MHz,
ICP2 = 3.2 mA, C1 = 0 pF, C2 = 12 nF, R2 = 1.8 kΩ, R3 = 600 Ω, R4 = 10 kΩ, C3 = 150 pF, C4 = 60 pF, LBW = 103 kHz, PM = 44°, CLKoutX_DIV = 2, CLKout_DLY
= OFF.
Note 33: For LMK040x2, FVCO = 1720.32 MHz. PLL1 parameters: FDET = 1.024 MHz, ICP1 = 100 µA, loop bandwidth = 20 Hz. A 12.288 MHz Vectron crystal
(model: VXB1-1127-12M288000) and tuning circuitry is used with on-chip XO circuitry. PLL2 parameters: VCO_DIV = 7, N2 = 10, EN_PLL2_REF2X = 1, FDET =
24.576 MHz, ICP2 = 3.2 mA, C1 = 0 pF, C2 = 12 nF, R2 = 1.8 kΩ, R3 = 600 Ω, R4 = 10 kΩ, C3 = 150 pF, C4 = 60 pF, LBW = 120 kHz, PM = 40°, CLKoutX_DIV
= 2, CLKout_DLY = OFF.
Note 34: For LMK040x3, FVCO = 1966.08 MHz. PLL1 parameters: FDET = 1.024 MHz, ICP1 = 100 µA, loop bandwidth = 20 Hz. A 12.288 MHz Ecliptek crystal
(model: ECX-6465) and tuning circuitry is used with on-chip XO circuitry. PLL2 parameters: VCO_DIV = 4, N2 = 20, EN_PLL2_REF2X = 1, FDET = 24.576 MHz,
ICP2 = 3.2 mA, C1 = 0 pF, C2 = 12 nF, R2 = 1.8 kΩ, R3 = 600 Ω, R4 = 10 kΩ, C3 = 150 pF, C4 = 60 pF, LBW = 91 kHz, PM = 47°, CLKoutX_DIV = 2, CLKout_DLY
= OFF.
Note 35: For Clock output frequencies > 1 GHz, the maximum allowable clock delay is limited to ½ of a period, or, 0.5/FCLKoutX.
Note 36: Equal loading and identical channel configuration on each channel is required for specification to be valid. Specification not valid for delay mode.
Note 37: LVPECL/2VPECL is programmable for all NSIDs.
Note 38: Guaranteed by characterization.
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LMK04000 Family
11.0 Serial Data Timing Diagram
30027103
Register programming information on the DATAuWire pin is clocked into a shift register on each rising edge of the CLKuWire signal.
On the rising edge of the LEuWire signal, the register is sent from the shift register to the register addressed. A slew rate of at least
30 V/µs is recommended for these signals. After programming is complete the CLKuWire, DATAuWire, and LEuWire signals should
be returned to a low state. If the CLKuWire or DATAuWire lines are toggled while the VCO is in lock, as is sometimes the case
when these lines are shared with other parts, the phase noise may be degraded during this programming.
12.0 Charge Pump Current Specification Definitions
30027131
I1 = Charge Pump Sink Current at VCPout = VCC - ΔV
I2 = Charge Pump Sink Current at VCPout = VCC/2
I3 = Charge Pump Sink Current at VCPout = ΔV
I4 = Charge Pump Source Current at VCPout = VCC - ΔV
I5 = Charge Pump Source Current at VCPout = VCC/2
I6 = Charge Pump Source Current at VCPout = ΔV
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LMK04000 Family
ΔV = Voltage offset from the positive and negative supply rails. Defined to be 0.5 V for this device.
12.1 CHARGE PUMP OUTPUT CURRENT MAGNITUDE VARIATION VS. CHARGE PUMP OUTPUT VOLTAGE
30027132
12.2 CHARGE PUMP SINK CURRENT VS. CHARGE PUMP OUTPUT SOURCE CURRENT MISMATCH
30027133
12.3 CHARGE PUMP OUTPUT CURRENT MAGNITUDE VARIATION VS. TEMPERATURE
30027134
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LMK04000 Family
13.0 Typical Performance Characteristics
13.1 CLOCK OUTPUT AC CHARACTERISTICS
LVDS VOD vs. Frequency
30027146
LVPECL VOD vs. Frequency
30027144
LVCMOS Vpp vs. Frequency
30027145
Typical Dynamic ICC, LVCMOS Driver, VCC = 3.3 V,
Temp = 25 °C, CL= 5 pF
30027162
Clock Channel Delay Noise Floor vs. Frequency (Note 40)
30027149
Clock Output Noise Floor vs. Frequency (Note 39)
30027148
Note 39: To estimate this noise, only the output frequency is required. Divide value and input frequency are not relevant.
Note 40: The noise of the delay block is independent of output type and only applies if the delay is enabled. The noise floor, due to the distribution section
accounting for the delay noise, can be calculated as: Total Output Noise = 10 x log(10Output Buffer Noise/10 + 10Delay Noise Floor/10).
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LMK04000 Family
13.1 Clock Output AC Characteristics (continued)
Typical LVDS Phase Noise, FCLK = 250 MHz, RMS Jitter = 192 fs (100 Hz to 20 MHz) (Note 41)
30027141
Typical LVPECL Phase Noise, FCLK = 250 MHz, RMS Jitter = 196 fs (100 Hz to 20 MHz) (Note 41)
30027142
Typical LVCMOS Phase Noise, FCLK = 250 MHz, RMS Jitter = 188 fs (100 Hz to 20 MHz) (Note 41)
30027143
Note 41: Reference clock = 10 MHz, PLL1_R = 10, PLL1_N = 100, PLL1_CP_GAIN = 100 µA, PLL1 Loop BW = 20 Hz, VCXO = 100 MHz Crystek CVPD-920-100,
PLL2_R = 2, PLL2_N = 10, PLL2_CP_GAIN = 1600 µA, PLL2 Loop BW = 137 kHz, fVCO = 1500 MHz, VCO_DIV = 3, CLKoutX_DIV = 2, CLK_DLY = OFF.
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LMK04000 Family
14.0 Features
14.1 SYSTEM ARCHITECTURE
The cascaded PLL architecture of the LMK040xx was chosen
to provide the lowest jitter performance over the widest range
of output frequencies and phase noise offset frequencies. The
first stage PLL (PLL1) is used in conjunction with an external
reference clock and an external VCXO to provide a frequency
accurate, low phase noise reference clock for the second
stage frequency multiplication PLL (PLL2). PLL1 typically us-
es a narrow loop bandwidth (10 Hz to 200 Hz) to retain the
frequency accuracy of the reference clock input signal while
at the same time suppressing the higher offset frequency
phase noise that the reference clock may have accumulated
along its path or from other circuits. The “cleaned” reference
clock frequency accuracy is combined with the low phase
noise of an external VCXO to provide the reference input to
PLL2. The low phase noise reference provided to PLL2 allows
it to use wider loop bandwidths (50 kHz to 200 kHz). The cho-
sen loop bandwidth for PLL2 should take best advantage of
the superior high offset frequency phase noise profile of the
internal VCO and the good low offset frequency phase noise
of the reference VCXO for PLL2. Ultra low jitter is achieved
by allowing the external VCXO’s phase noise to dominate the
final output phase noise at low offset frequencies and the in-
ternal VCO’s phase noise to dominate the final output phase
noise at high offset frequencies. This results in best overall
phase noise and jitter performance.
14.2 REDUNDANT REFERENCE INPUTS (CLKin0/
CLKin0*, CLKin1/CLKin1*)
The LMK040xx has two LVDS/LVPECL/LVCMOS compatible
reference clock inputs for PLL1, CLKin0 and CLKin1. The se-
lection of the preferred input may be fixed to either CLKin0 or
CLKin1, or may be configured to employ one of two automatic
switching modes when redundant clock signals are present.
The PLL1 reference clock input buffers may also be individ-
ually configured as either a CMOS buffered input or a bipolar
buffered input.
14.3 PLL1 CLKinX (X=0,1) LOSS OF SIGNAL (LOS)
When either of the two auto-switching modes is selected for
the reference clock input mode, the signal status of the se-
lected reference clock input is indicated by the state of the
CLKinX_LOS (loss-of-signal) output. These outputs may be
configured as either CMOS (active HIGH on loss-of-signal),
NMOS open-drain or PMOS open-drain. If PLL1 was origi-
nally locked and then both reference clocks go away, then the
frequency accuracy of the LMK04000 device will be set by the
absolute tuning range of the VCXO used on PLL1. The ab-
solute tuning range of the VCXO can be determined by mul-
tiplying its' tuning constant by the charge pump voltage.
14.4 INTEGRATED LOOP FILTER POLES
The LMK040xx features programmable 3rd and 4th order
loop filter poles for PLL2. When enabled, internal resistors
and capacitor values may be selected from a fixed range of
values to achieve either 3rd or 4th order loop filter response.
These programmable components compliment external com-
ponents mounted near the chip.
14.5 CLOCK DISTRIBUTION
The LMK040xx features a clock distribution block with a min-
imum of five outputs that are a mixture of LVPECL, 2VPECL,
LVDS, and LVCMOS. The exact combination is determined
by the part number. The 2VPECL is a National Semiconductor
proprietary configuration that produces a 2 Vpp differential
swing for compatibility with many data converters. More than
five outputs may be available for device versions that offer
dual LVCMOS outputs.
14.6 CLKout DIVIDE (CLKoutX_DIV, X = 0 to 4)
Each individual clock distribution channel includes a channel
divider. The range of divide values is 2 to 510, in steps of 2.
“Bypass” mode operates as a divide-by-1.
14.7 CLKout DELAY (CLKoutX_DLY, X = 0 to 4)
Each individual clock distribution channel includes a delay
adjustment. Clock output delay registers (CLKoutX_DLY)
support a nominal 150 ps step size and range from 0 to 2250
ps of total delay.
14.8 GLOBAL CLOCK OUTPUT SYNCHRONIZATION
(SYNC*)
The SYNC* input is used to synchronize the active clock out-
puts. When SYNC* is held in a logic low state, the outputs are
also held in a logic low state. When SYNC* goes high, the
clock outputs are activated and will transition to a high state
simultaneously with one another.
SYNC* must be held low for greater than one clock cycle of
the Clock Distribution Path. After this low event has been reg-
istered, the outputs will not reflect the low state for four more
cycles. Similarly after SYNC* becomes high, the outputs will
simultaneously transition high after four Clock Distribution
Path cycles have passed. See Figure 1 for further detail.
30027104
FIGURE 1. Clock Output synchronization using the
SYNC* pin
14.9 GLOBAL OUTPUT ENABLE AND LOCK DETECT
Each Clock Output Channel may be either enabled or put into
a high impedance state via the Clock Output Enable control
bit (one for each channel). Each output enable control bit is
gated with the Global Output Enable input pin (GOE). The
GOE pin provides an internal pull-up so that if it is un-termi-
nated externally, then the clock output states are determined
by the Clock Channel Output Enable Register bits. All clock
outputs can be disabled simultaneously if the GOE pin is
pulled low by an external signal.
TABLE 1. Clock Output Control
CLKoutX
_EN bit
EN_CLKout
_Global bit GOE pin CLKoutX
Output State
1 1 Low Low
Don't care 0 Don't care Off
0 Don't care Don't care Off
1 1 High / No
Connect Enabled
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LMK04000 Family
The Lock Detect (LD) signal can be connected to the GOE
pin in which case all outputs are disabled automatically if the
synthesizer is not locked. See Section 16.3.2 EN_CLKoutX:
Clock Channel Output Enable and also Section 17.1 SYS-
TEM LEVEL DIAGRAM for actual implementation details.
The Lock Detect (LD) pin can be programmed to output a
‘High’ when both PLL1 and PLL2 are locked, or only when
PLL1 is locked or only when PLL2 is locked.
15.0 Functional Description
15.1 ARCHITECTURAL OVERVIEW
The LMK040xx chip consists of two high performance syn-
thesizer blocks (Phase Locked Loop, internal VCO/VCO Di-
vider, and loop filter), source selection, distribution system,
and independent clock output channels.
The Phase Frequency Detector in PLL1 compares the divided
(R Divider 1) system clock signal from the selected CLKinX
and CLKinX* input with the divided (N Divider 1) output of the
external VCXO attached to the PLL2 OSCin port. The external
loop filter for PLL1 should be narrow to provide an ultra clean
reference clock from the external VCXO to the OSCin/OSCin*
pins for PLL2.
The Phase Frequency Detector in PLL2 then compares the
divided (R Divider 2) reference signal from the PLL2 OSCin
port with the divided (N Divider 2 and VCO Divider) output of
the internal VCO. The bandwidth of the external loop filter for
PLL2 should be designed to be wide enough to take advan-
tage of the low in-band phase noise of PLL2 and the low high
offset phase noise of the internal VCO. The VCO output is
passed through a common VCO divider block and placed on
a distribution path for the clock distribution section. It is also
routed to the PLL2_N counter. Each clock output channel al-
lows the user to select a path with a programmable divider
block, a phase synchronization circuit, a programmable de-
lay, and LVDS/LVPECL/2VPECL/LVCMOS compatible out-
put buffers.
15.2 PHASE DETECTOR 1 (PD1)
Phase Detector 1 in PLL1 (PD1) can operate up to 40 MHz.
Since a narrow loop bandwidth should be used for PLL1, the
need to operate at high phase detector rate to lower the in-
band phase noise becomes unnecessary.
15.3 PHASE DETECTOR 2 (PD2)
Phase Detector 2 in PLL2 (PD2) supports a maximum com-
parison rate of 100 MHz, though the actual maximum fre-
quency at the input port (PLL2 OSCin/OSCin*) is 250 MHz.
Operating at highest possible phase detector rate will ensure
low in-band phase noise for PLL2 which in turn produces low-
er total jitter, as the in-band phase noise from the reference
input and PLL are proportional to N2.
15.4 PLL2 FREQUENCY DOUBLER
The PLL2 reference input at the OSCin port may be optionally
routed through a frequency doubler function rather than
through the PLL2_R counter. The maximum phase compari-
son frequency of the PLL2 phase detector is 100 MHz, so the
input to the frequency doubler is limited to a maximum of 50
MHz. The frequency doubler feature allows the phase com-
parison frequency to be increased when a relative low fre-
quency oscillator is driving the OSCin port. By doubling the
PLL2 phase comparison frequency, the in-band PLL2 noise
is reduced by about 3 dB.
15.5 INPUTS / OUTPUTS
15.5.1 PLL1 Reference Inputs (CLKin0 / CLKin0*, CLKin1 /
CLKin1*)
The reference clock inputs for PLL1 may be selected from
either CLKin0 and CLKin1. The user has the capability to
manually select one of the two inputs or to configure an au-
tomatic switching mode operation. A detailed description of
this function is described in the uWire programming section
of this data sheet.
15.5.2 PLL2 OSCin / OSCin* Port
The feedback from the external oscillator being locked with
PLL1 is injected to the PLL2 OSCin/OSCin* pins. This input
may be driven with either a single- ended or differential signal.
If operated in single ended mode, the unused input should be
tied to GND with a 0.1 µF capacitor. Either AC or DC coupling
is acceptable. Internal to the chip, this signal is routed to the
PLL1_N Counter and to the reference input for PLL2. The in-
ternal circuitry of the OSCin port also supports the optional
implementation of a crystal based oscillator circuit. A crystal,
varactor diode and a small number of other external compo-
nents may be used to implement the oscillator. The internal
oscillator circuit is enabled by setting the EN_PLL2_XTAL bit.
15.5.3 CPout1 / CPout2
The CPout1 pin provides the charge pump current output to
drive the loop filter for PLL1. This loop filter should be config-
ured so that the total loop bandwidth for PLL1 is less than 200
Hz. When combined with an external oscillator that has low
phase noise at offsets close to the carrier, PLL1 generates a
reference for PLL2 that is frequency locked to the PLL1 ref-
erence clock but has the phase noise performance of the
oscillator. The CPout2 pin provides the charge pump current
output to drive the loop filter for PLL2. This loop filter should
be configured so that the total loop bandwidth for PLL2 is in
the range of 50 kHz to 200 kHz. See the section on uWire
device control for a description of the charge pump current
gain control.
15.5.4 Fout
The buffered output of the internal VCO is available at the
Fout pin. This is a single-ended output (sinusoid). Each time
the PLL2_N counter value is updated via the uWire interface,
an internal algorithm is triggered that optimizes the VCO per-
formance.
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LMK04000 Family
15.5.5 Digital Lock Detect 1 Bypass
The VCO coarse tuning algorithm requires a stable OSCin
clock (reference clock to PLL2) to frequency calibrate the in-
ternal VCO correctly. In order to ensure a stable OSCin clock,
the first PLL must achieve lock status. A digital lock detect is
used in PLL1 to monitor its lock status. After lock is achieved
by PLL1, the coarse tuning circuitry is enabled and frequency
calibration for the internal VCO begins.
The (DLD_BYP) pin is provided to allow an external bypass
cap to be connected to the digital lock detect 1. This capacitor
will eliminate potential glitches at initial startup of PLL1 due to
unknown phase relationships between the Ncntr1 and Rcntr1.
15.5.6 Bias
Proper bypassing of this pin by a 1 µF capacitor connected to
VCC is important for low noise performance.
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LMK04000 Family
16.0 General Programming
Information
LMK040xx devices are programmed using several 32-bit reg-
isters. Each register consists of a 4-bit address field and 28-
bit data field. The address field is formed by bits 0 through 3
(LSBs) and the data field is formed by bits 4 through 31 (MS-
Bs). The contents of each register are clocked in MSB first (bit
31), and the LSB (bit 0) last. During programming, the LE sig-
nal should be held LOW. The serial data is clocked in on the
rising edge of the CLK signal. After the LSB (bit 0) is clocked
in the LE signal should be toggled LOW-to-HIGH-to-LOW to
latch the contents into the register selected in the address
field. Registers R0-R4, R7, and R8-R15 must be programmed
in order to achieve proper device operation. Figure 2 illus-
trates the serial data timing sequence.
30027103
FIGURE 2. uWire Timing Diagram
To achieve proper frequency calibration, the OSCin port must
be driven with a valid signal before programming Register 15.
Changes to PLL2_R Counter or the OSCin port signal require
Register 15 to be reloaded in order to activate the frequency
calibration process.
16.1 RECOMMENDED PROGRAMMING SEQUENCE
The recommended programming sequence involves pro-
gramming R7 with the reset bit set to 1 (Reg. 7, bit 4) to ensure
the device is in a default state. If R7 is programmed again, the
reset bit should be set to 0. Registers are programmed in or-
der with R15 being the last register programmed. An example
programming sequence is shown below:
•Program R7 with the RESET bit = 1 (b4 = 1). This ensures
that the device is configured with default settings. When
RESET = 1, all other R7 bits are ignored.
- If R7 is programmed again during the initial configuration
of the device, the RESET bit should be cleared (b4 = 0)
•Program R0 through R4 as necessary to configure the
clock outputs as desired. These registers configure clock
channel functions such as the channel multiplexer output
selection, divide value, delay value, and enable/disable
bit.
•Program R5 and R6 with the default values shown in the
register map on the following pages.
•Program R7 with RESET = 0.
•Program R8 through R10 with the default values shown in
the register map on the following pages.
•Program R11 to configure the reference clock inputs
(CLKin0 and CLKin1).
- type, LOS timeout, LOS type, and mode (manual or auto-
switching)
•Program R12 to configure PLL1.
- Charge pump gain, polarity, R counter and N counter
•Program R13 through R15 to configure PLL2 parameters,
crystal mode options, and certain globally asserted
functions.
The following table provides the register map for device pro-
gramming:
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LMK04000 Family
Register Map
Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 1
5
1
4
1
3
1
2
1
1
1
09 8 7 6 5 4 3 2 1 0
Data [31:4] A3 A2 A1 A0
R0 0 0 0 0 0 0 0 1
CLKout0_PECL_LVL
0000CLKout0_
MUX
EN_CLKout0
CLKout0_DIV [7:0] CLKout0_DLY [3:0] 0 0 0 0
R1 0 0 0 0 0 0 0 1
CLKout1_PECL_LVL
CLKout1B_STATE [1:0]
CLKout1A_STATE [1:0]
CLKout1_
MUX [1:0]
EN_CLKout1
CLKout1_DIV [7:0] CLKout1_DLY [3:0] 0 0 0 1
R2 0 0 0 0 0 0 0 1
CLKout2_PECL_LVL
CLKout2B_STATE [1:0]
CLKout2A_STATE [1:0]
CLKout2_
MUX [1:0]
EN_CLKout2
CLKout2_DIV [7:0] CLKout2_DLY [3:0] 0 0 1 0
R3 0 0 0 0 0 0 0 1
CLKout3_PECL_LVL
CLKout3B_STATE [1:0]
CLKout3A_STATE [1:0]
CLKout3_
MUX [1:0]
EN_CLKout3
CLKout3_DIV [7:0] CLKout3_DLY [3:0] 0 0 1 1
R4 0 0 0 0 0 0 0 1
CLKout4_PECL
_LVL
0000CLKout4_
MUX [1:0]
EN_CLKout4
CLKout4_DIV [7:0] CLKout4_DLY [3:0] 0 1 0 0
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LMK04000 Family
Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 1
5
1
4
1
3
1
2
1
1
1
09 8 7 6 5 4 3 2 1 0
R5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1
R6 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 1 1 0
R7 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
RESET
0 1 1 1
R8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0
R9 0 0 0 0 0 0 0 0 1 0 1 0 0 0 1 0 0 0 1 0 1 0 1 0 0 0 0 0 1 0 0 1
R10 0 0
RC_DLD1_Start
0 0 0 0 1 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0
R11 0 0 0 0 0 0 0 0 0 1 1 0 0 1 0 1 0 0 0 0
CLKin1_BUFTYPE
CLKin0_BUFTYPE
LOS_TIMEOUT [1:0]
LOS_TYPE [1:0]
CLKin_SEL [1:0]
1 0 1 1
R12
PLL1_CP_POL
PLL1_CP_GAI
N [2:0] PLL1_R Counter [11:0] PLL1_N Counter [11:0] 1 1 0 0
R13 0 0 0 0 1 0 1 0 0 0
EN_PLL2_XTAL
EN_Fout
0
EN_CLKout_Global,
default=1
POWER DOWN,
default = 0
EN_PLL2_REF2X
PLL2 CP TRI-STATE
PLL1 CP TRI-STATE
PLL2_R4_LF [2:0]
PLL2_R3_LF [2:0]
PLL2_C3_C4_LF [3:0]
1 1 0 1
R14 0 0 0 OSCin_FREQ [7:0] PLL_MUX [4:0] PLL2_R Counter [11:0] 1 1 1 0
R15 0 0 0 1
PLL2_CP
_GAIN
[1:0]
VCO_DIV [3:0] PLL2_N Counter [17:0] 1 1 1 1
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LMK04000 Family
16.2 DEFAULT DEVICE REGISTER SETTINGS AFTER POWER ON/RESET
Table 2 illustrates the default register settings programmed in silicon for the LMK040xx after power on or asserting the reset bit.
TABLE 2. Default Device Register Settings after Power On/Reset
Field Name Default
Value
(decimal)
Default State Field Description Register Bit Location
(MSB:LSB)
CLKoutX_PECL_LVL 0 2VPECL disabled This bit sets LVPECL clock level. Valid
when the clock channel is configured as
LVPECL/2VPECL; otherwise, not relevant.
R0 to R4 23
CLKoutXB_STATE 0 Inverted This field sets the state of output B of an
LVCMOS Clock channel.
R1 to R3 22:21
CLKoutXA_STATE 1 Non-Inverted This field sets the state of output A of an
LVCMOS Clock channel.
R1 to R3 20:19
EN_CLKoutX 0 OFF Clock Channel enable bit. Note: The state
of CLKout2 is ON by default.
R0 to R4 16
Reserved Registers (Note 42) (Note 42) R5,R6,R8
R9,R10
NA
RC_DLD1_Start 1 Enabled Forces the VCO tuning algorithm state
machine to wait until PLL1 is locked.
R10 29
CLKin1_BUFTYPE 1 MOS mode CLKin1 Input Buffer Type R11 11
CLKin0_BUFTYPE 1 MOS mode CLKin0 Input Buffer Type R11 10
LOS_TIMEOUT 1 3 MHz (min.) Selects Lower Reference Clock input
frequency for LOS Detection.
R11 9:8
LOS_TYPE 3 CMOS Selects LOS output type (Note 43) R11 7:6
CLKin_SEL 0 CLKin0 Selects Reference Clock source R11 5:4
PLL1 CP Polarity 1 Positive polarity Selects the charge pump output polarity,
i.e., the tuning slope of the external VCXO
R12 31
PLL1_CP_GAIN 6 100 µA Sets the PLL1 Charge Pump Gain R12 30:28
PLL1_R Counter 1 Divide = 1 Sets divide value for PLL1_R Counter R12 27:16
PLL1_N Counter 1 Divide = 1 Sets divide value for PLL1_N Counter R12 15:4
EN_PLL2_REF2X 0 Disabled Enables or disables the OSCin frequency
doubler path for the PLL2 reference input
R13 16
EN_PLL2_XTAL 0 OFF Enables or Disables internal circuits that
support an external crystal driving the
OSCin pins
R13 21
EN_Fout 0 OFF Enables or disables the VCO output buffer R13 20
CLK Global Enable 1 Enabled Global enable or disable for output clocks R13 18
POWER DOWN 0 Disabled (device
is active)
Device power down control R13 17
PLL2 CP TRI-STATE 0 TRI-STATE
disabled
Enables or disables TRI-STATE for PLL2
Charge Pump
R13 15
PLL1 CP TRI-STATE 0 TRI-STATE
disabled
Enables or disables TRI-STATE for PLL1
Charge Pump
R13 14
OSCin_FREQ 200 200 MHz Source frequency driving OSCin port R14 28:21
PLL_MUX 31 Reserved Selects output routed to LD pin R14 20:16
PLL2_R Counter 1 Divide = 1 Sets Divide value for PLL2_R Counter R14 15:4
PLL2_CP_GAIN 2 1600 µA Sets PLL2 Charge Pump Gain R15 27:26
VCO_DIV 2 Divide = 2 Sets divide value for VCO output divider R15 25:22
PLL2_N Counter 1 Divide = 1 Sets PLL2_N Counter value R15 21:4
Note 42: These registers are reserved. The Power On/Reset values for these registers are shown in the register map and should not be changed during
programming.
Note 43: If the CLKin_SEL value is set to either [0,0] or [0,1], the LOS_TYPE field should be set to [0,0].
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LMK04000 Family
16.3 REGISTER R0 TO R4
Registers R0 through R4 control the five clock outputs. Reg-
ister R0 controls CLKout0, Register R1 controls CLKout1, and
so on. Aside from this, the functions of the bits in these reg-
isters are identical. The X in CLKoutX_MUX, CLKoutX_DIV,
CLKoutX_DLY, and CLKoutX_EN denote the actual clock
output which may be from 0 to 4.
16.3.1 CLKoutX_DIV: Clock Channel Divide Registers
Each of the five clock output channels (0 though 4) has a
dedicated 8-bit divider followed by a fixed divide by 2 that is
used to generate even integer related versions of the distri-
bution path clock frequency (VCO Divider output). If the VCO
Divider value is even then the Channel Divider may be by-
passed (See CLK Output Mux), giving an effective divisor of
1 while preserving a 50% duty cycle output waveform.
TABLE 3. CLKoutX_DIV: Clock Channel Divide Values
CLKoutX_DIV [ 7:0 ] Total Divide Value
b7 b6 b5 b4 b3 b2 b1 b0
0 0 0 0 0 0 0 0 invalid
0 0 0 0 0 0 0 1 2
0 0 0 0 0 0 1 0 4
0 0 0 0 0 0 1 1 6
0 0 0 0 0 1 0 0 8
0 0 0 0 0 1 0 1 10
- - - - -- - - - -
1 1 1 1 1 1 1 1 510
16.3.2 EN_CLKoutX: Clock Channel Output Enable
Each Clock Output Channel may be either enabled or dis-
abled via the Clock Output Enable control bits. Each output
enable control bit is gated with the Global Output Enable input
pin (GOE) and Global Output Enable bit (EN_CLKout_Glob-
al). The GOE pin provides an internal pull-up so that if it is
unterminated externally, the clock output states are deter-
mined by the Clock Output Enable Register bits. All clock
outputs can be set to the low state simultaneously if the GOE
pin is pulled low by an external signal. If EN_CLKout_Global
is programmed to 0 all outputs are turned off. If both GOE and
EN_CLKout_Global are low the clock outputs are turned off.
TABLE 4. EN_CLKoutX: Clock Channel Output Enable
Control Bits
BIT NAME BIT = 1 BIT = 0 DEFAULT
EN_CLKout0 ON OFF OFF
EN_CLKout1 ON OFF OFF
EN_CLKout2 ON OFF ON
EN_CLKout3 ON OFF OFF
EN_CLKout4 ON OFF OFF
EN_CLKout_
Global
According to
individual
channel
settings
All
EN_CLKout
X = OFF
-
Note the default state of CLKout2 is ON after power on or
RESET assertion. The nominal frequency is 62 MHz
(LMK040x1) or 81 MHz (LMK040x3). This is based on a
channel divide value of 12 and default VCO_DIV value of 2.
If an active CLKout2 at power on is inappropriate for the user’s
application, the following method can be employed to shut off
CLKout2 during system initialization:
•When the device is powered on, holding the GOE pin LOW
will disable all clock outputs. The device can be
programmed while the GOE is held LOW. The state of
CLKout2 can be altered during device programming
according to the user’s specific application needs. After
device configuration is complete, the GOE pin should be
set HIGH to enable the active clock channels.
16.3.3 CLKoutX_DLY: Clock Channel Phase Delay
Adjustment
Each output channel has an output delay register that can be
used to introduce a lag relative to the distribution path fre-
quency (VCO Divider output). These registers support a 150
ps stepsize and range from 0 to 2.25 ns of total delay. When
the channel phase delay registers are enabled, a nominal
fixed delay of 300 ps of delay is incurred in addition to the
programmed delay. The Channel Phase Delay Adjustment
Registers are 4 bits wide and are programmed as follows:
TABLE 5. CLKoutX_DLY: Clock Channel Delay Control
Bit Values
CLKoutX_DLY [ 3:0 ] DELAY
(ps)
b3 b2 b1 b0
00000
0 0 0 1 150
0 0 1 0 300
0 0 1 1 450
0 1 0 0 600
0 1 0 1 750
0 1 1 0 900
0 1 1 1 1050
1 0 0 0 1200
1 0 0 1 1350
1 0 1 0 1500
1 0 1 1 1650
1 1 0 0 1800
1 1 0 1 1950
1 1 1 0 2100
1 1 1 1 2250
16.3.4 CLKoutX/CLKoutX* LVCMOS Mode Control
For clock outputs that are configured as LVCMOS, the LVC-
MOS CLKoutX/CLKoutX* outputs can be independently con-
figured by uWire CLKoutXA_STATE and CLKoutXB_STATE
bits. The following choices are available for LVCMOS outputs:
TABLE 6. CLKoutXA_STATE, CLKoutXB_STATE Control
Bits for LVCMOS Modes
CLKoutXA_STATE CLKoutXB_STATE LVCMOS
Modes
b1 b0 b1 b0
0 0 0 0 Inverted
0 1 0 1 Normal
1 0 1 0 Low
1 1 1 1 TRI-
STATE
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LMK04000 Family
16.3.5 CLKoutX/CLKoutX* LVPECL Mode Control
Clock outputs designated as LVPECL can be configured in
one of two possible output levels. The default mode is the
common LVPECL swing of 800 mVp-p single-ended (1.6 Vp-
p differential). A second mode, 2VPECL, can be enabled in
which the swing is increased to 1000 mVp-p single-ended (2
Vp-p differential).
TABLE 7. LVPECL Output Format Control
CLKoutX_PECL_LVL Output Format
0 LVPECL (800 mVpp)
1 2VPECL (1000 mVpp)
16.3.6 CLKoutX_MUX: Clock Output Mux
The output of each CLKoutX channel pair is controlled by its'
channel multiplexer (mux). The mux can select between sev-
eral signals: bypassed, divided only, divided and delayed, or
delayed only.
TABLE 8. CLKoutX_MUX: Clock Channel Multiplexer
Control Bits
CLKout_MUX [1:0] Clock Mode
b1 b0
0 0 Bypassed
0 1 Divided
1 0 Delayed
1 1 Divided and Delayed
16.4 REGISTERS 5, 6
These registers are reserved. These register values should
not be modified from the values shown in the register map.
16.5 REGISTER 7
16.5.1 RESET bit
This bit is only in register R7. The use of this bit is optional
and it should be set to '0' if not used. Setting this bit to a '1'
forces all registers to their power on reset condition and there-
fore automatically clears this bit.
16.6 REGISTERS 8, 9
These registers are reserved. These register values should
not be modified from the values shown in the register map.
16.7 REGISTER 10
16.7.1 RC_DLD1_Start: PLL1 Digital Lock Detect Run
Control bit
This bit is used to control the state machine for the PLL2 VCO
tuning algorithm. The following table describes the function of
this bit.
TABLE 9. RC_DLD1_Start bit states
RC_DLD
1_Start
Description
1 The PLL2 VCO tuning algorithm trigger is
delayed until PLL1 Digital Lock Detect is valid.
0 The PLL2 VCO tuning algorithm runs
immediately after any PLL2_N counter update,
despite the state of PLL1 Digital Lock Detect.
If the user is unsure of the state of the reference clock input
at startup of the LMK040xx device, setting RC_DLD1_Start =
0 will allow PLL2 to tune and lock the internal VCO to the
oscillator attached to the OSCin port. This ensures that the
active clock outputs will start up at frequencies close to their
desired values. The error in clock output frequency will de-
pend on the open loop accuracy of the oscillator driving the
OSCin port. The frequency of an active clock output is nor-
mally given by:
30027160
If the open loop frequency accuracy of the external oscillator
(either a VCXO or crystal based oscillator) is "X" ppm, then
the error in the output clock frequency (FCLK error) will be:
30027161
Setting this bit to 0 does not prevent PLL1 from locking the
external oscillator to the reference clock input after the latter
input becomes valid.
16.8 REGISTER 11
16.8.1 CLKinX_BUFTYPE: PLL1 CLKinX/CLKinX* Buffer
Mode Control
The user may choose between one of two input buffer modes
for the PLL1 reference clock inputs: either bipolar junction
differential or MOS. Both CLKinX and CLKinX* input pins
must be AC coupled when driven differentially. In single end-
ed mode, the CLKinX* pin must be coupled to ground through
a capacitor. The active CLKinX buffer mode is selected by the
CLKinX_TYPE bits programmed via the uWire interface.
TABLE 10. PLL1 CLKinX_BUFTYPE Mode Control Bits
b1 b0 CLKin1_TYPE CLKin0_TYPE
0 0 BJT Differential BJT Differential
0 1 BJT Differential MOS
1 0 MOS BJT Differential
1 1 MOS MOS
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LMK04000 Family
16.8.2 CLKin_SEL: PLL1 Reference Clock Selection and
Revertive Mode Control Bits
This register allows the user to set the reference clock input
that is used to lock PLL1, or to select an auto-switching mode.
The automatic switching modes are revertive or non-re-
vertive. In either revertive or non-revertive mode, CLKin0 is
the initial default reference source for the auto-switching
mode. When revertive mode is active, the switching control
logic will always select CLKin0 as the reference if it is active,
otherwise it selects CLKin1. When non-revertive mode is ac-
tive, the switching logic will only switch the reference input if
the currently selected input fails.
Table 11 illustrates the control modes. Modes [1,0] and [1,1]
are the auto-switching modes. The behavior of both modes is
tied to the state of the LOS signals for the respective reference
clock inputs.
If the reference clock inputs are active prior to configuration
of the device, then the normal programming sequence de-
scribed under Section 16.0 General Programming Informa-
tion can be used without modification. If it cannot be
guaranteed that the reference clocks are active prior to device
programming, then the device programming sequence should
be modified in order to ensure that CLKin0 is selected as the
default. Under this scenario, the device should be pro-
grammed as described in "General Programming Informa-
tion", with CLKin_SEL bits programmed to [0,0] in register
R11. The other R11 fields for clock type and LOS timeout
should be programmed with the appropriate values for the
given application. After the reference clock inputs have start-
ed, register R11 should be programmed a second time with
the CLKin_SEL field modified to the set the desired mode.
The clock type field and LOS field values should remain the
same.
TABLE 11. CLKin_SEL: Reference Clock Selection Bits
CLKin_SEL [1:0] Function
b1 b0
0 0 Force CLKin0 / CLKin0* as PLL1
reference
0 1 Force CLKin1 / CLKin1* as PLL1
reference
1 0 Non-revertive. Auto-switching. CLKin0
is the default reference clock. If CLKin0
fails, CLKin1 is automatically selected if
active. If CLKin0 restarts, CLKin1
remains as the selected reference clock
unless it fails, then CLKin0 is re-
selected.
1 1 Revertive. Auto-switching. CLKin0 is
the preferred reference clock and is
selected when active.
16.8.3 CLKinX_LOS
The CLKin0_LOS and CLKin1_LOS pins indicate the state of
the respective PLL1 CLKinX reference input when the
CLKin_SEL bits are set set to either [1,0] or [1,1]. The detec-
tion logic that determines the state of the reference inputs is
sensitive to the frequency of the reference inputs and must
be configured to operate with the appropriate frequency range
of the reference inputs, as described in the next section.
16.8.4 PLL1 Reference Clock LOS Timeout Control
This register is used to tune the LOS timeout based upon the
frequency of the reference clock input(s). The register value
controls the timeout setting for both CLKin0 and CLKin1. The
value programmed in the LOS_TIMEOUT register represents
the minimum input frequency for which loss of signal can be
detected. For example, if the reference input frequency is
12.288 MHz, then either register values (0,0) or (0,1) will re-
sult in valid loss of signal detection. If the reference input
frequency is 1 MHz, then only the register value (0,0) will re-
sult in valid detection of signal loss.
TABLE 12. Reference Clock LOS Timeout Control Bits
b1 b0 Corresponding Minimum Input
Frequency
0 0 1 MHz
0 1 3.0 MHz
1 0 13 MHz
1 1 32 MHz
16.8.5 LOS Output Type Control
The output format of the LOS pins may be selected as active
CMOS, open drain NMOS and open drain PMOS, as shown
in the following table.
TABLE 13. Loss of Signal (LOS) Output Pin Format Type
LOS_TYPE [1:0] Functional Description
b1 b0
0 0 Reserved
0 1 NMOS open drain
1 0 PMOS open drain
1 1 Active CMOS
The LOS output signal is valid only when CLKin_SEL bits are
set to either [1,0] or [1,1]. If the CLKin_SEL field is pro-
grammed to either of the fixed inputs, [0,0] or [0,1], the
LOS_TYPE bits should be set to [0,0].
16.9 REGISTER 12
16.9.1 PLL1_N: PLL1_N Counter
The size of the PLL1_N counter is 12 bits. This counter will
support a maximum divide ratio of 4095 and minimum divide
ratio of 1. The 12 bit resolution is sufficient to support mini-
mum phase detector frequency resolution of approximately
50 kHz when the VCXO frequency is 200 MHz.
For a 200 MHz external VCXO, the minimum phase detector
rate will be PDmin = 200 MHz/4095 = 48.84 kHz
TABLE 14. PLL1_N Counter Values
N [17:0] VALUE
b11 b10 ... b6 b5 b4 b3 b2 b1 b0
0 0 0 0 0 0 0 0 0 Not Valid
0 0 0 0 0 0 0 0 1 1
0 0 0 0 0 0 0 1 0 2
. . . . . . . ...
1 1 1 4095
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LMK04000 Family
16.9.2 PLL1_R: PLL1_R Counter
The size of the PLL1_R counter is 12 bits. This counter will
support a maximum divide ratio of 4095 and minimum divide
ratio of 1.
TABLE 15. PLL1_R Counter Values
R [11:0] VALUE
b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0
0 0 0 0 0 0 0 0 0 0 0 0 Not
Valid
0 0 0000000001 1
. . . . . . . . . . . . ...
1 1 1 1 1 1 1 1 1 1 1 1 4095
16.9.3 PLL1 Charge Pump Current Gain (PLL1_CP_GAIN)
and Polarity Control (PLL1_CP_POL)
The Loop Band Width (LBW) on PLL1 should be narrow to
suppress the noise from the system or input clocks at CLKinX/
CLKinX* port. This configuration allows the noise of the ex-
ternal VCXO to dominate at low offset frequencies. Given that
the noise of the external VCXO is far superior than the noise
of PLL1, this setting produces a very clean reference clock to
PLL2 at the OSCin port.
In order to achieve a LBW as low as 10 Hz at the supported
VCXO frequency (1 MHz to 200 MHz), a range of charge
pump currents in PLL1 is provided. The table below shows
the available current gains. A small charge pump current is
required to obtain a narrow LBW at high phase detector rate
(small N value).
TABLE 16. PLL1 Charge Pump Current Selections
(PLL1_CP_GAIN)
PLL1_CP_GAIN
[2:0]
PLL1 Charge Pump Current
Magnitude (µA)
b2 b1 b0
0 0 0 RESERVED
0 0 1 RESERVED
0 1 0 20
0 1 1 80
1 0 0 25
1 0 1 50
1 1 0 100
1 1 1 400
The PLL1_CP_POL bit sets the PLL1 charge pump for oper-
ation with a positive or negative slope VCO/VCXO. A positive
slope VCO/VCXO increases frequency with increased tuning
voltage. A negative slope VCO/VCXO increases frequency
with decreased tuning voltage.
TABLE 17. PLL1 Charge Pump Polarity Control Bits
(PLL1_CP_POL)
PLL1_CP_POL DESCRIPTION
0 Negative Slope VCO/VCXO
1 Positive Slope VCO/VCXO
16.10 REGISTER 13
16.10.1 EN_PLL2_XTAL: Crystal Oscillator Option Enable
If an external crystal is being used to implement a discrete
VCXO, the internal feedback amplifier must be enabled in or-
der to complete the oscillator circuit.
TABLE 18. EN_PLL2_XTAL: External Crystal Option
EN_PLL2_XTAL Oscillator Amplifier State
0 OFF
1 ON
16.10.2 EN_Fout: Fout Power Down Bit
The EN_Fout bit allows the Fout port to be enabled or dis-
abled. By default EN_Fout = 0.
16.10.3 CLK Global Enable: Clock Global enable bit
In addition to the external GOE pin, an internal Register 13 bit
(b18) can be used to globally enable/disable the clock outputs
via the uWire programming interface. The default value is 1.
When CLK Global Enable = 1, the active output clocks are
enabled. The active output clocks are disabled if this bit is 0.
16.10.4 POWERDOWN Bit -- Device Power Down
This bit can power down the entire device. Enabling this bit
powers down the entire device and all functional blocks, re-
gardless of the state of any of the other bits or pins.
TABLE 19. Power Down Bit Values
POWERDOWN
Bit
Mode
0 Normal Operation
1 Entire device powered down
16.10.5 EN_PLL2 REF2X: PLL2 Frequency Doubler
control bit
When FOSCin is below 50 MHz, the PLL2 frequency doubler
can be enabled by setting EN_PLL2_REF2X = 1. The default
value is 0. When EN_PLL2_REF2X = 1, the signal at the OS-
Cin port bypasses the PLL2_R counter and is passed through
a frequency doubler circuit. The output of this circuit is then
input to the PLL2 phase comparator block. This feature allows
the phase comparison frequency to be increased for lower
frequency OSCin sources (< 50 MHz), and can be used with
either VXCOs or crystals. For instance, when using a pullable
crystal of 12.288 MHz to drive the OSCin port, the PLL2 phase
comparison frequency is 24.576 MHz when EN_PLL2_RE-
F2X = 1. A higher PLL phase comparison frequency reduces
PLL2 in-band phase noise and RMS jitter. The PLL in-band
phase noise can be reduced by approximately 2 to 3 dB. The
on-chip loop filter typically is enabled to reduce PLL2 refer-
ence spurs when EN_PLL2_REF2X is enabled. Suggested
values in this case are: R3 = 600 Ω, C3 = 50 pF, R4 = 10
kΩ, C4 = 60 pF.
16.10.6 PLL2 Internal Loop Filter Component Values
Internal loop filter components are available for PLL2, en-
abling the user to implement either 3rd or 4th order loop filters
without requiring external components. The user may select
from a fixed set of values for both the resistors and capacitors.
Internal loop filter resistance values for R3 and R4 can be set
individually according to Table 20 and Table 21.
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LMK04000 Family
TABLE 20. PLL2 Internal Loop Filter Resistor Values,
PLL2_R3_LF
PLL2_R3_LF [2:0] RESISTANCE
b2 b1 b0
0 0 0 < 600 Ω
0 0 1 10 kΩ
0 1 0 20 kΩ
0 1 1 30 kΩ
1 0 0 40 kΩ
1 0 1 Invalid
1 1 0 Invalid
1 1 1 Invalid
TABLE 21. PLL2 Internal Loop Filter Resistor Values,
PLL2_R4_LF
PLL2_R4_LF [2:0] RESISTANCE
b2 b1 b0
0 0 0 < 200 Ω
0 0 1 10 kΩ
0 1 0 20 kΩ
0 1 1 30 kΩ
1 0 0 40 kΩ
1 0 1 Invalid
1 1 0 Invalid
1 1 1 Invalid
Internal loop filter capacitors for C3 and C4 can be set indi-
vidually according to the following table.
TABLE 22. PLL2 Internal Loop Filter Capacitor Values
PLL2_C3_C4_
LF [3:0]
Loop Filter Capacitance (pF)
b3 b2 b1 b0
0 0 0 0 C3 = 0, C4 = 10
0 0 0 1 C3 = 0, C4 = 60
0 0 1 0 C3 = 50, C4 = 10
0 0 1 1 C3 = 0, C4 = 110
0 1 0 0 C3 = 50, C4 = 110
0 1 0 1 C3 = 100, C4 = 110
0 1 1 0 C3 = 0, C4 = 160
0 1 1 1 C3 = 50, C4 = 160
1 0 0 0 C3 = 100, C4 = 10
1 0 0 1 C3 = 100, C4 = 60
1 0 1 0 C3 = 150, C4 = 110
1 0 1 1 C3 = 150, C4 = 60
1 1 0 0 Reserved
1 1 0 1 Reserved
1 1 1 0 Reserved
1 1 1 1 Reserved
16.10.7 PLL1 CP TRI-STATE and PLL2 CP TRI-STATE
The charge pump output of either CPout1 or CPout2 may be
placed in a TRI-STATE mode by setting the appropriate PLLx
CP TRI-STATE bit.
TABLE 23. PLL1 Charge Pump TRI-STATE bit values
PLL1 CP TRI-STATE Description
1 PLL1 CPout1 is at TRI-
STATE
0 PLL1 CPout1 is active
TABLE 24. PLL2 Charge Pump TRI-STATE bit values
PLL2 CP TRI-STATE Description
1 PLL2 CPout2 is at TRI-
STATE
0 PLL2 CPout2 is active
16.11 REGISTER 14
16.11.1 OSCin_FREQ: PLL2 Oscillator Input Frequency
Register
The frequency of the PLL2 reference input to the PLL2 Phase
Detector (OSCin/OSCin* port) must be programmed in order
to support proper operation of the internal VCO tuning algo-
rithm. This is an 8-bit register that sets the frequency to the
nearest 1-MHz increment.
TABLE 25. OSCin_FREQ Register Values
OSCin_FREQ [7:0] VALUE
b7 b6 b5 b4 b3 b2 b1 b0
0 0 0 0 0 0 0 0 Not Valid
0 0 0 0 0 0 0 1 1 MHz
0 0 0 0 0 0 1 0 2 MHz
. . . . . . . ...
1 1 1 1 1 0 1 0 250 MHz
1 1 0 0 1 0 0 1 Not Valid
........ .
1 1 1 1 1 1 1 1 Not Valid
16.11.2 PLL2_R: PLL2_R Counter
The PLL2 R Counter is 12 bits wide. It divides the PLL2 OS-
Cin/OSCin* clock and is connected to the PLL2 Phase De-
tector.
TABLE 26. PLL2_R: PLL2_R Counter Values
R [11:0] VALUE
b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0
0 0 0 0 0 0 0 0 0 0 0 0 Not
Valid
0 0 0000000001 1
. . . . . . . . . . ...
1 1 1 1 1 1 1 1 1 1 1 1 4095
16.11.3 PLL_MUX: LD Pin Selectable Output
The signal appearing on the LD pin is programmable via the
uWire interface and provides access to several internal sig-
nals which may be valuable for either status monitoring during
normal operation or for debugging during the hardware de-
velopment phase. This pin may be forced to either a HIGH or
LOW state, and may also be configured as specified in Table
27.
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LMK04000 Family
TABLE 27. PLL_MUX: LD Pin Selectable Outputs
PLL_MUX [4:0] LD Output
b4 b3 b2 b1 b0
0 0 0 0 0 HiZ
0 0 0 0 1 Logic High
0 0 0 1 0 Logic Low
0 0 0 1 1 PLL2 Digital Lock Detect Active High
0 0 1 0 0 PLL2 Digital Lock Detect Active Low
0 0 1 0 1 PLL2 Analog Lock Detect Push Pull
0 0 1 1 0 PLL2 Analog Lock Detect Open Drain
NMOS
0 0 1 1 1 PLL2 Analog Lock Detect Open Drain
PMOS
0 1 0 0 0 Reserved
0 1 0 0 1 PLL2_N Divider Output / 2
0 1 0 1 0 Reserved
0 1 0 1 1 PLL2_R Divider Output / 2
0 1 1 0 0 Reserved
0 1 1 0 1 Reserved
0 1 1 1 0 PLL1 Digital Lock Detect Active HIGH
0 1 1 1 1 PLL1 Digital Lock Detect Active LOW
1 0 0 0 0 Reserved
1 0 0 0 1 Reserved
1 0 0 1 0 Reserved
1 0 0 1 1 Reserved
1 0 1 0 0 PLL1_N Divider Output / 2
1 0 1 0 1 Reserved
1 0 1 1 0 PLL1_R Divider Output / 2
1 0 1 1 1 PLL1 and PLL2 Digital Lock Detect
1 1 0 0 0 Inverted PLL1 and PLL2 Digital Lock
Detect
1 1 0 0 1 Reserved
1 1 0 1 0 Reserved
1 1 0 1 1 Reserved
1 1 1 0 0 Reserved
1 1 1 0 1 Reserved
1 1 1 1 0 Reserved
1 1 1 1 1 Reserved
16.12 REGISTER 15
16.12.1 PLL2_N: PLL2_N Counter
The PLL2_N Counter is 18 bits wide. It divides the output of
the VCO Divider and is connected to the PLL2 Phase Detec-
tor. Each time the PLL2_N Counter value is updated via the
uWire interface, an internal algorithm is triggered that opti-
mizes the VCO performance.
TABLE 28. PLL2_N: PLL2_N Counter Values
N [17:0] VALUE
b17 b16 ... b6 b5 b4 b3 b2 b1 b0
0 0 ... 0 0 0 0 0 0 0 Not Valid
0 0 0 0 0 0 0 0 1 1
0 0 0 0 0 0 0 1 0 2
. . . . . . . ...
1 1 1 1 1 1 1 1 1 262143
16.12.2 PLL2_CP_GAIN: PLL2 Charge Pump Current and
Output Control
The PLL2 charge pump output current level is controlled with
the PLL2_CP_GAIN register. The following table presents the
charge pump current control values.
TABLE 29. PLL2_CP_GAIN: PLL2 Charge Pump Current
Selections
PLL2_CP_GAIN [1:0] CP_TRI Charge
Pump
Current (µA)
b1 b0
X X 1 Hi-Z
0 0 0 100
0 1 0 400
1 0 0 1600
1 1 0 3200
16.12.3 VCO_DIV: PLL2 VCO Divide Register
A divider is provided on the output of the PLL2 VCO to enable
a wide range of output clock frequencies. The output of this
divider is placed on the input path for the clock distribution
section, which feeds each of the individual clock channels.
The divider provides integer divide ratios from 2 to 8.
TABLE 30. VCO_DIV: PLL2 VCO Divider Values
VCO_DIV [3:0] Divide
Value
b3 b2 b1 b0
0 0 0 0 Invalid
0 0 0 1 Invalid
00102
00113
01004
01015
01106
01117
10008
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LMK04000 Family
17.0 Application Information
17.1 SYSTEM LEVEL DIAGRAM
The following diagram illustrates the typical interconnection
of the LMK040xx in a clocking application.
30027170
FIGURE 3. Typical Application
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LMK04000 Family
17.1 System Level Diagram (continued)
Figure 3 shows an LMK04000 family device with external cir-
cuitry. The primary reference clock input is at CLKin0/0*. A
secondary reference clock is driving CLKin1/1*. Both clocks
are depicted as AC coupled differential drivers. The VCXO
attached to the OSCin/OSCin* port is configured as an AC
coupled single-ended driver. Any of the input ports
(CLKin0/0*, CLKin1/1*, or OSCin/OSCin*) may be configured
as either differential or single-ended. These options are dis-
cussed later in the data sheet.
The diagram shows an optional connection between the LD
pin and GOE. With this arrangement, the LD pin can be pro-
grammed to output a lock detect signal that is active HIGH
(see Table 27 for optional LD pin outputs). If lock is lost, the
LD pin will transition to a LOW, pulling GOE low and causing
all clock outputs to be disabled. This scheme should be used
only if disabling the clock outputs is desirable when lock is
lost.
The loop filter for PLL2 consists of three external components
that implement two lower order poles, plus optional internal
integrated components if 3rd or 4th order poles are needed.
The loop filter components for PLL1 must be external com-
ponents.
The VCO output buffer signal that appears at the Fout pin
when enabled (EN_Fout = 1) should be AC coupled using a
100 pF capacitor. This output is a single-ended signal by de-
fault. If a differential signal is required, a 50 Ω balun may be
connected to this pin to convert it to differential.
The clock outputs are all AC coupled with 0.1 µF capacitors.
CLKout1 and CLKout3 are depicted as LVPECL, with 120 Ω
emitter resistors as source termination. However, the output
format of the clock channels will vary by device part number,
so the designer should use the appropriate source termina-
tion for each channel. Later sections of this data sheet illus-
trate alternative methods for AC coupling, DC coupling and
terminating the clock outputs.
17.2 LDO BYPASS AND BIAS PIN
The LDObyp1 and LDObyp2 pins should be connected to
GND through external capacitors, as shown in the diagram.
Furthermore, the Bias pin should be connected to VCC
through a 1 µF capacitor in series.
17.3 LOOP FILTER
Each PLL of the LMK04000 family requires a dedicated loop
filter. The loop filter for PLL1 must be connected to the CPout1
pin. Figure 4 shows a simple 2-pole loop filter. The output of
the filter drives an external VCXO module or discrete imple-
mentation of a VCXO using a crystal resonator. Higher order
loop filters may be implemented using additional external R
and C components. It is recommended the loop filter for PLL1
result in a total closed loop bandwidth in the range of 10 Hz
to 200 Hz. The design of the loop filter is application specific
and highly dependent on parameters such as the phase noise
of the reference clock, VCXO phase noise, and phase detec-
tor frequency for PLL1. National’s Clock Conditioner Owner’s
Manual covers this topic in detail and National’s Clock Design
Tool can be used to simulate loop filter designs for both PLLs.
These resources may be found: http://www.national.com/tim-
ing/.
As shown in the diagram, the charge pump for PLL2 is directly
connected to the optional internal loop filter components,
which are normally used only if either a third or fourth pole is
needed. The first and second poles are implemented with ex-
ternal components. The loop must be designed to be stable
over the entire application-specific tuning range of the VCO.
The designer should note the range of KVCO listed in the table
of Electrical Characteristics and how this value can change
over the expected range of VCO tuning frequencies. Because
loop bandwidth is directly proportional to KVCO, the designer
should model and simulate the loop at the expected extremes
of the desired tuning range, using the appropriate values for
KVCO.
When designing with the integrated loop filter of the
LMK04000 family, considerations for minimum resistor ther-
mal noise often lead one to the decision to design for the
minimum value for integrated resistors, R3 and R4. Both the
integrated loop filter resistors and capacitors (C3 and C4) also
restrict the maximum loop bandwidth. However, these inte-
grated components do have the advantage that they are
closer to the VCO and can therefore filter out some noise and
spurs better than external components. For this reason, a
common strategy is to minimize the internal loop filter resis-
tors and then design for the largest internal capacitor values
that permit a wide enough loop bandwidth. In situations where
spurs requirements are very stringent and there is margin on
phase noise, it might make sense to design for a loop filter
with integrated resistor values larger than their minimum val-
ue.
www.national.com 40
LMK04000 Family
30027171
FIGURE 4. Loop Filter
41 www.national.com
LMK04000 Family
TABLE 31. Typical Current Consumption for Selected Functional Blocks
Block Condition
Typical ICC
(Temp = 25 °C,
VCC = 3.3 V)
(mA)
Power
Dissipated in
device
(mW)
Power
Dissipated in
LVPECL/
2VPECL Emitter
Resistors
(mW)
Entire device,
core current
Single input clock (CLKIN_SEL = 0 or 1); LOS
disabled; PLL1 and PLL2 locked; All CLKouts are off;
No LVPECL emitter resistors connected
115 380 -
REFMUX Enable auto-switch mode (CLKIN_SEL = 2 or 3) 4.3 14 -
LOS Enable LOS (LOS_TYPE = 1, or 2, or 3) 3.6 12 -
Low Channel
Internal Buffer
The low channel internal buffer is enabled when
CLKout0 is enabled 10 33 -
High Channel
Internal Buffer
The high channel internal buffer is enabled when one
of CLKout1 through CLKout4 is enabled 10 33 -
Divide circuitry
per output
Divider bypassed (CLKout_MUX = 0, 2) 0 0 -
Divider enabled, divide = 2 (CLKout_MUX = 1, 3) 5.3 17 -
Divider enabled, divide > 2 (CLKout_MUX = 1, 3) 8.5 28 -
Delay circuitry
per output
Delay bypassed (CLKout_MUX = 0, 1) 0 0 -
Delay enabled, delay < 8 (CLKout_MUX = 2, 3) 5.8 19 -
Delay enabled, delay > 7 (CLKout_MUX = 2, 3) 9.9 33 -
Fout Buffer EN_Fout = 1 14.5 48 -
LVDS Buffer LVDS buffer, enabled 19.3 64 -
LVPECL/
2VPECL Buffer
LVPECL/2VPECL buffer (enabled and with 120 Ω
emitter resistors) 40 82 50
LVPECL/2VPECL buffer (disabled and with 120 Ω
emitter resistors) 21.7 47 25
LVPECL/2VPECL (disabled and with no emitter
resistors) 0 0 -
LVCMOS Buffer
(Note 44)
LVCMOS buffer static ICC, CL = 5 pF 4.5 15 -
LVCMOS buffer dynamic ICC, CL = 5 pF, CLKout = 100
MHz 16 53 -
Entire device
(Single input
clock
(CLKIN_SEL = 0
or 1); LOS
disabled; PLL1
and PLL2 locked;
Fout disabled; All
CLKouts are on;
No delay); Divide
> 2 on each
output.
LMK0400x (Note 45, Note 46) 379.5 1102 150
LMK0401x (Note 45, Note 46) 377.5 996 250
LMK0403x (Note 45, Note 46)
337.1 1012 100
Note 44: Dynamic power dissipation of LVCMOS buffer varies with output frequency and can be found in the LVCMOS dynamic ICC vs frequency plot, as shown
in Section 13.1 CLOCK OUTPUT AC CHARACTERISTICS. Total power dissipation of the LVCMOS buffer is the sum of static and dynamic power dissipation.
CLKoutXa and CLKoutXb are each considered an LVCMOS buffer.
Note 45: Assuming ThetaJ = 27.4 °C/W, the total power dissipated on chip must be less than 40/27.4 = 1450 mW to guarantee a junction temperature is less
than 125 °C.
Note 46: Worst case power dissipation can be estimated by multiplying typical power dissipation with a factor of 1.2.
www.national.com 42
LMK04000 Family
17.4 CURRENT CONSUMPTION / POWER DISSIPATION
CALCULATIONS
Due to the myriad of possible configurations the following ta-
ble serves to provide enough information to allow the user to
calculate estimated current consumption of the device. Un-
less otherwise noted VCC = 3.3 V, TA = 25 °C.
From Table 31 the current consumption can be calculated in
any configuration. For example, the current for the entire de-
vice with 1 LVDS (CLKout0) & 1 LVPECL (CLKout1) output
in bypassed mode can be calculated by adding up the follow-
ing blocks: core current, clock buffer, one LVDS output buffer
current, and one LVPECL output buffer current. There will al-
so be one LVPECL output drawing emitter current, but some
of the power from the current draw is dissipated in the external
120 Ω resistors which doesn't add to the power dissipation
budget for the device. If delays or divides are switched in, then
the additional current for these stages needs to be added as
well.
For power dissipated by the device, the total current entering
the device is multiplied by the voltage at the device minus the
power dissipated in any emitter resistors connected to any of
the LVPECL outputs. If no emitter resistors are connected to
the LVPECL outputs, this power will be 0 watts. For example,
in the case of 1 LVDS (CLKout0) & 1 LVPECL (CLKout1) op-
erating at 3.3 V, we calculate 3.3 V × (115 + 10 + 10 + 19.3 +
40) mA = 3.3 V × 194.3 mA = 641.2 mW. Because the
LVPECL output (CLKout1) has the emitter resistors hooked
up and the power dissipated by these resistors is 50 mW, the
total device power dissipation is 641.2 mW - 50 mW = 591.2
mW.
When the LVPECL output is active, ~1.7 V is the average
voltage on each output as calculated from the LVPECL VOH
& VOL typical specification. Therefore the power dissipated in
each emitter resistor is approximately (1.7 V)2 / 120 Ω = 25
mW. When the LVPECL output is disabled, the emitter resis-
tor voltage is ~1.07 V. Therefore the power dissipated in each
emitter resistor is approximately (1.07 V)2 / 120 Ω = 9.5 mW.
17.5 POWER SUPPLY CONDITIONING
The recommended technique for power supply management
is to connect the power pins for the clock outputs (pins 13, 37,
40, 43, and 46) to a dedicated power plane and connect all
other power pins on the device (pins 3, 8, 18, 19, 22, 24, 30,
31, and 33) to a second power plane. Note: the LMK04000
family has internal voltage regulators for the PLL and VCO
blocks to provide noise immunity.
17.6 THERMAL MANAGEMENT
Power consumption of the LMK04000 family of devices can
be high enough to require attention to thermal management.
For reliability and performance reasons the die temperature
should be limited to a maximum of 125 °C. That is, as an es-
timate, TA (ambient temperature) plus device power con-
sumption times θJA should not exceed 125 °C.
The package of the device has an exposed pad that provides
the primary heat removal path as well as excellent electrical
grounding to a printed circuit board. To maximize the removal
of heat from the package a thermal land pattern including
multiple vias to a ground plane must be incorporated on the
PCB within the footprint of the package. The exposed pad
must be soldered down to ensure adequate heat conduction
out of the package. A recommended land and via pattern is
shown in Figure 5. More information on soldering LLP pack-
ages can be obtained: http:// www.national.com/analog/pack-
aging/.
30027173
FIGURE 5. Recommended Land and Via Pattern
To minimize junction temperature it is recommended that a
simple heat sink be built into the PCB (if the ground plane
layer is not exposed). This is done by including a copper area
of about 2 square inches on the opposite side of the PCB from
the device. This copper area may be plated or solder coated
to prevent corrosion but should not have conformal coating (if
possible), which could provide thermal insulation. The vias
shown in Figure 5 should connect these top and bottom cop-
per layers and to the ground layer. These vias act as “heat
pipes” to carry the thermal energy away from the device side
of the board to where it can be more effectively dissipated.
43 www.national.com
LMK04000 Family
30027163
FIGURE 6. Reference Design Circuit for Crystal Oscillator Option
17.7 OPTIONAL CRYSTAL OSCILLATOR
IMPLEMENTATION (OSCin/OSCin*)
The LMK04000 family features supporting circuitry for a dis-
cretely implemented oscillator driving the OSCin port pins.
Figure 6 illustrates a reference design circuit for a crystal os-
cillator:
This circuit topology represents a parallel resonant mode os-
cillator design. When selecting a crystal for parallel reso-
nance, the total load capacitance, CL, must be specified. The
load capacitance is the sum of the tuning capacitance
(CTUNE), the capacitance seen looking into the OSCin port
(CIN), and stray capacitance due to PCB parasitics (CSTRAY),
and is given by:
30027164
CTUNE is provided by the varactor diode shown in Figure 6,
Skyworks model SMV1249-074. A dual diode package with
common cathode and provides the variable capacitance for
tuning. The single diode capacitance ranges from approxi-
mately 31 pF at 0.3 V to 3.4 pF at 3 V. The capacitance range
of the dual package (anode to anode) is approximately 15.5
pF at 3 V to 1.7 pF at 0.3 V. The desired value of VTUNE applied
to the diode should be VCC/2, or 1.65 V for VCC = 3.3 V. The
typical performance curve from the data sheet for the
SMV1249-074 indicates that the capacitance at this voltage
is approximately 6 pF (12 pF/2).
The nominal input capacitance (CIN) of the LMK04000 family
OSCin pins is 6 pF. The stray capacitance (CSTRAY) of the
PCB should be minimized by arranging the oscillator circuit
layout to achieve trace lengths as short as possible and as
narrow as possible trace width (50 Ω characteristic
impedance is not required). As an example, assume that
CSTRAY is 4 pF. The total load capacitance is nominally:
30027165
Consequently the load capacitance specification for the crys-
tal in this case should be nominally 14 pF.
The 2.2 nF capacitors shown in the circuit are coupling ca-
pacitors that block the DC tuning voltage applied by the 4.7 k
and 10 k resistors. The value of these coupling capacitors
should be large, relative to the value of CTUNE (CC1 = CC2 >>
CTUNE), so that CTUNE becomes the dominant capacitance.
For a specific value of CL, the corresponding resonant fre-
quency (FL) of the parallel resonant mode circuit is:
30027166
FS = Series resonant frequency
C1 = Motional capacitance of the crystal
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LMK04000 Family
CL = Load capacitance
C0 = Shunt capacitance of the crystal, specified on the crystal
datasheet
The normalized tuning range of the circuit is closely approxi-
mated by:
30027167
CL1, CL2 = The endpoints of the circuit’s load capacitance
range, assuming a variable capacitance element is one com-
ponent of the load. FCL1, FCL2 = parallel resonant frequencies
at the extremes of the circuit’s load capacitance range.
A common range for the pullability ratio, C0/C1, is 250 to 280.
The ratio of the load capacitance to the shunt capacitance is
~(n * 1000), n < 10. Hence, picking a crystal with a smaller
pullability ratio supports a wider tuning range because this
allows the scale factors related to the load capacitance to
dominate.
Examples of the phase noise and jitter performance of the
LMK04031 with a crystal oscillator are shown in Table 32.
This table illustrates the clock output phase noise when a
12.288 MHz crystal is paired with PLL1.
TABLE 32. Example RMS Jitter and Clock Output Phase Noise for LMK04031 with a
12.288 MHz Crystal Driving OSCin (T = 25 °C, VCC = 3.3 V) (Note 47)
RMS Jitter (ps)
Integration Bandwidth Clock Output Type PLL2 PDF = 12.288 MHz
(EN_PLL2_REF2X = 0)
PLL2 PDF = 24.576 MHz
(EN_PLL2_REF2X = 1)
FCLK = 122.88 MHz FCLK = 153.6 MHz FCLK = 122.88 MHz
100 Hz – 20 MHz LVPECL 0.279 0.263 0.300
LVCMOS 0.244 0.248 0.218
LVDS 0.272 0.269 0.245
10 kHz – 20 MHz LVPECL 0.251 0.234 0.284
LVCMOS 0.211 0.215 0.193
LVDS 0.236 0.235 0.217
Phase Noise (dBc/Hz)
Offset Clock Output Type PLL2 FPD = 12.288 MHz
(EN_PLL2_REF2X = 0)
PLL2 FPD = 24.576 MHz
(EN_PLL2_REF2X = 1)
FCLK = 122.88 MHz FCLK = 153.6 MHz FCLK = 122.88 MHz
100 Hz LVPECL -107 -106 -106
LVCMOS -105 -103 -104
LVDS -105 -104 -106
1 kHz LVPECL -126 -124 -130
LVCMOS -125 -124 -127
LVDS -126 -123 -126
10 kHz LVPECL -125 -124 -131
LVCMOS -127 -125 -128
LVDS -126 -124 -131
100 kHz LVPECL -134 -133 -134
LVCMOS -135 -133 -134
LVDS -134 -132 -134
1 MHz LVPECL -155 -154 -154
LVCMOS -157 -155 -155
LVDS -155 -153 -154
10 MHz LVPECL -158 -158 -158
LVCMOS -160 -159 -159
LVDS -158 -158 -157
Note 47: Performance data and crystal specifications contained in this
section are based on Ecliptek model ECX-6465, 12.288 MHz.
45 www.national.com
LMK04000 Family
Example crystal specifications are presented in Table 33.
TABLE 33. Example Crystal Specifications
Parameter Value
Nominal Frequency (MHz) 12.288
Frequency Stability, T = 25 °C ± 10 ppm
Operating temperature range -40 °C to +85 °C
Frequency Stability, -40 °C to +85 °C ± 15 ppm
Load Capacitance 14 pF
Shunt Capacitance (C0) 5 pF Maximum
Motional Capacitance (C1) 20 fF ± 30%
Equivalent Series Resistance 25 Ω Maximum
Drive level 2 mWatts Maximum
C0/C1 ratio 225 typical, 250 Maximum
See Figure 7 for a representative tuning curve.
30027168
FIGURE 7. Example Tuning Curve, 12.288 MHz Crystal
The tuning curve achieved in the user's application may differ
from the curve shown above due to differences in PCB layout
and component selection.
This data is measured on the bench with the crystal integrated
with the LMK04000 family. Using a voltmeter to monitor the
VTUNE node for the crystal, the PLL1 reference clock input
frequency is swept in frequency and the resulting tuning volt-
age generated by PLL1 is measured at each frequency. At
each value of the reference clock frequency, the lock state of
PLL1 should be monitored to ensure that the tuning voltage
applied to the crystal is valid.
The curve shows over the tuning voltage range of 0.17 VDC
to 3.0 VDC, the frequency range is ± 163 ppm; or equivalently,
a crystal frequency range of ± 2000 Hz. The measured tuning
voltage at the nominal crystal frequency (12.288 MHz) is 1.4
V. Using the diode data sheet tuning characteristics, this volt-
age results in a tuning capacitance of approximately 6.5 pF.
The tuning curve data can be used to calculate the gain of the
oscillator (KVCO). The data used in the calculations is taken
from the most linear portion of the curve, a region centered
on the crossover point at the nominal frequency (12.288
MHz). For a well designed circuit, this is the most likely oper-
ating range. In this case, the tuning range used for the calcu-
lations is ± 1000 Hz (± 0.001 MHz), or ± 81.4 ppm. The
simplest method is to calculate the ratio:
30027169
ΔF2 and ΔF1 are in units of MHz. Using data from the curve
this becomes:
30027135
A second method uses the tuning data in units of ppm:
30027136
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LMK04000 Family
FNOM is the nominal frequency of the crystal and is in units of
MHz. Using the data, this becomes:
30027137
In order to ensure startup of the oscillator circuit, the equiva-
lent series resistance (ESR) of the selected crystal should
conform to the specifications listed in the table of Electrical
Characteristics. It is also important to select a crystal with ad-
equate power dissipation capability, or drive level. If the drive
level supplied by the oscillator exceeds the maximum speci-
fied by the crystal manufacturer, the crystal will undergo
excessive aging and possibly become damaged. Drive level
is directly proportional to resonant frequency, capacitive load
seen by the crystal, voltage and equivalent series resistance
(ESR). For more complete coverage of crystal oscillator de-
sign, see Application Note AN-1939 at http://
www.national.com/analog/timing/clocking or http://
www.national.com/appnotes.
17.8 TERMINATION AND USE OF CLOCK OUTPUT
(DRIVERS)
When terminating clock drivers keep in mind these guidelines
for optimum phase noise and jitter performance:
•Transmission line theory should be followed for good
impedance matching to prevent reflections.
•Clock drivers should be presented with the proper loads.
For example:
—LVDS drivers are current drivers and require a closed
current loop.
—LVPECL drivers are open emitters and require a DC
path to ground.
•Receivers should be presented with a signal biased to
their specified DC bias level (common mode voltage) for
proper operation. Some receivers have self-biasing inputs
that automatically bias to the proper voltage level. In this
case, the signal should normally be AC coupled.
It is possible to drive a non-LVPECL or non-LVDS receiver
with an LVDS or LVPECL driver as long as the above guide-
lines are followed. Check the datasheet of the receiver or
input being driven to determine the best termination and cou-
pling method to be sure that the receiver is biased at its
optimum DC voltage (common mode voltage). For example,
when driving the OSCin/OSCin* input of the LMK04000 fam-
ily, OSCin/OSCin* should be AC coupled because OSCin/
OSCin* biases the signal to the proper DC level (See Figure
3) This is only slightly different from the AC coupled cases
described in Section 17.9.2 Driving CLKin Pins with a Single-
Ended Source because the DC blocking capacitors are
placed between the termination and the OSCin/OSCin* pins,
but the concept remains the same. The receiver (OSCin/OS-
Cin*) sets the input to the optimum DC bias voltage (common
mode voltage), not the driver.
17.8.1 Termination for DC Coupled Differential Operation
For DC coupled operation of an LVDS driver, terminate with
100 Ω as close as possible to the LVDS receiver as shown in
Figure 8.
30027120
FIGURE 8. Differential LVDS Operation, DC Coupling, No
Biasing of the Receiver
For DC coupled operation of an LVPECL driver, terminate
with 50 Ω to VCC - 2 V as shown in Figure 9. Alternatively
terminate with a Thevenin equivalent circuit (120 Ω resistor
connected to VCC and an 82 Ω resistor connected to ground
with the driver connected to the junction of the 120 Ω and 82
Ω resistors) as shown in Figure 10 for VCC = 3.3 V.
30027118
FIGURE 9. Differential LVPECL Operation, DC Coupling
30027121
FIGURE 10. Differential LVPECL Operation, DC Coupling,
Thevenin Equivalent
17.8.2 Termination for AC Coupled Differential Operation
AC coupling allows for shifting the DC bias level (common
mode voltage) when driving different receiver standards.
Since AC coupling prevents the driver from providing a DC
bias voltage at the receiver it is important to ensure the re-
ceiver is biased to its ideal DC level.
When driving non-biased LVDS receivers with an LVDS driv-
er, the signal may be AC coupled by adding DC blocking
capacitors, however the proper DC bias point needs to be
established at the receiver. One way to do this is with the ter-
mination circuitry in Figure 11.
47 www.national.com
LMK04000 Family
30027119
FIGURE 11. Differential LVDS Operation, AC Coupling,
External Biasing at the Receiver
Some LVDS receivers may have internal biasing on the in-
puts. In this case, the circuit shown in Figure 11 is modified
by replacing the 50 Ω terminations to Vbias with a single 100
Ω resistor across the input pins of the receiver, as shown in
Figure 12. When using AC coupling with LVDS outputs, there
may be a startup delay observed in the clock output due to
capacitor charging. The previous figures employ a 0.1 µF ca-
pacitor. This value may need to be adjusted to meet the
startup requirements for a particular application.
30027182
FIGURE 12. LVDS Termination for a Self-Biased Receiver
LVPECL drivers require a DC path to ground. When AC cou-
pling an LVPECL signal use 120 Ω emitter resistors close to
the LVPECL driver to provide a DC path to ground as shown
in Figure 13. For proper receiver operation, the signal should
be biased to the DC bias level (common mode voltage) spec-
ified by the receiver. The typical DC bias voltage for LVPECL
receivers is 2 V. A Thevenin equivalent circuit (82 Ω resistor
connected to VCC and a 120 Ω resistor connected to ground
with the driver connected to the junction of the 82 Ω and 120
Ω resistors) is a valid termination as shown in Figure 13 for
VCC = 3.3 V. Note this Thevenin circuit is different from the
DC coupled example in Figure 10.
30027117
FIGURE 13. Differential LVPECL Operation, AC Coupling,
Thevenin Equivalent, External Biasing at the Receiver
17.8.3 Termination for Single-Ended Operation
A balun can be used with either LVDS or LVPECL drivers to
convert the balanced, differential signal into an unbalanced,
single-ended signal.
It is possible to use an LVPECL driver as one or two separate
800 mVpp signals. When using only one LVPECL driver of a
CLKoutX/CLKoutX* pair, be sure to properly terminated the
unused driver. When DC coupling one of the LMK04000 fam-
ily clock LVPECL drivers, the termination should be 50 Ω to
VCC - 2 V as shown in Figure 14. The Thevenin equivalent
circuit is also a valid termination as shown in Figure 15 for Vcc
= 3.3 V.
30027115
FIGURE 14. Single-Ended LVPECL Operation, DC
Coupling
30027116
FIGURE 15. Single-Ended LVPECL Operation, DC
Coupling, Thevenin Equivalent
When AC coupling an LVPECL driver use a 120 Ω emitter
resistor to provide a DC path to ground and ensure a 50 Ω
termination with the proper DC bias level for the receiver. The
typical DC bias voltage for LVPECL receivers is 2 V (See
Section 17.9.2 Driving CLKin Pins with a Single-Ended
Source). If the companion driver is not used it should be ter-
minated with either a proper AC or DC termination. This latter
example of AC coupling a single-ended LVPECL signal can
be used to measure single-ended LVPECL performance us-
ing a spectrum analyzer or phase noise analyzer. When using
most RF test equipment no DC bias point (0 VDC) is required
for safe and proper operation. The internal 50 Ω termination
of the test equipment correctly terminates the LVPECL driver
being measured as shown in Figure 16.
30027114
FIGURE 16. Single-Ended LVPECL Operation, AC
Coupling
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LMK04000 Family
17.9 DRIVING CLKin AND OSCin INPUTS
17.9.1 Driving CLKin Pins with a Differential Source
Both CLKin ports can be driven by differential signals. It is
recommended that the input mode be set to bipolar
(CLKinX_TYPE = 0) when using differential reference clocks.
The LMK04000 family internally biases the input pins so the
differential interface should be AC coupled. The recommend-
ed circuits for driving the CLKin pins with either LVDS or
LVPECL are shown in Figure 17 and Figure 18.
30027181
FIGURE 17. CLKinX/X* Termination for an LVDS
Reference Clock Source
30027187
FIGURE 18. CLKinX/X* Termination for an LVPECL
Reference Clock Source
Finally, a reference clock source that produces a differential
sinewave output can drive the CLKin pins using the following
circuit. Note: the signal level must conform to the require-
ments for the CLKin pins listed in the Electrical Characteristics
table.
30027124
FIGURE 19. CLKinX/X* Termination for a Differential
Sinewave Reference Clock Source
17.9.2 Driving CLKin Pins with a Single-Ended Source
The CLKin pins of the LMK04000 family can be driven using
a single-ended reference clock source, for example, either a
sinewave source or an LVCMOS/LVTTL source. Either AC
coupling or DC coupling may be used. In the case of the
sinewave source that is expecting a 50 Ω load, it is recom-
mended that AC coupling be used as shown in the circuit
below with a 50 Ω termination..
Note: The signal level must conform to the requirements for the CLKin pins
listed in the Electrical Characteristics table. CLKinX_TYPE in Regis-
ter 11 is recommended to be set to bipolar mode (CLKinX_TYPE =
0).
30027122
FIGURE 20. CLKinX/X* Single-ended Termination
If the CLKin pins are being driven with a single-ended LVC-
MOS/LVTTL source, either DC coupling or AC coupling may
be used. If DC coupling is used, the CLKinX_TYPE should be
set to MOS buffer mode (CLKinX_TYPE = 1) and the voltage
swing of the source must meet the specifications for DC cou-
pled, MOS-mode clock inputs given in the table of Electrical
Characteristics. If AC coupling is used, the CLKinX_TYPE
should be set to the bipolar buffer mode (CLKinX_TYPE = 0).
The voltage swing at the input pins must meet the specifica-
tions for AC coupled, bipolar mode clock inputs given in the
table of Electrical Characteristics. In this case, some attenu-
ation of the clock input level may be required. A simple
resistive divider circuit before the AC coupling capacitor is
sufficient.
30027185
FIGURE 21. DC Coupled LVCMOS/LVTTL Reference
Clock
17.10 ADDITIONAL OUTPUTS WITH AN LMK04000
FAMILY DEVICE
The number of outputs on a LMK04000 family device can be
expanded in many ways. The first method is to use the dif-
ferential outputs as two single-ended outputs. For CMOS
outputs, both the positive and negative outputs can be pro-
grammed to be in phase, or 180 degrees out of phase. LVDS/
LVPECL positive and negative outputs are always 180 de-
grees out of phase. LVDS single-ended is not recommended.
In addition to this technique, the number of outputs can be
expanded with a LMK01000 family device. To do this, one of
the clock outputs of a LMK04000 can drive the LMK01000
device. For more information on phase synchronication with
multiple devices, please refer to application note AN-1864:
http://www.national.com/an/AN/AN-1864.pdf.
17.11 OUTPUT CLOCK PHASE NOISE PERFORMANCE
VS. VCXO PHASE NOISE
The jitter cleaning capability of the LMK04000 family is highly
dependent on the phase noise performance of the VCXO (or
crystal) that is integrated with PLL1. The VCXO is the refer-
ence for PLL2 which provides the clock for the output distri-
bution path. Consequently, the designer must choose a
VCXO (or crystal) that supports the required performance at
the clock outputs.
An example of the difference in performance that can be ob-
tained from various VCXOs is illustrated in the following plots.
49 www.national.com
LMK04000 Family
Figure 22 compares the phase noise of two different VCXOs:
VCXO “A” and VCXO “B”. Both VCXOs have a center fre-
quency of 100 MHz. The figure of merit, RMS jitter, is mea-
sured over the bandwidth 100 Hz to 200 kHz. This is the most
relevant integration bandwidth for the VCXO because it will
have the most impact inside the loop bandwidth of PLL2.
30027147
FIGURE 22. VCXO Phase Noise Comparison, 100 MHz
This plot shows that VCXO “B” exhibits superior phase noise
when compared to VCXO “A”. Both VCXOs offer excellent
jitter performance from 100 Hz to 200 kHz. VCXO “A” exhibits
RMS jitter of 151 femtoseconds (fs), while VCXO “B” has RMS
jitter of 90 fs.
Figures 23, 24, 25 present a side-by-side comparison of clock
output phase noise at 250 MHz, organized by output format
and associated VCXO. The total RMS jitter listed on the plots
is integrated from 100 Hz to 20 MHz. Examining these plots,
the clock output phase noise associated with VCXO “B” is
superior in all cases. The average improvement in RMS jitter
due to VCXO “B” is approximately 47 fs. The plots show the
primary difference in clock output phase noise is in the band
from 100 Hz to approximately 4 kHz. Across this range, the
VCXO phase noise dominates that of the PLL, given the loop
bandwidth of this design, which is 152 kHz. Above 4 kHz, the
PLL noise dominates (inside the loop bandwidth), so it is ba-
sically the same for either VCXO. Comparing the jitter of two
VCXOs in the 100 Hz to 4 kHz band, it can be shown that
VCXO “A” exhibits jitter of 142 fs, and VCXO “B” exhibits jitter
of 90 fs. The difference, 52 fs, accounts for the majority of the
average difference in RMS jitter at the clock outputs when
comparing VCXOs.
The PLL configurations listed below were the same for both
VCXOs/LMK040xx pair:
•PLL1 loop filter components: C1 = 100 nF, C2 = 680 nF,
R2 = 39 kΩ
•PLL1 fPD = 1 MHz, CP gain = 100 µA, loop BW = 20 Hz
•PLL2 loop filter components: C1 = 0, C2 = 12 nF, R2 = 1.8
kΩ
•PLL2 fPD = 25 MHz, CP gain = 3200 µA, loop BW = 152
kHz
www.national.com 50
LMK04000 Family
30027150
FIGURE 23. LVDS Clock Output Phase Noise Comparison, 250 MHz
30027151
FIGURE 24. LVPECL Clock Output Phase Noise Comparison, 250 MHz
30027152
FIGURE 25. LVCMOS Clock Output Phase Noise Comparison, 250 MHz
51 www.national.com
LMK04000 Family
www.national.com 52
LMK04000 Family
18.0 Physical Dimensions inches (millimeters) unless otherwise noted
Leadless Leadframe Package (Bottom View)
48 Pin LLP (SQA48A) Package
19.0 Ordering Information
Order Number VCO Frequency
Band Packing Package Marking
LMK04000BISQX 1.2 GHz 2500 Unit Tape and Reel K04000BI
LMK04000BISQ 1.2 GHz 1000 Unit Tape and Reel K04000BI
LMK04000BISQE 1.2 GHz 250 Unit Tape and Reel K04000BI
LMK04001BISQX 1.5 GHz 2500 Unit Tape and Reel K04001BI
LMK04001BISQ 1.5 GHz 1000 Unit Tape and Reel K04001BI
LMK04001BISQE 1.5 GHz 250 Unit Tape and Reel K04001BI
LMK04002BISQX 1.6 GHz 2500 Unit Tape and Reel K04002BI
LMK04002BISQ 1.6 GHz 1000 Unit Tape and Reel K04002BI
LMK04002BISQE 1.6 GHz 250 Unit Tape and Reel K04002BI
LMK04010BISQX 1.2 GHz 2500 Unit Tape and Reel K04010BI
LMK04010BISQ 1.2 GHz 1000 Unit Tape and Reel K04010BI
LMK04010BISQE 1.2 GHz 250 Unit Tape and Reel K04010BI
LMK04011BISQX 1.5 GHz 2500 Unit Tape and Reel K04011BI
LMK04011BISQ 1.5 GHz 1000 Unit Tape and Reel K04011BI
LMK04011BISQE 1.5 GHz 250 Unit Tape and Reel K04011BI
LMK04031BISQX 1.5 GHz 2500 Unit Tape and Reel K04031BI
LMK04031BISQ 1.5 GHz 1000 Unit Tape and Reel K04031BI
LMK04031BISQE 1.5 GHz 250 Unit Tape and Reel K04031BI
LMK04033BISQX 2.0 GHz 2500 Unit Tape and Reel K04033BI
LMK04033BISQ 2.0 GHz 1000 Unit Tape and Reel K04033BI
LMK04033BISQE 2.0 GHz 250 Unit Tape and Reel K04033BI
53 www.national.com
LMK04000 Family
Notes
LMK04000 Family Low-Noise Clock Jitter Cleaner with Cascaded PLLs
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