Preliminary AEC Q100 Grade 1 Compliant
This is a product that has fixed target specifications but are subject Ramtron International Corporation
to change pending characterization results. 1850 Ramtron Drive, Colorado Springs, CO 80921
(800) 545-FRAM, (719) 481-7000
Rev. 1.1 http://www.ramtron.com
June 2011 Page 1 of 12
FM24CL64B - Automotive Temp.
64Kb Serial 3V F-RAM Memory
Features
64K bit Ferroelectric Nonvolatile RAM
Organized as 8192 x 8 bits
High Endurance 10 Trillion (1013) Read/Writes
NoDelay™ Writes
Advanced High-Reliability Ferroelectric Process
Fast Two-wire Serial Interface
Up to 1 MHz maximum bus frequency
Direct hardware replacement for EEPROM
Supports legacy timing for 100 kHz & 400 kHz
Low Power Consumption
Low Voltage Operation 3.0-3.6V
6 A Standby Current (+85C)
Industry Standard Configuration
Automotive Temperature -40C to +125C
o Qualified to AEC Q100 Specification
8-pin “Green”/RoHS SOIC Package
Description
The FM24CL64B is a 64Kbit nonvolatile memory
employing an advanced ferroelectric process. A
ferroelectric random access memory or F-RAM is
nonvolatile and performs reads and writes like a
RAM. It provides reliable data retention for years
while eliminating the complexities, overhead, and
system level reliability problems caused by
EEPROM and other nonvolatile memories.
The FM24CL64B performs write operations at bus
speed. No write delays are incurred. The next bus
cycle may commence immediately without the need
for data polling. In addition, the product offers write
endurance orders of magnitude higher than
EEPROM. Also, F-RAM exhibits much lower power
during writes than EEPROM since write operations
do not require an internally elevated power supply
voltage for write circuits.
These capabilities make the FM24CL64B ideal for
nonvolatile memory applications requiring frequent
or rapid writes. Examples range from data collection
where the number of write cycles may be critical, to
demanding industrial controls where the long write
time of EEPROM can cause data loss. The
combination of features allows more frequent data
writing with less overhead for the system.
The FM24CL64B provides substantial benefits to
users of serial EEPROM, yet these benefits are
available in a hardware drop-in replacement. The
device is available in industry standard 8-pin SOIC
package using a familiar two-wire (I2C) protocol. The
device is guaranteed over the automotive temperature
range of -40°C to +125°C.
Pin Configuration
A0
A1
A2
VSS
VDD
WP
SCL
SDA
1
2
3
4
8
7
6
5
Pin Name
Function
A0-A2
Device Select Address
SDA
Serial Data/address
SCL
Serial Clock
WP
Write Protect
VDD
Supply Voltage
VSS
Ground
Ordering Information
FM24CL64B-GA
“Green”/RoHS 8-pin SOIC,
Automotive Grade 1
FM24CL64B-GATR
“Green”/RoHS 8-pin SOIC,
Automotive Grade 1,
Tape & Reel
FM24CL64B - 64Kb 3V I2C F-RAM (Automotive Temp.)
Rev. 1.1
June 2011 Page 2 of 12
Address
Latch
1K x 64
FRAM Array
Data Latch
8
SDA
Counter
Serial to Parallel
Converter
Control Logic
SCL
WP
A0-A2
Figure 1. FM24CL64B Block Diagram
Pin Description
Pin Name
Pin Description
A0-A2
Device Select Address 0-2: These pins are used to select one of up to 8 devices of
the same type on the same two-wire bus. To select the device, the address value on
the two pins must match the corresponding bits contained in the slave address. The
address pins are pulled down internally.
SDA
Serial Data/Address: This is a bi-directional pin for the two-wire interface. It is
open-drain and is intended to be wire-OR‟d with other devices on the two-wire bus.
The input buffer incorporates a Schmitt trigger for noise immunity and the output
driver includes slope control for falling edges. An external pull-up resistor is
required.
SCL
Serial Clock: The serial clock pin for the two-wire interface. Data is clocked out of
the part on the falling edge, and into the device on the rising edge. The SCL input
also incorporates a Schmitt trigger input for noise immunity.
WP
Write Protect: When tied to VDD, addresses in the entire memory map will be write-
protected. When WP is connected to ground, all addresses may be written. This pin
is pulled down internally.
VDD
Supply Voltage
VSS
Ground
FM24CL64B - 64Kb 3V I2C F-RAM (Automotive Temp.)
Rev. 1.1
June 2011 Page 3 of 12
Overview
The FM24CL64B is a serial F-RAM memory. The
memory array is logically organized as a 8,192 x 8 bit
memory array and is accessed using an industry
standard two-wire interface. Functional operation of
the F-RAM is similar to serial EEPROMs. The major
difference between the FM24CL64B and a serial
EEPROM with the same pinout relates to its superior
write performance.
Memory Architecture
When accessing the FM24CL64B, the user addresses
8192 locations each with 8 data bits. These data bits
are shifted serially. The 8192 addresses are accessed
using the two-wire protocol, which includes a slave
address (to distinguish other non-memory devices)
and a 2-byte address. Only the lower 13 bits are used
by the decoder for accessing the memory. The upper
three address bits should be set to 0 for compatibility
with higher density devices in the future.
The access time for memory operation is essentially
zero beyond the time needed for the serial protocol.
That is, the memory is read or written at the speed of
the two-wire bus. Unlike an EEPROM, it is not
necessary to poll the device for a ready condition
since writes occur at bus speed. That is, by the time a
new bus transaction can be shifted into the part, a
write operation will be complete. This is explained in
more detail in the interface section below.
Users expect several obvious system benefits from
the FM24CL64B due to its fast write cycle and high
endurance as compared with EEPROM. However
there are less obvious benefits as well. For example
in a high noise environment, the fast-write operation
is less susceptible to corruption than an EEPROM
since it is completed quickly. By contrast, an
EEPROM requiring milliseconds to write is
vulnerable to noise during much of the cycle.
Note that it is the user‟s responsibility to ensure that
VDD is within datasheet tolerances to prevent
incorrect operation.
Two-wire Interface
The FM24CL64B employs a bi-directional two-wire
bus protocol using few pins or board space. Figure 2
illustrates a typical system configuration using the
FM24CL64B in a microcontroller-based system. The
industry standard two-wire bus is familiar to many
users but is described in this section.
By convention, any device that is sending data onto
the bus is the transmitter while the target device for
this data is the receiver. The device that is controlling
the bus is the master. The master is responsible for
generating the clock signal for all operations. Any
device on the bus that is being controlled is a slave.
The FM24CL64B always is a slave device.
The bus protocol is controlled by transition states in
the SDA and SCL signals. There are four conditions
including start, stop, data bit, or acknowledge. Figure
3 illustrates the signal conditions that specify the four
states. Detailed timing diagrams are shown in the
electrical specifications section.
Microcontroller
SDA SCL
FM24CL64B
A0 A1 A2
SDA SCL
FM24CL64B
A0 A1 A2
VDD
Rmin = 1.1 Kohm
Rmax = tR/Cbus
Figure 2. Typical System Configuration
FM24CL64B - 64Kb 3V I2C F-RAM (Automotive Temp.)
Rev. 1.1
June 2011 Page 4 of 12
Stop
(Master) Start
(Master)
7
Data bits
(Transmitter)
6 0
Data bit
(Transmitter)Acknowledge
(Receiver)
SCL
SDA
Figure 3. Data Transfer Protocol
Stop Condition
A stop condition is indicated when the bus master
drives SDA from low to high while the SCL signal is
high. All operations using the FM24CL64B should
end with a stop condition. If an operation is in
progress when a stop is asserted, the operation will be
aborted. The master must have control of SDA (not a
memory read) in order to assert a stop condition.
Start Condition
A start condition is indicated when the bus master
drives SDA from high to low while the SCL signal is
high. All commands should be preceded by a start
condition. An operation in progress can be aborted by
asserting a start condition at any time. Aborting an
operation using the start condition will ready the
FM24CL64B for a new operation.
If during operation the power supply drops below the
specified VDD minimum, the system should issue a
start condition prior to performing another operation.
Data/Address Transfer
All data transfers (including addresses) take place
while the SCL signal is high. Except under the two
conditions described above, the SDA signal should
not change while SCL is high.
Acknowledge
The acknowledge takes place after the 8th data bit has
been transferred in any transaction. During this state
the transmitter should release the SDA bus to allow
the receiver to drive it. The receiver drives the SDA
signal low to acknowledge receipt of the byte. If the
receiver does not drive SDA low, the condition is a
no-acknowledge and the operation is aborted.
The receiver would fail to acknowledge for two
distinct reasons. First is that a byte transfer fails. In
this case, the no-acknowledge ceases the current
operation so that the part can be addressed again.
This allows the last byte to be recovered in the event
of a communication error.
Second and most common, the receiver does not
acknowledge to deliberately end an operation. For
example, during a read operation, the FM24CL64B
will continue to place data onto the bus as long as the
receiver sends acknowledges (and clocks). When a
read operation is complete and no more data is
needed, the receiver must not acknowledge the last
byte. If the receiver acknowledges the last byte, this
will cause the FM24CL64B to attempt to drive the
bus on the next clock while the master is sending a
new command such as stop.
Slave Address
The first byte that the FM24CL64B expects after a
start condition is the slave address. As shown in
Figure 4, the slave address contains the device type
or slave ID, the device select address bits, a page
address bit, and a bit that specifies if the transaction
is a read or a write.
Bits 7-4 are the device type (slave ID) and should be
set to 1010b for the FM24CL64B. These bits allow
other function types to reside on the 2-wire bus
within an identical address range. Bits 3-1 are the
device select address bits. They must match the
corresponding value on the external address pins to
select the device. Up to eight FM24CL64B devices
can reside on the same two-wire bus by assigning a
different address to each. Bit 0 is the read/write bit.
R/W=1 indicates a read operation and R/W=0
indicates a write operation.
Figure 4. Slave Address
1
0
1
0
A2
R/W
Slave ID
7
6
5
4
3
2
1
0
A1
A0
Device Select
FM24CL64B - 64Kb 3V I2C F-RAM (Automotive Temp.)
Rev. 1.1
June 2011 Page 5 of 12
Addressing Overview
After the FM24CL64B (as receiver) acknowledges
the slave address, the master can place the memory
address on the bus for a write operation. The address
requires two bytes. The first is the MSB. Since the
device uses only 13 address bits, the value of the
upper three bits are “don‟t care”. Following the MSB
is the LSB with the remaining eight address bits. The
address value is latched internally. Each access
causes the latched address value to be incremented
automatically. The current address is the value that is
held in the latch -- either a newly written value or the
address following the last access. The current address
will be held for as long as power remains or until a
new value is written. Reads always use the current
address. A random read address can be loaded by
beginning a write operation as explained below.
After transmission of each data byte, just prior to the
acknowledge, the FM24CL64B increments the
internal address latch. This allows the next sequential
byte to be accessed with no additional addressing.
After the last address (1FFFh) is reached, the address
latch will roll over to 0000h. There is no limit to the
number of bytes that can be accessed with a single
read or write operation.
Data Transfer
After the address information has been transmitted,
data transfer between the bus master and the
FM24CL64B can begin. For a read operation the
FM24CL64B will place 8 data bits on the bus then
wait for an acknowledge from the master. If the
acknowledge occurs, the FM24CL64B will transfer
the next sequential byte. If the acknowledge is not
sent, the FM24CL64B will end the read operation.
For a write operation, the FM24CL64B will accept 8
data bits from the master then send an acknowledge.
All data transfer occurs MSB (most significant bit)
first.
Memory Operation
The FM24CL64B is designed to operate in a manner
very similar to other 2-wire interface memory
products. The major differences result from the
higher performance write capability of F-RAM
technology. These improvements result in some
differences between the FM24CL64B and a similar
configuration EEPROM during writes. The complete
operation for both writes and reads is explained
below.
Write Operation
All writes begin with a slave address, then a memory
address. The bus master indicates a write operation
by setting the LSB of the slave address (R/W bit) to a
„0‟. After addressing, the bus master sends each byte
of data to the memory and the memory generates an
acknowledge condition. Any number of sequential
bytes may be written. If the end of the address range
is reached internally, the address counter will wrap
from 1FFFh to 0000h.
Unlike other nonvolatile memory technologies, there
is no effective write delay with F-RAM. Since the
read and write access times of the underlying
memory are the same, the user experiences no delay
through the bus. The entire memory cycle occurs in
less time than a single bus clock. Therefore, any
operation including read or write can occur
immediately following a write. Acknowledge polling,
a technique used with EEPROMs to determine if a
write is complete is unnecessary and will always
return a ready condition.
Internally, an actual memory write occurs after the 8th
data bit is transferred. It will be complete before the
acknowledge is sent. Therefore, if the user desires to
abort a write without altering the memory contents,
this should be done using start or stop condition prior
to the 8th data bit. The FM24CL64B uses no page
buffering.
The memory array can be write-protected using the
WP pin. Setting the WP pin to a high condition
(VDD) will write-protect all addresses. The
FM24CL64B will not acknowledge data bytes that
are written to protected addresses. In addition, the
address counter will not increment if writes are
attempted to these addresses. Setting WP to a low
state (VSS) will deactivate this feature. WP is pulled
down internally.
Figures 5 and 6 below illustrate a single-byte and
multiple-byte write cycles.
FM24CL64B - 64Kb 3V I2C F-RAM (Automotive Temp.)
Rev. 1.1
June 2011 Page 6 of 12
S ASlave Address 0 Address MSB A Data Byte A P
By Master
By F-RAM
Start Address & Data Stop
Acknowledge
Address LSB A
Figure 5. Single Byte Write
S ASlave Address 0 Address MSB A Data Byte A P
By Master
By F-RAM
Start
Address & Data Stop
Acknowledge
Address LSB A Data Byte A
Figure 6. Multiple Byte Write
Read Operation
There are two basic types of read operations. They
are current address read and selective address read. In
a current address read, the FM24CL64B uses the
internal address latch to supply the address. In a
selective read, the user performs a procedure to set
the address to a specific value.
Current Address & Sequential Read
As mentioned above the FM24CL64B uses an
internal latch to supply the address for a read
operation. A current address read uses the existing
value in the address latch as a starting place for the
read operation. The system reads from the address
immediately following that of the last operation.
To perform a current address read, the bus master
supplies a slave address with the LSB set to a „1‟.
This indicates that a read operation is requested.
After receiving the complete slave address, the
FM24CL64B will begin shifting out data from the
current address on the next clock. The current address
is the value held in the internal address latch.
Beginning with the current address, the bus master
can read any number of bytes. Thus, a sequential read
is simply a current address read with multiple byte
transfers. After each byte the internal address counter
will be incremented.
Each time the bus master acknowledges a byte,
this indicates that the FM24CL64B should read
out the next sequential byte.
There are four ways to properly terminate a read
operation. Failing to properly terminate the read will
most likely create a bus contention as the
FM24CL64B attempts to read out additional data
onto the bus. The four valid methods are:
1. The bus master issues a no-acknowledge in the
9th clock cycle and a stop in the 10th clock cycle.
This is illustrated in the diagrams below. This is
preferred.
2. The bus master issues a no-acknowledge in the
9th clock cycle and a start in the 10th.
3. The bus master issues a stop in the 9th clock
cycle.
4. The bus master issues a start in the 9th clock
cycle.
If the internal address reaches 1FFFh, it will wrap
around to 0000h on the next read cycle. Figures 7 and
8 below show the proper operation for current
address reads.
Selective (Random) Read
There is a simple technique that allows a user to
select a random address location as the starting point
for a read operation. This involves using the first
three bytes of a write operation to set the internal
address followed by subsequent read operations.
FM24CL64B - 64Kb 3V I2C F-RAM (Automotive Temp.)
Rev. 1.1
June 2011 Page 7 of 12
To perform a selective read, the bus master sends out
the slave address with the LSB set to 0. This specifies
a write operation. According to the write protocol,
the bus master then sends the address bytes that are
loaded into the internal address latch. After the
FM24CL64B acknowledges the address, the bus
master issues a start condition. This simultaneously
aborts the write operation and allows the read
command to be issued with the slave address LSB set
to a „1‟. The operation is now a current address read.
S ASlave Address 1 Data Byte 1 P
By Master
By F-RAM
Start Address
Stop
Acknowledge
No
Acknowledge
Data
Figure 7. Current Address Read
S ASlave Address 1 Data Byte 1 P
By Master
By F-RAM
Start Address
Stop
Acknowledge
No
Acknowledge
Data
Data ByteA
Acknowledge
Figure 8. Sequential Read
S ASlave Address 1 Data Byte 1 P
By Master
By F-RAM
Start Address
Stop
No
Acknowledge
Data
S ASlave Address 0 Address MSB A
Start
Address
Acknowledge
Address LSB A
Figure 9. Selective (Random) Read
FM24CL64B - 64Kb 3V I2C F-RAM (Automotive Temp.)
Rev. 1.1
June 2011 Page 8 of 12
Electrical Specifications
Absolute Maximum Ratings
Symbol
Description
Ratings
VDD
Power Supply Voltage with respect to VSS
-1.0V to +4.5V
VIN
Voltage on any pin with respect to VSS
-1.0V to +4.5V
and VIN < VDD+1.0V *
TSTG
Storage Temperature
-55C to +125C
TLEAD
Lead Temperature (Soldering, 10 seconds)
260 C
VESD
Electrostatic Discharge Voltage
- Human Body Model (AEC-Q100-002 Rev. E)
- Charged Device Model (AEC-Q100-011 Rev. B)
- Machine Model (AEC-Q100-003 Rev. E)
4kV
1.25kV
300V
Package Moisture Sensitivity Level
MSL-1
* Exception: The “VIN < VDD+1.0V” restriction does not apply to the SCL and SDA inputs.
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating
only, and the functional operation of the device at these or any other conditions above those listed in the operational section of this
specification is not implied. Exposure to absolute maximum ratings conditions for extended periods may affect device reliability.
DC Operating Conditions (TA = -40 C to + 125 C, VDD =3.0V to 3.6V unless otherwise specified)
Symbol
Parameter
Min
Typ
Units
Notes
VDD
Main Power Supply
3.0
3.3
V
IDD
VDD Supply Current
@ SCL = 100 kHz
@ SCL = 400 kHz
@ SCL = 1 MHz
A
A
A
1
ISB
Standby Current
@ +85C
@ +125C
-
-
A
A
2
ILI
Input Leakage Current
A
3
ILO
Output Leakage Current
A
3
VIL
Input Low Voltage
-0.3
V
VIH
Input High Voltage
0.75 VDD
V
VOL
Output Low Voltage (IOL = 3 mA)
V
RIN
Address Input Resistance (WP, A2-A0)
For VIN = VIL (max)
For VIN = VIH (min)
40
1
K
M
5
VHYS
Input Hysteresis
0.05 VDD
V
4
Notes
1. SCL toggling between VDD-0.2V and VSS, other inputs VSS or VDD-0.2V.
2. SCL = SDA = VDD. All inputs VSS or VDD. Stop command issued.
3. VIN or VOUT = VSS to VDD. Does not apply to WP, A2-A0 pins.
4. This parameter is characterized but not tested.
5. The input pull-down circuit is stronger (40K) when the input voltage is below VIL and weak (1M) when the input voltage
is above VIH.
FM24CL64B - 64Kb 3V I2C F-RAM (Automotive Temp.)
Rev. 1.1
June 2011 Page 9 of 12
AC Parameters (TA = -40 C to + 125 C, VDD =3.0V to 3.6V unless otherwise specified)
Symbol
Parameter
Min
Max
Min
Max
Min
Max
Units
Notes
fSCL
SCL Clock Frequency
0
100
0
400
0
1000
kHz
1
tLOW
Clock Low Period
4.7
1.3
0.6
s
tHIGH
Clock High Period
4.0
0.6
0.4
s
tAA
SCL Low to SDA Data Out Valid
3
0.9
0.55
s
tBUF
Bus Free Before New
Transmission
4.7
1.3
0.5
s
tHD:STA
Start Condition Hold Time
4.0
0.6
0.25
s
tSU:STA
Start Condition Setup for Repeated
Start
4.7
0.6
0.25
s
tHD:DAT
Data In Hold
0
0
0
ns
tSU:DAT
Data In Setup
250
100
100
ns
tR
Input Rise Time
1000
300
300
ns
2
tF
Input Fall Time
300
300
100
ns
2
tSU:STO
Stop Condition Setup
4.0
0.6
0.25
s
tDH
Data Output Hold
(from SCL @ VIL)
0
0
0
ns
tSP
Noise Suppression Time Constant
on SCL, SDA
50
50
50
ns
Notes: All SCL specifications as well as start and stop conditions apply to both read and write operations.
1. The speed-related specifications are guaranteed characteristic points along a continuous curve of operation from DC to fSCL
(max).
2. This parameter is periodically sampled and not 100% tested.
Capacitance (TA = 25 C, f=1.0 MHz, VDD = 3.3V)
Symbol
Parameter
Min
Max
Units
Notes
CI/O
Input/Output Capacitance (SDA)
-
8
pF
1
CIN
Input Capacitance
-
6
pF
1
Notes
1. This parameter is periodically sampled and not 100% tested.
Power Cycle Timing
VDD min.
VDD
SDA,SCL
tVR
tPD
tPU
tVF
Power Cycle Timing (TA = -40 C to +125 C, VDD = 3.0V to 3.6V)
Symbol
Parameter
Min
Max
Units
Notes
tPU
Power Up (VDD min) to First Access (Start condition)
10
-
ms
tPD
Last Access (Stop condition) to Power Down (VDD min)
0
-
s
tVR
VDD Rise Time
30
-
s/V
1
tVF
VDD Fall Time
100
-
s/V
1
Notes
1. Slope measured at any point on VDD waveform.
FM24CL64B - 64Kb 3V I2C F-RAM (Automotive Temp.)
Rev. 1.1
June 2011 Page 10 of 12
AC Test Conditions Equivalent AC Test Load Circuit
Input Pulse Levels 0.1 VDD to 0.9 VDD
Input rise and fall times 10 ns
Input and output timing levels 0.5 VDD
Diagram Notes
All start and stop timing parameters apply to both read and write cycles.
Clock specifications are identical for read and write cycles. Write
timing parameters apply to slave address, word address, and write data
bits. Functional relationships are illustrated in the relevant datasheet
sections. These diagrams illustrate the timing parameters only.
Read Bus Timing
t
SU:SDA
Start
t
R
`t
F
Stop Start
t
BUF
t
HIGH
1/fSCL
t
LOW
t
SP
t
SP
Acknowledge
t
HD:DAT
t
SU:DAT
t
AA
t
DH
SCL
SDA
Write Bus Timing
t
SU:STO
Start Stop Start Acknowledge
t
AA
t
HD:DAT
t
HD:STA
t
SU:DAT
SCL
SDA
Data Retention
Parameter
Min
Max
Units
Notes
Data Retention
@ TA = +55C
@ TA = +105C
@ TA = +125C
17
10,000
1,000
-
-
-
Years
Hours
Hours
Note: Data retention qualification tests are accelerated tests and are performed such that all three conditions have been applied:
(1) 17 years at a temperature of +55C, (2) 10,000 hours at +105C, and (3) 1,000 hours at +125C.
Typical Grade 1 Operating Profile
0
200
400
600
800
1000
1200
1400
1600
70 75 80 85 90 95 100 105 110 115 120 125
Temperature (°C)
Hours
Typical Grade 1 Storage Profile
0
5000
10000
15000
20000
25000
0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80
Temperature (°C)
Hours
3.6V
Output
1.8 Kohm
100 pF
FM24CL64B - 64Kb 3V I2C F-RAM (Automotive Temp.)
Rev. 1.1
June 2011 Page 11 of 12
Mechanical Drawing
8-pin SOIC (JEDEC Standard MS-012 variation AA)
Pin 1
3.90 ±0.10 6.00 ±0.20
4.90 ±0.10
0.10
0.25
1.35
1.75
0.33
0.51
1.27 0.10 mm
0.25
0.50
45
0.40
1.27
0.19
0.25
0 - 8
Recommended PCB Footprint
7.70
0.65
1.27
2.00
3.70
Refer to JEDEC MS-012 for complete dimensions and notes.
All dimensions in millimeters.
SOIC Package Marking Scheme
Legend:
XXXXX= part number, P=package type
R=rev code, LLLLLLL= lot code
RIC=Ramtron Int‟l Corp, YY=year, WW=work week
Example: FM24CL64B-GA, “Green” SOIC, Automotive Temperature,
Rev A, Lot L3502G1, Year 2011, Work Week 04
24CL64BGA
AL3502G1
RIC1104
XXXXXX-P
RLLLLLLL
RICYYWW
FM24CL64B - 64Kb 3V I2C F-RAM (Automotive Temp.)
Rev. 1.1
June 2011 Page 12 of 12
Revision History
Revision
Date
Summary
1.0
2/22/2011
Initial Release
1.1
6/2/2011
Added ESD ratings. Fixed notes 4 and 5 in DC table.