®
1. General description
The ADC1212D is a dual channel 12-bit Analog-to-Digital Converter (ADC) optimized for
high dynamic performances and low power consumption at sample rates up to 125 Msps.
Pipelined architecture and output error correction ensure the ADC1212D is accurate
enough to guarantee zero missing codes over the entire operating range. Supplied from a
single 3 V source, it can handle output logic levels from 1.8 V to 3.3 V in
Complementary Metal Oxide Semiconductor (CMOS) mode, because of a separate digital
output supply. It supports the Low Voltage Differential Signalling (LVDS) Double Data Rate
(DDR) output standard. An integrated Serial Peripheral Interface (SPI) allows the user to
easily configure the ADC. The device also includes a programmable full-scale SPI to allow
a flexible input voltage range of 1 V (p-p) to 2 V (p-p). With excellent dynamic
performance from the baseband to input frequencies of 170 MHz or more, the ADC1212D
is ideal for use in communications, imaging and medical applications.
2. Features and benefits
3. Applications
ADC1212D series
Dual 12-bit ADC; 65 Msps, 80 Msps, 105 Msps or 125 Msps;
CMOS or LVDS DDR digital outputs
Rev. 03 — 2 July 2012 Product data sheet
SNR, 70 dBFS Input bandwidth, 600 MHz
SFDR, 86 dBc Power dissipation, 855 mW at 80 Msps
Sample rate up to 125 Msps Serial Peripheral Interface (SPI)
Clock input divided by 2 to reduce jitter
contribution
Duty cycle stabilizer
Single 3 V supply Fast OuT-of-Range (OTR) detection
Flexible input voltage range:
1Vto2V(p-p)
Offset binary, two’s complement, gray
code
CMOS or LVDS DDR digital outputs Power-down and Sleep modes
Pin and software compatible with
ADC1412D series and ADC1112D125.
HVQFN64 package
Wireless and wired broadband
communications
Spectral analysis
Portable instrumentation Ultrasound equipment
Imaging systems Software defined radio
ADC1212D_SER 3 © IDT 2012. All rights reserved.
Product data sheet Rev. 03 — 2 July 2012 2 of 40
Integrated Device Technology
ADC1212D series
Dual 12-bit ADC: CMOS or LVDS DDR digital outputs
4. Ordering information
5. Block diagram
Table 1. Ordering information
Type number fs (Msps) Package
Name Description Version
ADC1212D125HN-C1 125 HVQFN64 plastic thermal enhanced very thin quad flat package;
no leads; 64 terminals; body 9 90.85 mm
SOT804-3
ADC1212D105HN-C1 105 HVQFN64 plastic thermal enhanced very thin quad flat package;
no leads; 64 terminals; body 9 90.85 mm
SOT804-3
ADC1212D080HN-C1 80 HVQFN64 plastic thermal enhanced very thin quad flat package;
no leads; 64 terminals; body 9 90.85 mm
SOT804-3
ADC1212D065HN-C1 65 HVQFN64 plastic thermal enhanced very thin quad flat package;
no leads; 64 terminals; body 9 90.85 mm
SOT804-3
Fig 1. Block diagram
ADC1212D
SPI INTERFACE
OUTPUT
DRIVERS
OUTPUT
DRIVERS
SYSTEM
REFERENCE AND
POWER
MANAGEMENT
ERROR
CORRECTION AND
DIGITAL
PROCESSING
ADC CORE
12-BIT
PIPELINED
T/H
INPUT
STAGE
INAP
CS
SDIO/ODS
SCLK/DFS
OTRA
OTRB
CTRL
REFAT
REFAB
REFBB
REFBT
CMOS:
DA11 to DA0
or
LVDS/DDR:
DA10_DA11_P to DA0_DA1_P,
DA10_DA11_M to DA0_DA1_M
CMOS:
DB11 to DB0
or
LVDS/DDR:
DB10_DB11_P to DB0_DB1_P,
DB10_DB11_M to DB0_DB1_M
INAM
CLKP
CLKM
CLOCK INPUT
STAGE AND DUTY
CYCLE CONTROL
VCMA
VREF
SENSE
VCMB
OUTPUT
DRIVERS
ADC CORE
12-BIT
PIPELINED
T/H
INPUT
STAGE
INBP
INBM
ERROR
CORRECTION AND
DIGITAL
PROCESSING
CMOS:
DAV
or
LVDS/DDR:
DAVP
DAVM
005aaa128
ADC1212D_SER 3 © IDT 2012. All rights reserved.
Product data sheet Rev. 03 — 2 July 2012 3 of 40
Integrated Device Technology
ADC1212D series
Dual 12-bit ADC: CMOS or LVDS DDR digital outputs
6. Pinning information
6.1 CMOS outputs selected
6.1.1 Pinning
6.1.2 Pin description
Fig 2. Pin configuration with CMOS digital outputs selected
ADC1212D
HVQFN64
Transparent top view
DB5
INBM
INBP
DB4
AGND DB3
VCMB DB2
REFBT DB1
REFBB DB0
AGND n.c.
CLKM n.c.
CLKP n.c.
AGND DAV
REFAB n.c.
REFAT n.c.
VCMA DA0
AGND DA1
INAM DA2
INAP DA3
VDDA
VDDA
SCLK/DFS
SDIO/ODS
CS
CTRL
DECB
OTRB
DB11
DB10
DB9
DB8
DB7
DB6
VDDO
VDDO
VDDA
VREF
SENSE
VDDA
DECA
OTRA
DA11
DA10
DA9
DA8
DA7
DA6
DA5
DA4
VDDO
VDDO
16 33
15 34
14 35
13 36
12 37
11 38
10 39
940
841
742
643
544
445
346
247
148
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
terminal 1
index area
005aaa129
Table 2. Pin description (CMOS digital outputs)
Symbol Pin Type [1] Description
INAP 1 I analog input; channel A
INAM 2 I complementary analog input; channel A
AGND 3 G analog ground
VCMA 4 O common-mode output voltage; channel A
REFAT 5 O top reference; channel A
REFAB 6 O bottom reference; channel A
AGND 7 G analog ground
CLKP 8 I clock input
CLKM 9 I complementary clock input
AGND 10 G analog ground
REFBB 11 O bottom reference; channel B
REFBT 12 O top reference; channel B
ADC1212D_SER 3 © IDT 2012. All rights reserved.
Product data sheet Rev. 03 — 2 July 2012 4 of 40
Integrated Device Technology
ADC1212D series
Dual 12-bit ADC: CMOS or LVDS DDR digital outputs
VCMB 13 O common-mode output voltage; channel B
AGND 14 G analog ground
INBM 15 I complementary analog input; channel B
INBP 16 I analog input; channel B
VDDA 17 P analog power supply
VDDA 18 P analog power supply
SCLK/DFS 19 I SPI clock/data format select
SDIO/ODS 20 I/O SPI data input/output/output data standard
CS 21 I SPI chip select, active LOW
CTRL 22 I control mode select
DECB 23 O regulator decoupling node; channel B
OTRB 24 O out-of-range; channel B
DB11 25 O data output bit 11 (Most Significant Bit (MSB)); channel B
DB10 26 O data output bit 10; channel B
DB9 27 O data output bit 9; channel B
DB8 28 O data output bit 8; channel B
DB7 29 O data output bit 7; channel B
DB6 30 O data output bit 6; channel B
VDDO 31 P output power supply
VDDO 32 P output power supply
DB5 33 O data output bit 5; channel B
DB4 34 O data output bit 4; channel B
DB3 35 O data output bit 3; channel B
DB2 36 O data output bit 2; channel B
DB1 37 O data output bit 1; channel B
DB0 38 O data output bit 0 (Least Significant Bit (LSB)); channel B
n.c. 39 - not connected
n.c. 40 - not connected
n.c. 41 - not connected
DAV 42 O data valid output clock
n.c. 43 - not connected
n.c. 44 - not connected
DA0 45 O data output bit 0 (LSB); channel A
DA1 46 O data output bit 1; channel A
DA2 47 O data output bit 2; channel A
DA3 48 O data output bit 3; channel A
VDDO 49 P output power supply
VDDO 50 P output power supply
DA4 51 O data output bit 4; channel A
DA5 52 O data output bit 5; channel A
DA6 53 O data output bit 6; channel A
DA7 54 O data output bit 7; channel A
DA8 55 O data output bit 8; channel A
DA9 56 O data output bit 9; channel A
Table 2. Pin description (CMOS digital outputs) …continued
Symbol Pin Type [1] Description
ADC1212D_SER 3 © IDT 2012. All rights reserved.
Product data sheet Rev. 03 — 2 July 2012 5 of 40
Integrated Device Technology
ADC1212D series
Dual 12-bit ADC: CMOS or LVDS DDR digital outputs
[1] P: power supply; G: ground; I: input; O: output; I/O: input/output.
6.2 LVDS DDR outputs selected
6.2.1 Pinning
DA10 57 O data output bit 10; channel A
DA11 58 O data output bit 11 (MSB); channel A
OTRA 59 O out-of-range; channel A
DECA 60 O regulator decoupling node; channel A
VDDA 61 P analog power supply
SENSE 62 I reference programming pin
VREF 63 I/O voltage reference input/output
VDDA 64 P analog power supply
Table 2. Pin description (CMOS digital outputs) …continued
Symbol Pin Type [1] Description
Fig 3. Pin configuration with LVDS DDR digital outputs selected
ADC1212D
HVQFN64
Transparent top view
DB4_DB5_M
INBM
INBP
DB4_DB5_P
AGND DB2_DB3_M
VCMB DB2_DB3_P
REFBT DB0_DB1_M
REFBB DB0_DB1_P
AGND n.c.
CLKM n.c.
CLKP DAVM
AGND DAVP
REFAB n.c.
REFAT n.c.
VCMA DA0_DA1_P
AGND DA0_DA1_M
INAM DA2_DA3_P
INAP DA2_DA3_M
VDDA
VDDA
SCLK/DFS
SDIO/ODS
CS
CTRL
DECB
OTRB
DB10_DB11_M.
DB10_DB11_P
DB8_DB9_M
DB8_DB9_P
DB6_DB7_M
DB6_DB7_P
VDDO
VDDO
VDDA
VREF
SENSE
VDDA
DECA
OTRA
DA10_DA11_M
DA10_DA11_P
DA8_DA9_M
DA8_DA9_P
DA6_DA7_M
DA6_DA7_P
DA4_DA5_M
DA4_DA5_P
VDDO
VDDO
16 33
15 34
14 35
13 36
12 37
11 38
10 39
9 40
8 41
7 42
6 43
5 44
4 45
3 46
2 47
1 48
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
terminal 1
index area
005aaa130
ADC1212D_SER 3 © IDT 2012. All rights reserved.
Product data sheet Rev. 03 — 2 July 2012 6 of 40
Integrated Device Technology
ADC1212D series
Dual 12-bit ADC: CMOS or LVDS DDR digital outputs
6.2.2 Pin description
[1] Pins 1 to 24, pin 59 to 64 and pins 31, 32, 49 and 50 are the same for both CMOS and LVDS DDR outputs
(see Table 2).
[2] P: power supply; G: ground; I: input; O: output; I/O: input/output.
Table 3. Pin description (LVDS DDR) digital outputs)[1]
Symbol Pin Type [2] Description
DB10_DB11_M 25 O differential output data DB10 and DB11 multiplexed,
complement
DB10_DB11_P 26 O differential output data DB10 and DB11 multiplexed, true
DB8_DB9_M 27 O differential output data DB8 and DB9 multiplexed, complement
DB8_DB9_P 28 O differential output data DB8 and DB9 multiplexed, true
DB6_DB7_M 29 O differential output data DB6 and DB7 multiplexed, complement
DB6_DB7_P 30 O differential output data DB6 and DB7 multiplexed, true
DB4_DB5_M 33 O differential output data DB4 and DB5 multiplexed, complement
DB4_DB5_P 34 O differential output data DB4 and DB5 multiplexed, true
DB2_DB3_M 35 O differential output data DB2 and DB3 multiplexed, complement
DB2_DB3_P 36 O differential output data DB2 and DB3 multiplexed, true
DB0_DB1_M 37 O differential output data DB0 and DB1 multiplexed, complement
DB0_DB1_P 38 O differential output data DB0 and DB1 multiplexed, true
n.c. 39 - not connected
n.c. 40 - not connected
DAVM 41 O data valid output clock, complement
DAVP 42 O data valid output clock, true
n.c. 43 - not connected
n.c. 44 - not connected
DA0_DA1_P 45 O differential output data DA0 and DA1 multiplexed, true
DA0_DA1_M 46 O differential output data DA0 and DA1 multiplexed, complement
DA2_DA3_P 47 O differential output data DA2 and DA3 multiplexed, true
DA2_DA3_M 48 O differential output data DA2 and DA3 multiplexed, complement
DA4_DA5_P 51 O differential output data DA4 and DA5 multiplexed, true
DA4_DA5_M 52 O differential output data DA4 and DA5 multiplexed, complement
DA6_DA7_P 53 O differential output data DA6 and DA7 multiplexed, true
DA6_DA7_M 54 O differential output data DA6 and DA7 multiplexed, complement
DA8_DA9_P 55 O differential output data DA8 and DA9 multiplexed, true
DA8_DA9_M 56 O differential output data DA8 and DA9 multiplexed, complement
DA10_DA11_P 57 O differential output data DA10 and DA11 multiplexed, true
DA10_DA11_M 58 O differential output data DA10 and DA11 multiplexed,
complement
ADC1212D_SER 3 © IDT 2012. All rights reserved.
Product data sheet Rev. 03 — 2 July 2012 7 of 40
Integrated Device Technology
ADC1212D series
Dual 12-bit ADC: CMOS or LVDS DDR digital outputs
7. Limiting values
8. Thermal characteristics
[1] Value for six layers board in still air with a minimum of 64 thermal vias.
9. Static characteristics
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter Conditions Min Max Unit
VOoutput voltage pins DA11 to DA0 and
DB11 to DB0 or pins
DA10_DA11_P to DA0_DA1_P,
DA10_DA11_M to DA0_DA1_M,
DB10_DB11_P to DB0_DB1_P
and
DB10_DB11_M to DB0_DB1_M
0.4 +3.9 V
VDDA analog supply
voltage
0.4 +3.9 V
VDDO output supply voltage 0.4 +3.9 V
Tstg storage temperature 55 +125 C
Tamb ambient temperature 40 +85 C
Tjjunction temperature - 125 C
Table 5. Thermal characteristics
Symbol Parameter Conditions Typ Unit
Rth(j-a) thermal resistance from junction to ambient [1] 15.6 K/W
Rth(j-c) thermal resistance from junction to case [1] 6.3 K/W
Table 6. Static characteristics[1]
Symbol Parameter Conditions Min Typ Max Unit
Supplies
VDDA analog supply voltage 2.85 3.0 3.4 V
VDDO output supply voltage CMOS mode 1.65 1.8 3.6 V
LVDS DDR mode 2.85 3.0 3.6 V
IDDA analog supply current fclk =125Msps; f
i=70MHz - 400 - mA
IDDO output supply current CMOS mode; fclk =125Msps;
fi=70MHz
-16-mA
LVDS DDR mode:
fclk =125Msps; f
i=70MHz
-82-mA
ADC1212D_SER 3 © IDT 2012. All rights reserved.
Product data sheet Rev. 03 — 2 July 2012 8 of 40
Integrated Device Technology
ADC1212D series
Dual 12-bit ADC: CMOS or LVDS DDR digital outputs
P power dissipation ADC1212D125;
analog supply only
-1230-mW
ADC1212D105;
analog supply only
-1120-mW
ADC1212D080;
analog supply only
-855-mW
ADC1212D065;
analog supply only
-780-mW
Power-down mode - 24 - mW
Sleep mode - 80 - mW
Clock inputs: pins CLKP and CLKM
LVPECL
Vi(clk)dif differential clock input voltage peak-to-peak - 1.6 - V
Sine
Vi(clk)dif differential clock input voltage peak-to-peak 0.8 3.0 - V
LVCMOS
VIL LOW-level input voltage - - 0.3VDDA V
VIH HIGH-level input voltage 0.7VDDA --V
Logic input: pin CTRL
VIL LOW-level input voltage - 0 - V
LOW-medium level - 0.3VDDA -V
medium-HIGH level - 0.6VDDA -V
VIH HIGH-level input voltage - VDDA -V
IIL LOW-level input current 10 - +10 A
IIH HIGH-level input current 10 - +10 A
Serial peripheral interface: pins CS, SDIO/ODS, SCLK/DFS
VIL LOW-level input voltage 0 - 0.3VDDA V
VIH HIGH-level input voltage 0.7VDDA -V
DDA V
IIL LOW-level input current 10 - +10 A
IIH HIGH-level input current 50 - +50 A
CIinput capacitance - 4 - pF
Digital outputs, CMOS mode: pins DA11 to DA0, DB11 to DB0, OTRA, OTRB and DAV
Output levels, VDDO=3V
VOL LOW-level output voltage AGND - 0.2VDDO V
VOH HIGH-level output voltage 0.8VDDO -V
DDO V
COoutput capacitance high impedance; see Table 10 - 3 - pF
Output levels, VDDO =1.8V
VOL LOW-level output voltage AGND - 0.2VDDO V
VOH HIGH-level output voltage 0.8VDDO -V
DDO V
Table 6. Static characteristics[1] …continued
Symbol Parameter Conditions Min Typ Max Unit
ADC1212D_SER 3 © IDT 2012. All rights reserved.
Product data sheet Rev. 03 — 2 July 2012 9 of 40
Integrated Device Technology
ADC1212D series
Dual 12-bit ADC: CMOS or LVDS DDR digital outputs
[1] Typical values measured at VDDA =3V, V
DDO =1.8V, T
amb =25C; minimum and maximum values are across the full temperature
range Tamb =40 C to +85 C at VDDA =3V, V
DDO = 1.8 V; VINAP VINAM =1 dBFS; VINBP VINBM =1 dBFS; internal reference
mode; applied to CMOS and LVDS interface; unless otherwise specified.
Digital outputs, LVDS DDR mode: pins DA10_DA11_P to DA0_DA1_P, DA10_DA11_M to DA0_DA1_M,
DB10_DB11_P to DB0_DB1_P, DB10_DB11_M to DB0_DB1_M; DAVP and DAVM
Output levels, VDDO = 3 V only, RL= 100
VO(offset) output offset voltage output buffer current set to
3.5 mA
-1.2-V
VO(dif) differential output voltage output buffer current set to
3.5 mA
-350-mV
COoutput capacitance - 3 - pF
Analog inputs: pins INAP, INAM, INBP and INBM
IIinput current 5- +5A
RIinput resistance - 19.8 - k
CIinput capacitance - 2.8 - pF
VI(cm) common-mode input voltage VINAP =V
INAM; VINBP =V
INBM 0.9 1.5 2 V
Biinput bandwidth - 600 - MHz
VI(dif) differential input voltage peak-to-peak 1 - 2 V
Common-mode output voltage: pins VCMA and VCMB
VO(cm) common-mode output voltage - 0.5VDDA -V
IO(cm) common-mode output current - 4 - mA
I/O reference voltage: pin VREF
VVREF voltage on pin VREF output - 0.5 to 1 - V
input 0.5 - 1 V
Accuracy
INL integral non-linearity 1.25 0.25 +5 LSB
DNL differential non-linearity guaranteed no missing codes 0.95 0.5 +0.95 LSB
Eoffset offset error - 2-mV
EGgain error - 0.5 - %FS
MG(CTC) channel-to-channel gain
matching
-1.1-%
Supply
PSRR power supply rejection ratio 200 mV (p-p) on pin VDDA;
fi=DC
-37 - dB
Table 6. Static characteristics[1] …continued
Symbol Parameter Conditions Min Typ Max Unit
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ADC1212D_SER 3 © IDT 2012. All rights reserved.
Product data sheet Rev. 03 — 2 July 2012 10 of 40
Integrated Device Technology
ADC1212D series
Dual 12-bit ADC: CMOS or LVDS DDR digital outputs
10. Dynamic characteristics
10.1 Dynamic characteristics
Table 7. Characteristics[1]
Symbol Parameter Conditions ADC1212D065 ADC1212D080 ADC1212D105 ADC1212D125 Unit
Min Typ Max Min Typ Max Min Typ Max Min Typ Max
Analog signal processing
2H second harmonic level fi= 3 MHz - 87 - - 87 - - 86 - - 88 - dBc
fi=30MHz -86--86--86--87 -dBc
fi=70MHz -85--85--84--85 -dBc
fi= 170 MHz - 82 - - 82 - - 81 - - 83 - dBc
3H third harmonic level fi= 3 MHz - 86 - - 86 - - 85 - - 87 - dBc
fi=30MHz -85--85--85--86 -dBc
fi=70MHz -84--84--83--84 -dBc
fi= 170 MHz - 81 - - 81 - - 80 - - 82 - dBc
THD total harmonic distortion fi= 3 MHz - 83 - - 83 - - 82 - - 84 - dBc
fi=30MHz -82--82--82--83 -dBc
fi=70MHz -81--81--80--81 -dBc
fi= 170 MHz - 78 - - 78 - - 77 - - 79 - dBc
ENOB effective number of bits fi= 3 MHz - 11.3 - - 11.3 - - 11.3 - - 11.3 - Bits
fi= 30 MHz - 11.3 - - 11.3 - - 11.3 - - 11.2 - Bits
fi= 70 MHz - 11.2 - - 11.2 - - 11.2 - - 11.2 - Bits
fi= 170 MHz - 11.1 - - 11.1 - - 11.1 - - 11.1 - Bits
SNR signal-to-noise ratio fi= 3 MHz - 70.0 - - 69.9 - - 69.8 - - 69.6 - dBFS
fi= 30 MHz - 69.5 - - 69.5 - - 69.5 - - 69.4 - dBFS
fi= 70 MHz - 69.2 - - 69.2 - - 69.1 - - 69.0 - dBFS
fi= 170 MHz - 68.8 - - 68.8 - - 68.7 - - 68.6 - dBFS
SFDR spurious-free dynamic
range
fi= 3 MHz - 86 - - 86 - - 85 - - 87 - dBc
fi=30MHz -85--85--85--86 -dBc
fi=70MHz -84--84--83--84 -dBc
fi= 170 MHz - 81 - - 81 - - 80 - - 82 - dBc
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ADC1212D_SER 3 © IDT 2012. All rights reserved.
Product data sheet Rev. 03 — 2 July 2012 11 of 40
Integrated Device Technology
ADC1212D series
Dual 12-bit ADC: CMOS or LVDS DDR digital outputs
[1] Typical values measured at VDDA =3V, V
DDO =1.8V, T
amb =25C; minimum and maximum values are across the full temperature range Tamb =40 C to +85 C at VDDA =3V,
VDDO = 1.8 V; VINAP VINAM =1 dBFS; VINBP VINBM =1 dBFS; internal reference mode; applied to CMOS and LVDS interface; unless otherwise specified.
10.2 Clock and digital output timing
IMD intermodulation
distortion
fi= 3 MHz - 89 - - 89 - - 88 - - 89 - dBc
fi=30MHz -88--88--88--88 -dBc
fi=70MHz -87--87--86--86 -dBc
fi= 170 MHz - 84 - - 85 - - 83 - - 84 - dBc
ct(ch) channel crosstalk fi= 70 MHz - 100 - - 100 - - 100 - - 100 - dBc
Table 7. Characteristics[1] …continued
Symbol Parameter Conditions ADC1212D065 ADC1212D080 ADC1212D105 ADC1212D125 Unit
Min Typ Max Min Typ Max Min Typ Max Min Typ Max
Table 8. Clock and digital output timing characteristics[1]
Symbol Parameter Conditions ADC1212D065 ADC1212D080 ADC1212D105 ADC1212D125 Unit
Min Typ Max Min Typ Max Min Typ Max Min Typ Max
Clock timing input: pins CLKP and CLKM
fclk clock frequency 20 - 65 60 - 80 75 - 105 100 - 125 MHz
tlat(data) data latency time - 14 - - 14 - - 14 - - 14 - clock
cycles
clk clock duty cycle DCS_EN = 1 30 50 70 30 50 70 30 50 70 30 50 70 %
DCS_EN = 0 455055455055455055455055%
td(s) sampling delay
time
- 0.8 - - 0.8 - - 0.8 - - 0.8 - ns
twake wake-up time - 76 - - 76 - - 76 - - 76 - s
CMOS mode timing: pins DA11 to DA0, DB13 to DB0 and DAV
tPD propagation delay DATA - 3.9 - - 3.9 - - 3.9 - - 3.9 - ns
DAV - 4.2 - - 4.2 - - 4.2 - - 4.2 - ns
tsu set-up time - 8.6 - - 7.4 - - 6.1 - - 5.7 - ns
thhold time - 4.8 - - 3.4 - - 1.8 - - 1.4 - ns
trrise time DATA [2] 0.5 - 2.4 0.5 - 2.4 0.5 - 2.4 0.5 - 2.4 ns
DAV 0.5 - 2.4 0.5 - 2.4 0.5 - 2.4 0.5 - 2.4 ns
tffall time DATA [2] 0.5 - 2.4 0.5 - 2.4 0.5 - 2.4 0.5 - 2.4 s
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ADC1212D_SER 3 © IDT 2012. All rights reserved.
Product data sheet Rev. 03 — 2 July 2012 12 of 40
Integrated Device Technology
ADC1212D series
Dual 12-bit ADC: CMOS or LVDS DDR digital outputs
[1] Typical values measured at VDDA =3V, V
DDO =1.8V,
Tamb =25C; minimum and maximum values are across the full temperature range Tamb =40 Cto +85C at VDDA =3V,
VDDO = 1.8 V; VINAP VINAM =1 dBFS; VINBP VINBM =1 dBFS; unless otherwise specified.
[2] Measured between 20 % to 80 % of VDDO.
[3] Rise time measured from 50 mV to +50 mV; fall time measured from +50 mV to 50 mV.
LVDS DDR mode timing: pins DA10_DA11_P to DA0_DA1_P, DA10_DA11_M to DA0_DA1_M, DB10_DB11_P to DB0_DB1_P,
DB10_DB11_M to DB0_DB1_M; DAVP and DAVM
tPD propagation delay DATA - 3.9 - - 3.9 - - 3.9 - - 3.9 - ns
DAV - 4.2 - - 4.2 - - 4.2 - - 4.2 - ns
tsu set-up time - 5.1 - - 3.5 - - 2.1 - - 1.4 - ns
thhold time - 2.0 - - 2.0 - - 2.0 - - 2.0 - ns
trrise time DATA [3] 50 100 200 50 100 200 50 100 200 50 100 200 ps
DAV 50 100 200 50 100 200 50 100 200 50 100 200 ps
tffall time DATA [3] 50 100 200 50 100 200 50 100 200 50 100 200 ps
DAV 50 100 200 50 100 200 50 100 200 50 100 200 ps
Table 8. Clock and digital output timing characteristics[1] …continued
Symbol Parameter Conditions ADC1212D065 ADC1212D080 ADC1212D105 ADC1212D125 Unit
Min Typ Max Min Typ Max Min Typ Max Min Typ Max
ADC1212D_SER 3 © IDT 2012. All rights reserved.
Product data sheet Rev. 03 — 2 July 2012 13 of 40
Integrated Device Technology
ADC1212D series
Dual 12-bit ADC: CMOS or LVDS DDR digital outputs
tclk =1/f
clk
Fig 4. CMOS mode timing
tclk =1/f
clk
Fig 5. LVDS DDR mode timing
(N − 12)
td(s)
tclk
NN + 1
N + 2
tclk
tsu
tPD
thtPD
CLKP
CLKM
DATA
DAV
005aaa060
(N − 11)(N − 13)(N − 14)
005aaa114
(N − 14)
t
d(s)
t
clk
NN + 1
N + 2
CLKP
CLKM
DAVP
DAVM
t
PD
(N − 11)(N − 12)(N − 13)
DA
x
/
DB
x
DA
x
/
DB
x
DA
x
/
DB
x
DA
x
/
DB
x
DA
x+1/
DB
x+1
DA
x+1/
DB
x+1
DA
x+1/
DB
x+1
DA
x+1/
DB
x+1
DA
x+1/
DB
x+1
DA
x_
DA
x + 1_
P/
DB
x_
DB
x + 1_
P
DA
x_
DA
x + 1_
M/
DB
x_
DB
x + 1_
M
DA
x
/
DB
x
t
PD
t
clk
t
h
t
su
t
h
t
su
ADC1212D_SER 3 © IDT 2012. All rights reserved.
Product data sheet Rev. 03 — 2 July 2012 14 of 40
Integrated Device Technology
ADC1212D series
Dual 12-bit ADC: CMOS or LVDS DDR digital outputs
10.3 SPI timings
[1] Typical values measured at VDDA =3V, V
DDO =1.8V, T
amb =25C and CL= 5 pF; minimum and maximum
values are across the full temperature range Tamb =40 C to +85 C at VDDA =3V, V
DDO =1.8V.
Table 9. Characteristics [1]
Symbol Parameter Conditions Min Typ Max Unit
tw(SCLK) SCLK pulse width - 40 - ns
tw(SCLKH) SCLK HIGH pulse width - 16 - ns
tw(SCLKL) SCLK LOW pulse width - 16 - ns
tsu set-up time data to SCLK HIGH - 5 - ns
CS to SCLK HIGH - 5 - ns
thhold time data to SCLK HIGH - 2 - ns
CS to SCLK HIGH - 2 - ns
fclk(max) maximum clock frequency - 25 - MHz
Fig 6. SPI timing
t
su
SDIO
SCLK
R/W W1 W0 A12 A11 D2 D1 D0
t
su
t
h
t
h
t
w(SCLK)
005aaa065
CS
t
w(SCLKL)
t
w(SCLKH)
ADC1212D_SER 3 © IDT 2012. All rights reserved.
Product data sheet Rev. 03 — 2 July 2012 15 of 40
Integrated Device Technology
ADC1212D series
Dual 12-bit ADC: CMOS or LVDS DDR digital outputs
10.4 Typical characteristics
Fig 7. Capacitance as a function of frequency Fig 8. Resistance as a function of frequency
f (MHz)
50 550450250 350150
001aam619
2.8
2.6
3.0
3.2
C
(pF)
2.4
f (MHz)
50 550450250 350150
001aam614
8
4
12
16
R
(kΩ)
0
T=25C; VDD =3V; f
i= 170 MHz; fs= 125 Msps
(1) DCS on
(2) DCS off
T=25C; VDD =3V; f
i= 170 MHz; fs= 125 Msps
(1) DCS on
(2) DCS off
Fig 9. SFDR as a function of duty cycle () Fig 10. SNR as a function of duty cycle ()
δ (%)
10 907030 50
001aam616
40
60
20
80
100
SFDR
(dBc)
0
(1)
(2)
δ (%)
10 907030 50
001aam615
40
20
60
80
SNR
(dBFS)
0
(1)
(2)
ADC1212D_SER 3 © IDT 2012. All rights reserved.
Product data sheet Rev. 03 — 2 July 2012 16 of 40
Integrated Device Technology
ADC1212D series
Dual 12-bit ADC: CMOS or LVDS DDR digital outputs
(1) Tamb =40 C/typical supply voltages
(2) Tamb =+25C/typical supply voltages
(3) Tamb =+90C/typical supply voltages
(1) Tamb =40 C/typical supply voltages
(2) Tamb =+25C/typical supply voltages
(3) Tamb =+90C/typical supply voltages
Fig 11. SFDR as a function of duty cycle () Fig 12. SNR as a function of duty cycle ()
δ (%)
10 907030 50
001aam617
84
88
92
SFDR
(dBc)
80
(1)
(2)
(3)
δ (%)
10 907030 50
001aam618
40
60
80
SNR
(dBFS)
20
(1)
(2)
(3)
Fig 13. SFDR as a function of common-mode input
voltage (VI(cm))
Fig 14. SNR as a function of common-mode input
voltage (VI(cm))
VI(cm) (V) 3.52.50.5 3.02.01.00 1.5
001aam659
78
74
86
82
90
SFDR
(dBc)
70
VI(cm) (V) 3.52.50.5 3.02.01.00 1.5
001aam660
69
67
73
71
75
SNR
(dBFS)
65
ADC1212D_SER 3 © IDT 2012. All rights reserved.
Product data sheet Rev. 03 — 2 July 2012 17 of 40
Integrated Device Technology
ADC1212D series
Dual 12-bit ADC: CMOS or LVDS DDR digital outputs
11. Application information
11.1 Device control
The ADC1212D can be controlled via the Serial Peripheral Interface (SPI control mode) or
directly via the I/O pins (Pin control mode).
11.1.1 SPI and Pin control modes
The device enters Pin control mode at power-up and remains in this mode as long as pin
CS is held HIGH. In Pin control mode, the SPI pins SDIO, CS and SCLK are used as
static control pins.
SPI control mode is enabled by forcing pin CS LOW. Once SPI control mode has been
enabled, the device remains in this mode. The transition from Pin control mode to SPI
control mode is illustrated in Figure 15.
When the device enters SPI control mode, the output data standard and data format are
determined by the level on pin SDIO as soon as a transition is triggered by a falling edge
on CS.
11.1.2 Operating mode selection
The active ADC1212D operating mode (Power-up, Power-down or Sleep) can be selected
via the SPI interface (see Table 21) or by using pin CTRL in Pin control mode, as
described in Table 10.
11.1.3 Selecting the output data standard
The output data standard (CMOS or LVDS DDR) can be selected via the SPI interface
(see Table 24) or by using pin ODS in Pin control mode. LVDS DDR is selected when
ODS is HIGH, otherwise CMOS is selected.
Fig 15. Control mode selection.
R/W
SPI control mode
Pin control mode
Data format
offset binary
Data format
two's complement
LVDS DDR
SDIO/ODS
SCLK/DFS
W1 W0 A12
005aaa039
CMOS
CS
Table 10. Operating mode selection via pin CTRL
Pin CTRL Operating mode Output high-Z
0 Power-down yes
0.3VDDA Sleep yes
0.6VDDA Power-up yes
VDDA Power-up no
ADC1212D_SER 3 © IDT 2012. All rights reserved.
Product data sheet Rev. 03 — 2 July 2012 18 of 40
Integrated Device Technology
ADC1212D series
Dual 12-bit ADC: CMOS or LVDS DDR digital outputs
11.1.4 Selecting the output data format
The output data format can be selected via the SPI interface (offset binary,
two’s complement or gray code; see Table 24) or by using pin DFS in Pin control mode
(offset binary or two’s complement). Offset binary is selected when DFS is LOW. When
DFS is HIGH, two’s complement is selected.
11.2 Analog inputs
11.2.1 Input stage
The analog input of the ADC1212D supports a differential or a single-ended input drive.
Optimal performance is achieved using differential inputs with the common-mode input
voltage (VI(cm)) on pins INAP, INAM, INBP and INBM set to 0.5VDDA.
The full-scale analog input voltage range is configurable between 1 V (p-p) and 2 V (p-p)
via a programmable internal reference (see Section 11.3 and Table 23).
The equivalent circuit of the sample-and-hold input stage, including ElectroStatic
Discharge (ESD) protection and circuit and package parasitics, is shown in Figure 16.
The sample phase occurs when the internal clock (derived from the clock signal on pin
CLKP/CLKM) is HIGH. The voltage is then held on the sampling capacitors. When the
clock signal goes LOW, the stage enters the hold phase and the voltage information is
transmitted to the ADC core.
11.2.2 Anti-kickback circuitry
Anti-kickback circuitry (RC filter in Figure 17 is needed to counteract the effects of charge
injection generated by the sampling capacitance.
The RC filter is also used to filter noise from the signal before it reaches the sampling
stage. The value of the capacitor should be chosen to maximize noise attenuation without
degrading the settling time excessively.
Fig 16. Input sampling circuit
ADC1212D_SER 3 © IDT 2012. All rights reserved.
Product data sheet Rev. 03 — 2 July 2012 19 of 40
Integrated Device Technology
ADC1212D series
Dual 12-bit ADC: CMOS or LVDS DDR digital outputs
The component values are determined by the input frequency and should be selected so
as not to affect the input bandwidth.
11.2.3 Transformer
The configuration of the transformer circuit is determined by the input frequency. The
configuration shown in Figure 18 would be suitable for a baseband application.
The configuration shown in Figure 19 is recommended for high frequency applications. In
both cases, the choice of transformer is a compromise between cost and performance.
Fig 17. Anti-kickback circuit
Table 11. RC coupling versus input frequency, typical values
Input frequency (MHz) R ()C (pF)
32512
70 12 8
170 12 8
001aan679
R
R
C
INAP/
INBP
INAM/
INBM
Fig 18. Single transformer configuration suitable for baseband applications
005aaa094
100 nF100 nF
100 nF 100 nF
25 Ω
25 Ω
25 Ω
25 Ω
12 pF
INAP/INBP
INAM/INBM
VCMA/VCMB
100 nF
Analog
input
ADT1-1WT
100 nF
ADC1212D_SER 3 © IDT 2012. All rights reserved.
Product data sheet Rev. 03 — 2 July 2012 20 of 40
Integrated Device Technology
ADC1212D series
Dual 12-bit ADC: CMOS or LVDS DDR digital outputs
11.3 System reference and power management
11.3.1 Internal/external references
The ADC1212D has a stable and accurate built-in internal reference voltage to adjust the
ADC full-scale. This reference voltage can be set internally via SPI or with pin VREF and
SENSE (programmable in 1 dB steps between 0 dB and 6 dB via control bits
INTREF[2:0] when bit INTREF_EN = logic 1; see Table 23). See Figure 21 to Figure 24.
The equivalent reference circuit is shown in Figure 20. An external reference is also
possible by providing a voltage on pin VREF as described in Figure 23.
Fig 19. Dual transformer configuration suitable for high intermediate frequency
application
005aaa095
100 nF100 nF
100 nF
100 nF
12 Ω
12 Ω
8.2 pF
INAP/INBP
INAM/INBM
VCMA/VCMB
50 Ω
50 Ω
50 Ω
50 Ω
ADT1-1WTADT1-1WT
Analog
input
ADC1212D_SER 3 © IDT 2012. All rights reserved.
Product data sheet Rev. 03 — 2 July 2012 21 of 40
Integrated Device Technology
ADC1212D series
Dual 12-bit ADC: CMOS or LVDS DDR digital outputs
If bit INTREF_EN is set to logic 0, the reference voltage is determined either internally or
externally as detailed in Table 12.
[1] The voltage on pin VREF is doubled internally to generate the internal reference voltage.
Figure 21 to Figure 24 illustrate how to connect the SENSE and VREF pins to select the
required reference voltage source.
Fig 20. Reference equivalent schematic
Table 12. Reference selection
Selection SPI bit
INTREF_EN
SENSE pin VREF pin Full-scale
(V (p-p))
Internal
(Figure 21)
0 AGND 330 pF capacitor to
AGND
2 V
Internal
(Figure 22)
0 pin VREF connected to pin SENSE and
via a 330 pF capacitor to AGND
1 V
External
(Figure 23)
0V
DDA external voltage between
0.5V and 1V
[1]
1 V to 2 V
Internal via SPI
(Figure 24)
1 pin VREF connected to pin SENSE and
via 330 pF capacitor to AGND
1 V to 2 V
EXT_ref
EXT_ref
001aan670
REFAT/
REFBT
REFAB/
REFBB
SENSE
VREF
SELECTION
LOGIC
BANDGAP
REFERENCE
ADC CORE
BUFFER
REFERENCE
AMP
ADC1212D_SER 3 © IDT 2012. All rights reserved.
Product data sheet Rev. 03 — 2 July 2012 22 of 40
Integrated Device Technology
ADC1212D series
Dual 12-bit ADC: CMOS or LVDS DDR digital outputs
11.3.2 Programmable full-scale
The full-scale is programmable between 1 V (p-p) to 2 V (p-p) (see Table 13).
11.3.3 Common-mode output voltage (VO(cm))
A 0.1 F filter capacitor should be connected between pin VCMA/VCMB and ground to
ensure a low-noise common-mode output voltage. When AC-coupled, pin VCMA/VCMB
can then be used to set the common-mode reference for the analog inputs, for instance
via a transformer middle point.
Fig 21. Internal reference, 2 V (p-p) full-scale Fig 22. Internal reference, 1 V (p-p) full-scale
Fig 23. External reference, 1 V (p-p) to 2 V (p-p)
full-scale
Fig 24. Internal reference via SPI, 1 V (p-p) to 2 V (p-p)
full-scale
330 pF
VREF
SENSE
005aaa116
REFERENCE
EQUIVALENT
SCHEMATIC
330
pF
005aaa117
VREF
SENSE
REFERENCE
EQUIVALENT
SCHEMATIC
0.1 μF
VDDA
V
005aaa119
VREF
SENSE
REFERENCE
EQUIVALENT
SCHEMATIC
REFERENCE
EQUIVALENT
SCHEMATIC
330 pF
005aaa118
VREF
SENSE
Table 13. Programmable full-scale
INTREF Level (dB) Full-scale (V (p-p))
000 0 2
001 11.78
010 21.59
011 31.42
100 41.26
101 51.12
110 61
111 reserved x
ADC1212D_SER 3 © IDT 2012. All rights reserved.
Product data sheet Rev. 03 — 2 July 2012 23 of 40
Integrated Device Technology
ADC1212D series
Dual 12-bit ADC: CMOS or LVDS DDR digital outputs
11.3.4 Biasing
The common-mode input voltage (VI(cm)) on pins INAP/INBP and INAM/INBM should be
set externally to 0.5VDDA for optimal performance and should always be between 0.9 V
and 2 V (see Table 6).
11.4 Clock input
11.4.1 Drive modes
The ADC1212D can be driven differentially (LVPECL). It can also be driven by a
single-ended LVCMOS signal connected to pin CLKP (pin CLKM should be connected to
ground via a capacitor) or pin CLKM (pin CLKP should be connected to ground via a
capacitor).
Fig 25. Equivalent schematic of the common-mode reference circuit
1.5 V
VCMA/VCMB
0.1 μF
Package ESD Parasitics
005aaa099
COMMON MODE
REFERENCE
ADC CORE
a. Rising edge LVCMOS b. Falling edge LVCMOS
Fig 26. LVCMOS single-ended clock input
LVCMOS
clock input CLKP
CLKM
005aaa174
005aaa053
LVCMOS
clock input
CLKP
CLKM
ADC1212D_SER 3 © IDT 2012. All rights reserved.
Product data sheet Rev. 03 — 2 July 2012 24 of 40
Integrated Device Technology
ADC1212D series
Dual 12-bit ADC: CMOS or LVDS DDR digital outputs
11.4.2 Equivalent input circuit
The equivalent circuit of the input clock buffer is shown in Figure 28. The common-mode
voltage of the differential input stage is set via internal 5 k resistors.
a. Sine clock input b. Sine clock input (with transformer)
c. LVPECL clock input
Fig 27. Differential clock input
Sine
clock input
CLKP
CLKM
005aaa173
Sine
clock input CLKP
CLKM
005aaa054
LVPECL
clock input
005aaa172
CLKP
CLKM
Vcm(clk) = common-mode voltage of the differential input stage
Fig 28. Equivalent input circuit
CLKP
CLKM
005aaa056
Package ESD Parasitics
5 kΩ5 kΩ
V
cm(clk)
SE_SEL SE_SEL
ADC1212D_SER 3 © IDT 2012. All rights reserved.
Product data sheet Rev. 03 — 2 July 2012 25 of 40
Integrated Device Technology
ADC1212D series
Dual 12-bit ADC: CMOS or LVDS DDR digital outputs
Single-ended or differential clock inputs can be selected via the SPI interface
(see Table 22). If single-ended is enabled, the input pin (CLKM or CLKP) is selected via
control bit SE_SEL.
If single-ended is implemented without setting bit SE_SEL to the appropriate value, the
unused pin should be connected to ground via a capacitor.
11.4.3 Duty cycle stabilizer
The duty cycle stabilizer can improve the overall performances of the ADC by
compensating the duty cycle of the input clock signal. When the duty cycle stabilizer is
active (bit DCS_EN = logic 1; see Table 22), the circuit can handle signals with duty cycles
of between 30 % and 70 % (typical). When the duty cycle stabilizer is disabled
(DCS_EN = logic 0), the input clock signal should have a duty cycle of between 45 % and
55 %.
11.4.4 Clock input divider
The ADC1212D contains an input clock divider that divides the incoming clock by a factor
of 2 (when bit CLKDIV = logic 1; see Table 22). This feature allows the user to deliver a
higher clock frequency with better jitter performance, leading to a better SNR result once
acquisition has been performed.
11.5 Digital outputs
11.5.1 Digital output buffers: CMOS mode
The digital output buffers can be configured as CMOS by setting bit LVDS_CMOS to
logic 0 (see Table 24).
Each digital output has a dedicated output buffer. The equivalent circuit of the CMOS
digital output buffer is shown in Figure 29. The buffer is powered by a separate
AGND/VDDO to ensure 1.8 V to 3.3 V compatibility and is isolated from the ADC core.
Each buffer can be loaded by a maximum of 10 pF.
Fig 29. CMOS digital output buffer
VDDO
ESD PackageParasitics
AGND
Dx
005aaa057
50 Ω
LOGIC
DRIVER
ADC1212D_SER 3 © IDT 2012. All rights reserved.
Product data sheet Rev. 03 — 2 July 2012 26 of 40
Integrated Device Technology
ADC1212D series
Dual 12-bit ADC: CMOS or LVDS DDR digital outputs
The output resistance is 50 and is the combination of an internal resistor and the
equivalent output resistance of the buffer. There is no need for an external damping
resistor. The drive strength of both DATA and DAV buffers can be programmed via the SPI
in order to adjust the rise and fall times of the output digital signals (see Table 31).
11.5.2 Digital output buffers: LVDS DDR mode
The digital output buffers can be configured as LVDS DDR by setting bit LVDS_CMOS to
logic 1 (see Table 24).
Each output should be terminated externally with a 100 resistor (typical) at the receiver
side (Figure 30) or internally via SPI control bits LVDS_INT_TER[2:0] (see Figure 31 and
Table 33).
The default LVDS DDR output buffer current is set to 3.5 mA. It can be programmed via
the SPI (bits DAVI[1:0] and DATAI[1:0]; see Table 32) in order to adjust the output logic
voltage levels.
Fig 30. LVDS DDR digital output buffer - externally terminated
Fig 31. LVDS DDR digital output buffer - internally terminated
DAn_DAn + 1_M; DBn_DBn + 1_M
VDDO
3.5 mA
typical
AGND
100 Ω
-
005aaa112
+ -
+
RECEIVER
DAn_DAn + 1_P; DBn_DBn + 1_P
DAn_DAn + 1_P; DBn_DBn + 1_P
DAn_DAn + 1_M; DBn_DBn + 1_M
VDDO
3.5 mA
typical
AGND
100 Ω
-
005aaa113
+ -
+
RECEIVER
100 Ω
ADC1212D_SER 3 © IDT 2012. All rights reserved.
Product data sheet Rev. 03 — 2 July 2012 27 of 40
Integrated Device Technology
ADC1212D series
Dual 12-bit ADC: CMOS or LVDS DDR digital outputs
11.5.3 DAta Valid (DAV) output clock
A data valid output clock signal (DAV) is provided that can be used to capture the data
delivered by the ADC1212D. Detailed timing diagrams for CMOS and LVDS DDR modes
are provided in Figure 4 and Figure 5 respectively. In LVDS DDR mode, it is highly
recommended to shift ahead the DAV by 1 ns (bits DAVPHASE[2:0] = 0b100;
see Table 25).
11.5.4 OuT-of-Range (OTR)
An out-of-range signal is provided on pin OTRA for ADC channel A and on pin OTRB for
ADC channel B. The latency of OTRA/OTRB is fourteen clock cycles. The OTR response
can be speeded up by enabling Fast OTR (bit FASTOTR = logic 1; see Table 30). In this
mode, the latency of OTRA/OTRB is reduced to only four clock cycles. The Fast OTR
detection threshold (below full-scale) can be programmed via bits FASTOTR_DET[2:0].
11.5.5 Digital offset
By default, the ADC1212D delivers output code that corresponds to the analog input.
However, it is possible to add a digital offset to the output code via the SPI
(bits DIG_OFFSET[5:0]; see Table 26).
Table 14. LVDS DDR output register 2
LVDS_INT_TER[2:0] Resistor value ()
000 no internal termination
001 300
010 180
011 110
100 150
101 100
110 81
111 6
Table 15. Fast OTR register
FASTOTR_DET[2:0] Detection level (dB)
000 20.56
001 16.12
010 11.02
011 7.82
100 5.49
101 3.66
110 2.14
111 0.86
ADC1212D_SER 3 © IDT 2012. All rights reserved.
Product data sheet Rev. 03 — 2 July 2012 28 of 40
Integrated Device Technology
ADC1212D series
Dual 12-bit ADC: CMOS or LVDS DDR digital outputs
11.5.6 Test patterns
For test purposes, the ADC1212D can be configured to transmit one of a number of
predefined test patterns (via bits TESTPAT_SEL[2:0]; see Table 27). A custom test pattern
can be defined by the user (TESTPAT_USER[11:4]; see Table 28 and
TESTPAT_USER[3:0]; see Table 29) and is selected when TESTPAT_SEL[2:0] = 101.
The selected test pattern is transmitted regardless of the analog input.
11.5.7 Output codes versus input voltage
11.6 Serial Peripheral Interface (SPI)
11.6.1 Register description
The ADC1212D serial interface is a synchronous serial communications port that allows
easy interfacing with many commonly used microprocessors. It provides access to the
registers that control the operation of the chip.
This interface is configured as a 3-wire type (SDIO as bidirectional pin).
Pin SCLK is the serial clock input and CS is the chip select pin.
Each read/write operation is initiated by a LOW level on CS. A minimum of three bytes is
transmitted (two instruction bytes and at least one data byte). The number of data bytes is
determined by the value of bits W1 and W2 (see Table 18).
Table 16. Output codes
VINAP VINAM/
VINBP VINBM
Offset binary Two’s complement OTRA/OTRB
pin
< 1 0000 0000 0000 1000 0000 0000 1
1.0000000 0000 0000 0000 1000 0000 0000 0
0.9995117 0000 0000 0001 1000 0000 0001 0
0.9990234 0000 0000 0010 1000 0000 0010 0
0.9985352 0000 0000 0011 1000 0000 0011 0
0.9980469 0000 0000 0100 1000 0000 0100 0
.... .... .... 0
0.0009766 0111 1111 1110 1111 1111 1110 0
0.0004883 0111 1111 1111 1111 1111 1111 0
+0.0000000 1000 0000 0000 0000 0000 0000 0
+0.0004883 1000 0000 0001 0000 0000 0001 0
+0.0009766 1000 0000 0010 0000 0000 0010 0
.... .... .... 0
+0.9980469 1111 1111 1011 0111 1111 1011 0
+0.9985352 1111 1111 1100 0111 1111 1100 0
+0.9990234 1111 1111 1101 0111 1111 1101 0
+0.9995117 1111 1111 1110 0111 1111 1110 0
+1 1111 1111 1111 0111 1111 1111 0
> +1 1111 1111 1111 0111 1111 1111 1
ADC1212D_SER 3 © IDT 2012. All rights reserved.
Product data sheet Rev. 03 — 2 July 2012 29 of 40
Integrated Device Technology
ADC1212D series
Dual 12-bit ADC: CMOS or LVDS DDR digital outputs
[1] Bit R/W indicates whether it is a read (logic 1) or a write (logic 0) operation.
[2] Bits W1 and W0 indicate the number of bytes to be transferred (see Table 18).
Bits A12 to A0 indicate the address of the register being accessed. In the case of a
multiple byte transfer, this address is the first register to be accessed. An address counter
is increased to access subsequent addresses.
The steps for a data transfer:
1. A falling edge on pin CS in combination with a rising edge on pin SCLK determine the
start of communications.
2. The first phase is the transfer of the 2-byte instruction.
3. The second phase is the transfer of the data which can vary in length but is always a
multiple of 8 bits. The MSB is always sent first (for instruction and data bytes).
4. A rising edge on pin CS indicates the end of data transmission.
11.6.2 Default modes at start-up
During circuit initialization it does not matter which output data standard has been
selected. At power-up, the device enters Pin control mode.
A falling edge on pin CS triggers a transition to SPI control mode. When the ADC1212D
enters SPI control mode, the output data standard (CMOS/LVDS DDR) is determined by
the level on pin SDIO (see Figure 33). Once in SPI control mode, the output data standard
can be changed via bit LVDS_CMOS (see Ta b le 2 4).
Table 17. Instruction bytes for the SPI
MSB LSB
Bit 76543210
Description R/W[1] W1[2] W0[2] A12 A11 A10 A9 A8
A7 A6 A5 A4 A3 A2 A1 A0
Table 18. Number of data bytes to be transferred after the instruction bytes
W1 W0 Number of bytes transmitted
001 byte
012 bytes
103 bytes
1 1 4 bytes or more
Fig 32. SPI mode timing
CS
SCLK
SDIO R/W W1 W0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D3 D2 D1 D0D0 D7 D6 D5 D4
Instruction bytes Register N (data) Register N + 1 (data) 005aaa086
ADC1212D_SER 3 © IDT 2012. All rights reserved.
Product data sheet Rev. 03 — 2 July 2012 30 of 40
Integrated Device Technology
ADC1212D series
Dual 12-bit ADC: CMOS or LVDS DDR digital outputs
When the ADC1212D enters SPI control mode, the output data format (two’s complement
or offset binary) is determined by the level on pin SCLK (gray code can only be selected
via the SPI). Once in SPI control mode, the output data format can be changed via bit
DATA_FORMAT[1:0] (see Table 24).
Fig 33. Default mode at start-up: SCLK LOW = offset binary; SDIO HIGH = LVDS DDR
Fig 34. Default mode at start-up: SCLK HIGH = two’s complement; SDIO LOW = CMOS
CS
SDIO
(CMOS LVDS DDR)
SCLK
(Data format)
Offset binary, LVDS DDR
default mode at start-up 005aaa063
SDIO
(CMOS LVDS DDR)
SCLK
(Data format)
two's complement, CMOS
default mode at start-up
005aaa064
CS
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ADC1212D_SER 3 © IDT 2012. All rights reserved.
Product data sheet Rev. 03 — 2 July 2012 31 of 40
Integrated Device Technology
ADC1212D series
Dual 12-bit ADC: CMOS or LVDS DDR digital outputs
11.6.3 Register allocation map
Table 19. Register allocation map
Addr
(hex)
Register name Access Bit definition Default
(bin)
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
0003 Channel index R/W RESERVED[5:0] ADCB ADCA 1111 1111
0005 Reset and
operating mode
R/W SW_
RST
RESERVED[2:0] - - OP_MODE[1:0] 0000 0000
0006 Clock R/W - - - SE_SEL DIFF_SE - CLKDIV DCS_EN 0000 0001
0008 Internal reference R/W - - - - INTREF_EN INTREF[2:0] 0000 0000
0011 Output data
standard.
R/W - - - LVDS_
CMOS
OUTBUF OUTBUS_SWAP DATA_FORMAT[1:0] 0000 0000
0012 Output clock R/W - - - - DAVINV DAVPHASE[2:0] 0000 1110
0013 Offset R/W - - DIG_OFFSET[5:0] 0000 0000
0014 Test pattern 1 R/W - - - - - TESTPAT_SEL[2:0] 0000 0000
0015 Test pattern 2 R/W TESTPAT_USER[11:4] 0000 0000
0016 Test pattern 3 R/W TESTPAT_USER[3:0] - - - - 0000 0000
0017 Fast OTR R/W - - - - FASTOTR FASTOTR_DET[2:0] 0000 0000
0020 CMOS output R/W - - - - DAV_DRV[1:0] DATA_DRV[1:0] 0000 1110
0021 LVDS DDR O/P 1 R/W - - RESERVED DAVI[1:0] RESERVED DATAI[1:0] 0000 0000
0022 LVDS DDR O/P 2 R/W - - - - BIT_BYTE_WISE LVDS_INT_TER[2:0] 0000 0000
ADC1212D_SER 3 © IDT 2012. All rights reserved.
Product data sheet Rev. 03 — 2 July 2012 32 of 40
Integrated Device Technology
ADC1212D series
Dual 12-bit ADC: CMOS or LVDS DDR digital outputs
Table 20. Channel index control register (address 0003h) bit description
Default values are highlighted.
Bit Symbol Access Value Description
7 to 2 RESERVED[5:0] - 111111 reserved
1 ADCB R/W next SPI command for ADC B
0 ADC B not selected
1ADC B selected
0 ADCA R/W next SPI command for ADC A
0 ADC A not selected
1ADC A selected
Table 21. Reset and operating mode control register (address 0005h) bit description
Default values are highlighted.
Bit Symbol Access Value Description
7 SW_RST R/W reset digital section
0 no reset
1 performs a reset on SPI registers
6 to 4 RESERVED[2:0] - 000 reserved
3 to 2 - - 00 not used
1 to 0 OP_MODE[1:0] R/W operating mode
00 normal (Power-up)
01 Power-down
10 Sleep
11 normal (Power-up)
Table 22. Clock control register (address 0006h) bit description
Default values are highlighted.
Bit Symbol Access Value Description
7 to 5 - - 000 not used
4 SE_SEL R/W single-ended clock input pin select
0CLKM
1CLKP
3 DIFF_SE R/W differential/single-ended clock input select
0 fully differential
1 single-ended
2 RESERVED - 0 reserved
1 CLKDIV R/W clock input divide by 2
0 disabled
1 enabled
0 DCS_EN R/W duty cycle stabilizer
0 disabled
1 enabled
ADC1212D_SER 3 © IDT 2012. All rights reserved.
Product data sheet Rev. 03 — 2 July 2012 33 of 40
Integrated Device Technology
ADC1212D series
Dual 12-bit ADC: CMOS or LVDS DDR digital outputs
Table 23. Internal reference control register (address 0008h) bit description
Default values are highlighted.
Bit Symbol Access Value Description
7 to 4 - - 0000 not used
3 INTREF_EN R/W programmable internal reference enable
0 disable
1 active
2 to 0 INTREF[2:0] R/W programmable internal reference
000 0dB (FS=2V)
001 1 dB (FS = 1.78 V)
010 2 dB (FS = 1.59 V)
011 3 dB (FS = 1.42 V)
100 4 dB (FS = 1.26 V)
101 5 dB (FS = 1.12 V)
110 6dB (FS=1V)
111 reserved
Table 24. Output data standard control register (address 0011h) bit description
Default values are highlighted.
Bit Symbol Access Value Description
7 to 5 - - 000 not used
4 LVDS_CMOS R/W output data standard: LVDS DDR or CMOS
0CMOS
1 LVDS DDR
3 OUTBUF R/W output buffers enable
0 output enabled
1 output disabled (high Z)
2 OUTBUS_SWAP R/W output bus swap
0 no swapping
1 output bus is swapped (MSB becomes LSB and
vice versa)
1 to 0 DATA_FORMAT[1:0] R/W output data format
00 offset binary
01 two’s complement
10 gray code
11 offset binary
ADC1212D_SER 3 © IDT 2012. All rights reserved.
Product data sheet Rev. 03 — 2 July 2012 34 of 40
Integrated Device Technology
ADC1212D series
Dual 12-bit ADC: CMOS or LVDS DDR digital outputs
[1] tclk =1/f
clk
Table 25. Output clock register (address 0012h) bit description
Default values are highlighted.
Bit Symbol Access Value Description
7 to 4 - - 0000 not used
3 DAVINV R/W output clock data valid (DAV) polarity
0 normal
1 inverted
2 to 0 DAVPHASE[2:0] R/W DAV phase select
000 output clock shifted (ahead) by 6/16 tclk[1]
001 output clock shifted (ahead) by 5/16 tclk[1]
010 output clock shifted (ahead) by 4/16 tclk[1]
011 output clock shifted (ahead) by 3/16 tclk[1]
100 output clock shifted (ahead) by 2/16 tclk[1]
101 output clock shifted (ahead) by 1/16 tclk[1]
110 default value as defined in timing section
111 output clock shifted (delayed) by 1/16 tclk[1]
Table 26. Offset register (address 0013h) bit description
Default values are highlighted.
Bit Symbol Access Value Description
7 to 6 - - 00 not used
5 to 0 DIG_OFFSET[5:0] R/W digital offset adjustment
011111 +31 LSB
... ...
000000 0
... ...
100000 32 LSB
Table 27. Test pattern register 1 (address 0014h) bit description
Default values are highlighted.
Bit Symbol Access Value Description
7 to 3 - - 00000 not used
2 to 0 TESTPAT_SEL[2:0] R/W digital test pattern select
000 off
001 mid scale
010 FS
011 +FS
100 toggle ‘1111..1111’/’0000..0000’
101 custom test pattern
110 ‘0101..0101’
111 ‘1010..1010.’
ADC1212D_SER 3 © IDT 2012. All rights reserved.
Product data sheet Rev. 03 — 2 July 2012 35 of 40
Integrated Device Technology
ADC1212D series
Dual 12-bit ADC: CMOS or LVDS DDR digital outputs
Table 28. Test pattern register 2 (address 0015h) bit description
Default values are highlighted.
Bit Symbol Access Value Description
7 to 0 TESTPAT_USER[11:4] R/W 0000
0000
custom digital test pattern (bits 11 to 4)
Table 29. Test pattern register 3 (address 0016h) bit description
Default values are highlighted.
Bit Symbol Access Value Description
7 to 4 TESTPAT_USER[3:0] R/W 0000 custom digital test pattern (bits 3 to 0)
3 to 0 - - 0000 not used
Table 30. Fast OTR register (address 0017h) bit description
Default values are highlighted.
Bit Symbol Access Value Description
7 to 4 - - 0000 not used
3 FASTOTR R/W fast OuT-of-Range (OTR) detection
0 disabled
1 enabled
2 to 0 FASTOTR_DET[2:0] R/W set fast OTR detect level
000 20.56 dB
001 16.12 dB
010 11.02 dB
011 7.82 dB
100 5.49 dB
101 3.66 dB
110 2.14 dB
111 0.86 dB
Table 31. CMOS output register (address 0020h) bit description
Default values are highlighted.
Bit Symbol Access Value Description
7 to 4 - - 0000 not used
3 to 2 DAV_DRV[1:0] R/W drive strength for DAV CMOS output buffer
00 low
01 medium
10 high
11 very high
1 to 0 DATA_DRV[1:0] R/W drive strength for DATA CMOS output buffer
00 low
01 medium
10 high
11 very high
ADC1212D_SER 3 © IDT 2012. All rights reserved.
Product data sheet Rev. 03 — 2 July 2012 36 of 40
Integrated Device Technology
ADC1212D series
Dual 12-bit ADC: CMOS or LVDS DDR digital outputs
Table 32. LVDS DDR output register 1 (address 0021h) bit description
Default values are highlighted.
Bit Symbol Access Value Description
7 to 6 - - 00 not used
5 RESERVED - 0 reserved
4 to 3 DAVI[1:0] R/W LVDS current for DAV LVDS buffer
00 3.5 mA
01 4.5 mA
10 1.25 mA
11 2.5 mA
2 RESERVED - 0 reserved
1 to 0 DATAI[1:0] R/W LVDS current for DATA LVDS buffer
00 3.5 mA
01 4.5 mA
10 1.25 mA
11 2.5 mA
Table 33. LVDS DDR output register 2 (address 0022h) bit description
Default values are highlighted.
Bit Symbol Access Value Description
7 to 4 - - 0000 not used
3 BIT_BYTE_WISE R/W DDR mode for LVDS output
0 bit wise (even data bits output on DAV rising
edge/odd data bits output on DAV falling
edge)
1 byte wise (MSB data bits output on DAV rising
edge/LSB data bits output on DAV falling edge)
2 to 0 LVDS_INT_TER[2:0] R/W internal termination for LVDS buffer (DAV and
DATA)
000 no internal termination
001 300
010 180
011 110
100 150
101 100
110 81
111 60
ADC1212D_SER 3 © IDT 2012. All rights reserved.
Product data sheet Rev. 03 — 2 July 2012 37 of 40
Integrated Device Technology
ADC1212D series
Dual 12-bit ADC: CMOS or LVDS DDR digital outputs
12. Package outline
Fig 35. Package outline SOT804-3 (HVQFN64)
References
Outline
version European
projection Issue date
IEC JEDEC JEITA
SOT804-3 - - -
- - -
- - -
sot804-3_po
Unit
mm max
nom
min
1.00
0.85
0.80
0.05
0.02
0.00
0.30
0.21
0.18 0.2 9.1
9.0
8.9
9.1
9.0
8.9 0.5 0.1 0.05
A
Dimensions
Note
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.
HVQFN64: plastic thermal enhanced very thin quad flat package; no leads;
64 terminals; body 9 x 9 x 0.85 mm SOT804-3
A1bcD
(1)
0.1
y1
Dh
7.25
7.10
6.95
E(1) Eh
7.25
7.10
6.95
ee
1
7.5
e2
7.5
L
0.5
0.4
0.3
vw
0.05
y
0 2.5 5 mm
scale
terminal 1
index area
terminal 1
index area
B
DA
E
b
e1
eAC B
vCw
17 32
e2
e
33
48
Dh
4964
Eh
L
1
16
C
y
C
y1
X
detail X
A1
Ac
1/2 e
1/2 e
09-02-24
10-08-06
ADC1212D_SER 3 © IDT 2012. All rights reserved.
Product data sheet Rev. 03 — 2 July 2012 38 of 40
Integrated Device Technology
ADC1212D series
Dual 12-bit ADC: CMOS or LVDS DDR digital outputs
13. Abbreviations
Table 34. Abbreviations
Acronym Description
ADC Analog-to-Digital Converter
CMOS Complementary Metal Oxide Semiconductor
DAV DAta Valid
DCS Duty Cycle Stabilizer
DFS Data Format Select
ESD ElectroStatic Discharge
FS Full-Scale
IMD InterModulation Distortion
LSB Least Significant Bit
LVCMOS Low Voltage Complementary Metal Oxide Semiconductor
LVDS DDR Low Voltage Differential Signalling Double Data Rate
LVPECL Low-Voltage Positive Emitter-Coupled Logic
MSB Most Significant Bit
OTR OuT-of-Range
SFDR Spurious-Free Dynamic Range
SNR Signal-to-Noise Ratio
SPI Serial Peripheral Interface
TX Transmitter
ADC1212D_SER 3 © IDT 2012. All rights reserved.
Product data sheet Rev. 03 — 2 July 2012 39 of 40
Integrated Device Technology
ADC1212D series
Dual 12-bit ADC: CMOS or LVDS DDR digital outputs
14. Revision history
15. Contact information
For more information or sales office addresses, please visit: http://www.idt.com
Table 35. Revision history
Document ID Release date Data sheet status Change
notice
Supersedes
ADC1212D_SER v.3 20120702 Product data sheet - ADC1212D_SER v.2
ADC1212D_SER v.2 20110304 Product data sheet - ADC1212D_SER v.1
Modifications: •Data sheet status changed from Preliminary to Product.
•Text and drawings updated throughout entire data sheet.
•Section 10.4 “Typical characteristics” has been added to the data sheet.
•Section 13 “Abbreviations” has been added to the data sheet.
ADC1212D_SER v.1 20100806 Preliminary data sheet - -
ADC1212D_SER 3 © IDT 2012. All rights reserved.
Product data sheet Rev. 03 — 2 July 2012 40 of 40
Integrated Device Technology
ADC1212D series
Dual 12-bit ADC: CMOS or LVDS DDR digital outputs
16. Contents
1 General description . . . . . . . . . . . . . . . . . . . . . . 1
2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1
3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
4 Ordering information. . . . . . . . . . . . . . . . . . . . . 2
5 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 2
6 Pinning information. . . . . . . . . . . . . . . . . . . . . . 3
6.1 CMOS outputs selected . . . . . . . . . . . . . . . . . . 3
6.1.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
6.1.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3
6.2 LVDS DDR outputs selected. . . . . . . . . . . . . . . 5
6.2.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
6.2.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 6
7 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 7
8 Thermal characteristics . . . . . . . . . . . . . . . . . . 7
9 Static characteristics. . . . . . . . . . . . . . . . . . . . . 7
10 Dynamic characteristics . . . . . . . . . . . . . . . . . 10
10.1 Dynamic characteristics . . . . . . . . . . . . . . . . . 10
10.2 Clock and digital output timing . . . . . . . . . . . . 11
10.3 SPI timings . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
10.4 Typical characteristics . . . . . . . . . . . . . . . . . . 15
11 Application information. . . . . . . . . . . . . . . . . . 17
11.1 Device control. . . . . . . . . . . . . . . . . . . . . . . . . 17
11.1.1 SPI and Pin control modes . . . . . . . . . . . . . . . 17
11.1.2 Operating mode selection. . . . . . . . . . . . . . . . 17
11.1.3 Selecting the output data standard . . . . . . . . . 17
11.1.4 Selecting the output data format. . . . . . . . . . . 18
11.2 Analog inputs . . . . . . . . . . . . . . . . . . . . . . . . . 18
11.2.1 Input stage . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
11.2.2 Anti-kickback circuitry . . . . . . . . . . . . . . . . . . 18
11.2.3 Transformer . . . . . . . . . . . . . . . . . . . . . . . . . . 19
11.3 System reference and power management . . 20
11.3.1 Internal/external references . . . . . . . . . . . . . . 20
11.3.2 Programmable full-scale . . . . . . . . . . . . . . . . 22
11.3.3 Common-mode output voltage (VO(cm)) . . . . . 22
11.3.4 Biasing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
11.4 Clock input . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
11.4.1 Drive modes . . . . . . . . . . . . . . . . . . . . . . . . . 23
11.4.2 Equivalent input circuit . . . . . . . . . . . . . . . . . . 24
11.4.3 Duty cycle stabilizer . . . . . . . . . . . . . . . . . . . . 25
11.4.4 Clock input divider . . . . . . . . . . . . . . . . . . . . . 25
11.5 Digital outputs . . . . . . . . . . . . . . . . . . . . . . . . 25
11.5.1 Digital output buffers: CMOS mode . . . . . . . . 25
11.5.2 Digital output buffers: LVDS DDR mode . . . . 26
11.5.3 DAta Valid (DAV) output clock . . . . . . . . . . . . 27
11.5.4 OuT-of-Range (OTR) . . . . . . . . . . . . . . . . . . . 27
11.5.5 Digital offset . . . . . . . . . . . . . . . . . . . . . . . . . . 27
11.5.6 Test patterns . . . . . . . . . . . . . . . . . . . . . . . . . 28
11.5.7 Output codes versus input voltage. . . . . . . . . 28
11.6 Serial Peripheral Interface (SPI) . . . . . . . . . . 28
11.6.1 Register description . . . . . . . . . . . . . . . . . . . . 28
11.6.2 Default modes at start-up. . . . . . . . . . . . . . . . 29
11.6.3 Register allocation map . . . . . . . . . . . . . . . . . 31
12 Package outline. . . . . . . . . . . . . . . . . . . . . . . . 37
13 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 38
14 Revision history . . . . . . . . . . . . . . . . . . . . . . . 39
15 Contact information . . . . . . . . . . . . . . . . . . . . 39
16 Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40