February 2013
Revision: EB81_01.1
CSI2 to Parallel Bridge Board
User’s Guide
2
CSI2 to Parallel Bridge Board
User’s Guide
Introduction
The CSI2 to Parallel Bridge Board comprises a compact, low cost, MIPI CSI2 (Camera Serial Interface) image sen-
sor, lens and lens housing with adjustable focus, that can bolt directly onto the Lattice HDR-60 Base Board or the
MachXO2™ Dual Sensor Interface Board. Both the CSI2 to Parallel Bridge Board and the MachXO2 Dual Sensor
Interface Board are designed to work together. These boards plug into the HDR-60 Base Board to allow for a dem-
onstration. The CSI2 to Parallel Bridge Board is designed to use the Sony IMX169 CMOS Digital Image Sensors
which feature:
• Up to 13 megapixels
• HD video (1080p30 mode configurable)
• Selectable video or single frame modes
• MIPI CSI2 output, either two or four data lanes
Read more about the image sensor specifications in the Sony IMX169 data sheet.
Features
Key features of the CSI2 to Parallel Bridge Board include:
• Sony IMX169 CMOS Digital Image Sensor
• Lens: F/1.59, <7% distortion, with minimized flare, halo, and ghosting
• Lens holder with adjustable focus
• CSI2 or parallel signal connections to the MachXO2 Dual Sensor Interface Board or HDR-60 Base Board
• Selectable on-board 27.000 MHz MEMs oscillator, or HDR-60 Base Board oscillator
• Power status LEDs with one user-defined LED
General Description
The CSI2 to Parallel Bridge Board has been designed for use on the MachXO2 Dual Interface Sensor Board and
the HDR-60 Base Board. The CSI2 to Parallel Bridge Board contains the camera sensor portion, while the
MachXO2 Dual Sensor Interface Board performs the CSI2 to parallel conversion. The HDR-60 Base Board allows
the user to see an image on a HDMI monitor. See RD1146, MIPI CSI2 to CMOS Parallel Sensor Bridge, for more
information concerning a related demo.
Initial Setup and Handling
The following is recommended reading prior to removing the CSI2 to Parallel Bridge Board from the static shielding
bag and may or may not apply to your particular use of the board.
CAUTION: The devices on the boards can be damaged by improper handling.
The devices on the evaluation boards contain fairly robust ESD (Electro Static Discharge) protection structures
within them, able to withstand typical static discharges (see the “Human Body Model” specification for an example
of ESD characterization requirements). Even so, the devices are static-sensitive to conditions that exceed their
designed-in protection. For example: higher static voltages, as well as lower voltages with lower series resistance
or larger capacitance than the respective ESD specifications require can potentially damage or degrade the
devices on the evaluation board.
As such, it is recommended that you wear an approved and functioning grounded wrist strap at all times while han-
dling the evaluation boards when they are removed from the static shielding bag. If you will not be using the boards
for a while, it is best to put them back in the static shielding bag. Please save the static shielding bag and packing
box for future storage of the boards when they are not in use.
3
CSI2 to Parallel Bridge Board
User’s Guide
When reaching for the boards, it is recommended that you first touch the outside shield portion of the J11 BNC
connector on the HDR-60 Base Board. If the CSI2 to Parallel Bridge Board is not installed on the HDR-60 Base
Board, then when reaching for the CSI2 to Parallel Bridge Board, it is recommended that you first touch the outside
edge of the mounting holes on the CSI2 to Parallel Bridge Board. This will neutralize any static voltage difference
between your body and the board prior to any contact with signal I/O.
CAUTION: To minimize the possibility of ESD damage, the first and last electrical connection to the board, should
be from test equipment chassis ground to the J11 BNC shield GND on the HDR-60 Base Board.
Before connecting signals or power to the board, attach a cable from chassis ground on grounded test equipment
to the J11 BNC shield GND on the HDR-60 Base Board. Connecting the board ground to test equipment chassis
ground will decrease the risk of ESD damage to the I/O on the board as the initial connections to the board are
made. Likewise, when unplugging cables from the evaluation board, the last connection unplugged should be the
chassis GND connection to the evaluation board GND. If you have a signal source that is floating with respect to
chassis GND, attempt to neutralize any static charge on that signal source prior to attaching it to the evaluation
board.
If you are holding or carrying the board while it is not in a static shielding bag, please keep one finger on the J11
BNC shield GND on the HDR-60 Base Board. If carrying the CSI2 to Parallel Bridge Board alone, keep one finger
one of the mounting holes. This will keep the board at the same voltage potential as your body until you can pick up
the static shielding bag and put the board back in it.
Electrical, Mechanical, and Environmental Specifications
The nominal board dimensions are 42mm x 42mm (1.654” x 1.654”). Additional mechanical board dimension infor-
mation is included on the mechanical drawing shown in Appendix A, Figure . On the physical board itself, connec-
tors include pin 1 indictors as either an arrow, or triangle point near pin 1 on the outer layer silk screen. The
environmental specifications are as follows:
• Operating temperature: 0°C to 55°C
• Storage temperature: -40°C to 75°C
• Humidity: <95% without condensation
4
CSI2 to Parallel Bridge Board
User’s Guide
Functional Description
Figure 1. CSI2 to Parallel Bridge Board Revision B
Voltage Regulators
The CSI2 to Parallel Bridge Board power is supplied by the 5V DC power applied at connectors J7 and J8, pins 1,
2, 39 and 40. The on-board linear voltage regulators then provide the necessary supply voltages to power the sen-
sor: 2.7V, VDDIO, 1.2V, 1.8V, 2.5V and 3.3V. The regulator in location U10 can be configured as shown in Ta b le 1.
Table 1. CSI2 to Parallel Bridge Board Regulator Voltages
Supply Voltage Regulator Resistor Ratio Comment
V1P8_V3P3 On HDR-60 Base Board
R45/R50 1.8V
R58/R50 2.5V
R59/R50 3.3V
Jumper J253 short:
1.8V: 1 and 2
2.5V: 3 and 4 (default configuration)
3.3V: 5 and 6
Each of the LT3025 regulators are the linear low dropout voltage type that incorporate an external resistor divider
voltage feedback to divide down the regulator output voltage and compare it against an internal reference voltage.
The regulator then adjusts the output voltage higher or lower such that the resistor divided voltage matches the
internal reference. By doing this, each regulator output voltage remains at a constant voltage value independent of
the load it drives. Each regulator output voltage follows this equation:
VOUT = (1 + resistor ratio) x (regulator internal reference voltage)
See the LT3025 device data sheet for additional details about this device.
The default configuration for J253 is for 2.5V via shorting pins 3 and 4 as shown in Figure 2.
5
CSI2 to Parallel Bridge Board
User’s Guide
Figure 2. CSI2 to Parallel Bridge Board with Sony IMX169 CSI2 Sensor
J253:
• Short Pins 3 to 4
MEMS Oscillator (Y2)
As shown in Figure 2, J5 is set such that the IMX169 sensor will receive a clock input signal from the internal
27.000 MHz MEMS oscillator (Y2). The alternate position of J5 will select the HDR-60 Base Board oscillator for the
sensor clock input.
High-Speed CSI2 Connector (J8)
The Sony IMX169 (U12) will produce high-speed CSI2 differential signals after proper configuration via SCLK and
SADDR pins. There is a CSI2 differential clock and up to four CSI2 differential data lanes. The J8 connector can
plug into the MachXO2 Dual Sensor Interface Board or into the HDR-60 Base Board. The signals are identified in
Ta bl e 2.
Table 2. CSI2 to Parallel Bridge Board (J8)
J8 Pin IMX169 I/O Pin Signal Polarity Description
13 K4 CSI2 data0 P Differential CSI2 data
11 J4 CSI2 data0 N Differential CSI2 data
29 K6 CSI2 data1 P Differential CSI2 data
27 J6 CSI2 data1 N Differential CSI2 data
21 K3 CSI2 data2 P Differential CSI2 data
19 J3 CSI2 data2 N Differential CSI2 data
26 K7 CSI2 data3 P Differential CSI2 data
24 J7 CSI2 data3 N Differential CSI2 data
18 K5 CSI2 clock P Differential CSI2 clock
16 J5 CSI2 clock N Differential CSI2 clock
12 J4 CSI2 low speed data bit 0 —Single-ended CSI2 data 0 N side
6
CSI2 to Parallel Bridge Board
User’s Guide
Parallel Connector (J7)
Connector J7 is primarily reserved for future use. When used with the MachXO2 Dual Sensor Interface Board, only
a few pins are used as shown in Ta b l e 3.
Table 3. CSI2 to Parallel Bridge Board (J7)
J7 Pins IMX169 I/O Pin Signal Polarity Description
30 K4 CSI2 low speed data bit 0 —Single-ended CSI2 data 0 P side
28 C5 I2C SCLK —Serial clock to program IMX169
26 B5 I2C SADDR —Serial address to program IMX169
9-25, 27, 29, 31 —Reserved for future use via iCE40
References
• RD1146, MIPI CSI2 to CMOS Parallel Sensor Bridge
•HDR-60 Video Camera Development Kit web page
• DS1021, LatticeECP3 Family Data Sheet
• HB1009, LatticeECP3 Family Handbook
•EB59, HDR-60 Base Board User’s Guide
•EB69, MachXO2 Dual Sensor Interface Board User’s Guide
•QS010, LatticeECP3 Video Camera Development Kit QuickSTART Guide
Ordering Information
The CSI2 to Parallel Bridge Board is designed solely for use with the MachXO2 Dual Sensor Interface Board and/or
the HDR-60 Video Camera Development Kit.
Description Ordering Part Number China RoHS Environment Friendly
CSI2 to Parallel Bridge Board LF-C2P-EVN
MachXO2 Dual Sensor Interface Board LCMXO2-4000HE-DSIB-EVN
HDR-60 Video Camera Development Kit
(Contains: HDR-60 Base Board with LatticeECP3
FPGA pre-loaded with Image Signal Processing (ISP)
Demo, two USB cables, HDMI cable with HDMI-to-DVI
adapter, 12V AC adapter power supply, QuickSTART
Guide)
LFE3-70EAHDR60-DKN
Technical Support Assistance
Hotline: 1-800-LATTICE (North America)
+1-503-268-8001 (Outside North America)
e-mail: techsupport@latticesemi.com
Internet: www.latticesemi.com
7
CSI2 to Parallel Bridge Board
User’s Guide
Revision History
Date Version Change Summary
December 2012 01.0 Initial release.
February 2013 01.1 Clarify that CSI-2 is for use with MachXO2.
© 2013 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as
listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of
their respective holders. The specifications and information herein are subject to change without notice.
8
CSI2 to Parallel Bridge Board
User’s Guide
Appendix A. Schematic
Index
5
5
4
4
3
3
2
2
1
1
D D
CC
B B
A A
MIPI IMX NANOVESTA REV 2
1. INDEX
2. BLOCK DIAGRAM
3. BOTTOM CONN CONNECTION
4. I2C BYPASS CONNECTION
5. BANK2 & BANK3
6. BANK0 & BANK1
7. REGULATOR CONNECTION
8. LEVEL TRANSLATOR CONNECTION
9. POWER AND DECAPS
Title
veRrebmuN tnemucoDeziS
teehS:etaD of
2>coD<
MIPI_IMX_NANOVESTRA_REV_2
B
19Thursday, October 25, 2012
Title
veRrebmuN tnemucoDeziS
teehS:etaD of
2>coD<
MIPI_IMX_NANOVESTRA_REV_2
B
19Thursday, October 25, 2012
Title
veRrebmuN tnemucoDeziS
teehS:etaD of
2>coD<
MIPI_IMX_NANOVESTRA_REV_2
B
19Thursday, October 25, 2012
9
CSI2 to Parallel Bridge Board
User’s Guide
Block Diagram
5
5
4
4
3
3
2
2
1
1
D D
CC
B B
AA
iCE40
BANK 0
BANK 1
BANK 2
BANK 3
(Sheet 6)
(Sheet 6)
(Sheet 5)
(Sheet 5)
BLOCK DIAGRAM
BOTTOM PARALLEL CONNECTOR
(Sheet 3)
BOTTOM HIGH SPI CONNECTOR
(Sheet 3)
SONY SENSOR
MIPI
(Sheet 4)
REGULATORS
(Sheet 7)
OSCILLATOR
(Sheet 8)
TI CONNECTOR
(Sheet 4)
LVDS(0,1,2,3,CLK)
(Sheet 4)
SPI
FLASH (M25P80)
(Sheet 4)
2
3
4
1
1
2
3
CM81
LEVEL TRANSLATOR
(Sheet 8)
DNI
SADDR/SCLK
SADDR/SCLK
DPHY(0)
Title
veRrebmuN tnemucoDeziS
teehS:etaD of
2>coD<
MIPI_IMX_NANOVESTRA_REV_2
B
29Sunday, October 28, 2012
Title
veRrebmuN tnemucoDeziS
teehS:etaD of
2>coD<
MIPI_IMX_NANOVESTRA_REV_2
B
29Sunday, October 28, 2012
Title
veRrebmuN tnemucoDeziS
teehS:etaD of
2>coD<
MIPI_IMX_NANOVESTRA_REV_2
B
29Sunday, October 28, 2012
NOT
NOT
40
40
1
1
USED
USED
i
C
EiCE
C
MCM
10
CSI2 to Parallel Bridge Board
User’s Guide
Bottom Conn Connections
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Fitting & Boss have no electrical function, can be used as vias
BOTTOM - HIGH SPI to ECP3 BOTTOM CONN CONNECTIONS
BOTTOM - PARALLEL to ECP3
Fitting & Boss have no electrical function, can be used as vias
SLVS_0N_CSI_0N_HISPI
SLVS_0P_CSI_0P_HISPI
SLVS_2N_CSI_2N_HISPI
SLVS_2P_CSI_2P_HISPI
SLVS_1N_CSI_1N_HISPI
SLVS_1P_CSI_1P_HISPI
SLVS_CLKN_CSI_CKN_HISPI
SLVS_CLKP_CSI_CKP_HISPI
SLVS_3N_CSI_3N_HISPI
SLVS_3P_CSI_3P_HISPI
LED_CMOS_CSI0N_HISPI
SLVS_0N_CSI_0N_HISPI
LED_CMOS_CSI0N_HISPI
SLVS_0P_CSI_0P_HISPI
ICE40_SS_CSI_0_CMOS_LT
SLVS_0N_HISPI
SLVS_0P_HISPI
ECP3_PRL_SCLK
PIXCLK
FRAME_VALID
LINE_VALID
D06
D02
D07
D03
D10
D11
D04
D00
D05
D01
D08
D09
EXTCLK
ICE40_SO_CSI_0_CMOS_LT
ICE40_SI_CSI_0_CMOS_LT
XCLR_BOTTOM
ICE40_SCK_CSI_0_CMOS_LT
ICE40_SS_CSI_0_CMOS_LT
ECP3_PRL_SADDR
GND
GND
GNDGND
V1P8
V5P0_OR
V5P0_TI
V5P0
V5P0_OR
V5P0_OR
V5P0_OR
V5P0_OR
SLVS_2N_CSI_2N_HISPI[5]
SLVS_2P_CSI_2P_HISPI[5]
SLVS_1N_CSI_1N_HISPI[5]
SLVS_1P_CSI_1P_HISPI[5]
SLVS_CLKN_CSI_CKN_HISPI [5]
SLVS_CLKP_CSI_CKP_HISPI [5]
SLVS_3N_CSI_3N_HISPI [5]
SLVS_3P_CSI_3P_HISPI [5]
SLVS_0N_HISPI[5]
SLVS_0P_HISPI[5]
PIXCLK [4,6]
FRAME_VALID [4,6]
D04 [4,6]
D00 [4,6]
D05 [4,6]
D01 [4,6]
D08 [4,6]
D09 [4,6]
LINE_VALID[4,6]
D06[4,6]
D02[4,6]
D07[4,6]
D03[4,6]
D10[4,6]
D11[4,6]
EXTCLK[8]
ICE40_SO_CSI_0_CMOS_LT[4]
ICE40_SI_CSI_0_CMOS_LT[4]
XCLR_BOTTOM[5]
ICE40_SCK_CSI_0_CMOS_LT[4]
ICE40_SS_CSI_0_CMOS_LT [4]
ECP3_PRL_SADDR [4,8]
ECP3_PRL_SCLK [4,8]
Title
veRrebmuN tnemucoDeziS
teehS:etaD of
2>coD<
MIPI_IMX_NANOVESTRA_REV_2
B
39Sunday, October 28, 2012
Title
veRrebmuN tnemucoDeziS
teehS:etaD of
2>coD<
MIPI_IMX_NANOVESTRA_REV_2
B
39Sunday, October 28, 2012
Title
veRrebmuN tnemucoDeziS
teehS:etaD of
2>coD<
MIPI_IMX_NANOVESTRA_REV_2
B
39Sunday, October 28, 2012
R101 0
TP5
Hirose DF12 Series
J8
DF12(4.0)-40DP-0.5V_HEADER
PART_NUMBER = DF12(4.0)-40DP-0.5V
Manufacturer = HIROSE
PIN1
1PIN2 2
PIN3
3PIN4 4
PIN5
5PIN6 6
PIN7
7PIN8 8
PIN9
9PIN10 10
PIN11
11 PIN12 12
PIN13
13 PIN14 14
PIN15
15 PIN16 16
PIN17
17 PIN18 18
PIN19
19 PIN20 20
PIN21
21 PIN22 22
PIN23
23 PIN24 24
PIN25
25 PIN26 26
PIN27
27 PIN28 28
PIN29
29 PIN30 30
PIN31
31 PIN32 32
PIN33
33 PIN34 34
PIN35
35 PIN36 36
PIN37
37 PIN38 38
PIN39
39 PIN40 40
FITTING1
FITTING1
FITTING2
FITTING2
BOSS1 BOSS1
BOSS2 BOSS2
J251
SMD_0402_JPR
DEFAULT_OPTION = 1&2
1
2
3
J274
SMD_1210_JPR
DEFAULT_OPTION = 1&2
1
2
3
J252
SMD_0402_JPR
DEFAULT_OPTION = 1&2
1
2
3
TP1
R11
10.0K
1%
Hirose DF12 Series
J7
DF12_40DS-0.5V_RECEPTACLE
PART_NUMBER = DF12(4.0)-40DS-0.5V
Manufacturer = HIROSE
PIN1
1PIN2 2
PIN3
3PIN4 4
PIN5
5PIN6 6
PIN7
7PIN8 8
PIN9
9PIN10 10
PIN11
11 PIN12 12
PIN13
13 PIN14 14
PIN15
15 PIN16 16
PIN17
17 PIN18 18
PIN19
19 PIN20 20
PIN21
21 PIN22 22
PIN23
23 PIN24 24
PIN25
25 PIN26 26
PIN27
27 PIN28 28
PIN29
29 PIN30 30
PIN31
31 PIN32 32
PIN33
33 PIN34 34
PIN35
35 PIN36 36
PIN37
37 PIN38 38
PIN39
39 PIN40 40
FITTING1
FITTING1
FITTING2
FITTING2
BOSS1 BOSS1
BOSS2 BOSS2
11
CSI2 to Parallel Bridge Board
User’s Guide
12C Bypass Connection
5
5
4
4
3
3
2
2
1
1
D D
CC
B B
A A
I2C BYPASS CONNECTION
DEFAULT 1&2 DEFAULT 1&2
LINE_VALID
FRAME_VALID
PIXCLK
D05
D04
D03
D02
D00
D01
D06
D07
D08
D09
D10
D11
RESET_BAR
ECP3_PRL_SCLK
ECP3_PRL_SADDR
ICE40_SI_CSI_0_CMOS
ICE40_SCK_CSI_0_CMOS
ICE40_SO_CSI_0_CMOS
ICE40_SS_CSI_0_CMOS
ICE40_SO_CSI_0_CMOS
ICE40_SI_CSI_0_CMOS
ICE40_SCK_CSI_0_CMOS
ICE40_SS_CSI_0_CMOS
ICE40_SCK_CSI_0_CMOS
ICE40_SO_CSI_0_CMOS
ICE40_SS_CSI_0_CMOS
ICE40_SI_CSI_0_CMOS
GND
V3P3
V3P3
V3P3
GND
V3P3
GND
V3P3
GND
V1P8_3_3V
GND
V1P8_3_3V
GND
V3P3 V1P8_3_3V
GND
V5P0
V3P3
GND
V3P3
V5P0_TI
FRAME_VALID [3,6]
LINE_VALID [3,6]
PIXCLK [3,6]
D11 [3,6]
D10 [3,6]
D09 [3,6]
D08 [3,6]
D07 [3,6]
D06[3,6]
D05 [3,6]
D04 [3,6]
D03 [3,6]
D02 [3,6]
D01 [3,6]
D00 [3,6]
RESET_BAR [6]
ECP3_PRL_SCLK[3,8]
ECP3_PRL_SADDR [3,8]
ICE40_SO_CSI_0_CMOS_LT [3,4]
ICE40_SI_CSI_0_CMOS_LT [3,4]
ICE40_SCK_CSI_0_CMOS_LT [3,4]
ICE40_SS_CSI_0_CMOS_LT [3,4]
ICE40_SS_CSI_0_CMOS_LT[3,4]
ICE40_SCK_CSI_0_CMOS_LT[3,4]
ICE40_SO_CSI_0_CMOS_LT[3,4]
ICE40_SI_CSI_0_CMOS_LT[3,4]
SADDR_BOTTOM[8] SCLK_BOTTOM[8]
SADDR [5,6] SCLK [5,6]
SF8K_SADDR1[6] SF8K_SCLK[6]
Title
v
e
RrebmuN tnemucoDez
i
S
teehS:etaD of
2>coD<
MIPI_IMX_NANOVESTRA_REV_2
B
4 9Thursday, October 25, 2012
Title
veRrebmuN tne
muco
DeziS
teehS:etaD of
2>coD<
MIPI_IMX_NANOVESTRA_REV_2
B
4 9Thursday, October 25, 2012
Title
veRrebmuN tne
muco
DeziS
teehS:etaD of
2>coD<
MIPI_IMX_NANOVESTRA_REV_2
B
4 9Thursday, October 25, 2012
U14
M25P80-VMW6TG
Manufacturer = MICRON
PART_NUMBER = M25P80-VMW6TG
S_L
1
Q
2
W_L
3
VSS
4D5
C6
HOLD_L 7
VCC 8
J9
0541043631
PART_NUMBER = 0541043631
Manufacturer = MOLEX
VCC3.3_1 1
VCC3.3_2 2
VCC3.3_3 3
VCC5.5_1 4
VCC5.5_2 5
GND1 6
EXT_CLK 7
GND2 8
AFE_CLK 9
GND3 10
AFE_VD 11
AFE_HD 12
AFE_D13 13
AFE_D12 14
AFE_D11 15
AFE_D10 16
AFE_D9 17
AFE_D8 18
AFE_D7 19
AFE_D6 20
AFE_D5 21
AFE_D4 22
AFE_D3 23
AFE_D2 24
GND4 25
GND5 26
AFE_D1 27
AFE_D0 28
I2C_SCLK 29
I2C_SDATA 30
SPI_SDO 31
SPI_SCLK 32
AFE_RESET 33
SPI_EN 34
AFE_D14 35
AFE_D15 36
MECH1 37
MECH2 38
SEC 6/6
SPI
iCE40
U16F
iCE40_CM81
Manufacturer = LATTICE
PART_NUMBER = iCE40
PIOS_SPI_SO G6
PIOS_SPI_SI H7
PIOS_SPI_SCK G7
PIOS_SPI_SS_B F7
SPI_VCC H8
J277
3PIN_SMD_0603
DEFAULT_OPTION = Install 0/0603 Resitor
1
2
3
R24
10.0K
1%
TXB0104DR
U15
LT_TXB0104DR
Manufacturer = TI
PART_NUMBER = TXB0104DR
VCCA 1
A1 2
A2 3
A3 4
A4 5
NC1 6
GND
7
OE
8
NC2 9
B4
10
B3
11
B2
12
B1
13
VCCB
14
R12
10.0K
1%
C27
100nF
16V
R102 0
R31 DNL
R153
10K1%
J273
HDR_2X3
MISO
1NC_+5V 2
SCLK
3MOSI 4
SS
5GND 6
C28
100nF
16V
C928
0.1uF
16V
J276
3PIN_SMD_0603
DEFAULT_OPTION = Install 0/0603 Resitor
1
2
3
C927
0.1uF
16V
NOT
6
6
O
S
_
SPI
_
S
OS_SPI_S
OS
_
S
PI_
S
OS_SPI_
S_
SPI
_
S
C
S_SPI_SC
SPI SS
S
S
PI_V
CSPI VC
USED
SE
CSEC
SED
S
PI
SPI
iCiC
Bank2 and Bank3
5
5
4
4
3
3
2
2
1
1
DD
CC
B B
A A
BANK2 AND BANK3
PLACE resistors R103, R114, R115, R116,
CLOSE TO THE SONY SENSOR PINS
NOTE:
PLACE close to the device U16
SLVS_0P_CSI_0P SLVS_0P_LVDS
SLVS_0P_DPHY
SLVS_0N_CSI_0N SLVS_0N_LVDS
SLVS_0N_DPHY
SADDR
SCLK SLVS_0N_CSI_0N
SLVS_0P_CSI_0P
SLVS_2P_CSI_2P
SLVS_2N_CSI_2N
SLVS_1P_CSI_1P
SLVS_1N_CSI_1N
SLVS_3P_CSI_3P
SLVS_3N_CSI_3N
SLVS_CLKP_CSI_CKP
SLVS_CLKN_CSI_CKN
SLVS_3N_LVDS
SLVS_3P_LVDS
SLVS_2N_CSI_2N
SLVS_2N_LVDS
SLVS_2P_CSI_2P
SLVS_2P_LVDS
SLVS_3P_CSI_3P
SLVS_3N_CSI_3N
SONY_INCK
SLVS_1P_LVDS
SLVS_1P_CSI_1P SLVS_1N_CSI_1N
SLVS_1N_LVDS
SLVS_CLKP_CSI_CKP
SLVS_CLKP_LVDS
SLVS_CLKN_LVDS
SLVS_CLKN_CSI_CKN
SLVS_0P_LVDS SLVS_1P_LVDS
SLVS_1N_LVDSSLVS_0N_LVDS
SLVS_0P_LVDS_1
SLVS_0N_LVDS_1
SLVS_1P_LVDS_1
SLVS_1N_LVDS_1
SLVS_0N_LVDS_1
SLVS_0P_LVDS_1
SLVS_1P_LVDS_1
SLVS_1N_LVDS_1
SLVS_2N_LVDS_1
SLVS_2P_LVDS_1
SLVS_3N_LVDS_1
SLVS_3P_LVDS_1
SLVS_CLKN_LVDS_1
SLVS_CLKP_LVDS_1
V1P8
AGNDAGND
V1P8
V2P5
GND
GND
V2P5
V2P5 V1P8
V1P8 V1P8
V1P8
GND V1P8GND
GND
SLVS_0P_HISPI [3] SLVS_0N_HISPI[3]
SONY_INCK[6,8]
XCLR_SONY[5]
SLVS_2P_CSI_2P_HISPI [3] SLVS_2N_CSI_2N_HISPI [3]
SLVS_3P_CSI_3P_HISPI [3]
SLVS_3N_CSI_3N_HISPI [3]
SLVS_0N_DPHY[6]
SLVS_0P_DPHY [6]
SLVS_1P_CSI_1P_HISPI [3] SLVS_1N_CSI_1N_HISPI [3]
SLVS_CLKP_CSI_CKP_HISPI [3]
SLVS_CLKN_CSI_CKN_HISPI [3]
XCLR_iCE [6]
XCLR_BOTTOM [3]
XCLR_SONY[5]
SLVS_CLKP_LVDS [6]
SLVS_CLKN_LVDS [6]
SLVS_3P_LVDS [6]
SLVS_3N_LVDS[6]
SLVS_2P_LVDS [6] SLVS_2N_LVDS [6]
SCLK[4,6]
SADDR[4,6]
SLVS_2N_LVDS_1[6]
SLVS_2P_LVDS_1 [6]
SLVS_3N_LVDS_1 [6]
SLVS_3P_LVDS_1 [6]
SLVS_CLKN_LVDS_1[6]
SLVS_CLKP_LVDS_1 [6]
Title
veRrebmuN tnemucoDeziS
teehS:etaD of
2>coD<
MIPI_IMX_NANOVESTRA_REV_2
B
59Monday, October 29, 2012
Title
veRrebmuN tnemucoDeziS
teehS:etaD of
2>coD<
MIPI_IMX_NANOVESTRA_REV_2
B
59Monday, October 29, 2012
Title
veRrebmuN tnemucoDeziS
teehS:etaD of
2>coD<
MIPI_IMX_NANOVESTRA_REV_2
B
59Monday, October 29, 2012
C898
0.22UF
6.3V
R111
1K
1%
C899
0.22UF
6.3V
123
DPR35
0
DEFAULT_OPTION = 2&3
2
3
1
123
DPR33
0
DEFAULT_OPTION = 2&3
2
3
1
R110
1K
1%
J272
2 1
R422
120
J278
SMD_0402_JPR
DEFAULT_OPTION = 1&2
1
2
3
SEC 4/6
BANK 3
iCE40
U16D
iCE40_CM81
Manufacturer = LATTICE
PART_NUMBER = iCE40
PIO3_DP00A C2
PIO3_DP00B B2
PIO3_DP01B C1
PIO3_DP01A B1
PIO3_DP02B C3
PIO3_DP02A D2
PIO3_DP03A D1
PIO3_DP06B E4
PIO3_DP03B E1
PIO3_DP05A E2
PIO3_DP04B F3
PIO3_DP04A F1
PIO3_DP08B G1
PIO3_DP08A G3
GBIN6_PIO3_DP06A E3
GBIN7_PIO3_DP05B D3
VCCIO_3_H3
H3
PIO3_DP07B H2
PIO3_DP07A G2
R421
120
J275
SMD_0402_JPR
DEFAULT_OPTION = 1&2
1
2
3
R420
470
1%
R104 0
R429
300
R428
220
R430
120
123
DPR32
0
DEFAULT_OPTION = 2&3
2
3
1
R431
220
LED15
PART_NUMBER = SML-512MWT86
Green
12
R432
220
R448
DNL
R419
240
1%
R449
DNL
CONFIG
SEC 3/6
BANK 2
iCE40
U16C
iCE40_CM81
Manufacturer = LATTICE
PART_NUMBER = iCE40
VCCIO_2_J5
J5
GBIN4_PIO2 H4
PIO2_3 H1
PIO2_4 J2
PIO2_5 J1
PIO2_6 J3
PIO2_7 J4
GBIN5_PIO2 G4
PIO2_CBSEL0 G5
PIO2_CBSEL1 H5
CDONE E6
CRESET_B H6
J279
SMD_0402_JPR
DEFAULT_OPTION = 1&2
1
2
3
123
4
DPR26
0
DEFAULT_OPTION = 2&3
2
3
1
4
123
4
DPR25
0
DEFAULT_OPTION = 2&3
2
3
1
4
R115 10
1%
R10310
1%
R427
220
123
DPR31
0
DEFAULT_OPTION = 2&3
2
3
1
123
DPR38
0
DEFAULT_OPTION = 2&3
2
3
1
123
DPR37
0
DEFAULT_OPTION = 2&3
2
3
1
R15
10.0K
1%
R114 10
1%
LED14
PART_NUMBER = SML-512MWT86
Green
12
R426
120
TP3
SEC 2/3
SONY SENSOR
U12B
IMX169CQKC
Manufacturer = SONY
PART_NUMBER = IMX169CQK-C
DMO3N J7
DMO3P K7
DMO1N J6
DMO1P K6
DCKN J5
DCKP K5
DMO2N J3
DMO2P K3
DMO0N J4
DMO0P K4
VCAP1 H1
VCAP2 E1
INCK
A7
SCL
C5
SDA
B5
XCE
B6
XCLR
C6
SDO A5
XVS A6
TEST1
A8
TEST2
B8
TEST3
E2
TEST4
J2
TEST5
K2
123
DPR36
0
DEFAULT_OPTION = 2&3
2
3
1
R116 10
1%
R433
300
TP2
123
DPR34
0
DEFAULT_OPTION = 2&3
2
3
1
NOT
P
I
O
3_DP
0
PIO3_DP0
P
I
O
3_DP
0
PIO3_DP0
P
I
O
3_DP
0
IO3_DP
P
I
O
3
_
DP
0
O3_DP
PIO3 DP0
P0
P
I
O
3_DP
0
PIO3_DP0
P
I
O
3
_
DP
0
O3_DP0
P
I
O
3_DP
0
PIO3_DP0
P
I
O
3_DP
0
PIO3_DP0
P
I
O
3_DP
0
PIO3_DP0
P
I
O
3_DP
0
PIO3_DP0
USED
GB
GB
GB
GB
NOT
G
BIN4
_P
GBIN4_P
PIO
PIO
P
I
O
PIO
P
I
O
PIO
P
I
O
PIO
G
BIN5_
P
GBIN5_P
P
I
O
2_
C
B
S
IO2_CBS
P
I
O
2_
C
B
S
IO2_CBS
USED
O
_2_J5
O_2_J5
Bank0 and Bank1
5
5
4
4
3
3
2
2
1
1
DD
C C
BB
A A
BANK0 AND BANK1
DECAPS FOR BANK0 DECAPS FOR BANK1 DECAPS FOR BANK2 DECAPS FOR BANK3
NOTE:
PLACE close to the device U16
SF8K_SCLK
D00
D05
D01
D08
D09
PIXCLK
D04
FRAME_VALID
LINE_VALID
D06
D07
D03
D10
D11
D02
RESET_BAR
XCLR_iCE
SLVS_0P_DPHY
SLVS_0N_DPHY
SLVS_3P_LVDS
SLVS_3N_LVDS
SLVS_CLKP_LVDS
SLVS_CLKN_LVDS
SLVS_3P_LVDS_1
SLVS_3N_LVDS_1
SLVS_CLKP_LVDS_1
SLVS_CLKN_LVDS_1
SLVS_2P_LVDS
SLVS_2N_LVDS SLVS_2N_LVDS_1
SLVS_2P_LVDS_1
SONY_INCK
SF8K_SADDR1
V1P8_3_3V V1P8 V2P5 V1P8
V1P8
GND GND GND GND
V1P8_3_3V
V1P8 V1P8
V1P8 V1P8GND GND
V1P8
V1P8
GND
D00 [3,4]
D05 [3,4]
D08 [3,4]
D09 [3,4]
D01 [3,4]
PIXCLK [3,4]
FRAME_VALID [3,4]
D04 [3,4]
LINE_VALID [3,4]
D06 [3,4]
D02 [3,4]
D07 [3,4]
D03 [3,4]
D10 [3,4]
D11 [3,4]
RESET_BAR [4]
XCLR_iCE [5]
SLVS_0N_DPHY [5]
SLVS_0P_DPHY[5]
SLVS_3P_LVDS[5]
SLVS_3N_LVDS[5]
SLVS_CLKP_LVDS[5]
SLVS_CLKN_LVDS[5]
SLVS_3P_LVDS_1 [5]
SLVS_3N_LVDS_1[5]
SLVS_CLKP_LVDS_1[5]
SLVS_CLKN_LVDS_1[5]
SLVS_2P_LVDS[5]
SLVS_2N_LVDS[5]
SLVS_2P_LVDS_1 [5]
SLVS_2N_LVDS_1 [5]
SADDR[4,5]
SCLK [4,5]
SF8K_SCLK [4]
SONY_INCK[5,8]
SF8K_SADDR1[4]
Title
veRrebmuN tnemucoDeziS
teehS:etaD of
2>coD<
MIPI_IMX_NANOVESTRA_REV_2
B
69Thursday, October 25, 2012
Title
veRrebmuN tnemucoDeziS
teehS:etaD of
2>coD<
MIPI_IMX_NANOVESTRA_REV_2
B
69Thursday, October 25, 2012
Title
veRrebmuN tnemucoDeziS
teehS:etaD of
2>coD<
MIPI_IMX_NANOVESTRA_REV_2
B
69Thursday, October 25, 2012
R76 330.5%
C91
0.1uF
16V
R87 330.5%
R444
220
R434
120
R438
120
C95
0.1uF
16V
R75 330.5%
R81 330.5%
C57
0.1uF
16V
R84 330.5%
R445
300
C97
0.1uF
16V
R435
220
R450
DNL
C59
0.1uF
16V
R72330.5%
R440
220
R446 DNI
R436
220
C60
0.1uF
16V
J282
SMD_0402_JPR
DEFAULT_OPTION = 1&2
1
2
3
R424
120 R451
DNL
R77 330.5%
C93
0.1uF
16V
R86 330.5%
R83 330.5%
R441
220
SEC 2/6
BANK 1
iCE40
U16B
iCE40_CM81
Manufacturer = LATTICE
PART_NUMBER = iCE40
GBIN2_PIO1_1 D8
GBIN3_PIO1_2 E8
PIO1_3 F8
PIO1_4 G8
PIO1_5 D6
PIO1_6 E7
PIO1_7 D7
PIO1_8 D9
PIO1_9 B9
PIO1_10 C9
PIO1_11 A9
PIO1_12 H9
PIO1_13 J8
PIO1_14 G9
PIO1_15 J9
VCCIO_1_C6
C6
J281
SMD_0402_JPR
DEFAULT_OPTION = 1&2
1
2
3
R425
120
R71 330.5%
R74 330.5%
R437
300
C58
0.1uF
16V
R88 330.5%
R447 DNI
SEC 1/6
BANK 0
iCE40
U16A
iCE40_CM81
Manufacturer = LATTICE
PART_NUMBER = iCE40
PIO0_4 B7
PIO0_5 A8
PIO0_6 B6
PIO0_7 A7
PIO0_8 A6
PIO0_9 B5
PIO0_10 A4
PIO0_11 E5
PIO0_12 A3
PIO0_13 B4
PIO0_14 A2
PIO0_15 D5
PIO0_16 B3
PIO0_17 A1
VCCIO_0_A5
A5 GBIN0_PIO0_1 C4
GBIN1_PIO0_2 C5
PIO0_3 B8
J280
SMD_0402_JPR
DEFAULT_OPTION = 1&2
1
2
3
R442
300 R439
120
R82 330.5%
R73 330.5%
R85 330.5%
R443
220
R423
120 R452
DNL
NOT
G
BIN3_PI
O
BIN3_PIO
PI
OP
PI
OPIO
PI
O
PI
OPIO
PI
OPIO
PI
OPIO
PI
OPIO
PI
O1PIO
PI
O1PIO
PIO1O
USED
SEC
SEC
BB
AA
NN
KK
11
I
O
_1_
C
6
IO_
NOT
PI
OPIO
P
I
OPIO
P
I
OPIO
PI
OPIO
P
I
OPIO
P
I
OPIO
P
IO
0PIO
P
I
O0O0
P
IO
0PIO0
P
IO
0O0
PIOPIO
USED
B
A
N
K
0
O
_
0
_
A5
O_0_A5
Regulator Connections
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
AA
V1P2
1.2v
300mA
1ms RC
V1P8
1.8v
300mA
V2P7
2.7v
300mA
V2P5
2.5v
300mA
REGULATOR CONNECTIONS
V1P2_VDD
1.2v
300mA
1ms RC
V1P8_3_3V
1.8V or 2.5V or 3.3V
300mA
V3P3
3.3v
300mA
1 & 2 34.8K V1P8
3 & 4 52.3K V2P5
5 & 6 73.2K 3_3V
SHUNT VALUE VOLTAGE
GND
GND
GND GND
GND
GND
GND
GND
GND
GND
GND
GND GND
GND GND
GND GND
GND GND
GND
GND
GND GND
GND
GND
GND GND
GND GND
V5P0
V2P7
V5P0
V1P8
V5P0
V1P2
V1P2
V5P0
V5P0
V2P5
GND
GND
GND
GND
GND GND
V5P0
V1P2_VDD
GND
V1P8 GND GND
V1P8_3_3V
GND
GND GND
GND
V5P0
GNDGND
V3P3
Title
veRrebmuN tnemucoDeziS
teehS:etaD of
2>coD<
MIPI_IMX_NANOVESTRA_REV_2
B
79Thursday, October 25, 2012
Title
veRrebmuN tnemucoDeziS
teehS:etaD of
2>coD<
MIPI_IMX_NANOVESTRA_REV_2
B
79Thursday, October 25, 2012
Title
veRrebmuN tnemucoDeziS
teehS:etaD of
2>coD<
MIPI_IMX_NANOVESTRA_REV_2
B
79Thursday, October 25, 2012
R42
DNI-0603SMT
C81
0.1uF
16V
R40
DNI-0603SMT
C84
0.1uF
16V
J253
2x3_HEADER_100mil
12
3 4
5 6
C21
10uF/6V3
6.3V
R41
DNI-0603SMT
LTC3025
U11 LTC3025EDC#PBF
BIAS 1
EN
6
IN
3
GND
2
PWP
7
ADJ 5
OUT 4
C6
10uF/6V3
6.3V
R52
1R
5%
R107
0
R43
57.6K
R0402
1%
R57
100K-0402SMT
5%
C11
10uF/6V3
6.3V
R53
10.0K
R0402
1%
C19
10uF/6V3
6.3V
R19
DNI-0603SMT
R17
DNI-0603SMT
R32
1R
5%
LTC3025
U10
LTC3025EDC#PBF
BIAS 1
EN
6
IN
3
GND
2
PWP
7
ADJ 5
OUT 4
LTC3025
U4 LTC3025EDC#PBF
BIAS 1
EN
6
IN
3
GND
2
PWP
7
ADJ 5
OUT 4
C16
10uF/6V3
6.3V
R117
0
C7
10uF/6V3
6.3V
R20
10.0K
R0402
1%
C33
0.01uF
25V
C79
0.1uF
16V
R59 73.2K
R04021%
C13
10uF/6V3
6.3V
R109
0
R49
1R
5%
C78
0.1uF
16V
R44
34.8K
R0402
1%
R4534.8K
R04021%
R13
10.0K
1%
C5
10uF/6V3
6.3V
R33
1R
5%
LTC3025
U9 LTC3025EDC#PBF
BIAS 1
EN
6
IN
3
GND
2
PWP
7
ADJ 5
OUT 4
LTC3025
U8 LTC3025EDC#PBF
BIAS 1
EN
6
IN
3
GND
2
PWP
7
ADJ 5
OUT 4
R16
20K
R0402
1%
C77
0.1uF
16V
C32
0.01uF
25V
R14
DNI-0603SMT
R106
0
C4
10uF/6V3
6.3V
R22
10.0K
R0402
1%
R21
10.0K
R0402
1%
R54
52.3K
R0402
1%
C9
10uF/6V3
6.3V
C12
10uF/6V3
6.3V
R34
1R
5%
LTC3025
U5 LTC3025EDC#PBF
BIAS 1
EN
6
IN
3
GND
2
PWP
7
ADJ 5
OUT 4
R58 52.3K
R04021%
C20
10uF/6V3
6.3V
R55
DNI-0603SMT
R48
1R
5%
R46
10.0K
R0402
1%
R18
20K
R0402
1%
R56
1R
5%
C22
10uF/6V3
6.3V
R23
73.2K
R0402
1%
LTC3025
U6 LTC3025EDC#PBF
BIAS 1
EN
6
IN
3
GND
2
PWP
7
ADJ 5
OUT 4
C23
10uF/6V3
6.3V
C76
0.1uF
16V
R108
0
C80
0.1uF
16V
R47
100K-0402SMT
5%
R50
10.0K
R0402
1%
Level Translator Connections
5
5
4
4
3
3
2
2
1
1
DD
C C
B B
A A
LEVEL TRANSLATOR CONNECTIONS
OSCILLATOR
Place R28 near Y2
DEFAULT 1&2
EXTCLK_OSC
EXTCLK
SONY_INCK
V1P8
GND
V1P8_3_3V
GND
V1P8_3_3V
V1P8
V1P8
GND
GND GND
GND
V1P8 V1P8_3_3V
EXTCLK[3]
SONY_INCK [5,6]
ECP3_PRL_SADDR [3,4]
ECP3_PRL_SCLK [3,4]
SADDR_BOTTOM[4]
SCLK_BOTTOM[4]
Title
veRrebmuN tnemucoDeziS
teehS:etaD of
2>coD<
MIPI_IMX_NANOVESTRA_REV_2
B
8 9Sunday, October 28, 2012
Title
veRrebmuN tnemucoDeziS
teehS:etaD of
2>coD<
MIPI_IMX_NANOVESTRA_REV_2
B
8 9Sunday, October 28, 2012
Title
veRrebmuN tnemucoDeziS
teehS:etaD of
2>coD<
MIPI_IMX_NANOVESTRA_REV_2
B
8 9Sunday, October 28, 2012
R150 4_7K
1%
R112
1K
1%
C26
100nF
16V
R113
1K
1%
R28 27
1%
C10
1uF
6.3V
J5
SMD_0603_JPR
1
2
3
TXS0102DC
U13
TXS0102DC
Manufacturer = TI
PART_NUMBER = TXS0102DCUR
VCCA
3
A1
5
A2
4
GND 2
OE
6
B2 1
B1 8
VCCB 7
R152
10K1%
C225
0.1uF
16V
12
C25
100nF
16V
FB1
BLM21AG601SN1D Y2
27 MHZ
DI
Part Number = DSC1001AE2-27.0000
Manufacturer = DISCERA
VCC 4
OUT 3
GND
2EN
1
Sensor Power and Decaps
5
5
4
4
3
3
2
2
1
1
D D
CC
B B
A A
DECAPS FOR VIP2
DECAPS FOR V2P7
SENSOR POWER AND DECAPS
DECAPS FOR VIP8
DECAPS FOR V1P2_VDD
DECAPS FOR V2P5
V1P8_VDDM
V2P7_VDDH
V1P2_VDDL
V2P7_VDDH
V1P8_VDDM
V1P2_VDDL
PLLVCC_G2
PLLGND_H2
PLLVCC_G2
PLLGND_H2
AGND
GND
AGND
V1P2_VDD
GND
GND
V2P5
GND
V2P7
V1P8
V1P2
AGND GND
AGND
GND
V1P2_VDD
GND AGND
V2P5
V1P2_VDD
GND
Title
veRrebmuN tnemucoDeziS
teehS:etaD of
2>coD<
MIPI_IMX_NANOVESTRA_REV_2
B
9 9Thursday, October 25, 2012
Title
veRrebmuN tnemucoDeziS
teehS:etaD of
2>coD<
MIPI_IMX_NANOVESTRA_REV_2
B
9 9Thursday, October 25, 2012
Title
veRrebmuN tnemucoDeziS
teehS:etaD of
2>coD<
MIPI_IMX_NANOVESTRA_REV_2
B
9 9Thursday, October 25, 2012
C70
0.1uF
16V
L41
4.7UH
PART_NUMBER = 74437324047
1 2
C904
0.1uF
16V
L43
4.7UH
12
C902
0.1uF
16V
C126
1uF
16V
C71
0.1uF
16V
C915
10UF
10V
C125
1uF
16V
C897
2.2UF
16V
C903
0.1uF
16V
C919
0.1uF
16V
TP4
C127
1uF
16V C923
10UF
10V
R119
100
1%
C916
10UF
10V
SEC 5/6
iCE40
U16E
iCE40_CM81
Manufacturer = LATTICE
PART_NUMBER = iCE40
VCC_1
D4
VCC_2
F2
VCC_3
E9
VPP_2V5
C8
VPP_FAST
C7
GND_1 F5
GND_2 F4
GND_3 F9
GND_4 F6
PLLGND J6
PLLVCC
J7
C906
1uF
16V
C124
1uF
16V
C75
0.1uF
16V
C924
10UF
10V
C54
0.1uF
16V
L42
4.7UH
PART_NUMBER = 74437324047
12
C89
0.1uF
16V
C907
1uF
16V
C53
0.1uF
16V
C926
10UF
10V
C123
1uF
16V
C913
0.1uF
16V
R1200
C917
10UF
10V
C908
1uF
16V
C73
0.1uF
16V
C136
1uF
16V
C909
0.1uF
16V
C918
1uF
16V
C900
0.1uF
16V
C911
0.1uF
16V
C87
0.1uF
16V
SEC 1/3
SONY SENSOR
U12A
IMX169CQKC
Manufacturer = SONY
PART_NUMBER = IMX169CQK-C
VDDH1
A4
VDDH2
C1
VDDH3
C9
VDDH4
D1
VDDH5
G1
VDDH6
H3
VDDH7
H9
VDDL1
C7
VDDL2
E3
VDDL3
F1
VDDL4
H5
VDDL5
H6
VDDM
C8
VSSH1 B4
VSSH2 C2
VSSH3 D2
VSSH4 G2
VSSH5 G3
VSSH6 H2
VSSH7 H8
VSSL1 B7
VSSL2 C4
VSSL3 D7
VSSL4 F2
VSSL5 F3
VSSL6 G7
VSSL7 H4
VSSL8 H7
VCP A3
VRL B3
C914
0.1uF
16V
R1050
C905
0.1uF
16V
C921
1uF
16V
C922
10UF
10V
C74
0.1uF
16V
C137
1uF
16V
C138
1uF
16V
C910
0.1uF
16V
C901
0.1uF
16V
C912
0.1uF
16V
C920
0.1uF
16V
NOT
G
ND
_GND_
GND
_GN
G
ND
_GND
G
ND
_GND
PLL
GNGN
USED
S
ESE
CC
_1
CC_1
CC
_
2
CC_2
C
C
_3
CC_3
P
P
_2
V5
PP_2V5
P
P_FA
S
T
PP_FAST
L
LV
CC
LVCC
