SMSC USB3311 REV C PRODUCT PREVIEW Revision 2.1 (06-10-10)
Data Brief
PRODUCT FEATURES
USB3311
Hi-Speed USB Transceiver
with 1.8V ULPI Interface -
26MHz Reference Clock
USB-IF “Hi-Speed” compliant to the Universal Serial
Bus Specification Rev 2.0
Interface compliant with the ULPI Specification
revision 1.1 as a Single Data Rate (SDR) PHY
1.8V IO Voltage (±10%)
flexPWR® Technology
— Low current design ideal for battery powered
applications
— “Sleep” mode tri-states all ULPI pins and places the
part in a low current state
Supports FS pre-amble for FS hubs with a LS device
attached (UTMI+ Level 3)
Supports HS SOF and LS keep-alive pulse
Includes full support for the optional On-The-Go
(OTG) protocol detailed in the On-The-Go
Supplement Revision 1.0a specification
Supports the OTG Host Negotiation Protocol (HNP)
and Session Request Protocol (SRP)
Allows host to turn VBUS off to conserve battery
power in OTG applications
Support OTG monitoring of VBUS levels with internal
comparators
“Wrapper-less” design for optimal timing performance
and design ease
— Low Latency Hi-Speed Receiver (43 Hi-Speed clocks
Max) allows use of legacy UTMI Links with a ULPI
bridge
Internal 5V cable short-circuit protection of ID, DP
and DM lines to VBUS or ground
26MHz Reference Clock Operation
— 0 to 3.6V input drive tolerant
— Able to accept “noisy” clock sources
Internal low jitter PLL for 480MHz Hi-Speed USB
operation
Internal detection of the value of resistance to ground
on the ID pin
Integrated battery to 3.3V LDO regulator
— 2.2uF bypass capacitor
— 100mV dropout voltage
Integrated ESD protection circuits
—Up to ±15kV without any external devices
Carkit UART mode for non-USB serial data transfers
Integrated USB Switch
— Allows single USB port of connection
— High speed data
— Battery charging
— Stereo and mono/mic audio
— USB1.1 data
Industrial Operating Temperature -40°C to +85°C
Packaging Options
— 24 pin QFN lead-free RoHS compliant package
(4 x 4 x 0.90 mm height)
— 25 ball VFBGA lead-free RoHS compliant package also
available; (3 x 3 x 0.88mm height)
Applications
The USB3311 is targeted for any application where a Hi-
Speed USB connection is desired and when board
space, power, and interface pins must be minimized.
The USB3311 is well suited for:
Cell Phones
PDAs
MP3 Players
GPS Personal Navigation
Scanners
External Hard Drives
Digital Still and Video Cameras
Portable Media Players
Entertainment Devices
Printers
Set Top Boxes
Video Record/Playback Systems
IP and Video Phones
Gaming Consoles
POS Terminals
Order Number(s):
USB3311C-CP-TR FOR 24 PIN, QFN LEAD-FREE ROHS COMPLIANT PACKAGE (TAPE AND REEL)
USB3311C-GJ-TR FOR 25 PIN, VFBGA LEAD-FREE ROHS COMPLIANT PACKAGE (TAPE AND REEL)
REEL SIZE IS 4000 PIECES.
This product meets the halogen maximum concentration values per IEC61249-2-21
For RoHS compliance and environmental information, please visit www.smsc.com/rohs
Hi-Speed USB Transceiver with 1.8V ULPI Interface - 26MHz Reference Clock
Revision 2.1 (06-10-10) 2 SMSC USB3311 REV C
PRODUCT PREVIEW
80 ARKAY DRIVE, HAUPPAUGE, NY 11788 (631) 435-6000, FAX (631) 273-3123
Copyright © 2010 SMSC or its subsidiaries. All rights reserved.
Circuit diagrams and other information relating to SMSC products are included as a means of illustrating typical applications. Consequently, complete information sufficient for
construction purposes is not necessarily given. Although the information has been checked and is believed to be accurate, no responsibility is assumed for inaccuracies. SMSC
reserves the right to make changes to specifications and product descriptions at any time without notice. Contact your local SMSC sales office to obtain the latest specifications
before placing your product order. The provision of this information does not convey to the purchaser of the described semiconductor devices any licenses under any patent
rights or other intellectual property rights of SMSC or others. All sales are expressly conditional on your agreement to the terms and conditions of the most recently dated
version of SMSC's standard Terms of Sale Agreement dated before the date of your order (the "Terms of Sale Agreement"). The product may contain design defects or errors
known as anomalies which may cause the product's functions to deviate from published specifications. Anomaly sheets are available upon request. SMSC products are not
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TO HAVE FAILED OF ITS ESSENTIAL PURPOSE, AND WHETHER OR NOT SMSC HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
Hi-Speed USB Transceiver with 1.8V ULPI Interface - 26MHz Reference Clock
SMSC USB3311 REV C3 Revision 2.1 (06-10-10)
PRODUCT PREVIEW
General Description
The USB3311 is a highly integrated Hi-Speed USB 2.0 Transceiver (PHY) that supports systems
architectures based on a 26MHz reference clock. It is designed to be used in both commercial and
industrial temperature applications.
The USB3311 meets all of the electrical requirements to be used as a Hi-Speed USB Host, Device, or
an On-the-Go (OTG) device. In addition to the supporting USB signaling the USB3311 also provides
USB UART mode and USB Audio mode.
USB3311 uses the industry standard UTMI+ Low Pin Interface (ULPI) to connect the USB PHY to the
Link. The industry standard ULPI interface uses a method of in-band signaling and status byte transfers
between the Link and PHY, to facilitate a USB session. By using in-band signaling and status byte
transfers the ULPI interface requires only 12 pins.
The USB3311 uses SMSC’s “wrapper-less” technology to implement the ULPI interface. This “wrapper-
less” technology allows the PHY to achieve a low latency transmit and receive time. SMSC’s low
latency transceiver allows an existing UTMI Link to be reused by adding a UTMI to ULPI bridge. By
adding a bridge to the ASIC the existing and proven UTMI Link IP can be reused.
Figure 1 USB3311 Block Diagram
OTG
Carkit
Hi-Speed
USB
Transceiver
ULPI
Interface
ULPI
Registers
and State
Machine
BIAS
Low Jitter
Integrated
PLL
Integrated
Power
Management
VBUS
ID
DP
DM
RBIAS
ESD Protection
SPKR_L
SPKR_R/M
REFCLK
DATA[7:0]
RESETB
VDD18
VDD33
VBAT
DIR
NXT
STP
CLKOUT
Hi-Speed USB Transceiver with 1.8V ULPI Interface - 26MHz Reference Clock
Revision 2.1 (06-10-10) 4 SMSC USB3311 REV C
PRODUCT PREVIEW
The USB3311 is designed to run with a 26MHz reference clock. By using a reference clock from the
Link the USB3311 is able to remove the cost of a crystal reference from the design.
The USB3311 includes a integrated 3.3V LDO regulator to generate its own supply from power applied
at the VBAT pin. The voltage on the VBAT pin can range from 3.1 to 5.5V. The regulator dropout
voltage is less than 100mV which allows the PHY to continue USB signaling when the voltage on
VBAT drops to 3.1V. The USB transceiver will continue to operate at lower voltages, although some
parameters may be outside the limits of the USB specifications. If the user would like to provide a 3.3V
supply to the USB3311, the VBAT and VDD33 pins should be connected together.
The USB3311 also includes integrated pull-up resistors that can be used for detecting the attachment
of a USB Charger. By sensing the attachment to a USB Charger, a product using the USB3311 can
charge its battery at more than the 500mA allowed when charging from a USB Host.
The USB3311 also includes support for USB audio modes. The user can program the PHY into UART
or audio mode while in synchronous mode.
In USB UART mode, the USB3311 DP and DM pins are redefined to enable pass-through of
asynchronous serial data. The USB3311 can only enter UART mode when the user programs the part
into this mode.
In USB audio mode, the DP pin is shorted to the SPKR_R/M pin with a switch. The DM pin is shorted
to the SPKR_L pin. These switches are on when the RESETB pin of the USB3311 is asserted. Audio
signals may be transferred over the USB cable. In addition to audio signals, the switches can also be
used to connect Full Speed USB from another PHY onto the USB cable.
Hi-Speed USB Transceiver with 1.8V ULPI Interface - 26MHz Reference Clock
SMSC USB3311 REV C5 Revision 2.1 (06-10-10)
PRODUCT PREVIEW
USB3311 Pin Locations and Descriptions
Package Diagram with Pin Locations
The pinout below is viewed from the top of the package.
Figure 1.1 USB3311 QFN Pinout - Top View
Figure 2 USB3311 VFBGA Pinout - Top View
VBUS
ID
VDD3.3
DM
DP
NXT
DIR
STP
DATA0
DATA2
DATA3
DATA1
RBIAS
VDD1.8
REFCLK
DATA4
DATA6
DATA7
DATA5
RESETB
VBAT
SPKR_L
SPKR_R/M
CLKOUT
1
2
3
4
5
6
7
8
9
10
11
12
18
17
16
15
14
13
24
23
22
21
20
19
24Pin QFN
4x4mm
A
E
D
C
B
15432
TOP VIEW
Hi-Speed USB Transceiver with 1.8V ULPI Interface - 26MHz Reference Clock
Revision 2.1 (06-10-10) 6 SMSC USB3311 REV C
PRODUCT PREVIEW
Pin Definitions
The following table details the pin definitions for the figure above.
Table 1 USB3311 Pin Description
PIN/
BALL NAME
DIRECTION/
TYPE
ACTIVE
LEVEL DESCRIPTION
1
B1
ID Input,
Analog
N/A ID pin of the USB cable. For non-OTG
applications this pin can be floated. For
an A-Device ID is grounded. For a B-
Device ID is floated.
2
C1
VBUS I/O,
Analog
N/A VBUS pin of the USB cable. This pin is
used for the Vbus comparator inputs and
for Vbus pulsing during session request
protocol.
3
C2
VBAT Power N/A Regulator input. The regulator supply can
be from 5.5V to 3.1V.
4
D2
VDD3.3 Power N/A 3.3V Regulator Output. A 2.2uF (<1 ohm
ESR) bypass capacitor to ground is
required for regulator stability. The
bypass capacitor should be placed as
close as possible to the USB3311.
5
D1
DM I/O,
Analog
N/A D- pin of the USB cable.
6
E1
DP I/O,
Analog
N/A D+ pin of the USB cable.
7
E2
SPKR_R/M I/O,
Analog
N/A USB switch in/out for DP signals
8
E3
SPKR_L I/O,
Analog
N/A USB switch in/out for DM signals
9
D3
DATA[7] I/O,
CMOS
N/A ULPI bi-directional data bus. DATA[7] is
the MSB.
10
E4
DATA[6] I/O,
CMOS
N/A ULPI bi-directional data bus.
11
D4
DATA[5] I/O,
CMOS
N/A ULPI bi-directional data bus.
12
E5
DATA[4] I/O,
CMOS
N/A ULPI bi-directional data bus.
13
D5
CLKOUT Output,
CMOS
N/A 60MHz reference clock output. All ULPI
signals are driven synchronous to the
rising edge of this clock.
The system must not drive voltage on the
CLKOUT pin following POR or hardware
reset that exceeds the value of VIH_ED.
14
C4
DATA[3] I/O,
CMOS
N/A ULPI bi-directional data bus.
Hi-Speed USB Transceiver with 1.8V ULPI Interface - 26MHz Reference Clock
SMSC USB3311 REV C7 Revision 2.1 (06-10-10)
PRODUCT PREVIEW
15
C5
DATA[2] I/O,
CMOS
N/A ULPI bi-directional data bus.
16
B4
DATA[1] I/O,
CMOS
N/A ULPI bi-directional data bus.
17
B5
DATA[0] I/O,
CMOS
N/A ULPI bi-directional data bus. DATA[0] is
the LSB.
18
A5
NXT Output,
CMOS
High The PHY asserts NXT to throttle the data.
When the Link is sending data to the
PHY, NXT indicates when the current
byte has been accepted by the PHY. The
Link places the next byte on the data bus
in the following clock cycle.
19
A4
DIR Output,
CMOS
N/A Controls the direction of the data bus.
When the PHY has data to transfer to the
Link, it drives DIR high to take ownership
of the bus. When the PHY has no data to
transfer it drives DIR low and monitors
the bus for commands from the Link.
20
A3
STP Input,
CMOS
High The Link asserts STP for one clock cycle
to stop the data stream currently on the
bus. If the Link is sending data to the
PHY, STP indicates the last byte of data
was on the bus in the previous cycle.
21
B3
VDD1.8 Power N/A External 1.8V Supply input pin. This pad
needs to be bypassed with a 0.1uF
capacitor to ground, placed as close as
possible to the USB3311.
22
B2
RESETB Input,
CMOS,
Low When low, the part is suspended with all
of the I/O tri-stated. When high the
USB3311 will operate as a normal ULPI
device.
23
A2
REFCLK Input,
CMOS
N/A 26MHz Reference Clock input.
24
A1
RBIAS Analog,
CMOS
N/A Bias Resistor pin. This pin requires an
8.06kΩ (±1%) resistor to ground, placed
as close as possible to the USB3311.
FLAG
C3
GND Ground N/A Ground.
QFN only: The flag should be connected
to the ground plane with a via array
under the exposed flag. This is the main
ground for the IC.
Table 1 USB3311 Pin Description (continued)
PIN/
BALL NAME
DIRECTION/
TYPE
ACTIVE
LEVEL DESCRIPTION
Hi-Speed USB Transceiver with 1.8V ULPI Interface - 26MHz Reference Clock
Revision 2.1 (06-10-10) 8 SMSC USB3311 REV C
PRODUCT PREVIEW
Application Diagrams
Figure 3 USB3311 BGA Application Diagram (Device)
Link Controller
USB331X
RBIAS
DIR
NXT
STP
CLKOUT
DATA7
DATA6
DATA5
DATA4
DATA3
DATA2
DATA0
DATA1
VBAT
VDD3.3
VBUS
DM
DP
ID
RESETB
SPKR_L
SPKR_R/M
USB
Receptacle
DM
DP
DIR
NXT
STP
CLKOUT
DATA7
DATA6
DATA5
DATA4
DATA3
DATA2
DATA0
DATA1
RESETB
D3
E4
E1
D1
D4
E5
C4
C5
B4
B5
A3
A5
A4
D5
B2
A1
GND
2
3
VBUS 1
SHIELD
GND
E2
E3
D2
C2
C1
B1
Optional
Switched Signal
to DP/DM
C
BYP
C
VBUS
3.1-5.5V
Supply
RVBUS may be installed in this configuration to
assist in protecting the VBUS pin. 820 Ohms
will protect against VBUS transients up to
8.5V. 10K Ohms will protect against
transients up to 10V.
REFCLK
VDD18 B3
1.8V Supply
Reference
COUT
CBYP
CDC_BLOCK
8.06k
Steady state voltage at the VBUS pin must not be
allowed to exceed VVMAX.
R
VBUS
NC
A2
C3
The capacitor CVBUS must be
installed on this side of RVBUS.
Signal at REFCLK
must comply with
VIH and VIL
Hi-Speed USB Transceiver with 1.8V ULPI Interface - 26MHz Reference Clock
SMSC USB3311 REV C9 Revision 2.1 (06-10-10)
PRODUCT PREVIEW
Figure 3.1 USB3311 QFN Application Diagram (Host or OTG)
Link Controller
USB331X
RBIAS
DIR
NXT
STP
CLKOUT
DATA7
DATA6
DATA5
DATA4
DATA3
DATA2
DATA0
DATA1
VBUS
DM
DP
ID
RESETB
SPKR_L
SPKR_R/M
USB
Receptacle
DM
DP
DIR
NXT
STP
CLKOUT
DATA7
DATA6
DATA5
DATA4
DATA3
DATA2
DATA0
DATA1
RESETB
9
10
6
5
11
12
14
15
16
17
20
18
19
13
22
24
GND FLAG
2
3
VBUS 1
7
8
2
1
Optional
Switched Signal
to DP/DM
CVBUS
VBUS Switch
OUT
EN
IN
ID 4
CPEN
5V
REFCLK
VDD18 21
1.8V Supply
Reference
CBYP
8.06k
Signal at REFCLK
must comply with
VIH and VIL
Voltage at the VBUS pin must not be allowed
to exceed VVMAX.
23
The capacitor CVBUS must be
installed on this side of RVBUS.
R
VBUS may be installed in this
configuration to assist in protecting
the VBUS pin. 820 Ohms will
protect against VBUS transients up
to 8.5V.
R
VBUS
VBAT
VDD3.3
4
3
C
OUT
CBYP
3.1 - 5.5V
Supply
GND
SHIELD
Hi-Speed USB Transceiver with 1.8V ULPI Interface - 26MHz Reference Clock
Revision 2.1 (06-10-10) 10 SMSC USB3311 REV C
PRODUCT PREVIEW
Figure 4 USB3311 BGA Application Diagram (Host or OTG)
Link Controller
USB331X
RBIAS
DIR
NXT
STP
CLKOUT
DATA7
DATA6
DATA5
DATA4
DATA3
DATA2
DATA0
DATA1
VBUS
DM
DP
ID
RESETB
SPKR_L
SPKR_R/M
USB
Receptacle
DM
DP
DIR
NXT
STP
CLKOUT
DATA7
DATA6
DATA5
DATA4
DATA3
DATA2
DATA0
DATA1
RESETB
A1
2
3
VBUS 1
C1
Optional
Switched Signal
to DP/DM
CVBUS
VBUS Switch
OUT
EN
IN
ID 4
CPEN
5V
REFCLK
VDD18 B3
1.8V Supply
Reference
CBYP
8.06k
Signal at REFCLK
must comply with
VIH and VIL
Voltage at the VBUS pin must not be allowed
to exceed VVMAX.
The capacitor CVBUS must be
installed on this side of RVBUS.
RVBUS may be installed in this
configuration to assist in protecting
the VBUS pin. 820 Ohms will
protect against VBUS transients up
to 8.5V.
RVBUS
VBAT
VDD3.3
D2
C2
COUT
CBYP
3.1 - 5.5V
Supply
GND
SHIELD
E1
D1
E2
E3
B1
D3
E4
D4
E5
C4
C5
B4
B5
A3
A5
A4
D5
B2
A2
GND
C3
Hi-Speed USB Transceiver with 1.8V ULPI Interface - 26MHz Reference Clock
Revision 2.1 (06-10-10) 11 SMSC USB3311 REV C
PRODUCT PREVIEW
Package Outline
Figure 4.1 24-pin QFN, 4x4mm Body, 0.5mm Pitch
SMSC USB3311 REV C12 Revision 2.1 (06-10-10)
PRODUCT PREVIEW
Hi-Speed USB Transceiver with 1.8V ULPI Interface - 26MHz Reference Clock
Figure 5 25-Pin VFBGA, 3x3mm Body, 0.5mm Pitch
