Description
The A1190, A1192, and A1193 comprise a family of two-
wire, unipolar, Hall-effect switches, which can be trimmed
by the user at end-of-line to optimize magnetic switchpoint
accuracy in the application. These devices are produced on
the Allegro® advanced BiCMOS wafer fabrication process,
which implements a patented high frequency, 4-phase,
chopper-stabilization technique. This technique achieves
magnetic stability over the full operating temperature range,
and eliminates offsets inherent in devices with a single Hall
element that are exposed to harsh application environments.
The A119x family has a number of automotive applications.
These include sensing seat track position, seat belt buckle
presence, hood/trunk latching, and shift selector position.
Two-wire unipolar switches are particularly advantageous in
cost-sensitive applications because they require one less wire
for operation versus the more traditional open-collector output
switches. Additionally, the system designer inherently gains
diagnostics because there is always output current flowing,
which should be in either of two narrow ranges. Any current
level not within these ranges indicates a fault condition.
All family members are offered in two package styles. The LH
is a SOT-23W style, miniature, low profile package for surface-
mount applications. The UA is a 3-pin, ultra-mini, single inline
package (SIP) for through-hole mounting. Both packages are
lead (Pb) free, with 100% matte tin leadframe plating.
A1190-DS, Rev. 3
Features and Benefits
High speed, 4-phase chopper stabilization
Low switchpoint drift throughout temperature range
Low sensitivity to thermal and mechanical stresses
On-chip protection
Supply transient protection
Reverse battery protection
On-board voltage regulator
3.0 to 24 V operation
Solid-state reliability
Robust EMC and ESD performance
Field programmable for optimized switchpoints
Industry leading ISO 7637-2 performance through use of
proprietary, 40-V clamping structure
Programmable, Chopper-Stabilized, T wo Wire Hall-Effect Switches
Functional Block Diagram
A1190, A1192 and A1193
Amp
Regula
To all subcircuits
tor
Schmitt
Trigger
Polarity
Low-Pass
Filter
GND
VCC
Program
/
Lock ICC Adjust
Offset Adjust
GND
UA package only
0.01 F
V+
Clock/Logic
Dynamic Offset
Cancellation
Sample and Hold
Packages
Approximate footprint
3-pin SOT23-W
2 mm × 3 mm × 1 mm
(suffix LH)
3-pin ultramini SIP
1.5 mm × 4 mm × 3 mm
(suffix UA)
Programmable, Chopper-Stabilized,
T wo Wire Hall-Ef fect Switches
A1190, A1192,
and A1193
2
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
NC
1
2
3
1
3
2
Pin-out Diagrams
LH Package UA Package
Absolute Maximum Ratings
Characteristic Symbol Notes Rating Unit
Forward Supply Voltage VCC 28 V
Reverse Supply Voltage VRCC –18 V
Magnetic Flux Density B Unlimited G
Operating Ambient Temperature TARange L –40 to 150 ºC
Maximum Junction Temperature TJ(max) 165 ºC
Storage Temperature Tstg –65 to 170 ºC
Selection Guide
Part Number Package Packing1
Output (ICC) in
South Polarity
Field
Supply Current
at I
CC(L)
(mA)
Magnetic Operate
Point, BOP
(G)
A1190LLHLT-T2LH (Surface mount) 7-in. reel, 3000 pieces/reel
Low 2 to 5
10 to 200
A1190LLHLX-T LH (Surface mount) 13-in. reel, 10 000 pieces/reel
A1190LUA-T3UA (Through hole) Bulk, 500 pieces/bag
A1192LLHLT-T2LH (Surface mount) 7-in. reel, 3000 pieces/reel
Low
5 to 6.9
A1192LLHLX-T LH (Surface mount) 13-in. reel, 10 000 pieces/reel
A1192LUA-T3UA (Through hole) Bulk, 500 pieces/bag
A1193LLHLT-T2LH (Surface mount) 7-in. reel, 3000 pieces/reel
HighA1193LLHLX-T LH (Surface mount) 13-in. reel, 10 000 pieces/reel
A1193LUA-T3UA (Through hole) Bulk, 500 pieces/bag
1Contact Allegro® for additional packing options.
2These variants available only through authorized distributors.
3Contact factory for availability.
Terminal List Table
Number Name Function
LH package UA package
1 VCC VCC
Connects power supply to chip;
used to apply programming
signal
2 NC GND LH package: no connection
UA package: ground terminal
3 GND GND Ground terminal
ELECTRICAL CHARACTERISTICS Valid at TA = –40°C to 150°C, TJ < TJ(max), CBYP = 0.01 F, through operating supply voltage
range; unless otherwise noted
Characteristics Symbol Test Conditions Min. Typ. Max. Unit
Supply Voltage1,2 VCC Operating, TJ 165 °C 3.0 – 24 V
Supply Current
ICC(L)
A1190 B > BOP 2.0 – 5.0 mA
A1192 B > BOP 5 – 6.9 mA
A1193 B < BRP 5 – 6.9 mA
ICC(H)
A1190, A1192 B < BRP 12 – 17 mA
A1193 B > BOP 12 – 17 mA
Supply Zener Clamp Voltage VZ(sup) ICC = ICC(L)(max) + 3 mA, TA = 25°C 28 – – V
Supply Zener Clamp Current IZ(sup) VZ(sup) = 28 V – – ICC(L)(max)
+ 3 mA mA
Reverse Supply Current IRCC VRCC = –18 V – – –1.6 mA
Output Slew Rate3di/dt No bypass capacitor, capacitance of probe
CS = 20 pF –90–mA / s
Chopping Frequency fC– 700 – kHz
Power-Up Time2,4,5 ton
A1190, A1192 CBYP = 0.01 F, B > BOP + 10 G – – 25 s
A1193 CBYP = 0.01 F, B < BRP – 10 G – – 25 s
Power-Up State6,7 POS ton < ton(max) , VCC slew rate > 25 mV / s–I
CC(H) ––
1VCC represents the generated voltage between the VCC pin and the GND pin.
2The VCC slew rate must exceed 600 mV/ms from 0 to 3 V. A slower slew rate through this range can affect device performance.
3Measured without bypass capacitor between VCC pin and the GND pin. Use of a bypass capacitor results in slower current change.
4Power-Up Time is measured without and with a bypass capacitor of 0.01 F. Adding a larger bypass capacitor would cause longer Power-Up Time.
5Guaranteed by characterization and design.
6Power-Up State as defined is true only with a VCC slew rate of 25 mV / s or greater.
7For t > ton and BRP < B < BOP , Power-Up State is not defined.
MAGNETIC CHARACTERISTICS1 Valid at TA = –40°C to 150°C, TJ TJ (max); unless otherwise noted
Characteristics Symbol Test Conditions Min. Typ. Max. Unit2
Initial Operate Point BOP(init) – –14 10 G
Programmable Magnetic
Operating Point BOP TA = 25°C 10 – 200 G
Average Magnetic Step Size3STEPBOP TA = 25°C, VCC = 5 V 3 4.8 7.5 G
Switchpoint Temperature Drift ΔBOP – ±20 – G
Hysteresis BHYS 5 – 30 G
1Relative values of B use the algebraic convention, where positive values indicate south magnetic polarity, and negative values indicate north
magnetic polarity; therefore greater B values indicate a stronger south polarity field (or a weaker north polarity field, if present).
21 G (gauss) = 0.1 mT (millitesla).
3STEPBOP is a calculated average from the cumulative programmed bits.
PROGRAMMABLE PARAMETERS
Name Functional Description Quantity
of Bits
BOP Trim Fine trim of Programmable Magnetic Operating Point 6
Programming Lock Lock access to programming 1
Programmable, Chopper-Stabilized,
T wo Wire Hall-Ef fect Switches
A1190, A1192,
and A1193
3
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
6
7
8
9
2
3
4
5
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
20 40 60 80 100 120 140 160 180
Temperature (ºC)
Maximum Allowable V
CC
(V)
Power Derating Curve
(R
QJA
= 228 ºC/W)
4-layer PCB, Package LH
(R
QJA
= 110 ºC/W)
2-layer PCB, Package LH
(R
QJA
= 165 ºC/W)
1-layer PCB, Package UA
VCC(min)
VCC(max)
0
100
200
300
400
500
600
700
800
900
1000
1100
1200
1300
1400
1500
1600
1700
1800
1900
20 40 60 80 100 120 140 160 180
Temperature (°C)
Power Dissipation, P
D
(mW)
Power Dissipation versus Ambient Temperature
(R
QJA
= 165 ºC/W)
1-layer PCB, Package UA
(RQJA = 228 ºC/W)
4-layer PCB, Package LH
(RQJA = 110 ºC/W)
2-layer PCB, Package LH
Thermal Characteristics may require derating at maximum conditions, see application information
Characteristic Symbol Test Conditions* Value Unit
Package Thermal Resistance RJA
Package LH, on 4-layer PCB based on JEDEC standard 228 ºC/W
Package LH, on 2-layer PCB with 0.463 in.2 of copper area each side 110 ºC/W
Package UA, on 1-layer PCB with copper limited to solder pads 165 ºC/W
*Additional thermal information available on the Allegro website
Programmable, Chopper-Stabilized,
T wo Wire Hall-Ef fect Switches
A1190, A1192,
and A1193
4
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Characteristic Performance
VCC = 3.0 V
VCC = 24 V
-60 -40 -20 0 20 40 60 80 100 140120 160
Ambient Temperature, TA (°C)
Supply Current, ICC(H) (mA)
17
16
15
14
13
12
Average Supply Current (High) versus Temperature
A1190/A1192/A1193
VCC = 3.0 V
VCC = 24 V
7.0
6.5
6.0
5.5
5.0
-60 -40 -20 0 20 40 60 80 100 140120 160
Ambient Temperature, TA (°C)
Supply Current, ICC(L) (mA)
VCC = 3.0 V
VCC = 24 V
5.0
4.5
4.0
3.5
3.0
2.5
2.0
5.0
4.5
4.0
3.5
3.0
2.5
2.0
-60 -40 -20 0 20 40 60 80 100 140120 160
Ambient Temperature, TA (°C)
Supply Current, ICC(L) (mA)
Average Supply Current (Low) versus Temperature
A1192 and A1193
Average Supply Current (Low) versus Temperature
A1190
Supply Voltage, VCC (V)
Supply Current, ICC(H) (mA)
17
16
15
14
13
12
2 6 10 14 18 22 26
TA = 150°C
TA = –40°C
TA = 25°C
Average Supply Current (High) versus Supply Voltage
A1190/A1192/A1193
TA = 150°C
TA = –40°C
TA = 25°C
7.0
6.5
6.0
5.5
5.0
2 6 10 14 18 22 26
Supply Voltage, VCC (V)
Supply Current, ICC(L) (mA)
TA = 150°C
TA = –40°C
TA = 25°C
2 6 10 14 18 22 26
Supply Voltage, VCC (V)
Supply Current, ICC(L) (mA)
Average Supply Current (Low) versus Supply Voltage
A1192 and A1193
Average Supply Current (Low) versus Supply Voltage
A1190
Programmable, Chopper-Stabilized,
T wo Wire Hall-Ef fect Switches
A1190, A1192,
and A1193
5
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
VCC = 3.0 V
VCC = 24 V
Ambient Temperature, TA (°C)
-60 -40 -20 0 20 40 60 80 100 140120 160
30
25
20
15
10
5
Applied Flux Density at
Switchpoint Hysteresis, BHYS (G)
Ambient Temperature, TA (°C)
-60 -40 -20 0 20 40 60 80 100 140120 160
Bit #5
Bit #4
Bit #3
Bit #2
Bit #1
Bit #0
160
140
120
100
80
60
40
20
0
-20
Average Operate Point, BOP (G)
Code
0 4 8 12 16 20 24 28 32 36
BOP(init)
Average Switchpoint Hysteresis versus Temperature
Average Operate Point versus Code
A1190/A1192/A1193
A1190/A1192/A1193
Programmable, Chopper-Stabilized,
T wo Wire Hall-Ef fect Switches
A1190, A1192,
and A1193
6
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Functional Description
B
OP
B
RP
B
HYS
I
CC(H)
I
CC
I
CC(L)
Switch to Low
Switch to High
B+
B–
I+
0
(A) Hysteresis curve for A1190 and A1192
B
OP
B
RP
B
HYS
I
CC(H)
I
CC
I
CC(L)
Switch to High
Switch to Low
B+
I+
B–
0
(B) Hysteresis curve for A1193
Figure 1. Alternative switching behaviors are available in the A119x device family. On the horizontal axis, the B+ direction indicates
increasing south polarity magnetic field strength, and the B– direction indicates decreasing south polarity field strength (including the
case of increasing north polarity).
The A1190 and A1192 output, ICC, switches low after the mag-
netic field at the Hall sensor IC exceeds the operate point thresh-
old, BOP
. When the magnetic field is reduced to below the release
point threshold, BRP
, the device output goes high. This is shown
in figure 1, panel A.
In the case of the reverse output polarity, as in the A1193, the
device output switches high after the magnetic field at the Hall
sensor IC exceeds the operate point threshold, BOP
. When the
magnetic field is reduced to below the release point threshold,
BRP, the device output goes low (panel B).
The difference between the magnetic operate and release points
is called the hysteresis of the device, BHYS
. This built-in hyster-
esis allows clean switching of the output even in the presence of
external mechanical vibration and electrical noise.
Programmable, Chopper-Stabilized,
T wo Wire Hall-Ef fect Switches
A1190, A1192,
and A1193
7
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Figure 2. Typical application circuits
GND
A119x
VCC
V+
0.01 F
A
GND
ECU Package UA Only
A
RSENSE
CBYP
GND
A119x
VCC
V+
0.01 F
A
GND
RSENSE
CBYP
(A) Low side sensing (B) High side sensing
Figure 3. Chopper stabilization circuit (Dynamic Quadrature Offset Cancellation)
Amp
Regulator
Clock/Logic
Hall Element
Sample and
Hold
Low-Pass
Filter
Chopper Stabilization Technique
When using Hall-effect technology, a limiting factor for
switchpoint accuracy is the small signal voltage developed
across the Hall element. This voltage is disproportionally small
relative to the offset that can be produced at the output of the
Hall sensor IC. This makes it difficult to process the signal while
maintaining an accurate, reliable output over the specified oper-
ating temperature and voltage ranges. Chopper stabilization is
a unique approach used to minimize Hall offset on the chip. The
patented Allegro technique, namely Dynamic Quadrature Offset
Cancellation, removes key sources of the output drift induced by
thermal and mechanical stresses. This offset reduction technique
is based on a signal modulation-demodulation process. The
undesired offset signal is separated from the magnetic field-
induced signal in the frequency domain, through modulation.
The subsequent demodulation acts as a modulation process for
the offset, causing the magnetic field-induced signal to recover
its original spectrum at base band, while the DC offset becomes
a high-frequency signal. The magnetic-sourced signal then can
pass through a low-pass filter, while the modulated DC offset is
suppressed. The chopper stabilization technique uses a 350 kHz
high frequency clock. For demodulation process, a sample and
hold technique is used, where the sampling is performed at twice
the chopper frequency. This high-frequency operation allows
a greater sampling rate, which results in higher accuracy and
faster signal-processing capability. This approach desensitizes
the chip to the effects of thermal and mechanical stresses, and
produces devices that have extremely stable quiescent Hall out-
put voltages and precise recoverability after temperature cycling.
This technique is made possible through the use of a BiCMOS
process, which allows the use of low-offset, low-noise amplifiers
in combination with high-density logic integration and sample-
and-hold circuits.
Programmable, Chopper-Stabilized,
T wo Wire Hall-Ef fect Switches
A1190, A1192,
and A1193
8
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Programming Guidelines
Overview
Programming is accomplished by sending a series of input volt-
age pulses serially through the VCC (supply) pin of the device.
A unique combination of different voltage level pulses controls
the internal programming logic of the device to select a desired
programmable parameter and change its value. There are three
voltage levels that must be taken into account when program-
ming. These levels are referred to as high (VPH), mid (V
PM), and
low (VPL) (see figure 1 and table 1).
The A119x family features two programmable modes, Try mode
and Blow mode.
• In Try mode, programmable parameter values are set and mea-
sured. A parameter value is stored temporarily, and reset after
cycling the supply voltage.
• In Blow mode, the value of a programmable parameter may
be permanently set by blowing solid-state fuses internal to the
device. Device locking is also accomplished in this mode.
The programming sequence is designed to help prevent the
device from being programmed accidentally; for example, as a
result of noise on the supply line. Although any programmable
variable power supply can be used to generate the pulse wave-
forms, Allegro highly recommends using the Allegro Sensor IC
Evaluation Kit, available on the Allegro website On-line Store.
The manual for that kit is available for download free of charge,
and provides additional information on programming these
devices.
Definition of Terms
Register. The section of the programming logic that controls the
choice of programmable modes and parameters.
Bit Field. The internal fuses unique to each register, represented
as a binary number. Changing the bit field selection in a particu-
lar register causes its programmable parameter to change, based
on the internal programming logic.
Key. A series of VPM voltage pulses used to select a register or mode.
Table 1. Programming Pulse Requirements, Protocol at TA = 25°C (refer also to figure 4)
Characteristic Symbol Notes Min. Typ. Max. Unit
Programming Voltage
VPL
Measured at the VCC pin.
4.5 5 5.5 V
VP M 12.5 – 14 V
VPH 21 – 27 V
Programming Current IPP
tPr = 11 s, VCC = 5 → 26 V, CBLOW = 0.1 F (min). Minimum supply current
required to ensure proper fuse blowing. CBLOW must be connected between the
VCC and GND pins during programming to provide the current necessary for fuse
blowing.
175 – – mA
Pulse Width
tLOW Duration at VPL separating pulses at VPM or VPH.20––s
tACTIVE Duration of pulses at VPM or VPH for key/code selection. 20 – – s
tBLOW Duration of pulse at VPH for fuse blowing. 90 100 – s
Pulse Rise Time tPr VPL to VPM , or VPL to VPH. 5 – 100 s
Pulse Fall Time tPf V
PH to VPL , or VPM to VPL. 5 – 100 s
Blow Pulse Slew Rate SRBLOW 375 – – mV/ s
Supply Voltage, VCC
0
(Supply
cycled)
Programming
pulses
Blow
pulse
tACTIVE
tLOW
tLOW
tBLOW
tPr
tPf
VPH
VPM
VPL
Figure 4. Programming pulse definition (see table 1)
Programmable, Chopper-Stabilized,
T wo Wire Hall-Ef fect Switches
A1190, A1192,
and A1193
9
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Programmable, Chopper-Stabilized,
T wo Wire Hall-Ef fect Switches
A1190, A1192,
and A1193
10
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Table 2. Programming Logic Table
Register Bit Field Address (Code)
Description
Key Name Binary Format
[MSB → LSB]
Decimal
Equivalent
Try Mode
0B
OP Trim Up Counting 000000 0
Initial value (below minimum |BOP
| ) (Try mode sequence
starts with code 1); Code corresponds to bit field value (code
1 selects bit field value 000001)
111111 63 Maximum selectable value (above maximum |BOP
| )
1B
OP Trim Down Counting 111111 0
Initial value (above maximum |BOP
| ) (Try mode sequence
starts with code 1); Code is automatically inverted (code 1
selects bit field value 111110)
000000 63 Minimum selectable value (below minimum |BOP
|)
7 Fuse Check 000111 7 Check integrity of all fuse bits versus low threshold
001111 15 Check integrity of all fuse bits versus high threshold
Blow Mode
0B
OP Trim
000000 0 Initial value (below minimum |BOP
| ); (Only allows selection
of 1 bit per sequence)
111111 63 Maximum selectable value (above maximum |BOP
| ); (Only
allows selection of 1 bit per sequence)
7 Programming Lock 001000 8 Locks out access to all registers except Fuse Check
Code. The number used to identify the combination of fuses
activated in a bit field, expressed as the decimal equivalent of the
binary value. The LSB of a bit field is denoted as code 1, or bit 0.
Addressing. Setting the bit field code in a selected register by
serially applying a pulse train through the VCC pin of the device.
Each parameter can be measured during the addressing process,
but the internal fuses must be blown before the programming
code (and parameter value) becomes permanent.
Fuse Blowing. Applying a VPH pulse of sufficient duration to
permanently set an addressed bit by blowing a fuse internal to the
device. Once a bit (fuse) has been blown, it cannot be reset.
Blow Pulse. A VPH pulse of sufficient duration to blow the
addressed fuse.
Cycling the Supply. Powering-down, and then powering-up the
supply voltage. Cycling the supply is used to clear the program-
ming settings in Try mode.
Programming Procedure
Programming involves selection of a register, a mode, and then
setting values for parameters in the register for evaluation or for
fuse blowing. Figure 10 provides an overview state diagram.
Register Selection Each programmable parameter can be
accessed through a specific register. To select a register, a
sequence of voltage pulses consisting of a VPH pulse, a series of
VPM pulses, and a VPH pulse (with no VCC supply interruptions)
must be applied serially to the VCC pin. The quantity of VPM
pulses is called the key, and uniquely identifies each register. The
pulses for selection of register key 1, is shown in figure 5. No
V
PM pulse is sent for key 0. The register selections are shown in
table 2.
Mode Selection After register selection, the mode is selected,
either Try or Blow mode. Try mode is selected by default. To
select Blow mode, that mode selection key must be sent.
Programmable, Chopper-Stabilized,
T wo Wire Hall-Ef fect Switches
A1190, A1192,
and A1193
11
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Try Mode In Try mode, bit field addressing is accomplished by
applying a series of VPM pulses to the VCC pin of the device, as
shown in figure 6. Each pulse increases the bit field value for the
selected parameter, increasing by one on the falling edge of each
additional VPM pulse. When addressing the bit field in Try mode,
the quantity of VPM pulses is represented by a decimal number
called the code. Addressing activates the corresponding fuse
locations in the given bit field by increasing the binary value of
an internal DAC, up to the maximum possible code. As the value
of the bit field code increases, the value of the programmable
parameter changes. Measurements can be taken after each VPM
pulse to determine if the required result for the programmable
parameter has been reached. Cycling the supply voltage resets
all the locations in the bit field that have un-blown fuses to their
initial states.
When setting the BOP Trim parameter, as an aid to programming,
values can be traversed from low to high, or from high to low. To
accommodate this direction selection, the value of the bit field
(and code) defaults to the value 1, on the falling edge of the final
register selection VPH pulse (see figure 5). A complete example is
provided in figure 11.
Blow Mode After the required code is determined for a given
parameter, its value can be set permanently by blowing individual
fuses in the appropriate register bit field. Blowing is accom-
plished by selecting the register, then the Blow mode selection
key, followed by the appropriate bit field address, and ending
the sequence with the Blow pulse. The Blow mode selection key
is a sequence of nine VPM pulses followed by one VPH pulse. A
complete example is provided in figure 12.
The Blow pulse consists of a VPH pulse of sufficient duration,
tBLOW , to permanently set an addressed bit by blowing a fuse
internal to the device. Due to power requirements, the fuse for
each bit in the bit field must be blown individually. The A119x
family built-in circuitry allows only one fuse at a time to be
blown. During Blow mode, the bit field can be considered a “one-
hot” shift register. Table 3 relates the quantity of VPM pulses to
the binary and decimal values for Blow mode bit field address-
ing. It should be noted that the simple relationship between the
quantity of VPM pulses and the corresponding code is:
2n = Code,
where n is the quantity of VPM pulses. The bit field has an initial
state of decimal code 0 (binary 000000).
Figure 6. Try mode bit field addressing pulses
Figure 7. Example of code 5 broken into its binary components
Supply Voltage, V
CC
0
V
PH
V
PM
V
PL
Code 2
Code 3
Code 2n – 2
Code 2n – 1
Table 3. Blow Mode Bit Field Addressing
Quantity of
VPM Pulses
Binary Register
Setting Equivalent Code
1 000001 1
2 000010 2
3 000100 4
4 001000 8
5 010000 16
6 100000 32
(Decimal Equivalent)
Code 5
Bit Field Selection
Address Code Format
Code in Binary
Fuse Blowing
Target Bits
Fuse Blowing
Address Code Format
(Binary)
1 0 1
Bit 2 Bit 0
Code 4 Code 1
(Decimal Equivalents)
Supply Voltage, V
CC
0
Key
V
PH
V
PM
V
PL
Figure 5. Register selection pulse sequence
Programmable, Chopper-Stabilized,
T wo Wire Hall-Ef fect Switches
A1190, A1192,
and A1193
12
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
To correctly address the fuses to be blown, the code represent-
ing the required parameter value must be translated into a binary
number. For example, as shown in figure 7, decimal code 5 is
equivalent to the binary number 101. Therefore bit 2 must be
addressed and blown, the device power supply cycled, and then
bit 0 must be addressed and blown. The order of blowing bits,
however, is not important. Blowing bit 0 first, and then bit 2 is
acceptable.
Note: After blowing, the programming is not reversible, even
after cycling the supply power. Although a register bit field fuse
cannot be reset after it is blown, additional bits within the same
register can be blown at any time until the device is locked. For
example, if bit 1 (binary 10) has been blown, it is still possible to
blow bit 0. The end result would be binary 11 (decimal code 3).
Locking the Device
After the required code for each parameter is programmed, the
device can be locked to prevent further programming of any
parameters. To do so, perform the following steps:
1. Ensure that the CBLOW capacitor is mounted.
2. Select the Programming Lock register (key 7).
3. Select Blow mode (key 9).
4. Address bit 3 (001000) by sending four VPM pulses.
5. Send one Blow pulse, at IPP and SRBLOW, and sustain it for
tBLOW.
6. Delay for a tLOW interval, then power-down.
7. Optionally check all fuses.
Fuse Checking
Incorporated in the A119x family is circuitry to simultaneously
check the integrity of the fuse bits. The fuse checking feature is
enabled by using the Fuse Check register (selection key 7), and
while in Try mode, applying the codes shown in table 2. The
register is only valid in Try mode and is available before or after
the Programming Lock bit is set.
Setting the fuse threshold high checks that all blown fuses are
properly blown. Setting fuse threshold low checks all un-blown
fuses are properly intact. The supply current increases by 250 A
if a marginal fuse is detected. If all fuses are correctly blown or
fully intact, there will be no change in supply current.
Additional Guidelines
The additional guidelines in this section should be followed to
ensure the proper behavior of these devices:
• A 0.1 F blowing capacitor, CBLOW, must be mounted between
the VCC pin and the GND pin during programming, to ensure
enough current is available to blow fuses.
• The power supply used for programming must be capable of
delivering at least VPH and 175 mA.
• Be careful to observe the tLOW delay time before powering
down the device after blowing each bit.
• Lock the device (only after all other parameters have been pro-
grammed and validated) to prevent any further programming of
the device.
BOP Selection
Selecting BOP should be done in two stages. First, Try mode
should be used to adjust BOP and monitor the output state. Then
the optimum BOP is set permanently using Blow mode.
Use the BOP Trim Up Counting register to increase the BOP selec-
tion by one Magnetic Step Size, StepBOP , increment with each
bit field pulse (see figure 8). Use the BOP Trim Down Counting
register to decrease the BOP selection by one StepBOP with each
bit field pulse (see figure 9). As an aid to programming, when
using down-counting method, the A119x automatically inverts
the bit field selection (code 0 in down-counting sets the bit field
value 111111, and the actual bit field value decreases until code
63 sets bit field value 000000).
Note that the release point, BRP , is a value below BOP . The
difference is specified by the Hysteresis, BHYS , which is not
programmable.
Programmable, Chopper-Stabilized,
T wo Wire Hall-Ef fect Switches
A1190, A1192,
and A1193
13
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Figure 8. BOP Selection Up Counting Figure 9. BOP Selection Down Counting
|BOP(max)|
|BOP(min)|
|BOP(max)|
|BOP(min)|
Try Mode, Bit Field Code
03163
BOP
BRP
BHYS
(Code 0,
Bit value 111111 )
BOP
BRP
BHYS
(Code 63,
Bit value 000000)
Try Mode, Bit Field Code
03163
BOP
BRP
BHYS
(Code 0,
Bit value 000000 )
BOP
BRP
BHYS
(Code 63,
Bit value 111111 )
Programmable, Chopper-Stabilized,
T wo Wire Hall-Ef fect Switches
A1190, A1192,
and A1193
14
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Figure 10. Programming state diagram
Figure 11. Example of Try mode pulse sequence, Register Key = BOP selection down counting
Figure 12. Example of Blow mode pulse sequence, Register Key = BOP selection bit field 2 (code 4)
Power Derating
Programmable, Chopper-Stabilized,
T wo Wire Hall-Ef fect Switches
A1190, A1192,
and A1193
15
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
The device must be operated below the maximum junction tem-
perature of the device, TJ(max). Under certain combinations of
peak conditions, reliable operation may require derating supplied
power or improving the heat dissipation properties of the appli-
cation. This section presents a procedure for correlating factors
affecting operating TJ. (Thermal data is also available on the
Allegro MicroSystems Web site.)
The Package Thermal Resistance, RJA, is a figure of merit sum-
marizing the ability of the application and the device to dissipate
heat from the junction (die), through all paths to the ambient air.
Its primary component is the Effective Thermal Conductivity, K,
of the printed circuit board, including adjacent devices and traces.
Radiation from the die through the device case, RJC, is relatively
small component of RJA. Ambient air temperature, TA, and air
motion are significant external factors, damped by overmolding.
The effect of varying power levels (Power Dissipation, PD), can
be estimated. The following formulas represent the fundamental
relationships used to estimate TJ, at PD.
PD = VIN × IIN (1)
T = PD × RJA (2)
TJ = TA + T (3)
For example, given common conditions such as: TA= 25°C,
VCC = 12 V, ICC = 4 mA, and RJA = 140 °C/W, then:
P
D = VCC × ICC = 12 V × 4 mA = 48 mW
T = PD × RJA = 48 mW × 140 °C/W = 7°C
T
J = TA + T = 25°C + 7°C = 32°C
A worst-case estimate, PD(max), represents the maximum allow-
able power level (VCC(max), ICC(max)), without exceeding
TJ(max), at a selected RJA and TA.
Example: Reliability for VCC at TA =
150°C, package UA, using a
low-K PCB.
Observe the worst-case ratings for the device, specifically:
RJA
=
165 °C/W, TJ(max) =
165°C, VCC(max)
= 24 V, and
ICC(max) = 17 mA.
Calculate the maximum allowable power level, PD(max). First,
invert equation 3:
Tmax = TJ(max) – TA = 165
°C
–
150
°C = 15
°C
This provides the allowable increase to TJ resulting from internal
power dissipation. Then, invert equation 2:
PD(max) = Tmax ÷ RJA = 15°C ÷ 165 °C/W = 91 mW
Finally, invert equation 1 with respect to voltage:
VCC(est) = PD(max) ÷ ICC(max) = 91 mW ÷ 17 mA = 5 V
The result indicates that, at TA, the application and device can
dissipate adequate amounts of heat at voltages VCC(est).
Compare VCC(est) to VCC(max). If VCC(est) VCC(max), then reli-
able operation between VCC(est) and VCC(max) requires enhanced
RJA. If VCC(est) VCC(max), then operation between VCC(est)
and VCC(max) is reliable under these conditions.
Programmable, Chopper-Stabilized,
T wo Wire Hall-Ef fect Switches
A1190, A1192,
and A1193
16
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Package LH, 3-Pin SOT23W
0.55 REF
Gauge Plane
Seating Plane
0.25 BSC
0.95 BSC
0.95
1.00
0.70 2.40
2
1
AActive Area Depth, 0.28 mm REF
B
C
C
B
Reference land pattern layout
All pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary
to meet application process requirements and PCB layout tolerances
Branding scale and appearance at supplier discretion
A
PCB Layout Reference View
Standard Branding Reference View
1
Branded Face
N = Last two digits of device part number
T = Temperature code
NNT
2.90 +0.10
–0.20
4°±4°
8X 10° REF
0.180+0.020
–0.053
0.05 +0.10
–0.05
0.25 MIN
1.91 +0.19
–0.06
2.98 +0.12
–0.08
1.00 ±0.13
0.40 ±0.10
For Reference Only; not for tooling use (reference DWG-2840)
Dimensions in millimeters
Dimensions exclusive of mold flash, gate burrs, and dambar protrusions
Exact case and lead configuration at supplier discretion within limits shown
DHall element, not to scale
D
D
D
1.49
0.96
3
Programmable, Chopper-Stabilized,
T wo Wire Hall-Ef fect Switches
A1190, A1192,
and A1193
17
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Package UA, 3-Pin SIP
231
1.27 NOM
1.02
MAX
45°
45°
C
1.52 ±0.05
B
Gate and tie bar burr area
A
B
C
Dambar removal protrusion (6X)
A
D
E
D
E
E
1.44 NOM
2.05 NOM
E
Active Area Depth, 0.50 mm REF
Branding scale and appearance at supplier discretion
Hall element (not to scale)
For Reference Only; not for tooling use (reference DWG-9065)
Dimensions in millimeters
Dimensions exclusive of mold flash, gate burrs, and dambar protrusions
Exact case and lead configuration at supplier discretion within limits shown
Standard Branding Reference View
NNN
1
Mold Ejector
Pin Indent
= Supplier emblem
N = Last three digits of device part number
0.41 +0.03
–0.06
0.43 +0.05
–0.07
14.99 ±0.25
4.09 +0.08
–0.05
3.02 +0.08
–0.05
0.79 REF
10°
Branded
Face
Programmable, Chopper-Stabilized,
T wo Wire Hall-Ef fect Switches
A1190, A1192,
and A1193
18
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
For the latest version of this document, visit our website:
www.allegromicro.com
Copyright ©2009-2011, Allegro MicroSystems, Inc.
Allegro MicroSystems, Inc. reserves the right to make, from time to time, such de par tures from the detail spec i fi ca tions as may be required to per-
mit improvements in the per for mance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the
information being relied upon is current.
Allegro’s products are not to be used in life support devices or systems, if a failure of an Allegro product can reasonably be expected to cause the
failure of that life support device or system, or to affect the safety or effectiveness of that device or system.
The in for ma tion in clud ed herein is believed to be ac cu rate and reliable. How ev er, Allegro MicroSystems, Inc. assumes no re spon si bil i ty for its use;
nor for any in fringe ment of patents or other rights of third parties which may result from its use.
Revision History
Revision Revision Date Description of Revision
Rev. 3 November 17, 2011 Update product selection and VCC
, ton
, tBLOW,
and programming lock
