LM5046 Phase-Shifted Full-Bridge PWM Controller with Integrated MOSFET Drivers General Description Features The LM5046 PWM controller contains all of the features necessary to implement a Phase-Shifted Full-Bridge topology power converter using either current mode or voltage mode control. This device is intended to operate on the primary side of an isolated dc-dc converter with input voltage up to 100V. This highly integrated controller-driver provides dual 2A high and low side gate drivers for the four external bridge MOSFETs, plus control signals for the secondary side synchronous rectifier MOSFETs. External resistors program the dead-time to enable zero-volt switching of the primary FETs. Intelligent startup of the synchronous rectifiers allows monotonic turn-on of the power converter even with pre-bias load conditions. Additional features include cycle-by-cycle current limiting, hiccup mode restart, programmable soft-start, synchronous rectifier soft-start and a 2 MHz capable oscillator with synchronization capability and thermal shutdown. Highest Integration Controller for Small Form Factor, High Density Power Converters High Voltage Start-up Regulator Intelligent Sync Rectifier Start-up Allows Linear Turn-on into Pre-biased Loads Synchronous Rectifiers Disabled in UVLO mode and Hiccup Mode Two Independent, Programmable Dead-Time Adjustments to Enable Zero-Volt Switching. Four High Current 2A Bridge Gate Drivers Wide-Bandwidth Opto-coupler Interface Configurable for either Current Mode or Voltage Mode Control Dual-mode Over-Current Protection Resistor Programmed 2MHz Oscillator Programmable Line UVLO and OVP Packages eTSSOP-28 LLP-28 (5mm x 5mm) Simplified Phase-Shifted Full-Bridge Power Converter 30147801 (c) 2012 Texas Instruments Incorporated 301478 SNVS703F www.ti.com LM5046 Phase-Shifted Full-Bridge PWM Controller with Integrated MOSFET Drivers January 17, 2012 LM5046 Connection Diagrams Top View 30147802 TSSOP28 www.ti.com 2 LM5046 Top View 30147803 LLP-28 Package Ordering Information Order Number Package Type NSC Package Drawing Supplied As LM5046MH eTSSOP-28 MXA28A Rail of 48 Units LM5046MHX eTSSOP-28 MXA28A Tape and Reel of 2500 Units LM5046SQ LLP-28 SQA28A Tape and Reel of 1000 Units LM5046SQX LLP-28 SQA28A Tape and Reel of 4500 Units 3 www.ti.com LM5046 Pin Descriptions TSSOP Pin LLP Pin Name 1 25 UVLO 2 26 3 27 RAMP 4 28 CS 5 1 6 Description Application Information Line Under-Voltage Lockout An external voltage divider from the power source sets the shutdown and standby comparator levels. When UVLO reaches the 0.4V threshold the VCC and REF regulators are enabled. At the 1.25V threshold, the SS pin is released and the controller enters the active mode. Hysteresis is set by an internal current sink that pulls 20A from the external resistor divider. OVP/OTP Over Voltage Protection An external voltage divider from the input power supply sets the shutdown level during an over-voltage condition. Alternatively, an external NTC thermistor voltage divider can be used to set the shutdown temperature. The threshold is 1.25V. Hysteresis is set by an internal current that sources 20 A of current into the external resistor divider. Input to PWM Comparator Modulation ramp for the PWM comparator. This ramp can be a signal representative of the primary current (current mode) or proportional to the input voltage (feed-forward voltage mode). This pin is reset to GND at the end of every cycle. Current Sense Input If CS exceeds 750mV the PWM output pulse will be terminated, entering cycle-by-cycle current limit. An internal switch holds CS low for 40nS after either output switches high to blank leading edge transients. SLOPE Slope Compensation Current A ramping current source from 0 to 100A is provided for slope compensation in current mode control. This pin can be connected through an appropriate resistor to the CS pin to provide slope compensation. If slope compensation is not required, SLOPE must be tied to ground. 2 COMP Input to the Pulse Width Modulator An external opto-coupler connected to the COMP pin sources current into an internal NPN current mirror. The PWM duty cycle is at maximum with zero input current, while 1mA reduces the duty cycle to zero. The current mirror improves the frequency response by reducing the AC voltage across the opto-coupler. 7 3 REF 8 4 Output of a 5V reference Maximum output current is 15mA. Locally decouple with a 0.1F capacitor. RT/SYNC Oscillator Frequency Control and The resistance connected between RT and AGND sets the Frequency Synchronization oscillator frequency. Synchronization is achieved by AC coupling a pulse to the RT/SYNC pin that raises the voltage at least 1.5V above the 2V nominal bias level. 9 5 AGND Analog Ground Connect directly to the Power Ground. 10 6 RD1 Passive to Active Delay The resistance connected between RD1 and AGND sets the delay from the falling edge of HO1/SR1 or LO1/SR2 and the rising edge of LO1 or HO1 respectively. 11 7 RD2 Active to Passive Delay The resistance connected between RD2 and AGND sets the delay from the falling edge of LO2 or HO2 and the rising edge of HO2 or LO2 respectively. 12 8 RES Restart Timer Whenever the CS pin exceeds the 750mV cycle-by-cycle current limit threshold, 30A current is sourced into the RES capacitor for the remainder of the PWM cycle. If the RES capacitor voltage reaches 1.0V, the SS capacitor is discharged to disable the HO1, HO2, LO1, LO2 and SR1, SR2 outputs. The SS pin is held low until the voltage on the RES capacitor has been ramped between 2V and 4V eight times by 10A charge and 5A discharge currents. After the delay sequence, the SS capacitor is released to initiate a normal start-up sequence. www.ti.com 4 LLP Pin Name 13 9 SS 14 10 SSSR 15 11 SSOFF 19 15 21 17 Description Application Information Soft-Start Input An internal 20A current source charges the SS pin during startup. The input to the PWM comparator gradually rises as the SS capacitor charges to steadily increase the PWM duty cycle. Pulling the SS pin to a voltage below 200mV stops PWM pulses at HO1,2 and LO1,2 and turns off the synchronous rectifier FETs to a low state. Secondary Side Soft-Start An external capacitor and an internal 20A current source set the soft-start ramp for the synchronous rectifiers. The SSSR capacitor charge-up is enabled after the first output pulse and SS>2V and Icomp <800A Soft-Stop Disable When SS OFF pin is connected to the AGND, the LM5046 softstops in the event of a VIN UVLO and Hiccup mode current limit condition. If the SSOFF pin is connected to REF pin, the controller hard-stops on any fault condition. Refer Table 1 for more details. SR2 Synchronous Rectifier Driver Control output for synchronous rectifier gate. Capable of peak sourcing 100mA and sinking 400mA. VCC Output of Start-Up Regulator The output voltage of the start-up regulator is initially regulated to 9.5V. Once the secondary side soft-start (SSSR pin) reaches 1V, the VCC output is reduced to 7.7V. If an auxiliary winding raises the voltage on this pin above the regulation set-point, the internal start-up regulator will shutdown, thus reducing the IC power dissipation. Power Ground Connect directly to Analog Ground 22 18 23, 20 19, 16 PGND 24 20 SR1 25, 18 21, 14 26, 17 LO1, LO2 Low Side Output Driver Alternating output of the PWM gate driver. Capable of 1.5A peak source and 2A peak sink current. Synchronous Rectifier Driver Control output for synchronous rectifier gate. Capable of peak sourcing 100mA and sinking 400mA. BST1,2 Gate Drive Bootstrap Bootstrap capacitors connected between BST1,2 and SW1,2 provide bias supply for the high side HO1,2 gate drivers. External diodes are required between VCC and BST1,2 to charge the bootstrap capacitors when SW1,2 are low. 22, 13 HO1,2 High Side Output Driver High side PWM outputs capable of driving the upper MOSFET of the bridge with 1.5A peak source and 2A peak sink current. 27, 16 23, 12 HS1,2 Switch Node Common connection of the high side FET source, low side FET drain and transformer primary winding. 28 24 VIN Input Power Source Input to the Start-up Regulator. Operating input range is 14V to 100V. For power sources outside of this range, the LM5046 can be biased directly at VCC by an external regulator. 5 www.ti.com LM5046 TSSOP Pin LM5046 Absolute Maximum Ratings (Note 1) VIN to GND HS to GND (Note 4) BST1/BST2 to GND BST1/BST2 to HS1/HS2 HO1/HO2 to HS1/HS2 (Note 2) LO1/LO2/SR1/SR2 (Note 2) VCC to GND REF,SSOFF,RT,OVP,UVLO to GND RAMP COMP -0.3V to 105V -5V to 105V -0.3V to 116V -0.3V to 16V -0.3V to BST1/ BST2+0.3V -0.3V to VCC+0.3V -0.3V to 16V -0.3V to 7V -0.3V to 7V -0.3V COMP Input Current All other inputs to GND (Note 2) ESD Rating HBM (Note 3) +10mA -0.3 to REF+0.3V 2 kV Storage Temperature Range Junction Temperature -55C to 150C 150C Operating Ratings (Note 1) VIN Voltage External Voltage Applied to VCC Junction Temperature 14V to 100V 10V to 14V -40C to +125C SLOPE -0.3V to 2V Electrical Characteristics Limits in standard typeface are for TJ = 25C only; limits in boldface type apply the junction temperature range of -40C to +125C. Unless otherwise specified, the following conditions apply: VIN = 48V, RT = 25k, RD1=RD2=20k. No load on HO1, HO2, LO1, LO2, SR1, SR2, COMP=0V, UVLO=2.5V, OVP=0V, SSOFF=0V. Symbol Parameter Conditions Min Typ Max Units V Startup Regulator (VCC pin) VCC1 VCC voltage ICC= 10mA (SSSR<1V) 9.3 9.6 9.9 VCC2 8.1 VCC voltage ICC= 10mA (SSSR>1V) 7.5 7.8 ICC(Lim) VCC current limit VCC= 6V 60 80 mA ICC(ext) VCC supply current Supply current into VCC from an externally applied source. VCC = 10V 4.6 mA VCC load regulation ICC from 0 to 50 mA 35 mV VCC under-voltage threshold Positive going VCC VCC1- 0.2 VCC1- 0.1 V VCC under-voltage threshold Negative going VCC 5.9 6.3 VCC(UV) IIN VIN operating current VIN shutdown current VIN start-up regulator leakage 6.7 4 V V mA VIN=20V, VUVLO=0V 300 520 A VVIN=100V, VUVLO=0V 350 550 A VCC=10V 160 A Voltage Reference Regulator (REF pin) VREF REF Voltage IREF = 0mA REF voltage regulation IREF = 0 to 10mA IREF(Lim) REF current limit VREF = 4.5V 15 20 VREFUV VREF under-voltage threshold Positive going VREF 4.3 4.5 4.85 Hysteresis 5 5.15 V 25 50 mV mA 4.7 0.25 V V Under-Voltage Lock Out and shutdown (UVLO pin) VUVLO Under-voltage threshold IUVLO Hysteresis current UVLO pin sinking current when VUVLO<1.25V Under-voltage standby enable threshold UVLO voltage rising 1.18 1.25 1.32 V 16 20 24 A 0.32 0.4 0.48 V Hysteresis VOVP 0.05 OVP shutdown threshold OVP rising OVP hysteresis current OVP sources current when OVP>1.25V V 1.18 1.25 1.32 V 16 20 24 A Soft-Start (SS Pin) ISS SS charge current VSS = 0V SS threshold for SSSR charge current enable ICOMP<800A SS output low voltage Sinking 100A SS threshold to disable switching www.ti.com 6 16 20 24 A 1.93 2.0 2.20 V 40 mV 200 mV ISSSR Parameter Conditions Min Typ Max Units SSSR charge current VSS>2V, ICOMP<800A 16 20 24 A ISSSR-DIS1 SSSR discharge current 1 VUVLO<1.25V 54 65 75 A ISSSR-DIS2 SSSR discharge current 2 VRES>1V 109 125 147 SSSR output low voltage Sinking 100A SSSR threshold to enable SR1/SR2 A 50 mV 1.2 V Current Sense Input (CS Pin) VCS RCS Current limit threshold 0.710 0.750 CS delay to output 65 CS leading edge blanking 50 CS sink impedance (clocked) Internal FET sink impedance 18 0.785 V ns ns 45 Soft-Stop Disable (SS OFF Pin) VIH(min) SSOFF Input Threshold 2.8 V SSOFF pull down resistance 200 k 37 Current Limit Restart (RES Pin) RRES RES pull-down resistance Termination of hiccup timer VRES RES hiccup threshold 1 V RES upper counter threshold 4 V 2 V IRES-SRC1 RES lower counter threshold Charge current source 1 VRES<1V,VCS>750mV 30 A IRES-SRC2 Charge current source 2 1V<VRES<4V 10 A IRES-DIS2 Discharge current source 1 VCS<750mV 5 A IRES-DIS2 Discharge current source 2 2V<VRES<4V 5 A Ratio of time in hiccup mode to time VRES>1V, Hiccup counter in current limit 147 Voltage Feed-Forward (RAMP Pin) RAMP sink impedance (Clocked) 5.5 20 Oscillator (RT Pin) FSW1 Frequency (LO1, half oscillator frequency) RT = 25 k 185 200 215 kHz FSW2 Frequency (LO1, half oscillator frequency) RT = 10 k 420 480 540 kHz DC level 2.0 RT sync threshold V 2.8 3 3.3 V RD1=20 k 39 65 89 ns RD1=100 k 230 300 391 ns RD2=20 k 27 55 78 ns RD2=100 k 214 300 378 ns ZVS Timing Control (RD1 & RD2 Pins) TPA HO1/SR1 turn-off to LO1 turn-on LO1/SR2 turn-off to HO1 turn-on TAP LO2 turn-off to HO2 turn-on HO2 turn-off to LO2 turn-on 7 www.ti.com LM5046 Symbol LM5046 Symbol Parameter Conditions Min Typ Max Units VPWM-OS COMP current to RAMP offset VRAMP=0V 680 800 940 A VSS-OS SS to RAMP offset VRAMP=0V 0.78 1.0 1.22 COMP current to RAMP gain RAMP/ICOMP SS to RAMP gain SS/RAMP COMP current for SSSR charge current enable VSS > 2V Comp Pin 0.5 690 COMP to output delay Minimum duty cycle V 2400 800 915 120 ICOMP = 1mA A ns 0 % Slope Compensation (SLOPE Pin) ISLOPE Slope compensation current ramp Peak of RAMP current 100 A BOOST (BST Pin) VBst uv BST under-voltage threshold VBST-VHS rising Hysteresis 3.8 4.7 5.6 0.5 V V HO1, HO2, LO1, LO2 Gate Drivers VOL Low-state output voltage IHO/LO = 100mA 0.16 0.32 V VOH High-state output voltage IHO/LO = 100mA VOHL = VCC-VLO VOHH = VBST-VHO 0.27 0.495 V Rise Time C-load = 1000pF 16 Fall Time C-load = 1000pF 11 IOHL Peak Source Current VHO/LO = 0V 1.5 - A IOLL Peak Sink Current VHO/LO = VCC 2 - A ns ns SR1, SR2 Gate Drivers VOL Low-state output voltage ISR1/SR2 = 10mA 0.05 0.10 V VOH High-state output voltage ISR1/SR2 = 10mA, VOH = VREF-VSR 0.17 0.28 V Rise Time C-load = 1000pF 60 Fall Time C-load = 1000pF 20 IOHL Peak Source Current VSR = 0V 0.1 - A IOLL Peak Sink Current VSR = VREF 0.4 - A ns ns Thermal TSD Thermal Shutdown Temp 160 Thermal Shutdown Hysteresis RJA Junction to Ambient (Note 5) RJC Junction to Case eTSSOP - 28/LLP-28 C 25 C 40 C/W 4 C/W Note 1: Absolute Maximum Ratings are limits beyond which damage to the device may occur. Operating Ratings are conditions under which operation of the device is intended to be functional. For guaranteed specifications and test conditions, see the Electrical Characteristics. Note 2: These pins are output pins and as such should not be connected to an external voltage source. The voltage range listed is the limits the internal circuitry is designed to reliably tolerate in the application circuit. Note 3: The human body model is a 100pF capacitor discharged through a 1.5k resistor into each pin. Note 4: The negative HS voltage must never be more negative than VCC-16V. For example, if VCC=12V, the negative transients at HS must not exceed -4V. Note 5: 4 layer standard thermal test board. Cu thickness of layers (2oz, 1oz, 1oz, 2oz). www.ti.com 8 LM5046 Typical Performance Characteristics Application Board Efficiency VCC vs ICC 100 36V 48V 80 72V VOUT = 3.3V 70 60 50 5 10 15 20 25 LOAD CURRENT (A) 30 30147852 30147859 VVCC and VREF vs. VVIN IIN vs. VIN 6 5 VUVLO=3V 4 I IN (V) EFFICIENCY (%) 90 3 VUVLO=1V 2 1 VUVLO=0V 0 0 20 40 60 V IN (V) 30147855 80 100 30147860 VREF vs. IREF Oscillator Frequency vs. RT 30147809 30147856 9 www.ti.com LM5046 Dead-Time TPA, TAP vs. Temperature Dead-Time TPA, TAP vs. RD1, RD2 30147865 30147866 CS Threshold vs. Temperature 30147813 www.ti.com 10 LM5046 Block Diagram 30147804 FIGURE 1. 11 www.ti.com LM5046 Functional Description Line Under-Voltage Detector The LM5046 PWM controller contains all of the features necessary to implement a Phase-Shifted Full-Bridge (PSFB) topology power converter using either current mode or voltage mode control. This device is intended to operate on the primary side of an isolated dc-dc converter with input voltage up to 100V. This highly integrated controller-driver provides dual 2A high and low side gate drivers for the four external bridge MOSFETs plus control signals for secondary side synchronous rectifiers. External resistors program the dead-time to enable Zero-Volt Switching (ZVS) of the primary FETs. Please refer to the Applications Information for details on the operation of the PSFB topology. Intelligent startup of synchronous rectifier allows turn-on of the power converter into the pre-bias loads. Cycle-by-cycle current limit protects the power components from load transients while hiccup mode protection limits average power dissipation during extended overload conditions. Additional features include programmable soft-start, soft-start of the synchronous rectifiers, and a 2 MHz capable oscillator with synchronization capability and thermal shutdown. The LM5046 contains a dual level Under-Voltage Lockout (UVLO) circuit. When the UVLO pin voltage is below 0.4V, the controller is in a low current shutdown mode. When the UVLO pin voltage is greater than 0.4V but less than 1.25V, the controller is in standby mode. In standby mode the VCC and REF bias regulators are active while the controller outputs are disabled. When the VCC and REF outputs exceed their respective under-voltage thresholds and the UVLO pin voltage is greater than 1.25V, the soft-start capacitor is released and the normal operation begins. An external set-point voltage divider from VIN to GND can be used to set the minimum operating voltage of the converter. The divider must be designed such that the voltage at the UVLO pin will be greater than 1.25V when VIN enters the desired operating range. UVLO hysteresis is accomplished with an internal 20A current sink that is switched on or off into the impedance of the set-point divider. When the UVLO threshold is exceeded, the current sink is deactivated to quickly raise the voltage at the UVLO pin. When the UVLO pin voltage falls below the 1.25V threshold, the current sink is enabled causing the voltage at the UVLO pin to quickly fall. The hysteresis of the 0.4V shutdown comparator is internally fixed at 50mV. The UVLO pin can also be used to implement various remote enable / disable functions. Turning off the converter by forcing the UVLO pin to standby condition (0.4V < UVLO < 1.25V) provides a controlled soft-stop. Refer to the Soft Stop section for more details. High-Voltage Start-Up Regulator The LM5046 contains an internal high voltage start-up regulator that allows the input pin (VIN) to be connected directly to the supply voltage over a wide range from 14V to 100V. The input can withstand transients up to 105V. When the UVLO pin potential is greater than 0.4V, the VCC regulator is enabled to charge an external capacitor connected to the VCC pin. The VCC regulator provides power to the voltage reference (REF) and the gate drivers (HO1/HO2 and LO1/ LO2). When the voltage on the VCC pin exceeds its Under Voltage (UV) threshold, the internal voltage reference (REF) reaches its regulation set point of 5V and the UVLO voltage is greater than 1.25V, the soft-start capacitor is released and normal operation begins. The regulator output at VCC is internally current limited. The value of the VCC capacitor depends on the total system design, and its start-up characteristics. The recommended range of values for the VCC capacitor is 0.47F to 10F. The internal power dissipation of the LM5046 can be reduced by powering VCC from an external supply. The output voltage of the VCC regulator is initially regulated to 9.5V. After the synchronous rectifiers are engaged (which is approximately when the output voltage in within regulation), the VCC voltage is reduced to 7.7V. In typical applications, an auxiliary transformer winding is connected through a diode to the VCC pin. This winding must raise the VCC voltage above 8V to shut off the internal start-up regulator. Powering VCC from an auxiliary winding improves efficiency while reducing the controller's power dissipation. The VCC UV circuit will still function in this mode, requiring that VCC never falls below its UV threshold during the start-up sequence. The VCC regulator series pass transistor includes a diode between VCC and VIN that should not be forward biased in normal operation. Therefore, the auxiliary VCC voltage should never exceed the VIN voltage. An external DC bias voltage can be used instead of the internal regulator by connecting the external bias voltage to both the VCC and the VIN pins. This implementation is shown in the Applications Information section. The external bias must be greater than 10V and less than the VCC maximum voltage rating of 14V. www.ti.com Over Voltage Protection An external voltage divider can be used to set either an over voltage or an over temperature protection. During an OVP condition, the SS and SSSR capacitors are discharged and all the outputs are disabled. The divider must be designed such that the voltage at the OVP pin is greater than 1.25V when over voltage/temperature condition exists. Hysteresis is accomplished with an internal 20A current source. When the OVP pin voltage exceeds 1.25V, the 20A current source is activated to quickly raise the voltage at the OVP pin. When the OVP pin voltage falls below the 1.25V threshold, the current source is deactivated causing the voltage at the OVP to quickly fall. Refer to the Applications Information section for more details. Reference The REF pin is the output of a 5V linear regulator that can be used to bias an opto-coupler transistor and external housekeeping circuits. The regulator output is internally current limited to 15mA. The REF pin needs to be locally decoupled with a ceramic capacitor, the recommended range of values are from 0.1F to 10F Oscillator, Sync Input The LM5046 oscillator frequency is set by a resistor connected between the RT pin and AGND. The RT resistor should be located very close to the device. To set a desired oscillator frequency (FOSC), the necessary value of RT resistor can be calculated from the following equation: 12 Hiccup Mode The LM5046 provides a current limit restart timer to disable the controller outputs and force a delayed restart (i.e. Hiccup mode) if a current limit condition is repeatedly sensed. The number of cycle-by-cycle current limit events required to trigger the restart is programmed by the external capacitor at the RES pin. During each PWM cycle, the LM5046 either sources or sinks current from the RES capacitor. If current limit is detected, the 5A current sink is disabled and a 30A current source is enabled. If the RES voltage reaches the 1.0V threshold, the following restart sequence occurs, as shown in Figure 2: * The SS and SSSR capacitors are fully discharged * The 30A current source is turned-off and the 10A current source is turned-on. * Once the voltage at the RES pin reaches 4.0V the 10A current source is turned-off and a 5A current sink is turned-on, ramping the voltage on the RES capacitor down to 2.0V. * Once RES capacitor reaches 2.0V, threshold, the 10A current source is turned-on again. The RES capacitor voltage is ramped between 4.0V and 2.0V eight times. * When the counter reaches eight, the RES pin voltage is pulled low and the soft-start capacitor is released to begin a soft-start sequence. The SS capacitor voltage slowly increases. When the SS voltage reaches 1.0V, the PWM comparator will produce the first narrow pulse. * If the overload condition persists after restart, cycle-bycycle current limiting will begin to increase the voltage on the RES capacitor again, repeating the hiccup mode sequence. * If the overload condition no longer exists after restart, the RES pin will be held at ground by the 5A current sink and the normal operation resumes. The hiccup mode function can be completely disabled by connecting the RES pin to the AGND pin. In this configuration the cycle-by-cycle protection will limit the maximum output current indefinitely, no hiccup restart sequences will occur. Cycle-by-Cycle Current Limit The CS pin is to be driven by a signal representative of the transformer's primary current. If the voltage on the CS pin exceeds 0.75V, the current sense comparator immediately terminates the PWM cycle. A small RC filter connected to the CS pin and located near the controller is recommended to suppress noise. An internal 18 MOSFET discharges the external current sense filter capacitor at the conclusion of every cycle. The discharge MOSFET remains on for an additional 40ns after the start of a new PWM cycle to blank leading edge spikes. The current sense comparator is very fast and may respond to short duration noise pulses. Layout is critical for the current sense filter and the sense resistor. The capacitor associated with CS filter must be placed very close to the device and connected directly to the CS and AGND pins. If a current sense transformer is used, both the leads of the transformer secondary should be routed to the filter network, which should be located close to the IC. When designing with a current sense resistor, all of the noise sensitive low power ground connections should be connected together near the AGND pin, and a single connection should be made to the power ground (sense resistor ground point). 30147816 FIGURE 2. Hiccup Mode Delay and Soft-Start Timing Diagram 13 www.ti.com LM5046 For example, if the desired oscillator frequency is 400 kHz i.e. each phase (LO1 or LO2) at 200 kHz, the value of RT will be 25k. If the LM5046 is to be synchronized to an external clock, that signal must be coupled into the RT pin through a 100pF capacitor. The RT pin voltage is nominally regulated at 2.0V and the external pulse amplitude should lift the pin to between 3.5V and 5.0V on the low-to-high transition. The synchronization pulse width should be between 15 and 200ns. The RT resistor is always required, whether the oscillator is free running or externally synchronized and the SYNC frequency must be equal to, or greater than the frequency set by the RT resistor. When syncing to an external clock, it is recommended to add slope compensation by connecting an appropriate resistor from the VCC pin to the CS pin. Also disable the SLOPE pin by grounding it. LM5046 straints. Refer to the Applications Information section for more details on configuring the RAMP pin for feed-forward voltage mode control and peak current mode control. PWM Comparator The LM5046 pulse width modulator (PWM) comparator is a three input device, it compares the signal at the RAMP pin to the loop error signal or the soft-start, whichever is lower, to control the duty cycle. This comparator is optimized for speed in order to achieve minimum controllable duty cycles. The loop error signal is received from the external feedback and isolation circuit in the form of a control current into the COMP pin. The COMP pin current is internally mirrored by a matching pair of NPN transistors which sink current through a 5k resistor connected to the 5V reference. The resulting control voltage passes through a 1V offset, followed by a 2:1 resistor divider before being applied to the PWM comparator. An opto-coupler detector can be connected between the REF pin and the COMP pin. Because the COMP pin is controlled by a current input, the potential difference across the optocoupler detector is nearly constant. The bandwidth limiting phase delay which is normally introduced by the significant capacitance of the opto-coupler is thereby greatly reduced. Higher loop bandwidths can be realized since the bandwidth limiting pole associated with the opto-coupler is now at a much higher frequency. The PWM comparator polarity is configured such that with no current flowing into the COMP pin, the controller produces maximum duty cycle. Slope Pin For duty cycles greater than 50% (25% for each phase), peak current mode control is subject to sub-harmonic oscillation. Sub-harmonic oscillation is normally characterized by observing alternating wide and narrow duty cycles. This can be eliminated by adding an artificial ramp, known as slope compensation, to the modulating signal at the RAMP pin. The SLOPE pin provides a current source ramping from 0 to 100A, at the frequency set by the RT resistor, for slope compensation. The ramping current source at the SLOPE pin can be utilized in a couple of different ways to add slope compensation to the RAMP signal: 1) As shown in Figure 3(a), the SLOPE and RAMP pins can be connected together through an appropriate resistor to the CS pin. This configuration will inject current sense signal plus slope compensation to the RAMP pin but CS pin will not see any slope compensation. Therefore, in this scheme slope compensation will not affect the current limit. 2) In a second configuration, as shown in Figure 3(b), the SLOPE, RAMP and CS pins can be tied together. In this configuration the ramping current source from the SLOPE pin will flow through the filter resistor and filter capacitor, therefore both the CS pin and the RAMP pin will see the current sense signal plus the slope compensation ramp. In this scheme, the current limit is compensated by the slope compensation and the current limit onset point will vary. RAMP Pin The voltage at the RAMP pin provides the modulation ramp for the PWM comparator. The PWM comparator compares the modulation ramp signal at the RAMP pin to the loop error signal to control the duty cycle. The modulation ramp signal can be implemented either as a ramp proportional to the input voltage, known as feed-forward voltage mode control, or as a ramp proportional to the primary current, known as current mode control. The RAMP pin is reset by an internal MOSFET with an RDS(ON) of 5.5 at the conclusion of each PWM cycle. The ability to configure the RAMP pin for either voltage mode or current mode allows the controller to be implemented for the optimum control method depending upon the design con- If slope compensation is not required for e.g. in feed-forward voltage mode control, the SLOPE pin must be connected to the AGND pin. When the RT pin is synched to an external clock, it is recommended to disable the SLOPE pin and add slope compensation externally by connecting an appropriate resistor from the VCC pin to the CS pin. Please refer to the Applications Information section for more details. 30147851 FIGURE 3. Slope Compensation Configuration a) Slope Compensation Configured for PWM Only (No Current Limit Slope) b) Slope Compensation Configured for PWM and Current Limit www.ti.com 14 The soft-start circuit allows the power converter to gradually reach a steady state operating point, thereby reducing the start-up stresses and current surges. When bias is supplied to the LM5046, the SS capacitor is discharged by an internal MOSFET. When the UVLO, VCC and REF pins reach their operating thresholds, the SS capacitor is released and is charged with a 20A current source. Once the SS pin voltage crosses the 1V offset, SS controls the duty cycle. The PWM comparator is a three input device; it compares the RAMP signal against the lower of the signals between the soft-start and the loop error signal. In a typical isolated application, as the secondary bias is established, the error amplifier on the secondary side soft-starts and establishes closed-loop control, steering the control away from the SS pin. One method to shutdown the regulator is to ground the SS pin. This forces the internal PWM control signal to ground, reducing the output duty cycle quickly to zero. Releasing the SS pin begins a soft-start cycle and normal operation resumes. A second shutdown method is presented in the UVLO section. Gate Driver Outputs The LM5046 provides four gate drivers: two floating high side gate drivers HO1 and HO2 and two ground referenced low side gate drivers LO1 and LO2. Each internal driver is capable of sourcing 1.5A peak and sinking 2A peak. The low-side gate drivers are powered directly by the VCC regulator. The HO1 and HO2 gate drivers are powered from a bootstrap capacitor connected between BST1/BST2 and HS1/HS2 respectively. An external diode connected between VCC (anode pin) and BST (cathode pin) provides the high side gate driver power by charging the bootstrap capacitor from VCC when the corresponding switch node (HS1/HS2 pin) is low. When the high side MOSFET is turned on, BST1 rises to a peak voltage equal to VCC + VHS1 where VHS1 is the switch node voltage. The BST and VCC capacitors should be placed close to the pins of the LM5046 to minimize voltage transients due to par- Where, TPA is the time set by the RD1 resistor and FOSC is the frequency of the oscillator. For example, if the oscillator frequency is set at 400 kHz and the TPA time set by the RD1 resistor is 60ns, the resulting DMAX will be equal to 0.488. 15 www.ti.com LM5046 asitic inductances since the peak current sourced to the MOSFET gates can exceed 1.5A. The recommended value of the BST capacitor is 0.1F or greater. A low ESR / ESL capacitor, such as a surface mount ceramic, should be used to prevent voltage droop during the HO transitions. Figure 4 illustrates the sequence of the LM5046 gate-drive outputs. Initially, the diagonal HO1 and LO2 are turned-on together during the power transfer cycle, followed by the freewheel cycle, where HO1 and HO2 are kept on. In the subsequent phase, the diagonal HO2 and LO1 are turned-on together during the power transfer cycle, followed by a freewheel cycle, where LO1 and LO2 are kept on. The power transfer mode is often called the active mode and the freewheel mode is often called as the passive mode. The deadtime between the passive mode and the active mode, TPA, is set by the RD1 resistor and the dead-time between the active mode and the passive mode, TAP, is set by the RD2 resistor. Refer to the Applications Information section for more details on the operation of the phase-shifted full-bridge topology. If the COMP pin is open circuit, the outputs will operate at maximum duty cycle. The maximum duty cycle for each phase is limited by the dead-time set by the RD1 resistor. If the RD1 resistor is set to zero then the maximum duty cycle is slightly less than 50% due to the internally fixed dead-time. The internally fixed dead-time is 30ns which does not vary with the operating frequency. The maximum duty cycle for each output can be calculated from the following equation: Soft-Start LM5046 30147821 FIGURE 4. Timing Diagram Illustrating the Sequence of Gate-Driver Outputs in the PSFB Topology rising edge of the CLK, which also disables HO1 or LO1. As shown in Figure 5, SR1 is disabled at the same instant as HO1 is disabled, and SR2 is disabled at the same instant as LO1 is disabled. The dead-times, TSROFF and TPA achieve two different things but are set by single resistor, RD1. Therefore, RD1 value should be selected such that the SR1/SR2 turnsoff before the next power transfer cycle is initiated by TPA. The SR drivers are powered by the REF regulator and each SR output is capable of sourcing 0.1A and sinking 0.4A peak. The amplitude of the SR drivers is limited to 5V. The 5V SR signals enable the LM5046 to transfer SR control across the isolation barrier either through a solid-state isolator or a pulse transformer. The actual gate sourcing and sinking currents for the synchronous MOSFETs are provided by the secondaryside bias and gate drivers. TPA and TAP can be programmed by connecting a resistor between RD1 and RD2 pins and AGND. It should be noted that while RD1 effects the maximum duty cycle, RD2 does not. The RD1 and RD2 resistors should be located very close to the device. The formula for RD1 and RD2 resistors are given below: Synchronous Rectifier Control Outputs (SR1 & SR2) Synchronous rectification (SR) of the transformer secondary provides higher efficiency, especially for low output voltage converters, compared to the diode rectification. The reduction of rectifier forward voltage drop (0.5V - 1.5V) to 10mV 200mV VDS voltage for a MOSFET significantly reduces rectification losses. In a typical application, the transformer secondary winding is center tapped, with the output power inductor in series with the center tap. The SR MOSFETs provide the ground path for the energized secondary winding and the inductor current. From Figure 5 it can be seen that when the HO1/LO2 diagonal is turned ON, power transfer is enabled from the primary. During this period, the SR1 MOSFET is enabled and the SR2 MOSFET is turned-off. The secondary winding connected to the SR2 MOSFET drain is twice the voltage of the center tap at this time. At the conclusion of the HO1/LO2 pulse, the inductor current continues to flow through the SR2 MOSFET body diode. Since the body diode causes more loss than the SR MOSFET, efficiency can be improved by minimizing the TSRON period. In the LM5046, the time TSRON is internally fixed to be 30ns. The 30ns internally fixed dead-time, along with inherent system delays due to galvanic isolation, plus the gate drive ICs, will provide sufficient margin to prevent the shoot-through current. During the freewheeling period, the inductor current flows in both the SR1 and SR2 MOSFETs, which effectively shorts the transformer secondary. The SR MOSFETs are disabled at the www.ti.com If the desired dead-time for TPA is 60ns, then the RD1 will be 20 k. 16 LM5046 30147836 FIGURE 5. Synchronous Rectifier Timing Diagram 17 www.ti.com LM5046 < 800A, the SSSR discharge is released and SSSR capacitor begins charging with a 20A current source. Once the SSSR cap crosses the internal 1V threshold, the LM5046 begins the soft-start of the synchronous FETs. The SR soft-start follows a leading edge modulation technique i.e. the leading edge of the SR pulse is soft-started as opposed trailing edge modulation of the primary FETs. As shown in the figure 6(a), SR1 and SR2 are turned-on simultaneously with a narrow pulse-width during the freewheeling cycle. At the end of the freewheel cycle i.e. at the rising edge of the internal CLK, the SR FET in-phase with the next power transfer cycle is kept on while the SR FET out of phase with it is turned-off. The inphase SR FET is kept on throughout the power transfer cycle and at the end of it, both the primary FETs and the in-phase SR FETs are turned-off together. The synchronous rectifier outputs can be disabled by grounding the SSSR pin. Soft-Start of the Synchronous Rectifiers In addition to the basic soft-start already described, the LM5046 contains a second soft-start function that gradually turns on the synchronous rectifiers to their steady-state duty cycle. This function keeps the synchronous rectifiers off during the basic soft-start allowing a linear start-up of the output voltage even into pre-biased loads. Then the SR output duty cycle is gradually increased to prevent output voltage disturbances due to the difference in the voltage drop between the body diode and the channel resistance of the synchronous MOSFETs. Initially, when bias is supplied to the LM5046, the SSSR capacitor is discharged by an internal MOSFET. When the SS capacitor reaches a 2V threshold and once it is established that COMP is in control of the duty cycle i.e. ICOMP 30147832 FIGURE 6. (a) Waveforms during Soft-Start (b) Waveforms after Soft-Start sures the output voltage is in regulation avoiding any reverse current when the synchronous MOSFETs are engaged. Pre-Bias Startup A common requirement for power converters is to have a monotonic output voltage start-up into a pre-biased load i.e. a pre-charged output capacitor. In a pre-biased load condition, if the synchronous rectifiers are engaged prematurely they will sink current from the pre-charged output capacitors resulting in an undesired output voltage dip. This condition is undesirable and could potentially damage the power converter. The LM5046 utilizes unique control circuitry to ensure intelligent turn-on of the synchronous rectifiers such that the output has a monotonic startup. Initially, the SSSR capacitor is held at ground to disable the synchronous MOSFETs allowing the body diode to conduct. The synchronous rectifier soft-start is initiated once it is established the duty cycle is controlled by the COMP instead of the soft-start capacitor i.e. ICOMP < 800A and the voltage at the SS pin>2V. The SSSR capacitor is then released and is charged by a 20A current source. Further, as shown in Figure 7, a 1V offset on the SSSR pin is used to provide additional delay. This delay en- www.ti.com Soft-Stop As shown in Figure 8, if the UVLO pin voltage falls below the 1.25V standby threshold, but above the 0.4V shutdown threshold, the SSSR capacitor is soft-stopped with a 60A current source (3 times the charging current). Once the SSSR pin reaches the 1.0V threshold, both the SS and SSSR pins are immediately discharged to GND. Soft-stopping the power converter gradually winds down the energy in the output capacitors and results in a monotonic decay of the output voltage. During the hiccup mode, the same sequence is executed except that the SSSR is discharged with a 120A current source (6 times the charging current). In case of an OVP, VCC UV, thermal limit or a VREF UV condition, the power converter hard-stops, whereby all of the control outputs are driven to a low state immediately. 18 LM5046 30147833 FIGURE 7. Pre-Bias Voltage Startup Waveforms pin is pulled up to the 5V REF pin, the power converter hardstops in any fault condition. Hard-stop drives each control output to a low state immediately. Refer to Table 1 for more details. Soft-Stop Off The Soft-Start Off (SSOFF) pin gives additional flexibility by allowing the power converter to be configured for hard-stop during line UVLO and hiccup mode condition. If the SS OFF 30147834 FIGURE 8. Stop-Stop Waveforms during a UVLO Event 19 www.ti.com LM5046 Table 1: Soft-Stop in Fault Conditions Fault Condition SSSR UVLO (UVLO<1.25V) Soft-Stop 3x the charging rate OVP (OVP>1.25V) Hard-Stop Hiccup (CS>0.75 and RES>1V) Soft-Stop 6x the charging rate VCC/VREF UV Hard-Stop Internal Thermal Limit Hard-Stop Thermal Protection Internal thermal shutdown circuitry is provided to protect the integrated circuit in the event the maximum rated junction temperature is exceeded. When activated, typically at 160C, the controller is forced into a shutdown state with the output drivers, the bias regulators (VCC and REF) disabled. This helps to prevent catastrophic failures from accidental device overheating. During thermal shutdown, the SS and SSSR capacitors are fully discharged and the controller follows a normal start-up sequence after the junction temperature falls to the operating level (140 C). Applications Information Note: All the above conditions are valid with SSOFF pin tied to GND. If SSOFF=5V, the LM5046 hard-stops in all the conditions. The SS pin remains high in all the conditions until the SSSR pin reaches 1V. 30147862 FIGURE 9. Operating States of the PSFB Topology to the primary of the power transformer, which is typically stepped down on the secondary winding. Operating State 2 (Active to Passive Transition) At the end of the power transfer cycle, PWM turns off switch LO2. In the primary side, the reflected load current plus the magnetizing current propels the SW2 node towards VIN. The active to passive transition is finished when either the body diode of HO2 is forward-biased or HO2 is turned-on, whichever happens earlier. A delay can be introduced by setting RD2 to an appropriate value, such that HO2 is turned-on only after the body-diode is forward biased. In this mode, the Imag +ILpeak act as a current source charging the parasitic capacitor located at the node SW2. At light load conditions, it takes a longer time to propel SW node towards VIN. The active to passive transition time can be approximated by using the following formula: PHASE-SHIFTED FULL-BRIDGE OPERATION The phase shifted full-bridge topology is a derivative of the conventional full-bridge topology. When tuned appropriately the PSFB topology achieves zero voltage switching (ZVS) of the primary FETs while maintaining constant switching frequency. The ZVS feature is highly desirable as it reduces both the switching losses and the EMI emissions. The realization of the PSFB topology using the LM5046 is explained as follows: Operating State 1 (Power Transfer/Active Mode) The power transfer mode of the PSFB topology is similar to the hard switching full-bridge i.e. When the FETs in the diagonal of the bridge are turned-on (HO1 & LO2 or HO2 & LO1), a power transfer cycle from the primary to the secondary is initiated. Figure 9 depicts the case where the diagonal switches HO1 and LO2 are activated. In this state, full VIN is applied www.ti.com 20 Where, Im is the magnetizing current, NTR is the power transformer's turns ratio, ILpeak is the peak output filter inductor current and Cparasitic is the parasitic capacitance at the node SW2. Operating State 3 (Freewheel/Passive Mode) In the freewheel mode, unlike the conventional full-bridge topology where all the four primary FETs are off, in the PSFB topology the primary of the power transformer is shorted by activating either both the top FETs (HO1 and HO2) or both of the bottom FETs (LO1 and LO2) alternatively. In the current CLK cycle, the top FETs HO1 and HO2 are kept on together. Further in this mode, on the secondary side, similar to the classic full-bridge topology the synchronous FETs are both activated. During this state there is no energy transfer from the primary and the filter inductor current in the secondary freewheels through both the synchronous FETs. Operating State 4 (Passive to Active Transition) At the end of the switching cycle i.e. after the oscillator times out the current CLK cycle, the primary switch HO1 and the secondary FET SR1 are turned-off simultaneously. The voltage at the node SW1 begins to fall towards the GND. This is due to the resonance between leakage inductance of the power transformer plus any additional commutation inductor and the parasitic capacitances at SW1. The magnetizing in- When tuned appropriately either by deliberately increasing the leakage inductance or by adding an extra commutating inductor, the sinusoidal resonant waveform peaks such that it is clamped by the body-diode of the LO1 switch. At this instant, ZVS can be realized by turning on the LO1 switch. The switching sequence in this CLK cycle is as follows: activation of the switch LO1 turns the diagonal LO1 and HO2 on, resulting in power transfer. The power transfer cycle ends when PWM turns off HO2, which is followed by an active to passive transition where LO2 is turned on. In the freewheel mode, LO1 and LO2 are both activated. From this sequence, it can be inferred that the FETs on the right side of the bridge (HO2 and LO2) are always terminated by the PWM ending a power transfer cycle and the SW2 node always sees an active to passive transition. Further, the FETs on the left side of the bridge (HO1 and LO1) are always turned-off by the CLK ending a freewheel cycle and the SW1 node always sees a passive to active transition. 30147863 FIGURE 10. Simplified PSFB Topology Showing the Turn-Off Mechanism 21 www.ti.com LM5046 ductor is shorted in the freewheel mode and therefore it does not play any role in this transition. The LC resonance results in a half-wave sinusoid whose period is determined by the leakage inductor and parasitic capacitor. The peak of the halfwave sinusoid is a function of the load current. The passive to active transition time can be approximated by using the following formula: LM5046 control, a dc blocking capacitor can be placed in series with the primary winding of the power transformer to avoid any flux imbalance that may cause transformer core saturation. CONTROL METHOD SELECTION The LM5046 is a versatile PWM control IC that can be configured for either current mode control or voltage mode control. The choice of the control method usually depends upon the designer preference. The following must be taken into consideration while selecting the control method. Current mode control can inherently balance flux in both phases of the PSFB topology. The PSFB topology, like other double ended topologies, is susceptible to the transformer core saturation. Any asymmetry in the volt-second product applied between the two alternating phases results in flux imbalance that causes a dc buildup in the transformer. This continual dc buildup may eventually push the transformer into saturation. The voltsecond asymmetry can be corrected by employing current mode control. In current mode control, a signal representative of the primary current is compared against an error signal to control the duty cycle. In steady-state, this results in each phase being terminated at the same peak current by adjusting the pulse-width and thus applying equal volt-seconds to both the phases. Current mode control can be susceptible to noise and subharmonic oscillation, while voltage mode control employs a larger ramp for PWM and is usually less susceptible. Voltagemode control with input line feed-forward also has excellent line transient response. When configuring for voltage mode VOLTAGE MODE CONTROL USING THE LM5046 To configure the LM5046 for voltage mode control, an external resistor (RFF) and capacitor (C FF) connected to VIN, AGND, and the RAMP pins is required to create a saw-tooth modulation ramp signal shown in Figure 11. The slope of the signal at RAMP will vary in proportion to the input line voltage. The varying slope provides line feed-forward information necessary to improve line transient response with voltage mode control. With a constant error signal, the on-time (TON) varies inversely with the input voltage (VIN) to stabilize the VoltSecond product of the transformer primary. Using a line feedforward ramp for PWM control requires very little change in the voltage regulation loop to compensate for changes in input voltage, as compared to a fixed slope oscillator ramp. Furthermore, voltage mode control is less susceptible to noise and does not require leading edge filtering. Therefore, it is a good choice for wide input range power converters. Voltage mode control requires a Type-III compensation network, due to the complex-conjugate poles of the L-C output filter. 30147824 FIGURE 11. Feed-Forward Voltage Mode Configuration The recommended capacitor value range for CFF is from 100pF to 1800pF. Referring to Figure 11, it can be seen that CFF value must be small enough to be discharged with in the clock pulse-width which is typically within 50ns. The RDS(ON) of the internal discharge FET is 5.5. The value of RFF required can be calculated from CURRENT MODE CONTROL USING THE LM5046 The LM5046 can be configured for current mode control by applying a signal proportional to the primary current to the RAMP pin. One way to achieve this is shown in Figure 12. The primary current can be sensed using a current transformer or sense resistor, the resulting signal is filtered and applied to the RAMP pin through a resistor used for slope compensation. It can be seen that the signal applied to the RAMP pin consists of the primary current information from the CS pin plus an additional ramp for slope compensation, added by the resistor RSLOPE. The current sense resistor is selected such that during over current condition, the voltage across the current sense resistor is above the minimum CS threshold of 728mV. For example, assuming a VRAMP of 1.5V (a good compromise of signal range and noise immunity), at VINMIN of 36V (oscillator frequency of 400 kHz and CFF = 470pF results in a value for RFF of 125 k. www.ti.com 22 30147825 FIGURE 12. Current Mode Configuration the VIN pin drops below 1mA. VIN should remain at a voltage equal to or above the VCC voltage to avoid reverse current through the internal body diode of the internal VCC regulator. VIN and VCC The voltage applied to the VIN pin, which may be the same as the system voltage applied to the power transformer's primary (VPWR), can vary in the range of the 14 to 100V. It is recommended that the filter shown in Figure 13 be used to suppress the transients that may occur at the input supply. This is particularly important when VIN is operated close to the maximum operating rating of the LM5046. The current into VIN depends primarily on the LM5046's operating current, the switching frequency, and any external loads on the VCC pin, that typically include the gate capacitances of the power MOSFETs. In typical applications, an auxiliary transformer winding is connected through a diode to the VCC pin. This pin must raise VCC voltage above 8V to shut off the internal startup regulator. After the outputs are enabled and the external VCC supply voltage has begun supplying power to the IC, the current into FOR APPLICATIONS WITH > 100V INPUT For applications where the system input voltage exceeds 100V, VIN can be powered from an external start-up regulator as shown in Figure 14. In this configuration, the VIN and VCC pins should be connected together. The voltage at the VCC and VIN pins must be greater than 10V (>Max VCC reference voltage) yet not exceed 16V. To enable operation the VCC voltage must be raised above 10V. The voltage at the VCC pin must not exceed 16V. The voltage source at the right side of Figure 14 is typically derived from the power stage, and becomes active once the LM5046's outputs are active. 23 www.ti.com LM5046 Where NTR is the turns-ratio with respect to the secondary. For example, for a 3.3V output converter with a turns-ratio between primary and secondary of 9:1, an output filter inductance (LFILTER) of 800nH and a current sense resistor (RSENSE) of 150m, RSLOPE of 1.67k will suffice. In general, the amount of slope compensation required to avoid sub-harmonic oscillation is equal to at least one-half the down-slope of the output inductor current, transformed to the primary. To mitigate sub-harmonic oscillation after one switching period, the slope compensation has to be equal to one times the down slope of the filter inductor current transposed to primary. This is known as deadbeat control. The slope compensation resistor required to implement dead-beat control can be calculated as follows: LM5046 30147830 FIGURE 13. Input Transient Protection 30147837 FIGURE 14. Start-Up Regulator for VPWR>100V Where VPWR is the desired turn-on voltage and VHYS is the desired UVLO hysteresis at VPWR. For example, if the LM5046 is to be enabled when VPWR reaches 33V, and disabled when VPWR is decreased to 31V, R1 should be 100k, and R2 should be 4.2k. The voltage at the UVLO pin should not exceed 7V at any time. Two external resistors can be used to program the maximum operational voltage for the power converter as shown in Figure 16. When the OVP pin voltage rises above the 1.25V threshold, an internal 20A current source is enabled to raise the voltage at the OVP pin, thus providing threshold hysteresis. Resistance values for R1 and R2 can be determined from the following equations: UVLO AND OVP VOLTAGE DIVIDER SELECTION Two dedicated comparators connected to the UVLO and OVP pins are used to detect under voltage and over voltage conditions. The threshold values of both these comparators are set at 1.25V. The two functions can be programmed independently with two separate voltage dividers from VIN to AGND as shown in Figure 15 and Figure 16, or with a threeresistor divider as shown in Figure 17. Independent UVLO and OVP pins provide greater flexibility for the user to select the operational voltage range of the system. When the UVLO pin voltage is below 0.4V, the controller is in a low current shutdown mode. For a UVLO pin voltage greater than 0.4V but less than 1.25V the controller is in standby mode. Once the UVLO pin voltage is greater than 1.25V, the controller is fully enabled. Two external resistors can be used to program the minimum operational voltage for the power converter as shown in Figure 15. When the UVLO pin voltage falls below the 1.25V threshold, an internal 20A current sink is enabled to lower the voltage at the UVLO pin, thus providing threshold hysteresis. Resistance values for R1 and R2 can be determined from the following equations: If the LM5046 is to be disabled when VPWR-OFF reaches 80V and enabled when it is decreased to 78V. R1 should be 100k, and R2 should be 1.5 k. The voltage at the OVP pin should not exceed 7V at any time. www.ti.com 24 LM5046 30147838 FIGURE 15. Basic UVLO Configuration 30147839 FIGURE 16. Basic OVP Configuration The UVLO and OVP can also be set together using a 3 resistor divider ladder as shown in Figure 17. R1 is calculated as explained in the basic UVLO divider selection. Using the same values, as in the above two examples, for the UVLO and OVP set points, R1 and R3 remain the same at 100k and 1.5k. The R2 is 2.7k obtained by subtracting R3 from 4.2k. Remote configuration of the controller's operational modes can be accomplished with open drain device(s) connected to the UVLO pin as shown in Figure 18. Figure 19 shows an application of the OVP comparator for Remote Thermal Protection using a thermistor (or multiple thermistors) which may be located near the main heat sources of the power converter. The negative temperature coefficient (NTC) thermistor is nearly logarithmic, and in this example a 100k thermistor with the material constant of 4500 Kelvin changes to approximately 2k at 130C. Setting R1 to one-third of this resistance (665) establishes 130C as the desired trip point (for VREF = 5V). In a temperature band from 20C below to 20C above the OVP threshold, the voltage divider is nearly linear with 25mV per C sensitivity. R2 provides temperature hysteresis by raising the OVP comparator input by R2 x 20A. For example, if a 22k resistor is selected for R2, then the OVP pin voltage will increase by 22k x 20A = 506mV. The NTC temperature must therefore fall by 506mV / 25mV per C = 20C before the LM5046 switches from standby mode to the normal mode. 25 www.ti.com LM5046 30147843 FIGURE 17. UVLO/OVP Divider 30147844 FIGURE 18. Remote Standby and Disable Control 30147814 FIGURE 19. Remote Thermal Protection www.ti.com 26 30147815 FIGURE 20. Transformer Current Sense 30147822 FIGURE 21. Resistor Current Sense 27 www.ti.com LM5046 The current sense components must provide a signal > 710mV at the CS pin during an over-load event. Once the voltage on the CS pin crosses the current limit threshold, the current sense comparator terminates the PWM pulse and starts to charge the RES pin. Depending on the configuration of the RES pin, the LM5046 will eventually initiate a hiccup mode restart or be in continuous current limit. CURRENT SENSE The CS pin receives an input signal representative of its transformer's primary current, either from a current sense transformer or from a resistor located at the junction of source pin of the primary switches, as shown in Figure 20 and Figure 21, respectively. In both the cases, the filter components RF and CF should be located as close to the IC as possible, and the ground connection from the current sense transformer, or RSENSE should be a dedicated trace to the appropriate GND pin. Please refer to the layout section for more layout tips. LM5046 turned-on during the ramp up to 4V and a 5A is turned on during the ramp down to 2V. The hiccup mode off-time is given by: HICCUP MODE CURRENT LIMIT RESTART The operation of the hiccup mode restart circuit is explained in the Functional Description section. During a continuous current limit condition, the RES pin is charged with 30A current source. The restart delay time required to reach the 1.0V threshold is given by: With a CRES=0.01F, the hiccup time is 49ms. Once the hiccup time is finished, the RES pin is pulled-low and the SS pin is released allowing a soft-start sequence to commence. Once the SS pin reaches 1V, the PWM pulses will commence. The hiccup mode provides a cool-down period for the power converter in the event of a sustained overload condition thereby lowering the average input current and temperature of the power components during such an event. This establishes the number of current limit events allowed before the IC initiates a hiccup restart sequence. For example, if the CRES=0.01F, the time TCS as noted in Figure 22 below is 334s. Once the RES pin reaches 1.0V, the 30A current source is turned-off and a 10A current source is 30147816 FIGURE 22. Hiccup Mode Delay and Soft-Start Timing Diagram Generally, during the miller capacitance charge/discharge the total available driver current is lower during the turn-off process than during the turn-on process and often it is enough to speed-up the turn-off time to achieve the efficiency and thermal goals. This can be achieved simply by employing a PNP device, as shown in Figure 23, from gate to source of the power FET. During the turn-on process, when the LO1 goes high, the current is sourced through the diode D1 and the BJT Q1 provides the path for the turn-off current. Q1 should be located as close to the power FET as possible so that the turnoff current has the shortest possible path to the ground and does not have to pass through the controller. Augmenting the Gate Drive Strength The LM5046 includes powerful 2A integrated gate drivers. However, in certain high power applications (>500W), it might be necessary to augment the strength of the internal gate driver to achieve higher efficiency and better thermal performance. In high power applications, typically, the I2xR loss in the primary MOSFETs is significantly higher than the switching loss. In order to minimize the I2xR loss, either the primary MOSFETs are paralleled or MOSFETs with low RDS (on) are employed. Both these scenarios increase the total gate charge to be driven by the controller IC. An increase in the gate charge increases the FET transition time and hence increases the switching losses. Therefore, to keep the total losses within a manageable limit the transition time needs to be reduced. www.ti.com 28 LM5046 301478101 FIGURE 23. Circuit to Speed-up the Turn-off Process Depending on the gate charge characteristics of the primary FET, if it is required to speed up both the turn-on and the turnoff time, a bipolar totem pole structure as shown in Figure 24 can be used. When LO1 goes high, the gate to source current is sourced through the NPN transistor Q1 and similar to the circuit shown in Figure 23 when LO1 goes low the PNP transistor Q2 expedites the turn-off process. 301478102 FIGURE 24. Bipolar Totem Pole Arrangement Alternatively, a low side gate driver such as LM5112 can be utilized instead of the discrete totem pole. The LM5112 comes in a small package with a 3A source and a 7A sink capability. While driving the high-side FET, the HS1 acts as a local ground and the boot capacitor between the BST and HS pins acts as VCC. 29 www.ti.com LM5046 301478103 FIGURE 25. Using a Low Side Gate Driver to Augment Gate Drive Strength ductance in the PC board. The boot-strap capacitors required for the high side gate drivers should be located very close to the IC and connected directly to the BST and HS pins. The VCC and REF capacitors should also be placed close to their respective pins with short trace inductance. Low ESR and ESL ceramic capacitors are recommended for the boot-strap, VCC and the REF capacitors. The two ground pins (AGND, PGND) must be connected together directly underneath the IC with a short, direct connection, to avoid jitter due to relative ground bounce. Printed Circuit Board Layout The LM5046 current sense and PWM comparators are very fast and respond to short duration noise pulses. The components at the CS, COMP, SLOPE, RAMP, SS, SSSR, RES, UVLO, OVP, RD1, RD2, and RT pins should be physically close as possible to the IC, thereby minimizing noise pickup on the PC board trace inductance. Eliminating or minimizing via's in these critical connections are essential. Layout consideration is critical for the current sense filter. If a current sense transformer is used, both leads of the transformer secondary should be routed to the sense filter components and to the IC pins. The ground side of the transformer should be connected via a dedicated PC board trace to the AGND pin, rather than through the ground plane. If the current sense circuit employs a sense resistor in the drive transistor source, low inductance resistors should be used. In this case, all the noise sensitive, low-current ground trace should be connected in common near the IC, and then a single connection made to the power ground (sense resistor ground point). The gate drive outputs of the LM5046 should have short, direct paths to the power MOSFETs in order to minimize in- www.ti.com Application Circuit Example The following schematic shows an example of a 100W phaseshifted full-bridge converter controlled by LM5046. The operating input voltage range is 36V to 75V, and the output voltage is 3.3V. The output current capability is 30 Amps. The converter is configured for current mode control with external slope compensation. An auxiliary winding is used to raise the VCC voltage to reduce the controller power dissipation. 30 LM5046 FIGURE 26. 30147858 Evaluation Board Schematic 31 www.ti.com LM5046 Physical Dimensions inches (millimeters) unless otherwise noted Molded TSSOP-28 NS Package Number MXA28A 28-Lead LLP Package NS Package Number SQA28A www.ti.com 32 LM5046 Notes 33 www.ti.com LM5046 Phase-Shifted Full-Bridge PWM Controller with Integrated MOSFET Drivers Notes www.ti.com IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. 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