1 Ω Typical On Resistance, ±5 V, +12 V,
+5 V, and +3.3 V Quad SPST Switches
Data Sheet ADG1611/ADG1612/ADG1613
Rev. C Document Feedback
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Technical Support www.analog.com
FEATURES
1 Ω typical on resistance
0.2 Ω on resistance flatness
±3.3 V to ±8 V dual-supply operation
3.3 V to 16 V single-supply operation
No VL supply required
3 V logic-compatible inputs
Rail-to-rail operation
Continuous current per channel
LFCSP package: 280 mA
TSSOP package: 175 mA
16-lead TSSOP and 16-lead, 4 mm × 4 mm LFCSP
APPLICATIONS
Communication systems
Medical systems
Audio signal routing
Video signal routing
Automatic test equipment
Data acquisition systems
Battery-powered systems
Sample-and-hold systems
Relay replacements
GENERAL DESCRIPTION
The ADG1611/ADG1612/ADG1613 contain four independent
single-pole/single-throw (SPST) switches. The ADG1611 and
ADG1612 differ only in that the digital control logic is inverted.
The ADG1611 switches are turned on with Logic 0 on the
appropriate control input, while Logic 1 is required for the
ADG1612 switches. The ADG1613 has two switches with
digital control logic similar to that of the ADG1611; the logic is
inverted on the other two switches. Each switch conducts equally
well in both directions when on and has an input signal range that
extends to the supplies. In the off condition, signal levels up to
the supplies are blocked.
The ADG1613 exhibits break-before-make switching action for use
in multiplexer applications. Inherent in the design is the low charge
injection for minimum transients when switching the digital inputs.
The ultralow on resistance of these switches make them ideal
solutions for data acquisition and gain switching applications
where low on resistance and distortion is critical. The on resistance
profile is very flat over the full analog input range, ensuring
excellent linearity and low distortion when switching audio signals.
The CMOS construction ensures ultralow power dissipation, making
them ideally suited for portable and battery-powered instruments.
FUNCTIONAL BLOCK DIAGRAMS
IN1
IN2
IN3
IN4
S1
D1
S2
D2
S3
D3
S4
D4
ADG1611
07981-001
NOTES
1. SWITCHES SHOWN FOR A L OGIC 1 INPUT.
Figure 1.
IN1
IN2
IN3
IN4
S1
D1
S2
D2
S3
D3
S4
D4
ADG1612
07981-033
NOTES
1. SWITCHES SHOWN FOR A LOG I C 1 INPUT.
Figure 2.
NOTES
1. SWITCHES SHOWN FOR A L OGIC 1 INPUT.
IN1
IN2
IN3
IN4
S1
D1
S2
D2
S3
D3
S4
D4
ADG1613
07981-034
Figure 3.
PRODUCT HIGHLIGHTS
1. 1.6 Ω maximum on resistance over temperature.
2. Minimum distortion: THD + N = 0.007%.
3. 3 V logic-compatible digital inputs: VINH = 2.0 V, VINL = 0.8 V.
4. No VL logic power supply required.
5. Ultralow power dissipation: <16 nW.
6. 16-lead TSSOP and 16-lead, 4 mm × 4 mm LFCSP.
ADG1611/ADG1612/ADG1613 Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
General Description ......................................................................... 1
Functional Block Diagrams ............................................................... 1
Product Highlights ........................................................................... 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
±5 V Dual Supply ......................................................................... 3
12 V Single Supply ........................................................................ 4
5 V Single Supply .......................................................................... 5
3.3 V Single Supply ........................................................................6
Continuous Current per Channel, S or D ..................................7
Absolute Maximum Ratings ............................................................8
ESD Caution...................................................................................8
Pin Configurations and Function Descriptions ............................9
Typical Performance Characteristics ........................................... 10
Test Circuits ..................................................................................... 13
Terminology .................................................................................... 15
Outline Dimensions ....................................................................... 16
Ordering Guide .......................................................................... 16
REVISION HISTORY
5/15—Rev. B to Rev. C
Changed NC Pin to NIC Pin ........................................ Throughout
Updated Outline Dimensions ....................................................... 16
Changes to Ordering Guide .......................................................... 16
3/12—Rev. A to Rev. B
Changes to Figure 16 ...................................................................... 11
8/09—Rev. 0 to Rev. A
Changes to On Resistance (RON) Parameter, On Resistance Match
Between Channels (∆RON) Parameter, and On Resistance Flatness
(RFLATON) Parameter, Table 4 ............................................................ 6
Changes to Figure 7 Caption ......................................................... 10
1/09—Revision 0: Initial Version
Rev. C | Page 2 of 16
Data Sheet ADG1611/ADG1612/ADG1613
SPECIFICATIONS
±5 V DUAL SUPPLY
VDD = +5 V ± 10%, VSS = −5 V ± 10%, GND = 0 V, unless otherwise noted.
Table 1.
Parameter 25°C
−40°C to
+85°C
−40°C to
+125°C Unit Test Conditions/Comments
ANALOG SWITCH
Analog Signal Range VDD to VSS V
On Resistance (RON) 1 Ω typ VS = ±4.5 V, IS = −10 mA; see Figure 24
1.2 1.4 1.6 Ω max VDD = ±4.5 V, VSS = ±4.5 V
On Resistance Match Between Channels (∆RON) 0.04 Ω typ VS = ±4.5 V, IS = −10 mA
0.08 0.09 0.1 Ω max
On Resistance Flatness (RFL AT(O N)) 0.2 Ω typ VS = ±4.5 V, IS = −10 mA
0.25 0.29 0.34 Ω max
LEAKAGE CURRENTS VDD = +5.5 V, VSS = −5.5 V
Source Off Leakage, I
S
(Off )
±0.1
nA typ
VS = ±4.5 V, VD = ∓4.5 V; see Figure 25
±0.3 ±1 ±6 nA max
Drain Off Leakage, ID (Off ) ±0.1 nA typ VS = ±4.5 V, VD = ∓4.5 V; see Figure 25
±0.3 ±1 ±6 nA max
Channel On Leakage, ID, IS (On) ±0.2 nA typ VS = VD = ±4.5 V; see Figure 26
±0.4
±1.5
±10
nA max
DIGITAL INPUTS
Input High Voltage, VINH 2.0 V min
Input Low Voltage, VINL 0.8 V max
Input Current, IINL or IINH +0.005 ±0.1 µA typ VIN = VGND or VDD
±0.1 µA max
Digital Input Capacitance, CIN 5 pF typ
DYNAMIC CHARACTERISTICS1
tON 165 ns typ RL = 300 Ω, CL = 35 pF
212 253 285 ns max VS = 2.5 V; see Figure 31
tOFF 105 ns typ RL = 300 Ω, CL = 35 pF
137
150
159
ns max
V
S
= 2.5 V; see Figure 31
Break-Before-Make Time Delay, t
D
(ADG1613 Only)
25
ns typ
R
L
= 300 Ω, C
L
= 35 pF
20 ns min VS1 = VS2 = 2.5 V; see Figure 32
Charge Injection 140 pC typ VS = 0 V, RS = 0 Ω, CL = 1 nF; see Figure 33
Off Isolation 70 dB typ RL = 50 Ω, CL = 5 pF, f = 1 MHz;
see Figure 27
Channel-to-Channel Crosstalk 110 dB typ RL = 50 Ω, CL = 5 pF, f = 1 MHz;
see Figure 28
Total Harmonic Distortion + Noise (THD + N) 0.007 % typ RL = 110 Ω, 5 V p-p, f = 20 Hz to 20 kHz;
see Figure 30
−3 dB Bandwidth 42 MHz typ RL = 50 Ω, CL = 5 pF; see Figure 29
CS (Off ) 63 pF typ VS = 0 V, f = 1 MHz
C
D
(Off )
63
pF typ
V
S
= 0 V, f = 1 MHz
CD, CS (On) 154 pF typ VS = 0 V, f = 1 MHz
POWER REQUIREMENTS
V
DD
= +5.5 V, V
SS
= −5.5 V
IDD 0.001 µA typ Digital inputs = 0 V or VDD
1.0 µA max
VDD/VSS ±3.3/±8 V min/max
1 Guaranteed by design, not subject to production test.
Rev. C | Page 3 of 16
ADG1611/ADG1612/ADG1613 Data Sheet
12 V SINGLE SUPPLY
VDD = 12 V ± 10%, VSS = 0 V, GND = 0 V, unless otherwise noted.
Table 2.
Parameter 25°C
−40°C to
+85°C
−40°C to
+125°C Unit Test Conditions/Comments
ANALOG SWITCH
Analog Signal Range 0 V to VDD V
On Resistance (RON) 0.95 Ω typ VS = 0 V to 10 V, IS = −10 mA; see Figure 24
1.1
1.25
1.45
Ω max
V
DD
= 10.8 V, V
SS
= 0 V
On Resistance Match Between Channels (∆RON) 0.03 Ω typ VS = 0 V to 10 V, IS = −10 mA
0.06 0.7 0.08 Ω max
On Resistance Flatness (RFL AT(O N)) 0.2 Ω typ VS = 0 V to 10 V, IS = −10 mA
0.23 0.27 0.32 Ω max
LEAKAGE CURRENTS VDD = 13.2 V, VSS = 0 V
Source Off Leakage, IS (Off ) ±0.1 nA typ VS = 1 V/10 V, VS = 10 V/1 V, see Figure 25
±0.3 ±1 ±6 nA max
Drain Off Leakage, ID (Off ) ±0.1 nA typ VS = 1 V/10 V, VS = 10 V/1 V see Figure 25
±0.3 ±1 ±6 nA max
Channel On Leakage, ID, IS (On) ±0.2 nA typ VS = VD = 1 V or 10 V; see Figure 26
±0.4 ±1.5 ±10 nA max
DIGITAL INPUTS
Input High Voltage, VINH 2.0 V min
Input Low Voltage, VINL 0.8 V max
Input Current, IINL or IINH 0.001 µA typ VIN = VGND or VDD
±0.1
µA max
Digital Input Capacitance, C
IN
5
pF typ
DYNAMIC CHARACTERISTICS1
tON 125 ns typ RL = 300 Ω, CL = 35 pF
156 190 215 ns max VS = 8 V; see Figure 31
tOFF 75 ns typ RL = 300 Ω, CL = 35 pF
87 93 99 ns max VS = 8 V; see Figure 31
Break-Before-Make Time Delay, tD (ADG1613
Only)
35 ns typ RL = 300 Ω, CL = 35 pF
30
ns min
V
S1
= V
S2
= 8 V; see Figure 32
Charge Injection 170 pC typ VS = 6 V, RS = 0 Ω, CL = 1 nF; see Figure 33
Off Isolation 70 dB typ RL = 50 Ω, CL = 5 pF, f = 1 MHz; see Figure 27
Channel-to-Channel Crosstalk 110 dB typ RL = 50 Ω, CL = 5 pF, f = 1 MHz; see Figure 28
Total Harmonic Distortion + Noise 0.012 % typ RL = 110 Ω, 5 V p-p, f = 20 Hz to 20 kHz;
see Figure 30
−3 dB Bandwidth
38
MHz typ
R
L
= 50 Ω, C
L
= 5 pF; see Figure 29
CS (Off ) 60 pF typ VS = 6 V, f = 1 MHz
CD (Off ) 60 pF typ VS = 6 V, f = 1 MHz
CD, CS (On) 154 pF typ VS = 6 V, f = 1 MHz
POWER REQUIREMENTS VDD = 12 V
IDD 0.001 µA typ Digital inputs = 0 V or VDD
1 µA max
IDD 320 µA typ Digital inputs = 5 V
480 µA max
VDD 3.3/16 V min/max
1 Guaranteed by design, not subject to production test.
Rev. C | Page 4 of 16
Data Sheet ADG1611/ADG1612/ADG1613
5 V SINGLE SUPPLY
VDD = 5 V ± 10%, VSS = 0 V, GND = 0 V, unless otherwise noted.
Table 3.
Parameter 25°C
−40°C to
+85°C
−40°C to
125°C Unit Test Conditions/Comments
ANALOG SWITCH
Analog Signal Range 0 V to VDD V
On Resistance (RON) 1.7 Ω typ VS = 0 V to 4.5 V, IS = −10 mA; see Figure 24
2.15
2.4
2.7
Ω max
V
DD
= 4.5 V, V
SS
= 0 V
On Resistance Match Between Channels (∆RON) 0.05 Ω typ VS = 0 V to 4.5 V, IS = −10 mA
0.09 0.12 0.15 Ω max
On Resistance Flatness (RFL AT(O N)) 0.4 Ω typ VS = 0 V to 4.5 V, IS = −10 mA
0.53 0.55 0.6 Ω max
LEAKAGE CURRENTS VDD = 5.5 V, VSS = 0 V
Source Off Leakage, IS (Off ) ±0.05 nA typ VS = 1 V/4.5 V, VD = 4.5 V/1 V; see Figure 25
±0.3 ±1 ±6 nA max
Drain Off Leakage, ID (Off ) ±0.05 nA typ VS = 1 V/4.5 V, VD = 4.5 V/1 V; see Figure 25
±0.3 ±1 ±6 nA max
Channel On Leakage, ID, IS (On) ±0.15 nA typ VS = VD = 1 V or 4.5 V; see Figure 26
±0.4 ±1.5 ±10 nA max
DIGITAL INPUTS
Input High Voltage, VINH 2.0 V min
Input Low Voltage, VINL 0.8 V max
Input Current, IINL or IINH 0.001 µA typ VIN = VGND or VDD
±0.1
µA max
Digital Input Capacitance, C
IN
5
pF typ
DYNAMIC CHARACTERISTICS1
tON 215 ns typ RL = 300 Ω, CL = 35 pF
279 334 376 ns max VS = 2.5 V; see Figure 31
tOFF 115 ns typ RL = 300 Ω, CL = 35 pF
150 169 180 ns max VS = 2.5 V; see Figure 31
Break-Before-Make Time Delay, tD (ADG1613 Only) 35 ns typ RL = 300 Ω, CL = 35 pF
25 ns min VS1 = VS2 = 2.5 V; see Figure 32
Charge Injection
80
pC typ
V
S
= 0 V, R
S
= 0 Ω, C
L
= 1 nF; see Figure 33
Off Isolation 70 dB typ RL = 50 Ω, CL = 5 pF, f = 100 kHz;
see Figure 27
Channel-to-Channel Crosstalk 110 dB typ RL = 50 Ω, CL = 5 pF, f = 100 kHz;
see Figure 28
Total Harmonic Distortion + Noise 0.093 % typ RL = 110 Ω, f = 20 Hz to 20 kHz,
VS = 3.5 V p-p; see Figure 30
−3 dB Bandwidth 42 MHz typ RL = 50 Ω, CL = 5 pF; see Figure 29
CS (Off ) 72 pF typ VS = 2.5 V, f = 1 MHz
CD (Off ) 72 pF typ VS = 2.5 V, f = 1 MHz
CD, CS (On) 160 pF typ VS = 2.5 V, f = 1 MHz
POWER REQUIREMENTS VDD = 5.5 V
IDD 0.001 µA typ Digital inputs = 0 V or VDD
1 µA max
V
DD
3.3/16
V min/max
1 Guaranteed by design, not subject to production test.
Rev. C | Page 5 of 16
ADG1611/ADG1612/ADG1613 Data Sheet
3.3 V SINGLE SUPPLY
VDD = 3.3 V, VSS = 0 V, GND = 0 V, unless otherwise noted.
Table 4.
Parameter 25°C
−40°C to
+85°C
−40°C to
+125°C Unit Test Conditions/Comments
ANALOG SWITCH
Analog Signal Range 0 V to VDD V
On Resistance (RON) 3.2 3.4 3.6 Ω typ VS = 0 V to VDD, IS = −10 mA, VDD = 3.3 V,
VSS = 0 V; see Figure 24
On Resistance Match Between Channels (∆RON) 0.06 0.07 0.08 Ω typ VS = 0 V to VDD, IS = −10 mA
On Resistance Flatness (RFL AT(O N)) 1.2 1.3 1.4 Ω typ VS = 0 V to VDD, IS = −10 mA
LEAKAGE CURRENTS VDD = 3.6 V, VSS = 0 V
Source Off Leakage, IS (Off ) ±0.02 nA typ VS = 0.6 V/3 V, VD = 3 V/0.6 V; see Figure 25
±0.3 ±1 ±6 nA max
Drain Off Leakage, ID (Off ) ±0.02 nA typ VS = 0.6 V/3 V, VD = 3 V/0.6 V; see Figure 25
±0.3 ±1 ±6 nA max
Channel On Leakage, ID, IS (On) ±0.1 nA typ VS = VD = 0.6 V or 3 V; see Figure 26
±0.4 ±1.5 ±10 nA max
DIGITAL INPUTS
Input High Voltage, V
INH
2.0
V min
Input Low Voltage, VINL 0.8 V max
Input Current, IINL or IINH 0.001 µA typ VIN = VGND or VDD
±0.1 µA max
Digital Input Capacitance, CIN 3 pF typ
DYNAMIC CHARACTERISTICS1
tON 350 ns typ RL = 300 Ω, CL = 35 pF
493 556 603 ns max VS = 1.5 V; see Figure 31
tOFF 190 ns typ RL = 300 Ω, CL = 35 pF
263
286
300
ns max
V
S
= 1.5 V; see Figure 31
Break-Before-Make Time Delay, tD (ADG1613 Only) 25 ns typ RL = 300 Ω, CL = 35 pF
18 ns min VS1 = VS2 = 1.5 V; see Figure 32
Charge Injection 50 pC typ VS = 1.5 V, RS = 0 Ω, CL = 1 nF; see Figure 33
Off Isolation 70 dB typ RL = 50 Ω, CL = 5 pF, f = 100 kHz;
see Figure 27
Channel-to-Channel Crosstalk 110 dB typ RL = 50 Ω, CL = 5 pF, f = 100 kHz;
see Figure 28
Total Harmonic Distortion + Noise 0.18 % typ RL = 110 Ω, f = 20 Hz to 20 kHz,
VS = 2 V p-p; see Figure 30
−3 dB Bandwidth 52 MHz typ RL = 50 Ω, CL = 5 pF; see Figure 29
CS (Off ) 76 pF typ VS = 1.5 V, f = 1 MHz
CD (Off ) 76 pF typ VS = 1.5 V, f = 1 MHz
CD, CS (On) 160 pF typ VS = 1.5 V, f = 1 MHz
POWER REQUIREMENTS
V
DD
= 3.6 V
IDD 0.001 µA typ Digital inputs = 0 V or VDD
1.0 1.0 µA max
VDD 3.3/16 V min/max
1 Guaranteed by design, not subject to production test.
Rev. C | Page 6 of 16
Data Sheet ADG1611/ADG1612/ADG1613
CONTINUOUS CURRENT PER CHANNEL, S OR D
Table 5.
Parameter 25°C 85°C 125°C Unit
CONTINUOUS CURRENT, S OR D
VDD = +5 V, VSS = −5 V
TSSOP (θJA = 150.4°C/W) 175 119 70 mA maximum
LFCSP (θJA = 48.7°C/W) 280 175 95 mA maximum
VDD = 12 V, VSS = 0 V
TSSOP (θJA = 150.4°C/W) 206 135 84 mA maximum
LFCSP (θJA = 48.7°C/W) 336 203 108 mA maximum
VDD = 5 V, VSS = 0 V
TSSOP (θJA = 150.4°C/W) 140 91 63 mA maximum
LFCSP (θJA = 48.7°C/W) 220 140 84 mA maximum
VDD = 3.3 V, VSS = 0 V
TSSOP (θJA = 150.4°C/W) 140 98 70 mA maximum
LFCSP (θJA = 48.7°C/W) 228 150 91 mA maximum
Rev. C | Page 7 of 16
ADG1611/ADG1612/ADG1613 Data Sheet
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 6.
Parameter Rating
VDD to VSS 18 V
VDD to GND −0.3 V to +18 V
VSS to GND +0.3 V to −18 V
Analog Inputs1 VSS − 0.3 V to VDD + 0.3 V or
30 mA, whichever occurs first
Digital Inputs1 GND − 0.3 V to VDD + 0.3 V or
30 mA, whichever occurs first
Peak Current, S or D 630 mA (pulsed at 1 ms,
10% duty-cycle maximum)
Continuous Current, S or D2 Data + 15%
Operating Temperature Range
Industrial (Y Version) −40°C to +125°C
Storage Temperature Range −65°C to +150°C
Junction Temperature 150°C
16-Lead TSSOP, θJA Thermal
Impedance (2-Layer Board)
150.4°C/W
16-Lead LFCSP, θJA Thermal
Impedance (4-Layer Board)
48.7°C/W
Reflow Soldering Peak
Temperature, Pb free
260°C
1 Overvoltages at IN, S, or D are clamped by internal diodes. Current should be
limited to the maximum ratings given.
2 See Table 5.
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
ESD CAUTION
Rev. C | Page 8 of 16
Data Sheet ADG1611/ADG1612/ADG1613
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
1
2
3
4
5
6
7
8
D1
S1
V
SS
D4
S4
GND
IN1
IN4
16
15
14
13
12
11
10
9
D2
S2
V
DD
D3
IN3
S3
NIC
IN2
07981-002
TOP VIEW
(No t t o Scal e)
ADG1611/
ADG1612/
ADG1613
NOTES
1. NI C = NOT INTE RNALL Y CONNECTED.
Figure 4. 16-Lead TSSOP Pin Configuration
07981-003
NOTES
1. NI C = NOT INTE RNALL Y CONNECT E D.
2. EXPOSED PAD TIED TO SUBSTRATE, V
SS
.
12
11
10
1
3
49
2
6
5
7
8
16
15
14
13
ADG1611/
ADG1612/
ADG1613
TOP VIEW
(No t t o Scal e)
S1
V
SS
GND
S4
S2
D2
IN2
IN1
D1
V
DD
NIC
S3
D4
IN4
IN3
D3
Figure 5. 16-Lead LFCSP Pin Configuration
Table 7. Pin Function Descriptions
Pin No.
Mnemonic Description
16-Lead TSSOP 16-Lead LFCSP
1 15 IN1 Logic Control Input.
2 16 D1 Drain Terminal. This pin can be an input or output.
3
1
S1
Source Terminal. This pin can be an input or output.
4 2 VSS Most Negative Power Supply Potential.
5 3 GND Ground (0 V) Reference.
6 4 S4 Source Terminal. This pin can be an input or output.
7 5 D4 Drain Terminal. This pin can be an input or output.
8 6 IN4 Logic Control Input.
9 7 IN3 Logic Control Input.
10 8 D3 Drain Terminal. This pin can be an input or output.
11 9 S3 Source Terminal. This pin can be an input or output.
12 10 NIC Not Internally Connected.
13 11 VDD Most Positive Power Supply Potential.
14 12 S2 Source Terminal. This pin can be an input or output.
15
13
D2
Drain Terminal. This pin can be an input or output.
16 14 IN2 Logic Control Input.
Not applicable 17 (EPAD) EP (EPAD) Exposed Pad. Tied to substrate, VSS.
Table 8. ADG1611/ADG1612 Truth Table
ADG1611 INx ADG1612 INx Switch Condition
0 1 On
1 0 Off
Table 9. ADG1613 Truth Table
Logic (INx) Switch 1, Switch 4 Switch 2, Switch 3
0 Off On
1 On Off
Rev. C | Page 9 of 16
ADG1611/ADG1612/ADG1613 Data Sheet
TYPICAL PERFORMANCE CHARACTERISTICS
0.4
0.6
0.8
1.0
1.2
1.4
–8 –6 –4 –2 02468
ON RES ISTANCE (Ω)
V
S
OR V
D
VOLTAGE (V)
T
A
= 25° C
V
DD
= +3. 3V
V
SS
= –3.3V
V
DD
= +5V
V
SS
= –5V
V
DD
= +8V
V
SS
= –8V
07981-013
Figure 6. On Resistance as a Function of VD (VS) for Dual Supply
0.5
1.0
1.5
2.0
2.5
3.0
3.5
0 2 4 6 8 10 12 14 16
ON RES ISTANCE (Ω)
VS OR VD VOLTAGE (V)
VDD = 3.3V
VSS = 0V
VDD = 12V
VSS = 0V
VDD = 5V
VSS = 0V
VDD = 16V
VSS = 0V
TA = 25° C
07981-014
Figure 7. On Resistance as a Function of VD (VS) for Single Supply
0.4
0.6
0.8
1.0
1.2
1.4
–6 –4 –2 0 2 4 6
ON RES ISTANCE (Ω)
V
S
OR V
D
VOLTAGE (V)
T
A
= +125°C
T
A
= +85°C
T
A
= +25°C
T
A
= –40° C
T
A
= +125°C
T
A
= +85°C
T
A
= +25°C
T
A
= –40° C
V
DD
= +5V
V
SS
= –5V
07981-011
Figure 8. On Resistance as a Function of VD (VS) for Different Temperatures,
±5 V Dual Supply
0.4
0.6
0.8
1.0
1.2
1.4
0 2 4 6 8 10 12
ON RES ISTANCE (Ω)
V
S
OR V
D
VOLTAGE (V)
T
A
= +125°C
T
A
= +85°C
T
A
= +25°C
T
A
= –40° C
V
DD
= 12V
V
SS
= 0V
07981-010
Figure 9. On Resistance as a Function of VD (VS) for Different Temperatures,
12 V Single Supply
1.0
1.5
2.0
2.5
00.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
ON RES ISTANCE (Ω)
VS OR VD VOLTAGE (V)
TA = +125°C
TA = +85°C
TA = +25°C
TA = –40° C
TA = +125°C
TA = +85°C
TA = +25°C
TA = –40° C
VDD = 5V
VSS = 0V
07981-012
Figure 10. On Resistance as a Function of VD (VS) for Different Temperatures,
5 V Single Supply
1.5
2.0
2.5
3.0
3.5
4.0
00.5 1.0 1.5 2.0 2.5 3.0 3.5
ON RES ISTANCE (Ω)
V
S
OR V
D
VOLTAGE (V)
V
DD
= 3.3V
V
SS
= 0V
T
A
= –40° C
T
A
= +25°C
T
A
= +85°C
T
A
= +125°C
07981-006
Figure 11. On Resistance as a Function of VD (VS) for Different Temperatures,
3.3 V Single Supply
Rev. C | Page 10 of 16
Data Sheet ADG1611/ADG1612/ADG1613
07981-032
TEMPERATURE (°C)
LEAKAGE CURRE NT (nA)
020 40 60 80 100 120
ID (OFF) +, –
ID, IS (ON) +, +
ID (OFF) –, +
IS (OFF) +, –
IS (OFF) –, +
ID, IS (ON) –, –
–15
–10
–5
0
5
10
15
20
Figure 12. Leakage Currents as a Function of Temperature, ±5 V Dual Supply
TEMPERATURE (°C)
LEAKAGE CURRE NT (nA)
020 40 60 80 100 120
ID (OFF) +, –
ID, IS (ON) +, +
ID (OFF) –, +
IS (OFF) +, –
IS
(OFF) –, +
I
D
, I
S
(O N) –, –
–15
–20
–10
–5
0
5
10
15
20
25
07981-031
Figure 13. Leakage Currents as a Function of Temperature,
12 V Single Supply
–5
0
5
10
15
20
020 40 60 80 100 120
LEAKAGE CURRE NT (nA)
TEMPERATURE (°C)
I
D
, I
S
(OFF) +, +
I
D
, I
S
(OFF) –, –
I
D
(OFF) –, +
I
S
(OFF) +, –
I
D
(OFF) +, –
I
S
(OFF) –, +
07981-019
Figure 14. Leakage Currents as a Function of Temperature,
5 V Single Supply
020 40 60 80 100 120
TEMPERATURE (°C)
ID, IS (OFF) +, +
ID, IS (OFF) –, –
ID (OFF) –, +
IS (OFF) +, –
ID (OFF) +, –
IS (OFF) –, +
–4
–2
0
2
4
6
8
10
12
14
16
18
LEAKAGE CURRE NT (nA)
07981-030
Figure 15. Leakage Currents as a Function of Temperature,
3.3 V Single Supply
–100
0
100
200
300
400
500
600
I
DD
(µA)
0246810 12
LOGIC (V)
I
DD
PER CHANNEL
T
A
= 25° C
V
DD
= +12V
V
SS
= 0V
V
DD
= +5V
V
SS
= –5V
V
DD
= +5V
V
SS
= 0V
V
DD
= +3. 3V
V
SS
= 0V
07981-005
Figure 16. IDD vs. Logic Level
0
50
100
150
200
250
300
–6 –4 –2 0246 8 10 12 14
CHARGE INJECTION (pC)
V
S
(V)
V
DD
= +12V
V
SS
= 0V
V
DD
= +5V
V
SS
= 0V
V
DD
= +3. 3V
V
SS
= 0V
V
DD
= +5V
V
SS
= –5V
07981-009
Figure 17. Charge Injection vs. Source Voltage (VS)
Rev. C | Page 11 of 16
ADG1611/ADG1612/ADG1613 Data Sheet
0
50
100
150
200
250
300
350
400
500
450
–60 –40 –20 020 40 60 80 100 120 140
TIME (ns)
TEMPERATURE (°C)
07981-018
t
OFF
(+3. 3V )
t
ON
(+3. 3V )
t
OFF
(+5V)
t
OFF
(±5V)
t
ON
(+5V)
t
OFF
(+12V)
t
OFF
(±5V)
t
ON
(+12V)
Figure 18. tON/tOFF Times vs. Temperature
–85
–80
–75
–70
–65
–60
–55
–50
–45
–40
–35
–30
–25
–20
–15
–10
–5
OFF ISOLATION (dB)
FREQUENCY (Hz)
100k 1M 10M 100M 1G10k1k
TA = 25° C
VDD = +5V
VSS = –5V
07981-007
Figure 19. Off Isolation vs. Frequency
–140
–120
–100
–80
–60
–40
–20
0
CROSSTALK ( dB)
FREQUENCY (Hz)
100k 1M 10M 100M 1G
10k
1k
T
A
= 25° C
V
DD
= +5V
V
SS
= –5V
07981-017
Figure 20. Crosstalk vs. Frequency
INSERTION LOSS (dB)
FREQUENCY ( Hz )
100k 1M 10M 100M 1G10k1k
–6
–5
–3
–1
–4
–2
0T
A
= 25° C
V
DD
= +5V
V
SS
= –5V
07981-004
Figure 21. On Response vs. Frequency
–120
–100
–80
–60
–40
–20
0
FREQUENCY (Hz)
100k 1M 10M10k1k
T
A
= 25° C
V
DD
= +5V
V
SS
= –5V
ACPSRR (dB)
07981-008
NO DECOUPLING
CAPACITORS
DECOUPLING
CAPACITORS
Figure 22. ACPSRR vs. Frequency
00
0.02
0.04
0.06
0.08
0.10
0.12
0.14
0.16
0.18
0.20
THD + N ( %)
FREQUENCY (Hz)
15k 20k
10k
5k 25k
R
L
= 110Ω
T
A
= 25° C
V
DD
= +3. 3V
V
S
= 2V
V
DD
= +5V
V
S
= 3.5V
V
DD
= +5V
V
SS
= –5V
V
S
= 5V p-p
V
DD
= +12V
V
S
= 5V p-p
07981-016
Figure 23. THD + N vs. Frequency
Rev. C | Page 12 of 16
Data Sheet ADG1611/ADG1612/ADG1613
Rev. C | Page 13 of 16
TEST CIRCUITS
Sx Dx
VS
IS
V1
RON = V1/IS
07981-020
Figure 24. On Resistance
Sx Dx
VS
A A
VD
IS (OFF) ID (OFF)
0
7981-021
Figure 25. Off Leakage
Sx Dx A
V
D
I
D
(ON)
NIC
NIC = NOT INTERNALLY
CONNECTED.
07981-022
Figure 26. On Leakage
V
OUT
50Ω
NETWORK
ANALYZER
R
L
50Ω
INx
V
IN
Sx
Dx
50Ω
OFF ISOLATION = 20 log
V
OUT
V
S
V
S
V
DD
V
SS
0.1µF
V
DD
0.1µF
V
SS
GND
07981-026
Figure 27. Off Isolation
CHANNEL-TO-CHANNEL CROSSTALK = 20 log V
OUT
GND
S1
Dx
S2
V
OUT
NETWORK
ANALYZER
R
L
50Ω
R
L
50Ω
V
S
V
S
V
DD
V
SS
0.1µF
V
DD
0.1µF
V
SS
07981-027
Figure 28. Channel-to-Channel Crosstalk
V
OUT
50Ω
NETWORK
ANALYZER
R
L
50Ω
INx
V
IN
Sx
Dx
INSERTION LOSS = 20 log
V
OUT
WITH SWITCH
V
OUT
WITHOUT SWITCH
V
S
V
DD
V
SS
0.1µF
V
DD
0.1µF
V
SS
GND
0
7981-028
Figure 29. Bandwidth
ADG1611/ADG1612/ADG1613 Data Sheet
Rev. C | Page 14 of 16
V
OUT
R
S
AUDIO PRECISION
R
L
110
INx
V
IN
Sx
Dx
V
S
V p-p
V
DD
V
SS
0.1µF
V
DD
0.1µF
V
SS
GND
07981-029
Figure 30. THD + Noise
V
S
INx
Sx Dx
GND
R
L
300
C
L
35pF
V
OUT
V
DD
V
SS
0.1µF
V
DD
0.1µF
V
SS
ADG1612
ADG1611
V
IN
V
IN
V
OUT
tON tOFF
50% 50%
90% 90%
50% 50%
07981-023
Figure 31. Switching Times
V
S2
IN1,
IN2
S2 D2
V
S1
S1 D1
GND
R
L
300
C
L
35pF
V
OUT2
V
OUT1
V
DD
V
SS
0.1µF
V
DD
0.1µF
V
SS
V
IN
V
OUT1
V
OUT2
ADG1613
t
D
t
D
50% 50%
90%
90%
90%
90%
0V
0V
0V
R
L
300
C
L
35pF
07981-024
Figure 32. Break-Before-Make Time Delay
INx
V
OUT
ADG1612
ADG1611
V
IN
V
IN
V
OUT
OFF
V
OUT
ON
Q
INJ
= C
L
× V
OUT
Sx Dx
V
DD
V
SS
V
DD
V
SS
V
S
R
S
GND
C
L
1nF
07981-025
Figure 33. Charge Injection
Data Sheet ADG1611/ADG1612/ADG1613
TERMINOLOGY
IDD
The positive supply current.
ISS
The negative supply current.
VD (VS)
The analog voltage on Terminal D and Terminal S.
RON
The ohmic resistance between Terminal D and Terminal S.
RFLAT(ON)
Flatness that is defined as the difference between the maximum
and minimum value of on resistance measured over the specified
analog signal range.
IS (Off)
The source leakage current with the switch off.
ID (Off)
The drain leakage current with the switch off.
ID, IS (On)
The channel leakage current with the switch on.
VINL
The maximum input voltage for Logic 0.
VINH
The minimum input voltage for Logic 1.
IINL (IINH)
The input current of the digital input.
CS (Off)
The off switch source capacitance, which is measured with
reference to ground.
CD (Off)
The off switch drain capacitance, which is measured with
reference to ground.
CD, CS (On)
The on switch capacitance, which is measured with reference to
ground.
CIN
The digital input capacitance.
tON
The delay between applying the digital control input and the
output switching on. See Figure 31.
tOFF
The delay between applying the digital control input and the
output switching off. See Figure 31.
Charge Injection
A measure of the glitch impulse transferred from the digital
input to the analog output during switching. See Figure 33.
Off Isolation
A measure of unwanted signal coupling through an off switch.
See Figure 27.
Crosstalk
A measure of unwanted signal that is coupled through from one
channel to another as a result of parasitic capacitance. See
Figure 28.
Bandwidth
The frequency at which the output is attenuated by 3 dB. See
Figure 29.
On Response
The frequency response of the on switch.
Insertion Loss
The loss due to the on resistance of the switch.
Total Harmonic Distortion + Noise (THD + N)
The ratio of the harmonic amplitude plus noise of the signal to
the fundamental. See Figure 30.
AC Power Supply Rejection Ratio (ACPSRR)
The ratio of the amplitude of signal on the output to the amplitude
of the modulation. This is a measure of the ability of the part to
avoid coupling noise and spurious signals that appear on the supply
voltage pin to the output of the switch. The dc voltage on the device
is modulated by a sine wave of 0.62 V p-p.
Rev. C | Page 15 of 16
ADG1611/ADG1612/ADG1613 Data Sheet
Rev. C | Page 16 of 16
OUTLINE DIMENSIONS
16 9
81
PIN 1
SEATING
PLANE
8°
0°
4.50
4.40
4.30
6.40
BSC
5.10
5.00
4.90
0.65
BSC
0.15
0.05
1.20
MAX 0.20
0.09 0.75
0.60
0.45
0.30
0.19
COPLANARITY
0.10
COM PLI ANT T O JEDEC S TANDARDS MO-153-AB
Figure 34. 16-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-16)
Dimensions shown in millimeters
COMPLIANT
TO
JEDEC STANDARDS MO-220-WGGC.
042709-A
1
0.65
BSC
BOTTOM VIEWTOP VIEW
16
5
8
9
1213
4
EXPOSED
PAD
PIN1
INDICATOR
4.10
4.00 SQ
3.90
0.50
0.40
0.30
SEATING
PLANE
0.80
0.75
0.70 0.05 MAX
0.02 NOM
0.20 REF
COPLANARITY
0.08
PIN 1
INDICATOR
0.35
0.30
0.25
2.60
2.50 SQ
2.40
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
Figure 35. 16-Lead Lead Frame Chip Scale Package [LFCSP_WQ]
4 mm × 4 mm Body, Very Very Thin Quad
(CP-16-26)
Dimensions shown in millimeters
ORDERING GUIDE
Model1 Temperature Range Package Description Package Option
ADG1611BRUZ −40°C to +125°C 16-Lead Thin Shrink Small Outline Package [TSSOP] RU-16
ADG1611BRUZ-REEL −40°C to +125°C 16-Lead Thin Shrink Small Outline Package [TSSOP] RU-16
ADG1611BRUZ-REEL7 −40°C to +125°C 16-Lead Thin Shrink Small Outline Package [TSSOP] RU-16
ADG1611BCPZ-REEL −40°C to +125°C 16-Lead Lead Frame Chip Scale Package [LFCSP_WQ] CP-16-26
ADG1611BCPZ-REEL7 −40°C to +125°C 16-Lead Lead Frame Chip Scale Package [LFCSP_WQ] CP-16-26
ADG1612BRUZ −40°C to +125°C 16-Lead Thin Shrink Small Outline Package [TSSOP] RU-16
ADG1612BRUZ-REEL −40°C to +125°C 16-Lead Thin Shrink Small Outline Package [TSSOP] RU-16
ADG1612BRUZ-REEL7 −40°C to +125°C 16-Lead Thin Shrink Small Outline Package [TSSOP] RU-16
ADG1612BCPZ- REEL −40°C to +125°C 16-Lead Lead Frame Chip Scale Package [LFCSP_WQ] CP-16-26
ADG1612BCPZ-REEL7 −40°C to +125°C 16-Lead Lead Frame Chip Scale Package [LFCSP_WQ] CP-16-26
ADG1613BRUZ −40°C to +125°C 16-Lead Thin Shrink Small Outline Package [TSSOP] RU-16
ADG1613BRUZ-REEL −40°C to +125°C 16-Lead Thin Shrink Small Outline Package [TSSOP] RU-16
ADG1613BRUZ-REEL7 −40°C to +125°C 16-Lead Thin Shrink Small Outline Package [TSSOP] RU-16
ADG1613BCPZ-REEL −40°C to +125°C 16-Lead Lead Frame Chip Scale Package [LFCSP_WQ] CP-16-26
ADG1613BCPZ-REEL7 −40°C to +125°C 16-Lead Lead Frame Chip Scale Package [LFCSP_WQ] CP-16-26
1 Z = RoHS Compliant Part.
©2009-2015 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D07981-0-5/15(C)
