34.807IRELESS
IMPORTANT NOTICE
Dear customer,
As from August 2nd 2008, the wireless operations of STMicroelectronics have moved to a
new company, ST-NXP Wireless.
As a result, the following changes are applicable to the attached document.
●Company name - STMicroelectronics NV is replaced with ST-NXP Wireless.
●Copyright - the copyright notice at the bottom of the last page “© STMicroelectronics
200x - All rights reserved”, shall now read: “© ST-NXP Wireless 200x - All rights
reserved”.
●Web site - http://www.st.com is replaced with http://www.stnwireless.com
●Contact information - the list of sales offices is found at http://www.stnwireless.com
under Contacts.
If you have any questions related to the document, please contact our nearest sales office.
Thank you for your cooperation and understanding.
ST-NXP Wireless
34.807IRELESS
www.stnwireless.com
Ju ne 200 7 Rev 6 1/65
1
STw8009
STw8019
Mobile video DENC
Features
■Two analog outputs (10 bits DAC) with:
– CVBS (Composite) output or Y/C (S-VHS)
– NTSC-J, M & 4.43 & PAL-BDGHI, N, Nc, M
support
– 35 mA current driver
■8-bit digital interface input supporting both
embedded and external synchro
– CCIR 601 / YCbCr 4:2:2 format
– CCIR 656: 27 Mhz pixel input clock
■Latest Macrovision (7.1.L1) (STw8019 only)
■2-wire serial MPU interface (I2C compatible)
■Master and slave modes
■TV / VCR plug insertion detection
■Supply voltages
– 2.8V/3.3V analog
– 1.8V/ 2.8V digital I/O
– 1.2V/1.4V for core
■Power consumption
– Sleep mode: 5 µW
– Standby mode: 150 µW maximum
– CVBS: 125 mW
– Y/C: 245 mW
■Package
– TFBGA 4x4x1.2 mm height, 0.5 mm pitch,
– VFBGA 3x3x1 mm height, 0.4 mm pitch
■Full matrix: 7 x 7
Applications
■Mobile video Digital ENCoder (DENC)
Description
STw80x9 is aimed at mobile video Digital
ENCoder (DENC). This device converts digital
video signals into high quality analog signal
compliant with TV standards, it is able to encode
interlaced (in all standards) and non-interlaced (in
PAL and NTSC).
Fe aturing ultra low power consumption, it suits
perfectly mobile appliances that interface
occasionally with TV sets or VCRs. It is also the
ideal companion for digital application processors
such as ST’s Nomadik family.
To minimize PCB space usage, STw80x9 features
a high lev el of integration. STw80x9 driv es directly
the video input, CVBS of a TV set or the Y/C
video input of a VCR through optional ESD
protection devices.
The 27 MHz clock and the device power
management are controlled through the digital
processor interface [PORn, Suspend and 2-wire
I2C compatible serial MPU]. This digital processor
interface also controls the STw80x9 operating
modes (off, sleep, standby and active).
STw8009
TFBGA 4 mm x 4 mm x 1.2 mm
VFBGA 3 mm x 3 mm x 1.0 mm
www.st.com
Contents STw8009/STw8019
2/65
Contents
1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2 Functional block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3 Ball/pin information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
4 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
4.1 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
4.2 Master & slave modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
4.3 Auto te st mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
4.4 Input demultipl exor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
4.5 Video timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4.6 Sub-carrier generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4.7 Luminance encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4.8 Chrominance encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.9 Composit e video signal generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4.10 MacrovisionTM copy protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4.11 TV/VCR plug insertion detecti on . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4.12 DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4.13 Pow e r management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4.13.1 Operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
4.13.2 Mode transition diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
4.14 JTAG interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
5 Control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
5.1 Register addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
5.2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
5.2.1 DENC registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
5.2.2 Control & power management unit registers . . . . . . . . . . . . . . . . . . . . . 45
6 Bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
6.1 2 wire serial MPU control interfac e (I2C compatible) . . . . . . . . . . . . . . . . 47
7-bit address mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
STw8009/STw8019 Contents
3/65
10 bits address mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
6.2 YcbCr bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
7 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
7.1 Absolute maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
7.2 Oper ating condit ions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
7.3 Electrical and timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
8 Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
9 Color test pattern waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
10 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
10.1 TFBGA 49 balls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
10.2 VFBGA 49 balls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
11 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
12 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
List of tables STw8009/STw8019
4/65
List of tables
Table 1. Product name ball functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Table 2. NTSC and PAL timings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 3. Register addresses. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Table 4. std1, std0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 5. sync2, sync1, sync0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 6. Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 7. valrst1 and valrst0 selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Table 8. syncin_ad[1:0]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 9. syncout_ad[1:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 10. jump, dec_ninc, free_jump . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 11. cfc[1:0]: color frequency control via CFC line . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 12. ph_rst_mode[1:0]:sub-carrier phase reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Table 13. dac2_mult[5:0]: multiplying factor on dac2_c digital signal. . . . . . . . . . . . . . . . . . . . . . . . . 35
Table 14. c_mult[3:0]: multiplying factor of C digital output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Table 15. Chroma main_coef_[8:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Table 16. main_del[3:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Table 17. Luma_coef_[0:9]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Table 18. dac12_conf. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Table 19. dac1_multi[5:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Table 20. main_chr_del[3:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Table 21. STw80x9 addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Table 22. YcBCr data bus timing (
Figure 22
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Table 23. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Table 24. Operating conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Table 25. 2 wire serial MPU control interface timing (
Figure 20
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Table 26. Digital I/O interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Table 27. Power consumption/R load = 37.5 ohm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Table 28. DAC & Video output characteristics / Rload = 37.5 ohm – F = 27 MHz – Rext = 2.4 kohm 53
Table 29. TFBGA 4x4x1.2 mm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Table 30. VFBGA 3x3x1.0 mm - 49 balls - Pitch 0.4 ball 0.25 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Table 31. Order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Table 32. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
STw8009/STw8019 List of figures
5/65
List of figures
Figure 1. Application diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 2. STw8009 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 3. STw8019 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 4. Ball layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 5. Input data format (ITU-R656/D1 4:2:2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 6. PAL-BDGHI, PAL-N typical VBI waveform, interlaced mode (ITU-R625 line numbering) . 13
Figure 7. NTSC-M typical VBI waveforms, interlaced mode (SMTPE-524 line numbering . . . . . . . . 13
Figure 8. PAL-M typical VBI waveforms, interlaced mode (ITU-R/CCIR-525 line numbering) . . . . . 14
Figure 9. Horizontal blanked interval and active video timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 10. Luma filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 11. Luma filtering with 3.58 MHz trap . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 12. Luma filtering with 4.43 MHz trap . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 13. 1.1 MHz chroma filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 14. 1.3 MHz chroma filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 15. 1.6 MHz chroma filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 16. 1.9 MHz chroma filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 17. Mode transition diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 18. 2-wire serial MPU control interface format (I2C compatible) / 7-bit addresses. . . . . . . . . . 48
Figure 19. 2-wire serial MPU control interface format (I2C compatible) / 10-bit addresses. . . . . . . . . 49
Figure 20. 2-wire serial MPU control interface timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Figure 21. YcbCr bus format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Figure 22. Data bus timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Figure 23. Typical application schematic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Figure 24. NTSC composite. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Figure 25. NTSC S-video. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Figure 26. PAL composite . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Figure 27. PAL S-video . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Figure 28. TFBGA 49 balls 4 x 4 x 1.2 mm body size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Figure 29. VFBGA 49 balls 3 x 3 x 1.0 mm body size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Overview STw8009/STw8019
6/65
1 Overview
STw80x9 is aimed at mobile video Digital ENCoder (DENC). This device converts digital
video signals into high quality analog signal compliant with TV standards, it is able to
encode interlaced (in all standards) and non-interlaced (in PAL and NTSC).
Featuring ultra low power consumption, it suits perfectly mobile appliances that interface
occasionally with TV sets or VCRs. It is also the ideal companion for digital application
processors s uch as ST’s Nomadi k family.
To minimize PCB space usage, the device features a high level of integration. The 35 mA
high performance DAC allows direct drive of 37.5 Ω load.
STw80x9 drives directly the video input, CVBS of a TV set or the Y/C video input of a VCR
through optional ESD protection de vices. It is powered by three voltage supplies, 2.8V/3.3V,
1.8V/2.8V and 1.2V/1.4V (VccA, VI/O, Vdd).
The 27 MHz clock and the device power management are controlled through the digital
processor interface [PORn, Suspend and 2-wire I2C compatible serial MPU]. This digital
processor interface also controls the operating modes (off, sleep, standby and active).
Figure 1. Application diagram
Naming convention
Unless clearly specified in the document, STw80x9 stands for both STw8009 and STw8019.
Video
Digital
processor
STw80x9
Clk
TV set
or
VCR
Supply
Vdd Vo VccA
YCbCr
PORn
I2C
Suspend
Vdd Vo VccA
C/CVBS
Y
ESD
protection
75 Ω
75 Ω
STw8009/STw8019 Functional block diagram
7/65
2 Functional block diagram
Figure 2. STw8009 block diagram
Figure 3. STw8019 block diagram
Ball/pin information STw8009/STw8019
8/65
3 Ball/pin information
Table 1. Product name ball functions
Ball Name Type Voltage Description
E1 Vdd Power 1.2V/1.4V Digital core chip supply
D2 Gndd GND 0 V Digital core chip ground
C1 VddIO1 Power 1.8V/2.8V Digital I/O supply
D1 VssIO1 GND 0 V Digital I/O ground
G4 VddIO2 Power 1.8V/2.8V Digital I/O supply
E4 VssIO2 GND 0 V Digital I/O ground
A3 VccA1 Power 2.8V/ 3.3V DAC2 matr ix analog power supply
A5 VccA2 Power 2.8V/ 3.3V DAC1 matr ix analog power supply
A7 VccA3 Power 2.8V/3.3V 2.8/3.3 V digital feature supply
B7 VccA4 Power 2.8V/3.3V 2.8 /3.3 V digital feature supply
B3 GNDA1 GND 0 V DAC2 ground
B5 GNDA2 GND 0 V DAC1 ground
C5 GNDA3 GND 0 V 2.8 /3.3 V digital feature ground
B4 GNDA4 GND 0 V Rext ground connection
B6 GNDA5 GND 0 V Analog ground
A4 Rext Analog DAC current reference setting
G2 CLK Digital Input 1.8V/2.8V 27 MHz master pixel clock (pixclk)
G7, G6,
F7, F6,
E7, E6,
D7, D6
YCbCr[0:7] Digital Input 1.8V/2.8V
Time multiplexed 4:2:2 luminance and
chromin an ce dat a as defin ed in CCI R 601
and CCIR 656 (excepted for TTL input
signals)
G5 Hs yn c Digital I/O 1.8V/2. 8V
Horizontal synchronization signal:
- Input in slave mode, except when sync is
extracted from YcbCr data
- Output in master mode and when sync is
extracted from YcbCr signal.
F5 Vsync
Odd/Even Digi tal I/O 1. 8V/2. 8V
Vertical Synchronization – Odd/Even signal:
- Input in slave mode, except when sync is
extracted from YcbCr data
- Output in master mode and when sync is
extracted from YcbCr signal.
F3 SDA Digital I/O 1.8V/2.8V 2 wire serial MPU data line
G3 SCL Digital Input 1.8V/2.8V 2 wire serial MPU clock
E3 Add Digital input 1.8V/2.8V Device address selection
C7 PORn Digital input 1.8V/2.8V Power On Reset (Active low)
F2 Suspend Digital input 1.8V/2.8V Suspend input
STw8009/STw8019 Ball/pin information
9/65
Figure 4. Ball layout
A2 C/CVBS Analog output The output can be selected to be composite
video or chroma signal for s-video.
A6 Y Analog output Luminance signal for s-video
B1 TDI Digital input 1.8V/2.8V JTAG test data in
If not used, connected to GND
B2 TDO Digital output 1.8V/2.8V JTAG test data out
If not used, left open
C2 TCK Digital input 1.8V/2.8V JTAG test clock
If not used, connected to GND
C3 TMS Digital input 1.8V/2.8V JTAG test mode sele ct
If not used, connected to GND
D4 Test Digital input 1.8V/2.8V Put the device in test mode
If not used, connected to GND
D3, F1,
E2 tst_ana[0:2] Digital input 1.8V/2.8V DENC test
If not used, connected to GND
F4 PlugDet Digital input 1.8V/2.8V TV / VCR plug c onn ec tio n d etec ti on / C MOS
input
Table 1. Product name ball functions (continued)
Ball Name Type Voltage Description
GNDA3
Rext
VccA4
A
B
C
E
F
D
G
1234567
VccA2 Y
GNDA2
C/CVBS
GNDA4
VccA3
GNDA5
Suspend
CLK
Vdd_IO1
VccA1
GNDA1
Test YCbCr[7] YCbCr[6]
YCbCr[4]
YCbCr[2]
YCbCr[3]
YCbCr[0]YCbCr[1]
YCbCr[5]
Vss_IO1
TDI
TCK
TDO
Vdd
TMS
tst_ana[0]
tst_ana[2]
tst_ana[1] SDA
Gndd
Add
HsyncSCL Vdd_IO2
Vss_IO2
Vsync
PORn
PlugDet
GNDA3
Rext
VccA4
A
B
C
E
F
D
G
1234567
VccA2 Y
GNDA2
C/CVBS
GNDA4
VccA3
GNDA5
Suspend
CLK
Vdd_IO1
VccA1
GNDA1
Test YCbCr[7] YCbCr[6]
YCbCr[4]
YCbCr[2]
YCbCr[3]
YCbCr[0]YCbCr[1]
YCbCr[5]
Vss_IO1
TDI
TCK
TDO
Vdd
TMS
tst_ana[0]
tst_ana[2]
tst_ana[1] SDA
Gndd
Add
HsyncSCL Vdd_IO2
Vss_IO2
Vsync
PORn
PlugDet
Functional description STw8009/STw8019
10/65
4 Functional description
4.1 General
STw80x9 operates either in master mode where it supplies all sync signal or in slave mode.
The digital input is an 8-bit bus carrying Y, Cb and Cr at 13.5 MHz. Input samples are
latched in on the rising edge of the clock input signal.
STw80x9 is able to encode interlaced (in all standards) and non interlaced (in PAL and
NTSC) video.
STw80x9 outputs interlaced or non-interlaced video in PAL-B,D,G,H,I,PAL-N,PAL-M or
NTSC-M standards (“NTSC-4.43” is also possible).
The burst sequences are internally generated, subcarrier generation being performed
numerically with the 27 MHz as reference. 4-frame bursts are generated for PAL or 2-frame
bursts for NTSC . Rise and fall times of synchronization tips and burst env elope are internally
controlled according to the relevant ITU_R and SMPTE recommendations.
4.2 Master & slave modes
In master mode, STw80x9 supplies Hsync and Odd/Even sync signals (with independently
programmable polarities) to drive other blocks. STw80x9 starts encoding and counting clock
cycles as soon as the master mode has been loaded into the control register (Reg 0).
Configuration bits “Syncout_ad[1:0]” (Reg 4) allow to shift the relative position of the sync
signals by up to 3 clock cycles to cope with any YcbCr phasing.
In slave modes, several modes are available, Odd/Even+Hsync based, Vsync+Hsync
based, Odd/Even-only based, Vsync-only based or Sync-in-data based.
4.3 Auto test mode
An auto test mode is av ailable, which causes STw80x9 to produce a color bar pattern, in the
appropriate standard, independently from the video input.
4.4 Input demultiplexor
The incoming YcbCr 4:2:2 data are demultiplexed into chroma information stream, a “blue-
difference” and a “red-difference”, and a luma information stream. Incoming data bits are
treated as blue, red or luma samples according to their relative position with respect to the
sync signals. Brightness, Saturation and Contrast are then performed on demultiplexed
data.
The ITU-R601 recommendation defines the blac k luma level as Y=16dec and the maximum
white luma level as Y=235dec. Similarly it defines 255 quantification levels for the color
difference components (Cr , Cb) centered around 128. Accordingly, incoming YcbCr samples
can be saturated. In this case STw80x9 provides a saturation limitation feature to avoid
having heavily saturated signal bef ore digital to analog conversion and to a void generating a
distorted signal at STw80x9 CVBS or Y/C outputs.
STw8009/STw8019 Functional description
11/65
4.5 Video timing
The DENC outputs video in PAL-B,D,G,H,I, PAL-N, PAL-M or NTSC-J, M standards (‘NTSC-
4.43’ is also possible).
The burst sequences are internally generated, subcarrier generation being performed
numerically with PIX_CLK as reference. 4-frame bursts are generated for PAL or 2-frame
bursts for NTSC . Rise and fall times of synchronization tips and burst env elope are internally
controlled according to the relevant ITU-R and SMPTE recommendations.
Figure 5
,
6
,
7
and
8
depict typical VBI waveforms.
It is possible to allow encoding of incoming YCrCb data on those lines of the VBI that do not
bear line sync pulses or pre/post-equalization pulses (
Figure 5
,
6
,
7
and
8
). This mode of
operation is referred to as “partial blanking” and is the def ault set-up. It allows to keep in the
encoded waveform any VBI data present in digitized form in the incoming YCrCb stream.
Alternatively, the complete VBI may be fully blanked, so no incoming YCrCb data encoded
on these lines.
The ‘complete’ VBI comprises of the following lines:
– f or 525/60 systems (SMPTE line numbering con vention): lines 1 to 19 and second
half of line 263 to line 282
– for 625/50 systems (CCIR line numbering convention): second half of line 623 to
line 22 and lines 311 to 335
The ‘partial’ VBI consists of:
– for 525/60 systems (SMPTE line numbering convention): lines 1 to 9 and second
half of line 263 to line 272
– for 625/50 systems (CCIR line numbering convention): second half of line 623 to
line 5 and lines 311 to 318
Full or partial blanking is controlled by configuration bit ‘
blkli
in configuration register1’.
Note: line 282 in 525/60/SMPTE systems is either fully blanked or fully active.
line 23 in 625/60/CCIR systems is always fully active.
In an ITU-R656-compliant digital TV line, the active portion of the digital line is the portion
included between the SAV (Start of Active Video) and EAV (End of Active Video) words.
However, this digital active line starts somewhat earlier and may end slightly later than the
active line usually defined by analog standards.
The DENC permits two approaches:
●Encodes the full digital line (720 pixels / 1440 clock cycles). In this case, the output
waveform will reflect the full YCrCb stream included between SAV and EAV.
●Drops some YCrCb samples at the extremities of the digital line so that the encoded
analog line fits within the ‘analog’ ITU-R/SMPTE specifications.
Selection between these two modes of operation is performed with bit ‘aline’ in configuration
register 4.
In all cases, the transitions between horizontal blanking and active video are shaped to
avoid too steep edges within the active video. Figure 11 on page 15 gives timings
concerning the horizontal blanking interval and the active video interval.
Functional description STw8009/STw8019
12/65
Figure 5. Input data format (ITU-R656/D1 4:2:2)
Note: The burst env elope shown here indicates the location from which the first subcarrier positive
zero crossing is sought (with respect to the 0H refer ence). The normal burst always starts
with such a positive zero crossing.
Digital active line
1440T
1716T
NTSC, PAL M
PAL B, G, H, I, N
SECAM
Square pixel
525 / 60 system
Square pixel
625 / 50 system
T = clock period
PAL, NTSC: 37.037 ns
4T
ESE
A
VA
VA
V
4T
128T
137T
146T (PAL M)
Digital active line
1440T
1728T
128T
151T (145T in SECAM)
Digital active line
1280T
1560T
115T
131T
Digital active line
1536T
1888T
139T
169T
0H
STw8009/STw8019 Functional description
13/65
Figure 6. PAL-BDGHI, PAL-N typical VBI waveform, interlaced mode (ITU-R625 line numbering)
Figure 7. NTSC-M typical VBI waveforms, interlaced mode (SMTPE-524 line numbering
A
311 312 313 314 315 316 317 318 317 336308 309 310
AB
624 625 1 2 3 4 5 6 7 8621 622 623
III
I
II
III
IV
II
C
0
V
:
I, II, III, IV :
A :
B :
C :
Frame synchronization reference
1
st
and 5
th
, 2
nd
and 6
th
, 3
rd
and 7
th
, 4
th
and 8
th
fields
Burst phase : nominal value +135°
Burst phase : nominal value -135°
Burst su
pp
ression internal
308 309 310 311 312 313 314 315 316 317 318 319 320
AB
0
V
IV
A
624 625 1234567 23621 622 623
I
Partial VBI1 Full VBI1
Partial VBI2 Full VBI2 22
335
1
Full VBI1
2 3
Partial VBI1
45678910 18 19
H0.5HHH
282273272271270269268267266265264263262
HH0.5H
Full VBI2
VBI3
12345678910 18 19525
282273272271270269268267266265264263
VBI4
Partial VBI2
Functional description STw8009/STw8019
14/65
Figure 8. PAL-M typical VBI waveforms, interlaced mode (ITU-R/CCIR-525 line numbering)
Figure 9. Horizontal blanked interval and active video timings
F'
519
F
520
F'
521
F
522 523 524 525 1 2 3 4 5 6 7 8 9
AB
AB
AB
261 262 263 264 265 266 267 268 269 270 271 280
523 524 525 123456789
F
519
F'
520
F
521 522
F
257
F'
258
F
259 260
AB
261 262 263 264 265 266 267 268 269 270 271 272
F'
257
F
258 259 260
0
V
IV
I
II
III
IV
III
II
I
C
0
V
:
I, II, III, IV :
A :
B :
C :
Frame synchronization reference
1
st
and 5
th
, 2
nd
and 6
th
, 3
rd
and 7
th
, 4
th
and 8
th
fields
Burst phase : nominal value +135°
Burst phase : nominal value -135°
Burst su
pp
ression internal
Partial VBI1 Full VBI1
16 1
7
Partial VBI2 Full VBI2
279
0H
Active video
Horizontal blanking interval
a
b1 (bit aline = 0)
c1 (bit aline = 0)
c2 (bit aline = 1)
d
Full digital line encoding
‘Analog’ line encoding
(720 pixels - 1440 T)
b2 (bit aline = 1)
STw8009/STw8019 Functional description
15/65
4.6 Sub-carrier generation
A Direct Digital Frequency Synthesizer (DDFS) generates the required color sub-carrier
frequency using a 24-bit phase accumulator. Sub-carrier frequency is programmable with a
1.6 Hz step.
4.7 Luminance encoding
The luminance that is added to the chrominance to create the composite CVBS signal can
be trap-filtered at 3.58 MHz (NTSC) or 4.43 MHz (PAL). This supports application oriented
towards low-end TV sets which ar e subjec t to cross -c olor.
A 7.5 IRE pedestal can be programmed if needed with all standards. This allows in
particular to encode Argentinian and non-Argentinian PAL-N, or Japanese NTSC.
A programmable delay can be inserted on the luminance path to offset any chroma/luma
delay introduced by off-chip filtering.
STw80x9 output signals are IF modulated in NTSC M standard so that a sound notch filter is
required. The notch filter which is on the Luma path is defined by a set of coefficients and is
implemented in the STw80x9 as default values. The set is also programmable.
Table 2. NTSC and PAL timings
NTSC-M PAL-BDGHI PAL-N PAL-M
a(1)
1. These are typical values. Actual values will depend on the static offset programmed for subcarrier
generation
5.38 μs (even lines)
5.52 μs (odd lines) 5.54 μs (A-type)
5.66 μs (B-type) 5.54 μs (A-type)
5.66 μs (B-type) 5.73 μs (A-type)
5.87 μs (B-type)
b1 1.56 μs1.3 μs1.3 μs1.56 μs
b2 1.56 μs1.52 μs 1.52 μs1.56 μs
c1 8.8 μs9.6 μs9.6 μs8.8 μs
c2 9.41 μs10.48 μs10.48 μs9.41 μs
d 9 cycles of 3.58MHz 10 cycles of 4.43MHz 9 cycles of 3.58MHz 9 cycles of 3.58MHz
Functional description STw8009/STw8019
16/65
Figure 10. Luma filtering
Figure 11. Luma filtering with 3.58 MHz trap
Amplitude (dB)
Frequency (MHz)
Frequency (MHz)
STw8009/STw8019 Functional description
17/65
Figure 12. Luma filtering with 4.43 MHz trap
4.8 Chrominance encoding
Chroma components are computed from demultiplexed Cb, Cr samples. Before modulating
the subcarrier, the chroma components are band-limited and interpolated at pixel clock rate.
A set of 4 diff erent filters is a vailable f or chroma filtering to suit a wide variety of applications
in the different standards and filters recommended by ITU-R 624-4 and SMPTE170-M. The
available –3dB bandwidths are 1.1, 1.3, 1.6 and 1.9 MHz.
Narrow bandwidths are useful against cross-luminance artifacts while wide bandwidths
allow to keep higher chroma contents.
Figure 13. 1.1 MHz chroma filter
Fr equ enc y (MHz )
Amplitude (dB)
Frequency (MHz)
Functional description STw8009/STw8019
18/65
Figure 14. 1.3 MHz chroma filter
Figure 15. 1.6 MHz chroma filter
Figure 16. 1.9 MHz chroma filter
Amplitu de (dB)
Frequency (MHz)
Amplitu de (dB)
Fr equ enc y (MHz )
Amplitude (dB)
Frequency (MHz)
STw8009/STw8019 Functional description
19/65
4.9 Composite video signal generation
The composite video signal is created by adding the luminance and the chrominance
components. A saturation function is included in the adder to avoid overflow errors.
4.10 MacrovisionTM copy protection
The chrominance luminance and composite video signals and RGB video signals can be
altered according to the MacrovisionTM copy protection Revision 7.01 and Revision 6.1.
This process is controlled via the I²C bus. A programming document is av ailable to those
customers who have executed a license or a non-disclosure agreement with Macrovision
Corporation.
For all relevant information or document please contact:
Macrovision Corp oration:
2830 De La Cruz Blvd.
Santa Clara, CALIFORNIA 95050
USA
www.macrovision.com
4.11 TV/VCR plug insertion detection
Plugdet ball is used to detect the connection of a TV or a VCR. The host can read the status
in a dedicated register in standby and active modes.
4.12 DAC
STw80x9 outputs generate Composite video signal on one output or Y/C video signals on
two outputs.
Two embedded 10-bit DACs allow the STw80x9 to directly drive 37.5 Ohms loads on each
output.
4.13 Power management
Power management includes power supplies, reset signals, clock gating and a set of
dedicated pins and registers. Power management is used to set the STw80x9 in different
operating modes.
Functional description STw8009/STw8019
20/65
4.13.1 Operating modes
STw80x9 can be in the following operating modes.
●OFF
– 1.2V/1.4V, 1.8V/2.8V, 2.8V/3.3V are not present.
– All values from STw80x9 registers are lost.
●Sleep
– 1.2V/1.4V, 1.8V/2.8V, 2.8V/3.3V are present.
– The suspend signal is active.
– The DA Cs are in their minimum power consumption mode.
– All values from the STw80x9 registers are lost.
– The 27 MHz pixel clock must be activated
●Standby
– All power supplies are present: 1.2V/1.4V, 1.8V/2.8V, 2.8V/3.3V.
– The 27 MHz pixel clock must be activated.
– The suspend signal is inactive.
– STw80x9 is set in standby mode by programming the Control and power
Management Unit registers (Reg 128 to 132) through the 2 wire serial MPU
interface. STw80x9 saves the register values.
– The other registers (Reg 00 to 109) are not accessible in this mode.
– The DA Cs are in their minimum power consumption mode.
– This mode is a low power state that enables a fast switching to active mode.
●Active
– All power supplies are present: 1.2V/1.4V, 1.8V/2.8V, 2.8V/3.3V.
– STw80x9 receives the 27 MHz pixel clock.
– The suspend signal is inactive.
– STw80x9 is placed in active mode by programming the control and power
management unit registers (Reg 128 to 132), through the 2 wire serial MPU
interface. STw80x9 saves the register values.
– The 27 MHz pixel clock is distributed in all STw80x9.
The DACs are supplied by the 2.8 /3.3 V and can be individually activated or deactivated.
For example only one DAC in CVBS output and both DACs in Y/C output.
STw8009/STw8019 Functional description
21/65
4.13.2 Mode transition diagram
The following mode transition diagram shows the main possible transitions between the
modes and the actions.
Figure 17. Mode transition diagram
Transitions to OFF mode
The possible transitions are indicated in
Figure 17: Mode transition diagram
10 in dotted
lines. No internal data needs to be saved and the STw80x9 can be turned OFF from any
mode. The only restriction is to comply with the power supply rules described here after.
Transition from OFF mode to Sleep mode then to Active mode
Power up must be done by starting from OFF to Sleep mode and then from Sleep to Active
mode. Sleep to Standby is not possibl e.
The host sends the order for the STw80x9 to switch from Sleep to Active mode by releasing
Suspend ball. The device then generates a reset sequence to the DENC part.
Transition from Active mode to Sleep mode
In Sleep mode, DENC is not powered on. When Suspend signal changes from « 0 » to
« 1 », the device goes from Active to Sleep mode and an internal Reset signal is generated
by the Control Power Unit management to the DENC part. This signal has a 6 pixclk
durati on (pixcl k = 27 M Hz) .
OFF
Sleep
Standby
Active
Registers maintained
Power consu mp tion reduced
DEN C c lock gated
DACs in low power
Normal oper a t i on
All functions available
DACs dynamically used on demand
No Power s upply applied
Registers values los t All supplies are applied but STw8009
suspend is asse rted
Register values lost
DAC in low power mo de
STw8009 loos es all its
registers and configuration
when entering Sleep mode
A PORn reset occurs
afte r the 1.2 V & 1.8 V
have been applied
No need to reset or
reconfigure DENC
in either direc tion
Suspend = « 0 »
By Sw
Suspend = « 1 »
OFF
Sleep
Standby
Active
Registers maintained
Power consu mp tion reduced
DEN C c lock gated
DACs in low power
Normal oper a t i on
All functions available
DACs dynamically used on demand
No Power s upply applied
Registers values los t All supplies are applied but STw8009
suspend is asse rted
Register values lost
DAC in low power mo de
STw8009 loos es all its
registers and configuration
when entering Sleep mode
STw8009 loos es all its
registers and configuration
when entering Sleep mode
A PORn reset occurs
afte r the 1.2 V & 1.8 V
have been applied
No need to reset or
reconfigure DENC
in either direc tion
No need to reset or
reconfigure DENC
in either direc tion
Suspend = « 0 »
By Sw
Suspend = « 1 »
A PORn reset occurs
after the 1.2V, 1.8V
and CLK27 M
have been applied
(see AN2347).
Functional description STw8009/STw8019
22/65
Transition between Standby and Active modes
Transitions between these two modes are applied by software configuration through I2C
interface.
Supply management
At power up, supplies must be applied according to the following sequence:
VddIO1, VddIO2 (1.8V/2.8V) then,
Vdd (1.2V/1.4V) then,
VccA1, VccA2, VccA3, VccA4 (2.8V/3.3V)
and removed according to the following sequence:
VccA1, VccA2, VccA3, VccA4 (2.8V/3.3V) then,
Vdd (1.2V/1.4V) then,
VddIO1, VddIO2 (1.8V/2.8V)
4.14 JTAG interface
To ease the integration of STw80x9 in its system application, a JTAG interface is availab le.
STw8009/STw8019 Control registers
23/65
5 Control registers
5.1 Register addresses
Table 3. Register addresses
Name Type N° Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
DENC registers
configuration0 R/W 00 std1 std0 sync2 sync1 sync0 polh polv freerun
configuration1 R/W 01 blkli flt1 flt0 sync_ok coki setup_main [0] [0]
configuration2 R/W 02 nintrl enrst bursten xxx selrst rstosc_buf valrst1 valrst0
configuration3 R/W 03 main_
entrap trap_4.43 [0] [0] main_del_
en val_422_ck
_mux xxx [0]
configuration4 R/W 04 syncin_ad1 syncin_ad0 syncout_ad
1syncout_ad
0aline hue_en xxx xxx
configuration5 R/W 05 selrst_inc bkdac2 bkdac1 [0] [0] [0] [0] dacinv
configuration6 R/W 06 softreset jump dec_ninc free_jump cfc1 cfc0 [0] maxdyn
configuration7 R/W 07 [0] [0] [0] xxx [0] bypass_
sync_corr [0] [0]
configuration8 R/W 08 ph_rst_
mode1 ph_rst_
mode0 xxx val_422_
mux blk_all xxx xxx xxx
Status R 09 hok atfr fldct2 flsct1 fldct0 jump
increment_dfs R/W 10 d23 d22 d21 d20 d19 d18 d17 d16
increment_dfs R/W 11 d15 d14 d13 d12 d11 d10 d9 d8
increment_dfsR/W12d7d6d5d4d3d2d1 d0
phase_dfs R/W 13 xxx xxx xxx xxx xxx xxx o23 o22
phase_dfs R/W 14 o21 o20 o19 o18 o17 o16 o15 o14
dac2mult R/W 17 dac2_mult5 dac2_mult4 dac2_mult3 dac2_mult2 dac2_mult1 dac2_mult0 [1] [0]
reserved R/W 20 xxx xxx xxx xxx xxx xxx xxx xxx
line_reg R/W 21 ltarg8 ltarg7 ltarg6 ltarg5 ltarg4 ltarg3 ltarg2 ltarg1
line_reg R/W 22 ltarg0 lref8 lref7 lref6 lref5 lref4 lref3 lref2
line_reg R/W 23 lref1 lref0 - - - - - -
Reserved R 24 - - - - - - - -
reserved xxx 45 xxx xxx xxx xxx xxx xxx xxx xxx
... ... ... ... ... ... ... ... ... ... ...
reserved xxx 63 xxx xxx xxx xxx xxx xxx xxx xxx
c_mult & ttx R/W 65 c_mult3 c_mult2 c_mult1 c_mult0 [0] xxx [0] bcs_en_main
BrightnessR/W69b7b6b5b4b3b2b1 b0
Contrast R/W70c7c6c5c4c3c2c1 c0
SaturationR/W71s7s6s5s4s3s2s1 s0
Chroma_coef_0 R/W 72 flt_s plg_div1 plg_div0 c0(4) c0(3) c0(2) c0(1) c0(0)
Chroma_coef_1 R/W 73 xxx c8(8) c1(5) c1(4) c1(3) c1(2) c1(1) c1(0)
Chroma_coef_2 R/W 74 xxx c2(6) c2(5) c2(4) c2(3) c2(2) c2(1) c2(0)
Control registers STw8009/STw8019
24/65
Chroma_coef_3 R/W 75 xxx c3(6) c3(5) c3(4) c3(3) c3(2) c3(1) c3(0)
Chroma_coef_4 R/W 76 c4(7) c4(6) c4(5) c4(4) c4(3) c4(2) c4(1) c4(0)
Chroma_coef_5 R/W 77 c5(7) c5(6) c5(5) c5(4) c5(3) c5(2) c5(1) c5(0)
Chroma_coef_6 R/W 78 c6(7) c6(6) c6(5) c6(4) c6(3) c6(2) c6(1) c6(0)
Chroma_coef_7 R/W 79 c7(7) c7(6) c7(5) c7(4) c7(3) c7(2) c7(1) c7(0)
Chroma_coef_8 R/W 80 c8(7) c8(6) c8(5) c8(4) c8(3) c8(2) c8(1) c8(0)
configuration9 R/W 81 main_del3 main_del2 main_del1 main_del0 xxx plg_div_y1 plg_div_y0 flt_ys
luma_coef_0 R/W 82 xxx xxx l8(8) l0(4) l0(3) l0(2) l0(1) l0(0)
luma_coef_1 R/W 83 l9(9) l9(8) l1(5) l1(4) l1(3) l1(2) l1(1) l1(0)
luma_coef_2 R/W 84 l6(8) l2(6) l2(5) l2(4) l2(3) l2(2) l2(1) l2(0)
luma_coef_3 R/W 85 l7(8) l3(6) l3(5) l3(4) l3(3) l3(2) l3(1) l3(0)
luma_coef_4 R/W 86 l4(7) l4(6) l4(5) l4(4) l4(3) l4(2) l4(1) l4(0)
luma_coef_5 R/W 87 l5(7) l5(6) l5(5) l5(4) l5(3) l5(2) l5(1) l5(0)
luma_coef_6 R/W 88 l6(7) l6(6) l6(5) l6(4) l6(3) l6(2) l6(1) l6(0)
luma_coef_7 R/W 89 l7(7) l7(6) l7(5) l7(4) l7(3) l7(2) l7(1) l7(0)
luma_coef_8 R/W 90 l8(7) l8(6) l8(5) l8(4) l8(3) l8(2) l8(1) l8(0)
luma_coef_9 R/W 91 l9(7) l9(6) l9(5) l9(4) l9(3) l9(2) l9(1) l9(0)
configuration11 R/W 93 [0] [0] [1] [0] xxx main_if_del xxx xxx
configuration12 R/W 94 [0] [0] [0] [0] [0] ennotch [0] xxx
configuration13 R/W 95 [0] [0] dac12_conf [0] [0] [0] [0] [1]
hue_control R/W 105 hue_cont
(7) hue_cont
(6) hue_cont
(5) hue_cont
(4) hue_cont
(3) hue_cont
(2) hue_cont
(1) hue_cont(0)
dac1_mult R/W 106 - - dac1_mult5 dac1_mult4 dac1_mult3 dac1_mult2 dac1_mult1 dac1_mult0
Chroma_delay R/W 108 [0] [0] [0] [0] main_chr_
del3 main_chr_
del2 main_chr_
del1 main_chr_del
0
Chroma_delay_
en R/W 109 - - - - - [0] [0] main_chr_
del_en
Control & power management unit registers
Cpmu_conf0 R/W 128 - - - - - - - standby
Cpmu_conf1 R/W 129 - - - - - - - cpmuswrst
dac2ctrl R/W 130 - - - - - poff1 notzero-d1 pedestalOnd
1
dac1ctrl R/W 131 - - - - - poff2 notzerod2 pedestalOnd
2
Plugdet R 132 - - - - - - - loadD
I_test0 R/W 133 - - - - - - - -
Table 3. Register addresses
Name Type N° Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
STw8009/STw8019 Control registers
25/65
5.2 Description
(*) = DEFAULT mode when not_reset pin is active (LOW level)
Caution: All binary values quoted should be understood as MSB........LSB
5.2.1 DENC registers
polh: synchro: active edge of HSYNC selection (when input) or polarity of HSYNC (when
output)
(*) 0 = HSYNC is a negative pulse (128 Tpix_clk wide) or falling edge is active
1 = HSYNC is a positive pulse (128 Tpix_clk wide) or rising edge is active
polv: synchro: active edge of ODDEV/VSYNC selection (when input)
0 = falling edge of ODDEV flags start of field1 (odd field) or VSYNC is active low
(*) 1 = rising edge of ODDEV flags start of field1 (odd field) or VSYNC is active high
REGISTER 0 configuration0 Address: 0x0000 Type: R/W
content std1 std0 sync2 sync1 sync0 polh polv freerun
default 10010010
Table 4. std1, std0
std1 std0 Standard selected
00PAL BDGHI
0 1 PAL N (see bit set-up)
(*) 1 0 NTSC M(1)
1. Standard on hardware reset is NTSC; any standard modification selects automatically the right
parameters for correct subcarrier generation.
11PAL M
Table 5. sync2, sync1, sync0
sync2 sync1 sync0 Configuration
0 0 0 ODDEV-only bas ed SLAVE mode (fram e lock ed )
0 0 1 ‘ F’ based SLAVE mode (frame locked)
(*) 0 1 0 ODDEV+HSYNC based SLAVE mode (line locked)
1 0 0 VSYNC-only based SLAVE mode (frame locked)(1)
1. In VSYNC-only based slave mode (sync[2:0 ]=”100”), HSYNC is nevertheless needed as an input.
1 0 1 VSYNC+HSYNC based SLAVE mode (line locked)
1 1 0 MASTER mode
1 1 1 AUTOTEST mode (colour bar pattern)
Control registers STw8009/STw8019
26/65
freerun:
(*) 0 = disabled
1 = enabled
Note: This bit is taken into account in ODDEV-only or VSYNC-only based slave modes and is
irrelevant for other synchronization modes.
blkli: Vertical Blanking Interval selection for active video lines area
(*) 0 = (‘partial blanking’) Only the follo wing lines inside Vertical Interval are blanked
1 = “full blanking” All lines inside VBI are blanked
flt[1:0]: U/V Chroma filter bandwidth selection
sync_ok: availability of sync signals (analog and digital) in case of input synchronization
loss with no free-run active (i.e. freerun=0)
(*) 0 = no synchro output signals
1 = output synchro signals available on YS, CVBS and, when applicable, HSYNC (if
output port), ODDEV (if output port): i.e same behavior as free-run except that video
outputs are blanked in the active portion of the line.
coki: color killer
(*) 0 = color ON
1 = color suppressed on CVBS output signal (CVBS=YS) but color still present on C
output. For color suppression on chroma DAC ‘C’, see register 5 bit bkdac1.
REGISTER 1 configuration1 Address: 0x0001 Type: R/W
content blkli flt1 flt0 sync_ok coki setup_
main
default 010001[0][0]
NTSC-M: lines [1; 9], [263(half); 272] (525-SMPTE)
PAL-M: lines [523; 6], [260(half); 269] (525-CCIR)
Other PAL: lines [623(half); 5], [311; 318] (625-CCIR)
NTSC-M: lines [1; 19], [263(half); 282] (525-SMPTE)
PAL-M: lines [523; 16], [260(half); 279] (525-CCIR)
Other PAL: lines [623(half); 22], [311; 335] (625-CCIR)
Table 6. Register 1
flt1 flt0 3dB bandwidth Typical application
00 f
-3dB=1.1MHz low def NTSC filter
01 f
-3dB=1.3MHz low def PAL filter
(*) 1 0 f-3dB=1.6MHz high def. NTSC filter (ATSC compliant) & PAL
M/N (ITU-R 624.4 compliant)
11 f
-3dB=1.9MHz high def. PAL filter: Rec 624 - 4 for PAL BDG/I
compliant.
STw8009/STw8019 Control registers
27/65
setup_main: pedestal
0 = Blanking level and black level are identical on all lines.
(e.g.: Argentinian PAL-N, Japan NTSC-M, PAL-BDGHI)
(*) 1 = Black level is 7.5 IRE above blanking level on all lines outside VBI
(e.g. Paraguayan and Uruguayan PAL-N).
In all cases, gain factor is adjusted to obtain the required levels for chrominance.
Note: Depending on the different output configurations chosen by programming bit from
dac12_conf, pedestal is automatically selected on it.
nintrl: non-interlaced mode select
(*) 0 = interlaced mode (625/50 or 525/60 system)
1 = non-interlaced mode(2x312/50 or 2x262/60 system)
enrst: cyclic update of DDFS phase
(*) 0 = no cyclic subcarrier phase reset
1 = cyclic subcarrier phase reset depending of valrst1 and valrst0 (see below)
bursten: chrominance burst control
0 = burst is turned off on CVBS, chrominance output is not affected
(*) 1 = burst is enabled
selrst: selects set of reset values for Direct Digital Frequency Synthesizer accumulator
(*) 0 = hardware reset values for phase of subcarrier oscillator (see description of
registers 13 and14 for values)
1 = loaded reset values selected (see contents of registers 13 and 14)
rstosc_buf: software phase reset of DDFS (Direct Digital Frequency Synthesizer) buffer
(*) 0
1 = when a 0-to-1 transition occurs either the hard-wired default phase value or the
value loaded in Reg. 13-14 (according to bit ‘selrst’) is put to the phase buffer. This
value is then loaded into accumulator (phase of sub-carrier) when the bits
‘ph_rst_mode’ from register 8 are programmed or when standard changes or when a
soft reset occur.
Note: Bit ‘rstosc_buf’ is automatically set back to ‘0’ after the buffer is loaded.
valrst [1:0]
Note: valrst[1:0] is taken into account only if bit ‘enrst’ is set.
REGISTER 2 configuration2 Address: 0x0002 Type: R/W
content nintrl enrst bursten xxx selrst rstosc_
buf valrst1 valrst0
default 00100000
Control registers STw8009/STw8019
28/65
Resetting the oscillator means forcing the value of the phase accumulator to its nominal
value to avoid accumulating errors due to the finite number of bits used internally. The value
at which the accumulator is reset is either the hard-wired default phase value or the value
loaded in Reg. 13-14 (according to bit ‘selrst’) at which a 00, 900, 1800, or 2700 correction is
applied according to the field and line at which the reset is performed.
main_entrap: enable trap filter
(*) 0 = trap filter disabled
1 = trap filter enabled
trap_4.43: trap filter centered frequency value selection
(*) 0 = trap filter centered around 3.58 MHz
1 = trap filter centered around 4.43 MHz
Note: ‘trap_4.43’ is taken into account only if bit ‘main_entrap’ is set.
main_del_en: Enable chroma to luma delay programming on cvbs output:
(*) 0 = disabled (DENC automatically set this delay)
1 = enab led (chroma to luma delay is programmed by del(3:0) bits from register 81.
Note: This delay affects only the cvbs output. The component outputs Y/C remain unaffected.
Refer to register 109 to program chroma to luma delay on Y/C output.
val_422_ck_mux: should be programmed to “0” only.
Table 7. valrst1 and valrst0 selection
valrst1 valrst0 selection
(*) 0 0 Automatic reset of the oscillator every line
0 1 Automatic reset of the oscillator every 2nd field
1 0 Automatic reset of the oscillator every 4th field
1 1 Automatic reset of the oscillator every 8th field
REGISTER 3 configuration3 Address: 0x0003 Type: R/W
content main_
entrap trap_4.43 main_del_
en val_422_
ck_ mux xxx
default 00[0][0]000[0]
STw8009/STw8019 Control registers
29/65
syncin_ad[1:0]: Adjustment of incoming sync signals.
Used to insure correct interpretation of incoming video samples as Y, Cr or Cb when the
encoder is slaved to incoming sync signals (inc. ‘F/H’ flags stripped off ITU-R656/D1 data).
syncout_ad[1:0]: Adjustment of outgoing sync signals.
Used to ensure correct interpretation of incoming video samples as Y, Cr or Cb when the
encoder is master and supplies sync signals.
aline: video active line duration control
(*) 0 = Full digital video line encoding (720 pixels - 1440 clock cycles)
1 = Active line duration follows ITU-R/SMPTE ‘analog’ standard requirements
hue_en: Enables variance in phase of the subcarrier, as programmed in register_105,
during active video with respect to the phase of the subcarrier during the color burst. Once
set, this bit is automatically reset to ‘0’.
(*) 0 = Disabled
1 = Enabled
REGISTER 4 configuration4 Address: 0x0004 Type: R/W
content syncin_
ad1 syncin_
ad0 syncout_
ad1 syncout_
ad0 aline hue_en xxx xxx
default 00000000
Table 8. syncin_ad[1:0]
syncin_ad1 syncin_ad0 Internal delay undergone by incoming sync
(*) 0 0 nominal*
0 1 +1 pix_ clk
1 0 +2 pix_ clk
1 1 +3 pix_ clk
Table 9. syncout_ad[1:0]
syncout_ad1 syncout_ad0 Delay added to sync signals before they are output
(*) 0 0 nominal*
0 1 +1 pix_ clk
1 0 +2 pix_ clk
1 1 +3 pix_ clk
Control registers STw8009/STw8019
30/65
selrst_inc: Choice of Digital Frequency Synthesizer increment after soft reset or when
ph_rst_mode = ‘01’ . See Register 8.
(*) 0 = hard wired value (depending on TV standard)
1 = soft (value from registers 10 to 12)
bkdacN: blanking of D ACs (N = 1 or 2)
(*) 0 = DAC N in normal operation
1 = DAC N input code forced to black level for C output or blanking level for Y or CVBS
output depending of dac12_conf bit of configuration13 register.
dacinv: ‘Inverts’ DAC codes to compensate for an inverting output stage in the application
(*) 0 = non inverted DAC inputs (outputs)
1 = inverted DAC inputs (outputs)
softreset: software reset
(*) 0 = no reset
1 = software reset
Note: Bit ‘softreset’ is automatically reset after internal reset generation. Software reset is active
during 4 PIX_CLK periods. When softreset is activated, all the de vice is reset as with
hardware reset except for the first nine user registers (registers 0 to 8:
configurations).Registers 10 up to 14 (increment and phase of oscillator), 25-30, 31-33 and
39-42 are never reset (hard/soft).
REGISTER 5 configuration5 Address: 0x0005 Type: R/W
content selrst_
inc bkdac2 bkdac1 dacinv
default 000[0][0][0][0]0
REGISTER 6 configuration6 Address: 0x0006 Type: R/W
content softreset jump dec_ninc free_
jump cfc1 cfc0 maxdyn
default 000100[0]0
Table 10. jump, dec_ninc, free_jump
jump dec_
ninc
free_
jump update mode
000
Normal mode (no line skip/insert capability)
ITU-R (CCIR): 313/312 or 263/262
non-interlaced: 312/312 or 262/262
(*) 0 x 1
Manual mode for line insert (“dec_ninc”=0) or skip
(“dec_ninc”=1) capability.
Both fields of all the frames following the writing of this value
are modified according to “lref” and “ltar” bits of registers 21-
22-23 (by default, “lref”=0 and “ltar”=1 which leads to normal
mode abov e ).
STw8009/STw8019 Control registers
31/65
Note: bit “jump” is automatically reset after use.
maxdyn: max dynamic magnitude allowed on YCrCb inputs for encoding.
(*) 0 = 10he x to EBhex for Y, 10hex to F0hex for chrominance (Cr,Cb)
1= 01hex to FEhex for Y, Cr and Cb
Note: In any case, EAV and SAV words are replaced by blanking values before being fed to the
luminance and Chrominance processing.
bypass_sync_corr: tst_dac bypass mode with sync correction. This is a test mode in which
data coming from port tst_dac can be output with or without sync correction and given to the
dacs.
(*) 0 = There is no sync correction applicable to the data coming from tst_dac.
1 = Sync correction takes place before setting the dacs provided tst_ana(0) is set to ‘1’.
Please note that in this case only 8 MSBs are used to generate a 10-bit sync corrected
output from the filter.
100
Automatic line insert mode.
The 2nd field of the frame following the writing of this value is
increased. Line insertion is done after line 245 in 525/60 and
after line 290 in 625/50.
“lref” and “ltar” are ignored.(1)
110
Automatic line skip mode.
The 2nd field of the frame following the writing of this value is
decreased. Line suppression is done after line 245 in 525/60
and after line 290 in 625/50.
“lref” and “ltar” are ignored.(1)
1 x 1 Not to be used.
1. Two lines are skipped (inserted) in 525/60 and four lines in 625/50 standards
Table 10. jump, dec_ninc, free_jump
jump dec_
ninc
free_
jump update mode
Table 11. cfc[1:0]: color frequency control via CFC line
cfc1 cfc0 update mode
(*) 0 0 disabled (update is done by loading of registers 10,11 and12)
0 1 update of increment for DDFS just after serial loading via CFC
1 0 update of increment for DDFS on next active edge of HSYNC
1 1 update of increment for DDFS just before next color burst
REGISTER 7 configuration7 Address: 0x0007 Type: R/W
content xxx bypass_
sync_
corr
default [0] [0] [0] 0 [0] 0 [0] [0]
Control registers STw8009/STw8019
32/65
Note: Bits ‘ph_rst_mode(1:0)’ are automatically set back to ‘00’ following the oscillator reset in
modes ‘01’ and ‘10’.
val_422_mux: should be programmed to “1” only after each reset.
blk_all: blanking of all video lines
(*) 0 = disabled
1 = enabled
(all inputs are ignored - 80hex instead of Cr and Cb and 10hex instead of Y and Y4)
(*) = DEFAULT mode when not_reset pin is active (LOW level)
hok: Hamming decoding of frame sync flag embedded within ITU-R656 / D1 compliant
YCrCb streams
0 = Consecutive errors
(*) 1 = A single or no error
Note: Signal quality detector is issued from Hamming decoding of EAV, SAV from YcrCb
atfr: Frame synchronization flag
(*) 0 = encoder not synchronized
1 = in slave mode: encoder synchronized
REGISTER 8 configuration8 Address: 0x0008 Type: R/W
content ph_rst_
mode1 ph_rst_
mode0 xxx val_422_
mux blk_all xxx xxx xxx
default 00100000
Table 12. ph_rst_mode[1:0]:sub-carrier phase reset
ph_rst_mode
1
ph_rst_mode
0update mode
(*) 0 0 disabled
01
enabled - phase is updated with value from phase buffer
register (see Reg2 bit rstosc_buf) at the beginning of the next
video line. In the mean time, the increment is updated with
hard or soft values depending on selreg_inc value (see
Register 5)
10
enabled - phase is updated with values from Registers 10 and
11, based on the next increment update from cfc (depending
on cfc loading moment and Register6 cfc(1:0) bits.
11
enab led - phas e is res et following th e de tec tion of rs t bi t on c fc
line, up to 9 pix_clk after loading of cfc’s LSB.
REGISTER 9 Address: 0x0009 Type: Read only
content hok atfr fieldct2 fieldct1 fieldct0 jump
STw8009/STw8019 Control registers
33/65
fieldct[2:0]: Digital field identification number
000 = indicates field 1
...
111 = indicates field 8
fieldct[0] also represents the odd/even information (odd=’0’, even=’1’)
jump: indicates whether a frame length modification has been programmed at ‘1’ from
programming of bit’ jump’ to end of frame(s) concerned.
(*)default = 0
Refer to register 6 and registers 21-22-23
These registers contain the 24-bit increment used by the DDFS if bit ‘selrst_inc’ equals ‘1’ to
generate the subcarrier phase i.e. the address that is supplied to the sine ROM. It therefore
allows to customize the subcarrier synthesized frequency.
1 LSB ~ 1.609325 Hz
The procedure to validate the usage of these registers rather than the hard-wired values is
the following:
- Load the registers with the required value
- Set bit ‘selrst_inc’ to 1 (Reg 5)
- Perform a software reset (Reg 6)
Note: 1 The values loaded in Reg10-12 are taken into account after a software reset, and ONLY IF
bit ‘selrst_inc’=’1’ (Reg. 5).
2 These registers are never reset and must be ex plicitly written into to contain sensible
information.
3 On hardware or on software reset with selrst_inc=’0’, the DDFS is initialized with a
hardwired increment, independent of Registers 10-12. These hardwired values being out of
any user register cannot be r ead.
These values are:
REGISTERS 10, 11, 12 Increment_dfs Address:
0x000A to 0x000C Type: R/W
register_10 d23 d22 d21 d20 d19 d18 d17 d16
register_11 d15 d14 d13 d12 d11 d10 d9 d8
register_12 d7 d6 d5 d4 d3 d2 d1 d0
Value Frequency synthesized
d(23:0): 21F07C hexa for NTSC M f=3.5795452 MHz
d(23:0): 2A098B hexa for PAL B ,G,H,I,N f
=4.43361875MHz
d(23:0): 21F694 hexa for PAL N f=3.5820558 MHz
d(23:0): 21E6F0 hexa for PAL M
f=3.575 611 49 MHz
Control registers STw8009/STw8019
34/65
Static phase offset for digital frequency synthesizer (10 bits only)
Under certain circumstances (detailed below), these registers contain the 10 MSBs of the
value with which the phase accumulator of the DDFS is initialized after a 0-to-1 transition of
bit ‘rstosc_buf’ of Reg 2, or after a standard change, or when cyclic phase readjustment has
been programmed (see bits valrst[1:0] of Reg 2). The 14 remaining LSBs loaded into the
accumulator in these cases are all ‘0’s (this allows to define the phase reset value with a
0.35o accuracy ) .
The procedure to validate the usage of these registers rather than the hard-wired values is
the following:
- Load the registers with the required value
- Set bit ‘selrst’ to 1 (Reg 2)
- Perform a software reset or set ‘rstosc_buf’ to 1 (Reg 2) (to put soft phase value into a
tampon register) and ph_rst_mode[1:0]
Note: 1 Registers 13-14 are never reset and must be explicitly written into to contain sensible
information.
2 If bit ‘selrst’=0 (e.g. after a hardware reset) the phase offset used ev ery time the DDFS is re
initialized is a hard-wired value. The hard-wired values being out of any register , they cannot
be read out.
Reset values:
D9C000hex for PAL BDGHI, N, M,
1FC000hex for NTSC-M,
000000hex (blue lines)
REGISTERS 13, 14 Phase_dfs Address:
0x000D to 0x000E Type: R/W
register_13 xxx xxx xxx xxx xxx xxx o23 o22
register_14 o21 o20 o19 o18 o17 o16 o15 o14
STw8009/STw8019 Control registers
35/65
dac2_mult[5:0]: multiplying factor on dac2_c digital signal before the D/A converters with
0.78% step.
These registers may be used to jump from a reference line (end of that line) to a target line
of the SAME FIELD. However, not all lines can be skipped or repeated with no problems
and, if needed, this functionality should BE USED WITH CAUTION.
lref[8:0] contains, in binary format, the reference line from which a jump is required.
ltarg[8:0] contains the target line as a binary number.
Default values: lref[8:0]:= 000000000 and ltarg[8:0]:= 000000001.
REGISTER 17 dac2 multiplying
factors Address: 0x0011 Type: R/W
content dac2_
mult5 dac2_
mult4 dac2_
mult3 dac2_
mult2 dac2_
mult1 dac2_
mult0
default 100000[1][0]
Table 13. dac2_mult[5:0]: multiplying factor on dac2_c digital signal
dac2_mult[5:0]
000000 75.00%
000001 75.78%
000010 76.56%
000011 77.34%
... ... ... ... ...
(*)100000 100%
... ... ... ... ...
1 1 1 1 1 1 124.22%
REGISTERS 21, 22, 23
clig_i_reg = ltarg[8:0] and lref[8:0]
Address:
0x0015 to 0x0017 Type: R/W
register 21 ltarg8 ltarg7 ltarg6 ltarg5 ltarg4 ltarg3 ltarg2 ltarg1
register 22 ltarg0 lref8 lref7 lref6 lref5 lref4 lref3 lref2
register 23 lref1lref0------
Control registers STw8009/STw8019
36/65
c_mult[3:0]: multiplying f actor of C digital output (before D/A convertors) and of color part of
CVBS signal.
bcs_en_main: Brightness, Contrast and Saturation control by Registers 69 to 71 on 4:4:4
video input
0 = disab le
(*) 1 = enable
To adjust the luminance intensity of the display video image, the following formula is used:
Yout = Yin + b –128
Yin is the 8-bit input luminance
Yout is the result of ‘Brightness’ operation (still on 8 bits)
This value is saturated at 235 (16) or 254 (1) according to register6 bit ‘maxdyn’,
b: brightness (unsigned value with center at 128, default 128)
REGISTER 65 C_mult&ttxs Address: 0x0041 Type: R/W
content c_mult3 c_mult2 c_mult1 c_mult0 xxx bcs_en_
main
default 0000[0]0[0]1
Table 14. c_mult[3:0]: multiplying factor of C digital output
c_mult3 c_mult2 c_mult1 c_mult0 factor value (c_mult)
(*) 0 0 0 0 1.000000 (1.000000 Dec.)
0 0 0 1 1.000001 (1.015625 Dec.)
0 0 1 0 1.000010 (1.031250 Dec.)
0 0 1 1 1.000011 (1.046875 Dec.)
... ... ... ... ...
1 1 1 1 1.001111 (1.234375 Dec.)
REGISTER 69 Brightness Address: 0x0045 Type: R/W
content b7 b6 b5 b4 b3 b2 b1 b0
default 10000000
STw8009/STw8019 Control registers
37/65
Adjustment of the relative diff erence between high and low intensity luminance values of the
displayed image is made according to the following formula:
Yin is the 8-bit input luminance,
Yout is the result of ‘Contrast’ operation (still on 8 bits)
This value is saturated at 235 (16) or 254 (1) according to register6 bit ‘maxdyn’,
c: contrast (2’s complement value from -128 to 127, default 0)
To adjust the color intensity of the displayed video image, the following formula is used:
Crin, Cbin 8-bit input chroma,
Crout, Cbout the result of ‘Saturation’ operation (still on 8 bits)
This value is saturated at 240 (16) or 254 (1) according to bit ‘maxdyn’ (Reg 6),
s: saturation value (unsigned value with centre at 128, default 128)
REGISTER 70 Contrast Address: 0x0046 Type: R/W
content c7 c6 c5 c4 c3 c2 c1 c0
default 00000000
REGISTER 71 Saturation Address: 0x0047 Type: R/W
content s7 s6 s5 s4 s3 s2 s1 s0
default 10000000
Yo u t Yi n 128–()c128+()
128
------------------------------------------------- 1 2 8+=
Cbout sCbin 128–()
128
----------------------------------- 128+=
Crout sCrin 128–()
128
---------------------------------- 1 2 8+=
Control registers STw8009/STw8019
38/65
:
Values from these registers are used only when bit main_flt_s (Reg 72) is set to 1. Bit
main_flt_s has the highest priority over the rest. With main_flt_s bit set to 1, all bits from
main_plg_div[1:0] need to be programmed to the chroma coefficients. Alternatively, the
coefficients default values are loaded depending on the selected mode or the selected filter
type in a particular mode with flt(1:0) bits from register 1.
The values are soft loaded when main_flt_s = 1. The value to be loaded in the register
should be the actual coefficient value + an offset. The hardware will internally subtract this
offset to get the actual coefficient value.
main_flt-s default value: 0
The main_plg_div value is chosen according to the sum of all the coefficients.
Offset change before loading to user register:
REGISTERS 72 to 80
Chroma filter coefficients
Address:
0x0048 to 0x0050 Type: R/W
Table 15. Chroma main_coef_[8:0]
chroma_main_coef_0 reg_
72 main_flt_s main_plg
_div1 main_plg
_div0 coef0(4) coef0(3) coef0(2) coef0(1) coef0(0)
chroma_main_coef_1 reg_
73 xxx coef8(8) coef1(5) coef1(4) coef1(3) coef1(2) coef1(1) coef1(0)
chroma_main_coef_2 reg_
74 xxx coef2(6) coef2(5) coef2(4) coef2(3) coef2(2) coef2(1) coef2(0)
chroma_main_coef_3 reg_
75 xxx coef3(6) coef3(5) coef3(4) coef3(3) coef3(2) coef3(1) coef3(0)
chroma_main_coef_4 reg_
76 coef4(7) coef4(6) coef4(5) coef4(4) coef4(3) coef4(2) coef4(1) coef4(0)
chroma_main_coef_5 reg_
77 coef5(7) coef5(6) coef5(5) coef5(4) coef5(3) coef5(2) coef5(1) coef5(0)
chroma_main_coef_6 reg_
78 coef6(7) coef6(6) coef6(5) coef6(4) coef6(3) coef6(2) coef6(1) coef6(0)
chroma_main_coef_7 reg_
79 coef7(7) coef7(6) coef7(5) coef7(4) coef7(3) coef7(2) coef7(1) coef7(0)
chroma_main_coef_8 reg_
80 coef8(7) coef8(6) coef8(5) coef8(4) coef8(3) coef8(2) coef8(1) coef8(0)
main_plg_div = 11 when sum of coeffs = 4096
main_plg_div = 10 when sum of coeffs = 2048
main_plg_div = 01 when sum of coeffs = 1024, (default)
main_plg_div = 00 when sum of coeffs = 512
chroma_main_coef0 = Actual value + 16;
chroma_main_coef1 = Actual value + 32;
chroma_main_coef2 = Actual value + 64;
chroma_main_coef3 = Actual value + 32;
STw8009/STw8019 Control registers
39/65
Def ault values:
The FIR symmetrical filter has the following response:
The filter working frequency is comprised in the r ange [pix_clk, 27 MHz] and the filtering is
done on upsampled signal (half pix_clk to pix_clk frequency by padding by zeros).
chroma_main_coef4 = Actual value + 32;
chroma_main_coef5 = Actual value + 32;
chroma_main_coef6 = Actual value
chroma_main_coef7 = Actual value
chroma_main_coef8 = Actual value
chroma_main_coef0[4:0] = 10001 means c0 = 1.
chroma_main_coef1[5:0] = 100111 means c1 = 7;
chroma_main_coef2[6:0] = 1010100 means c2= 20;
chroma_main_coef3[6:0] = 1000111 means c3 = 39;
chroma_main_coef4[7:0] = 01011111 means c4 = 63;
chroma_main_coef5[7:0] = 01110111 means c5 = 87;
chroma_main_coef6[7:0] = 01101100 means c6 = 108;
chroma_main_coef7[7:0] = 01111011 means c7 = 123;
chroma_main_coef8[8:0] = 010000000 means c8 = 128.
Hz() c0c1z1– c2z2– c +7z7– c8z8– c7z9– c+2z14–c1z15–c0z16–
+++ +++ + +=
Control registers STw8009/STw8019
40/65
main_del[3:0]: delay on chroma path with reference to luma path, on the encoded signal
coming from the main outputs. The delay value varies with modes, delays are hardwired to
have different delays in different modes. If the delays are to be made programmable, set bit
main_del_en to 1 (Reg 03) to enable soft delay from main_del[3:0].
If main_del_en = 0 then the delays used are:
Bit flt_ys enables the software loading capability of luma coefficients. Values from registers
82 to 91 are used only when bit “flt_ys” of this register is set to 1. Bit “flt_ys” has the highest
priority. With this bit set to 1, all bits from plg_div_y[1:0] must be programmed as luma
coefficients. Alternatively, the default values of the coefficients are loaded. The luma
coefficients are mode and standard independent.
flt_ys default value is “0”.
REGISTER 81 Configuration 9 Address: 0x0051 Type: R/W
content main_de
l3 main_de
l2 main_de
l1 main_de
l0 xxx plg_div_
y1 plg_div_
y0 flt_ys
default 00100010
Table 16. main_del[3:0]
main_
del3
main_
del2
main_
del1
main_
del0
Delay on chroma path with reference to luma path
encoding [One pixel corresponds to 2/fpix_clk]
(*)0010- 0.5 pixel delay on chroma
0011- 1 pixel delay on chroma
0100- 1.5 pixel delay on chroma
0101- 2 pixel delay on chroma
1100+ 2.5 pixel delay on chroma
1101+ 2 pixel delay on chroma
1110+ 1.5 pixel delay on chroma
1111+ 1 pixel delay on chroma
Others 1 0 pixel delay on chroma (reference delay)
Others 0 + 0.5 pixel delay on chroma
main_del[3:0] = 0010 when mode = PAL/NTSC in 4:2:2 format on CVBS
main_del[3:0] = 0001 when mode = PAL/NTSC in 4:4:4.
plg_div_y = 00 when sum of coefficients = 256
plg_div_y = 01 when sum of coefficients = 512 (default)
plg_div_y = 10 when sum of coefficients = 1024
plg_div_y = 11 when sum of coefficients = 2048
STw8009/STw8019 Control registers
41/65
Values from these registers are used only when bit flt_ys of register 81 is set to 1.
The coefficient values of luma_coef_0 to luma_coef_7 should be entered as 2’s
complement, and the rest as normal positive values. The hardware will internally generate
normal positive values. Default values:
The FIR filter is symmetrical with the following response:
Working frequency of this filter is the one of pix_clk (27, 24.545454 or 29.5 MHz), and the
filtering is done on upsampled signal (half pix_clk to pix_clk frequency by padding by zeros).
REGISTERS 82 to 91: luma filter
coefficients
Address:
0x0052 to 0x005B Type: R/W
Table 17. Luma_coef_[0:9]
luma_coef_0 reg_82 xxx xxx l8(8) l0(4) l0(3) l0(2) l0(1) l0(0)
luma_coef_1 reg_83 l9(9) l9(8) l1(5) l1(4) l1(3) l1(2) l1(1) l1(0)
luma_coef_2 reg_84 l6(8) l2(6) l2(5) l2(4) l2(3) l2(2) l2(1) l2(0)
luma_coef_3 reg_85 l7(8) l3(6) l3(5) l3(4) l3(3) l3(2) l3(1) l3(0)
luma_coef_4 reg_86 l4(7) l4(6) l4(5) l4(4) l4(3) l4(2) l4(1) l4(0)
luma_coef_5 reg_87 l5(7) l5(6) l5(5) l5(4) l5(3) l5(2) l5(1) l5(0)
luma_coef_6 reg_88 l6(7) l6(6) l6(5) l6(4) l6(3) l6(2) l6(1) l6(0)
luma_coef_7 reg_89 l7(7) l7(6) l7(5) l7(4) l7(3) l7(2) l7(1) l7(0)
luma_coef_8 reg_90 l8(7) l8(6) l8(5) l8(4) l8(3) l8(2) l8(1) l8(0)
luma_coef_9 reg_91 l9(7) l9(6) l9(5) l9(4) l9(3) l9(2) l9(1) l9(0)
a0 = luma_coef_0[4:0] = 00001 means +1;
a1 = luma_coef_1[5:0] = 111111 means -1;
a2 = luma_coef_2[6:0] = 1110111 means -9;
a3 = luma_coef_3[6:0] = 0000011 means +3;
a4 = luma_coef_4[7:0] = 00011111 means +31;
a5 = luma_coef_5[7:0] = 11111011 means -5;
a6 = luma_coef_6[8:0] = 110101100 means -84;
a7 = luma_coef_7[8:0] = 000000111 means +7;
a8 = luma_coef_8[8:0] = 100111101 means +317;
a9 = luma_coef_9[9:0] = 0111111000 means +504;
Hz() a0a1z1– a2z2– a+8z8– a9z9– a8z10– a+2z16–a1z17–
a
+++ ++ + + +=
Control registers STw8009/STw8019
42/65
main_if_del: The delay on the luma comparing to chroma in CVBS and S-VHS outputs.
This delay is 5 clock cycles (2 7 MHz clock).
(*) 0 = enabled
1 = disabled
ennotch: Notch filtering on the cvbs output
(*) 0 = disabled
1 = enabled
dac12_conf: Please refer to the table below for all combinations to be observed at D ACs.
Defines the phase shift in the subcarrier during active video with respect to the subcarrier
phase during the color burst. Once enabled by Register_4(2) “hue_en”, phase variation
would be in a range of +/- 22.324 degrees with increments of 0.17578127.
Note: Pulse the Register_4(2) “hue_en” to make sure that a value programmed in this register is
effective immediately after programming Hue_control. Once enabled, to disable any phase
shift in active subcarrier wrt burst, write the default value into the Hue_control register
followed by a pulse on Register_4(2) “hue_en”.
REGISTER 93 Configuration 11 Address: 0x005D Type: R/W
content xxx main_if_
del xxx xxx
default [0][0][1][0]1000
REGISTER 94 Configuration 12 Address: 0x005E Type: R/W
content xxx xxx xxx ennotch xxx
default [0]0 0 0[0]0[0]0
REGISTER 95 Configuration 13 Address: 0x005F Type: R/W
content dac12_
conf
default [0] [0] 0 [0] [0] [0] [0] [1]
Table 18. dac12_conf
dac12_conf dac1 dac2
(*)0 Y C
1 CVBS
REGISTER 105 Hue control Address: 0x0069 Type: R/W
content hue_
cont (7) hue_
cont (6) hue_con
t (5) hue_
cont (4) hue_
cont (3) hue_
cont (2) hue_
cont (1) hue_
cont (0)
default 00000000
STw8009/STw8019 Control registers
43/65
hue_control [6:0]: absolute value of phase adjustment, range 1 to 127.
LSB (0x01) implies 0.17578127 degrees, 0x7F imply 22.324 degrees
hue_control [7]: Sign of phase
1 = +ve; (*) 0 = -ve
(*)
dac1_mult(5:0): multiplying factor on dac1_y digital signal before the D/A converters with
0.78% step.
main_chr_del[3:0]: delay on chroma path with reference to luma path on encoded
component outputs. The delay value varies with modes and the delays are hardwired to
have different delays in different modes. If the delays are to be made programmable make
bitmain_chr_del_en = 1 (Reg 109). That way, soft delay from main_chr_del[3:0] is enabled.
“00000000” : No phase shift
“10000000” : No phase shift
“11111111” : +22.324 degrees phase
“01111111” : -22.324 degrees phase
REGISTER 106 dac1 multiplying factor Address: 0x006A Type: R/W
content xxx xxx dac1_
mult5 dac1_
mult4 dac1_
mult3 dac1_
mult2 dac1_
mult1 dac1_
mult0
default 00100000
Table 19. dac1_multi[5:0]
dac1_mult[5:0]
000000 75.00%
000001 75.78%
000010 76.56%
000011 77.34%
... ... ... ... ...
(*)100000 100%
... ... ... ... ...
111111 124.22%
REGISTER 108 Chroma Delay Address: 0x006C Type: R/W
content main_chr_
del3 main_chr_
del2 main_chr_
del1 main_chr_
del0
default [0] [0] [0] [0] 0 0 1 0
Control registers STw8009/STw8019
44/65
If main_chr_del_en = 0 then the delays used are:
main_chr_del[3:0] = 0010 when mode = PAL/NTSC in 4:2:2 format on CVBS.
main_chr_del[3:0] = 0001 when mode = PAL/NTSC in 4:4:4
main_chr_del_en: Enable of luma to chroma delay on the 4:4:4 component outputs.
(*) 0 = disabled (DENC automatically sets this delay)
1 = enabled (chroma to luma delay is programmed by main_chr_del[3:0] bits (Reg
108).
Note: This delay affects only the component Y/C. The cvbs output remains unaffected. Refer to
register 3 to program chroma to luma delay on cvbs output signal.
Table 20. main_chr_del[3:0]
main_
chr_ del3
main_
chr_ del2
main_
chr_ del1
main_
chr_ del0
Delay on chroma path with reference to luma
path encoding [One pixel corresponds to
/fpix_clk]
(*)0010- 0.5 pixel delay on chroma
0011- 1 pixel delay on chroma
0100- 1.5 pixel delay on chroma
0101- 2 pixel delay on chroma
1100+ 2.5 pixel delay on chroma
1101+ 2 pixel delay on chroma
1110+ 1.5 pixel delay on chroma
1111+ 1 pixel delay on chroma
Others 1 0 pixel delay on chroma (reference delay)
Others 0 + 0.5 pixel delay on chroma
REGISTER 109 Chroma Delay Enable Address: 0x006D Type: R/W
content main_chr
_del_en
default -----[0][0]0
STw8009/STw8019 Control registers
45/65
5.2.2 Control & power management unit registers
Control and power management unit
standby: In this mode the analog subsystem is supplied by the 1.2V/1.4V and the
2.8V/3.3V, but the DACs are set in pow er down mode, via poff[1:2] bits (Reg 130 & 131).
Digital to analog data conversion is disabled.
(*) 0 = disabled (active mode)
1 = standby
Control and power management unit reset
cpmuswrst: Control and power management unit reset
(*) 0 = disabled
1 = control and power management unit software reset
Note: Bit cpmuswrst is automatically reset to its default value after internal reset generation and
the I2C data transfer is stopped. This reset is kept available for a CLK cycle.
poff1: DAC2 power off, then turn off DAC2 is in a low power consumption mode
0 = disabled (DAC2 active)
(*) 1 = turned off
Note: As Default value is “1”, Digital processor must write “0” when going from sleep or standby to
active mode.
notzerod1 : null digital data inputed on DAC2
0 = independently of what is coming from the digital part, “0000000000” is forced on
DAC2 input.
(*) 1 = disabled, values issued from DENC are transmitted to DAC2.
pedestalOnd1 : Black level video pedestal active on DAC2
(*) 0 = disabled
1 = video pedestal active
REGISTER 128 Configuration0 Address: 0x0080 Type: R/W
content standby
default 00000000
REGISTER 129 Configuration 1 Address: 0x0081 Type: R/W
content cpmuswrst
default 0 000000 0
REGISTER 130 DAC1 control Address: 0x0082 Type: R/W
content poff1 notzerod1 pedestal
Ond1
default 0 00001 1 0
Control registers STw8009/STw8019
46/65
poff2: DAC1 power off, then turn off DAC1 is in a low power consumption mode.
0 = disabled (DAC1 active)
(*)1 = turned off
Note: As Default value is “1”, Digital processor must write “0” when going from sleep or standby to
active mode.
notzerod2 : null digital data input on DAC1
0 = independently of that is coming from the digital part, “0000000000” is forced on
DAC1 input.
(*)1 = disabled, values issued from DENC are transmitted to DAC1.
pedestalOnd2: Black level video pedestal active on DAC1
(*) 0 = disabled
1 = video pedestal active
LoadD: Reports Plugdet Ball status. Unless otherwise specified all voltages are referenced
to GND.
0 = Plugdet ball voltage less than VIL
1 = Plugdet ball voltage higher than VIH
REGISTER 131 DAC2 control Address: 0x0083 Type: R/W
content poff2 notzerod2 pedestal
Ond2
default 00000 1 1 0
REGISTER 132 Plugdet Address: 0x0084 Type: R
content LoadD
default --------
STw8009/STw8019 Bus interface
47/65
6 Bus interface
6.1 2 wire serial MPU control interface (I2C compatible)
STw80x9 serial MPU control interface is compliant with I2C standard and acts only as a
slave device. It supports 100 kHz and 400 kHz speeds. In addition to the basic definition of
the I2C standard (SDA & SCL signals), STw80x9 serial MPU interface has an additional
“Add” input used to select one out of two slave addresses.
The device supports 7-bit and 10-bit addresses.
7-bit address mode
In Write mode, sev eral data can be sent without re-initializing a transfer and data is written in
succes siv e regist ers . (
Figure 18: 2-wire serial MPU control interface f ormat (I2C compatible)
/ 7-bit addre ss es
).
In Read mode: (
Figure 18
).
●Double transaction read: The operation is split into to transactions:
The first one is a write that transmits the desired address. The I2C interface memorizes
the address of the register.
The second transfer is a read that can be repeated to read successive registers. After
each read byte and except for the last one, the master issues an “acknowledge”. The
master indicates that it is reading the last byte by issuing a “no acknowledge” instead of
an “acknowledge”.
●Single transaction read:
As opposed to the double transaction, instead of stopping the first transaction and
starting the second one, the transactions are combined with a repeated start condition.
Table 21. STw80x9 addresses
7-bit addresses 10-bit addresses
Read Write Read Write
Add pin = 0 01000001 01000000 00001000001 00001000000
Add pin = 1 01000011 01000010 00001000011 00001000010
Bus interface STw8009/STw8019
48/65
Figure 18. 2-wire serial MPU control interface format (I2C compatible) / 7-bit addresses
10 bits address mode
In Write mode, sev er al data can be sent without re-initializing a transf er, in this case, data is
written in successive registers. (
Figure 19: 2-wire serial MPU control interface format (I2C
compatible) / 10-bit addresses
)
In Read mode: (
Figure 19
)
●Double transaction read:
The operation is split into two transactions:
The first one is a write that transmits the desired address. The I2C interface memorizes
the address of the register.
The second transfer is a read that can be repeated to read successive registers. After
each read byte and except for the last one, the master issues an “acknowledge”. The
master indicates that it is reading the last byte by issuing a “no acknowledge” instead of
an “acknowledge”.
Note: Only the higher part of the address is sent again before sending the read indication.
●Single transaction read:
As opposed to the double transaction, instead of stopping the first transaction and
starting the second one, the transactions are combined with a repeated start condition.
S STw8009 slave address r/w ASTw8009 register address A
Write (0)
* Write operation (7 bits addresses)
SStart condition PStop condi tion A/NA Acknowledge / No Acknoledge
PSTw8009 register data A
Can be repeated n times to write in successive registers
From mas ter to s lave From slave to master
S STw8009 slave address r/w ASTw8009 register address A P
Write (0)
* Double transaction read
S STw8009 slave address r/w ASTw8009 register data A/NA P
Read (1) Can be repeated n times to read in successive registers
Sr Repeated start condition
S STw8009 slave address r/w ASTw8009 register address A
Write (0)
* Single transaction read
STw8009 register data P
Can be repeated n times
to read in successive registers
Sr STw8009 slave address r/w
Read (1)
A/NA
S STw8009 slave address r/w ASTw8009 register address A
Write (0)
* Write operation (7 bits addresses)
SStart condition PStop condi tion A/NA Acknowledge / No Acknoledge
PSTw8009 register data A
Can be repeated n times to write in successive registers
From mas ter to s lave From slave to master
S STw8009 slave address r/w ASTw8009 register address A P
Write (0)
* Double transaction read
S STw8009 slave address r/w ASTw8009 register data A/NA P
Read (1) Can be repeated n times to read in successive registers
Sr Repeated start condition
S STw8009 slave address r/w ASTw8009 register address A
Write (0)
* Single transaction read
STw8009 register data P
Can be repeated n times
to read in successive registers
Sr STw8009 slave address r/w
Read (1)
A/NA
STw8009/STw8019 Bus interface
49/65
Figure 19. 2-wire serial MPU control interface format (I2C compatible) / 10-bit addresses
Figure 20. 2-wire serial MPU control interface timing
8 LSBs A2 STw8009 register address A
* Write operation (10 bits addresses)
PSTw8009 register data A
Can be repeated n times to write in successive registers
STw8009 register address A P
* Double transaction read
Sr r/w A3 STw8009 register data P
Read (1) Can be repeated n times to read in successive registers
STw8009 register address A3
* Single transaction read
STw8009 register data P
Can be repeated n times
to read in successive registers
Sr r/w
Read (1)
S 11110 r/w A1
Write (0)
2MSBs
8 LSBs A2S 11110 r/w A12MSBs
STw8009 slave address
Write (0)
STw8009 slave address
11110 2MSBs8 LSBs A2S 11110 r/w A12MSBs
Write (0)
STw8009 slave address
8 LSBs A2S 11110 r/w A12MSBs
Write (0)
STw8009 slave address
11110 2MSBs A
A/NA
A/NA
SStart condition PStop condition A/NA Ack n ow ledge / No Acknoledg e From master to slav e From slave to master
Sr Repeated start condition
8 LSBs A2 STw8009 register address A
* Write operation (10 bits addresses)
PSTw8009 register data A
Can be repeated n times to write in successive registers
STw8009 register address A P
* Double transaction read
Sr r/w A3 STw8009 register data P
Read (1) Can be repeated n times to read in successive registers
STw8009 register address A3
* Single transaction read
STw8009 register data P
Can be repeated n times
to read in successive registers
Sr r/w
Read (1)
S 11110 r/w A1
Write (0)
2MSBs
8 LSBs A2S 11110 r/w A12MSBs
STw8009 slave address
Write (0)
STw8009 slave address
11110 2MSBs8 LSBs A2S 11110 r/w A12MSBs
Write (0)
STw8009 slave address
8 LSBs A2S 11110 r/w A12MSBs
Write (0)
STw8009 slave address
11110 2MSBs A
A/NA
A/NA
SStart condition PStop condition A/NA Ack n ow ledge / No Acknoledg e From master to slav e From slave to master
Sr Repeated start condition
tBUF
tHD_STA
tLOW
tR
S=StartP=Stop
SCLK
SDA
tF
tHD_DAT
tHI GH
tSU_DAT
tSU_STA tHD_STA
Sr=Start repeated
tSU_STO
P = Stop
Bus interface STw8009/STw8019
50/65
6.2 YcbCr bus
Figure 21. YcbCr bus format
Figure 22. Data bus timing
Cb4Y3Cr2Y2Cb2Y1Cr0Y0Cb0
Clk
YCbCr[7:0]
Table 22. YcBCr data bus timing (
Figure 22
)
Symbol Parameter Test conditions Min. Typ. Max. Unit
CLK27M Clock frequency 27 MHz
CLKdc Clock duty cycle 45 55 %
th Data input hold time 3 ns
ts Data input setup time 1.5 ns
CCIR data
CLK27M
ts: CCIR data to CLK27M setup time
th: CCIR data to CLK27M hold time
1V8
GND
th
ts
STw8009/STw8019 Electrical characteristics
51/65
7 Electrical characteristics
7.1 Absolute maximum rating
Unless otherwise specified: TA=+25°C, all voltages are referenced to GND.
7.2 Operating conditions
Unless otherwise specified: TA=+25°C, all voltages are referenced to GND.
Table 23. Absolute maximum ratings
Symbol Parameter Value Unit
Vdd Digital core supply voltage -0.3 to +1.65 V
VddIO I/O digital supply voltage -0.3 to +3.6 V
VccA Analog supply voltage -0.3 to +3.8 V
VDCdig DC input voltage on any digital pin -0.3 to +2.0 V
VDCana DC input voltage on any analog pin -0.3 to +3.8 V
Pmax Maximum power dissipation 700 mW
Tstg Storage temperature range -40 to 125 °C
Vesd Electrostatic
discha rge vol tag e
Human body model(1)
1. HBM tests have been performed in compliance with JESD22-A114-B and ESD STM 5.1-2001.HBM
-2 to +2 KV
Charge device
model(2)
2. CDM tests have been performed in compliance with CDM ANSI-ESD ST M5. 3.1-1999
-500 to +500 V
Table 24. Operating conditions
Symbol Parameter Min. Typ. Max. Unit
Vdd Digital core supply
voltage 1.08 1.2 1.47 V
VddIO I/O digital supply voltage 1.65 1.8 3.0 V
VccA Analog supply voltage 2.7 3.6 V
TAOperating temperature -30 +85 °C
Electrical characteristics STw8009/STw8019
52/65
7.3 Electrical and timing characteristics
Unless otherwise specified: TA=+25°C, all voltages are referenced to GND.
)
Table 25. 2 wire serial MPU control interface timing (
Figure 20
)
Symbol Parameter Test conditions Min. Typ. Max. Unit
fSCL Clock Frequency 400 kHz
tBUF Bus free time 1300 ns
tHD_STA Start condition hold time 600 ns
tfSDA & SCLK fall time 300 ns
tLOW SCLK pulse width low 1300 ns
trSDA & SCLK rise time 300 ns
tHIGH SCLK pulse width high 600 ns
tHD_DAT Data input hold time 0 ns
tSU_DAT Data input set up time 100 ns
tSU_STA Start condition set up
time 600 ns
tSU_STO Stop condition set up
time 600 ns
Table 26. Digital I/O interface
Symbol Parameter Test conditions Min. Typ. Max. Unit
VIL Input Low voltag e Al l digi tal inp uts 0.2*Vdd IO V
VIH Input High voltage All digital inputs 0.7*VddIO V
VOL Output Low level All digital outputs 0.1*VddIO V
VOH Output High level All digital outputs 0.8*VddIO V
IIL Input Lo w curr ent All digital inputs /
0V < Vin < VIL -10 10 µA
IIH Input H igh curren t All digital inputs /
VCCIO < Vin < VIH -10 10 µA
STw8009/STw8019 Electrical characteristics
53/65
Table 27. Power consumption/R load = 37.5 ohm
Symbol Parameter Test conditions Min. Typ. Max. Unit
PSLVdd Sleep mo de on Vdd Vdd = 1.2V
no 27 MHz clock 3µW
PSTVdd Stand by mode on Vdd Vdd = 1.2V 150 µW
PSTVcca Stand by mode on Vcca Vcca = 2.8V 1 µW
PACVdd Active mode on Vdd Vdd = 1.2 V
0, 1 or 2 DAC enabled 5mW
PACVddIO Active mode on VddIO VddIO = 1.8V 180 µW
PAC0Vcca Active mode on Vcca Vcca = 2.8V
no DAC enabled 2µW
PAC1Vcca Active mode on Vcca Vcca = 2.8V
1 DAC enable d 120 mW
PAC2Vcca Active mode on Vcca Vcca = 2.8V
2 DAC enable d 240 mW
Table 28. DAC & Video output characteristics / Rload = 37.5 ohm – F = 27 MHz – Rext = 2.4 kohm
Symbol Parameter Test conditions Min. Typ. Max. Unit
RDAC Resolution 10 Bits
INLDAC Integral non linearity -1.5 +1.5 LSB
DNLDAC Differential non linearity -0.8 +0.8 LSB
VFR1 Full ra nge outpu t v o ltage Pedes tal on lo w 1.14 1.21 1.27 V
VFR2 Full ra nge outpu t voltage Pedestal on high 1.24 1.31 1.38 V
SFDR Spurious free dynamic
range F = 1 MHz / 1 Vpp TBD 49 dB
SNR Signal to noise ratio With white level 55 62 dB
PSRR Power supply rejectio n
ratio 2.8 V sup ply / F = 200 Hz 65 dB
DiffG Differential gain
Average measurements
on VSA R&S on
NTC7comp and CCIR17
line test patterns
1%
DiffPh Differential phase
Average measurements
on VSA R&S on
NTC7comp and CCIR17
line test patterns
1deg
Application information STw8009/STw8019
54/65
8 Application information
Figure 23. Typical application schematic
75 W Optional
L.P. fi lter
75 W Optional
L.P. fi lter
ESD
Protection
75 W
75 W
STw8009
Digital
Processor
C/CVBS
Y
Vdd VIO VccA
Rext
2.4 K
Clk
YCbCr[0:7]
PORn
2 wire MPU bus
Suspend
TV set
or
VCR
Video
Interface
Only for S-VHS
Vdd VIO VccA
Cvd Cio Cca
Supply
100 nF / One capacitor
connected on each ball sup ply
Gnd
75 W Optional
L.P. fi lter
75 W Optional
L.P. fi lter
ESD
Protection
75 W
75 W
STw8009
Digital
Processor
C/CVBS
Y
Vdd VIO VccA
Rext
2.4 K
Clk
YCbCr[0:7]
PORn
2 wire MPU bus
Suspend
TV set
or
VCR
Video
Interface
Only for S-VHS
Vdd VIO VccA
Cvd Cio Cca
Supply
100 nF / One capacitor
connected on each ball sup ply
Gnd
Ω
Ω
Ω
Ω
STw8009/STw8019 Color test pattern waveforms
55/65
9 Color test pattern waveforms
Figure 24. NTSC composite
Color test pattern waveforms STw8009/STw8019
56/65
Figure 25. NTSC S-video
STw8009/STw8019 Color test pattern waveforms
57/65
Figure 26. PAL composite
Color test pattern waveforms STw8009/STw8019
58/65
Figure 27. PAL S-video
STw8009/STw8019 Package mechanical data
59/65
10 Package mechanical data
10.1 TFBGA 49 balls
Table 29. TFBGA 4x4x1.2 mm
Dimensions (mm)
Reference Min Typ Max
A1.2
A1 0.15
A2 0.8
A3 0.2
A4 0.6
b 0.25 0.3 0.35
D 3.85 4.00 4.15
D1 3.00
E 3.85 4.00 4.15
E1 3.00
e0.50
F0.5
ddd 0.08
eee 0.15
fff 0.05
Package mechanical data STw8009/STw8019
60/65
Figure 28. TFBGA 49 balls 4 x 4 x 1.2 mm body size
STw8009/STw8019 Package mechanical data
61/65
10.2 VFBGA 49 balls
Table 30. VFBGA 3x3x1.0 mm - 49 balls - Pitch 0.4 ball 0.25
Dimensions (mm)
Reference Min Typ Max
A(1)
1. VFBG A stands for Very thin profile Fine pitch Ball Grid Array.
Very thin profile: 0.80mm<A<=1.00mm/Fine pitch: e<1.00mm
The maximum total package height is calculated by the following methodology
1.00
A1 0.125
A2 0.615
A3 0.18
A4 0.45
b(2)
2. The typical ball diameter before mounting is 0.25mm
0.22 0.26 0.30
D 2.95 3.00 3.05
D1 2.40
E 2.95 3.00 3.05
E1 2.40
e0.40
F0.30
ddd 0.08
eee(3)
3. VFBGA with 0.40mm ball pitch is not yet registered in JEDEC publications.
0.13
fff(4)
4. The tolerance of position that controls the location of the balls with respect to datum A and B. For each ball
there is a cylindrical tolerance zone eee perpendicular to datum C and located on true position with respect
to datum A and B as defined by e. The axis perpendicular to datum C of each ball must lie within this
tolerance zone.
The tolerance of position that controls the location of the balls within the matrix with respect to each other.
For each ball there is a cylindrical tolerance zone perpendicular to datum C and located on true position
as defined by e. The axis perpendicular to datum C of each ball must lie within this tolerance zone. Each
tolerance zone in the array is contained entirely in the respective zone eee above.
The axis of each ball must lie simultaneously in both tolerance zones.
0.04
A2Typ A1Typ A12A32A42
++tolerancevalues
⎝⎠
⎛⎞
++
Package mechanical data STw8009/STw8019
62/65
Figure 29. VFBGA 49 balls 3 x 3 x 1.0 mm body size
Note: The terminal A1 corner must be identified on the top surface by using a corner chamfer, ink
or metallized markings, or other feature of package body or integral heatslug.
A distinguishing feature is allowable on the bottom surface of the package to identify the
terminal A1 corner. Exact shape of each corner is optional.
See
Note Note:
STw8009/STw8019 Ordering information
63/65
11 Ordering information
Table 31. Order codes
Part number Package Packing
STW8009B27 R/ LF TFBG A49 4x 4 Tr ay
STW8019B27 R/ LF TFBG A49 4x 4 Tr ay
STW8009B27T/LF TFBGA49 4x4 Tape and reel
STW8019B27T/LF TFBGA49 4x4 Tape and reel
STW8009BS3R/L F VFBGA49 3x3 Tra y
STW8019BS3R/L F VFBGA49 3x3 Tra y
STW8009BS3T/LF VFBGA49 3x3 Tape and reel
STW8019BS3T/LF VFBGA49 3x3 Tape and reel
Revision history STw8009/STw8019
64/65
12 Revision history
Table 32. Document revision history
Date Revision Changes
02-Feb-2006 1Initial release.
08-Mar-2006 2Correction in
Tab le 18: dac12_c onf on page 42
9-Jun-2006 3
Added
Section 4.5: Video timing
.
Corrected list of supported formats (NTSC-J, M).
Updated
Section 7.3: Electrical and timing characteristics
.
Added
Chapter 9: Color test pattern waveforms
.
Reverted Dac 1 into Dac 2 and Dac 2 into Dac 1.
Moved ordering information from the cover page to
Chapter 11:
Or dering in formation
.
Document status updated to final datasheet.
08-Mar-2007 4
Updated Tsg and Vesd values in
Table 23: Absolute maximum
ratings
and added table footnotes about CDM and HBM test
conditions.
Added DiffG and DiffPh in
Table 28: DAC & Video output
characteristics / Rload = 37.5 ohm – F = 27 MHz – Rext = 2.4 kohm
.
Updated the definition of CDM (charge device model) in
Table 23:
Absolute maximum ratings
.
Removed reference to TQFP64 on cover page.
21-Mar-2007 5
Updated
Figure 17: Mode trans iti on dia g r am
.
Reviewed the text in paragraph” transition from off mode to sleep
mode” in
Section 4 .13.2: Mode transition diagram
.
Updated “sleep mode” paragraph in
Section 4.13.1: Operating
modes
.
Added
Table 22
and
Figure 21
in
Section 6.2: YcbCr bus
.
15-Jun-2007 6Updated
Section 4.10: Macrovisi onTM copy protect ion
.
STw8009/STw8019
65/65
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