8602501XA - e2v - Product.Network

REVISIONS

LTR DESCRIPTION DATE (YR-MO-DA) APPROVED

A Outline letter, Y, case outline changed to F-11 for standardization.

Convert to military drawing format. Editorial changes throughout.

88-01-19 Michael A. Frye

B Make change to table I, table II, 1.2. 2, 3. 3, and 4.3. Add figure 5.

Editorial changes throughout. Make change to figure 4.

89-04-04 Michael A. Frye

C Updated boilerplate. Added device type 02. Removed CAGE 34335

from drawing and added CAGE 0DKS7. - glg

99-10-19 Raymond Monnin

D Added provisions for the addition of QD certified parts to drawing.

Added CAGE OC7V7 as supplier. - glg

00-02-03 Raymond Monnin

E Corrected marking paragraph 3.5, updated boilerplate paragraphs.

ksr 05-04-01 Raymond Monnin

F

Updated body of drawing to reflect current requirements. - glg

11-03-08 Charles Saffle

THE ORIGINAL FIRST PAGE OF THIS DRAWING HAS BEEN REPLACED

CURRENT CAGE CODE 67268

REV

SHEET

REV F F

SHEET 15 16

REV STATUS REV F F F F F F F F F F F F F F

OF SHEETS SHEET 1 2 3 4 5 6 7 8 9 10 11 12 13 14

PMIC N/A PREPARED BY

Sandra Rooney

DLA LAND AND MARITIME

COLUMBUS, OHIO 43218-3990

http://www.dscc.dla.mil

STANDARD

MICROCIRCUIT

DRAWING

CHECKED BY

D. A. DiCenzo

THIS DRAWING IS

AVAILABLE

FOR USE BY ALL

DEPARTMENTS

AND AGENCIES OF THE

DEPARTMENT OF DEFENSE

APPROVED BY

Nelson Hauck

MICROCIRCUITS, MEMORY,

DIGITAL, BIPOLAR, 16-WORD BY

4-BIT, 2-PORT, RAM,

MONOLITHIC SILICON

DRAWING APPROVAL DATE

31 MARCH 1986

REVISION LEVEL

F SIZE

A CAGE CODE

14933

86025

AMSC N/A

SHEET

1 OF

16

DSCC FORM 2233

APR 97 5962-E188-11

.

STANDARD

MICROCIRCUIT DRAWING

SIZE

A

86025

DLA LAND AND MARITIME

COLUMBUS, OHIO 43218-3990 REVISION LEVEL

F SHEET 2

DSCC FORM 2234

APR 97

1. SCOPE

1.1 Scope. This drawing describes device requirements for MIL-STD-883 compliant, non-JAN class level B microcircuits in

accordance with MIL-PRF-38535, appendix A.

1.2 Part or Identifying Number (PIN). The complete PIN is as shown in the following example:

86025 01 X X

⏐ ⏐ ⏐ ⏐

Drawing number Device type Case outline Lead finish

(see 1.2.1) (see 1.2.2) (see 1.2.3)

1.2.1 Device type(s). The device type(s) identify the circuit function as follows:

Device type Generic number Circuit

01 29705A 16-word by 4-bit, 2-port RAM, 30 ns

02 29705A-35 16-word by 4-bit, 2-port RAM, 35 ns

1.2.2 Case outline(s). The case outline(s) are as designated in MIL-STD-1835 and as follows:

Outline letter Descriptive designator Terminals Package style

X GDIP1-T 28 or CDIP2-T28 28 dual-in-line package

Y GDFP2-F28 28 flat package

3 CQCC1-N28 28 square chip carrier package

1.2.3 Lead finish. The lead finish is as specified in MIL-PRF-38535, appendix A.

1.3 Absolute maximum ratings.

Storage temperature ...................................................... -65°C to +150°C

Supply voltage to ground potential ................................. -0.5 V dc to +7.0 V dc

DC voltage applied to outputs for high output stage ........ -0.5 V dc to +VCC maximum

DC input voltage .............................................................. -0.5 V dc to +5.5 V dc

DC output current, into outputs ........................................ 30 mA

DC input current .............................................................. -30 mA to +5.0 mA

Maximum power dissipation (PD) 1/ ............................... 1.155 mW

Lead temperature (soldering, 10 seconds) ..................... +300°C

Thermal resistance, junction-to-case (θJC): ...................... See MIL-STD-1835

Junction temperature (TJ) ................................................ +175°C

1.4 Recommended operating conditions.

Supply voltage (VCC) ...................................................... +4.5 V dc to +5.5 V dc

Minimum high level input voltage (VIH) ........................... +2.0 V dc

Maximum low level input voltage (VIL) ............................ +0.8 V dc

Case operating temperature range (TC) ......................... -55°C to +125°C

2. APPLICABLE DOCUMENTS

2.1 Government specification, standards, and handbooks. The following specification, standards and handbooks form a part

of this drawing to the extent specified herein. Unless otherwise specified, the issues of these documents are those cited in the

solicitation or contract.

1/ Must withstand the added PD due to short circuit test; e.g., IOS.

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DEPARTMENT OF DEFENSE SPECIFICATION

MIL-PRF-38535 - Integrated Circuits, Manufacturing, General Specification for.

DEPARTMENT OF DEFENSE STANDARDS

MIL-STD-883 - Test Method Standard Microcircuits.

MIL-STD-1835 - Interface Standard Electronic Component Case Outlines.

DEPARTMENT OF DEFENSE HANDBOOKS

MIL-HDBK-103 - List of Standard Microcircuit Drawings.

MIL-HDBK-780 - Standard Microcircuit Drawings.

(Copies of these documents are available online at https://assist.daps.dla.mil/quicksearch/ or from the Standardization

Document Order Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094.)

2.2 Order of precedence. In the event of a conflict between the text of this drawing and the references cited herein, the text

of this drawing takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a

specific exemption has been obtained.

3. REQUIREMENTS

3.1 Item requirements. The individual item requirements shall be in accordance with MIL-PRF-38535, appendix A for non-

JAN class level B devices and as specified herein. Product built to this drawing that is produced by a Qualified Manufacturer

Listing (QML) certified and qualified manufacturer or a manufacturer who has been granted transitional certification to MIL-

PRF-38535 may be processed as QML product in accordance with the manufacturers approved program plan and qualifying

activity approval in accordance with MIL-PRF-38535. This QML flow as documented in the Quality Management (QM) plan

may make modifications to the requirements herein. These modifications shall not affect form, fit, or function of the device.

These modifications shall not affect the PIN as described herein. A "Q" or "QML" certification mark in accordance with MIL-

PRF-38535 is required to identify when the QML flow option is used. This drawing has been modified to allow the manufacturer

to use the alternate die/fabrication requirements of paragraph A.3.2.2 of MIL-PRF-38535 or other alternative approved by the

qualifying activity.

3.2 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall be as specified

in MIL-PRF-38535, appendix A and herein.

3.2.1 Terminal connections. The terminal connections shall be as specified on figure 1.

3.2.2 Truth table. The truth table shall be as specified on figure 2.

3.2.3 Logic diagram. The logic diagram shall be as specified on figure 3.

3.2.4 Case outlines. The case outlines shall be in accordance with 1.2.2 herein.

3.3 Electrical performance characteristics. Unless otherwise specified herein, the electrical performance characteristics are

as specified in table I and shall apply over the full case operating temperature range.

3.4 Electrical test requirements. The electrical test requirements shall be the subgroups specified in table II. The electrical

tests for each subgroup are described in table I.

3.5 Marking. Marking shall be in accordance with MIL-PRF-38535, appendix A. The part shall be marked with the PIN listed

in 1.2 herein. In addition, the manufacturer's PIN may also be marked.

3.5.1 Certification/compliance mark. A compliance indicator “C” shall be marked on all non-JAN devices built in compliance

to MIL-PRF-38535, appendix A. The compliance indicator “C” shall be replaced with a "Q" or "QML" certification mark in

accordance with MIL-PRF-38535 to identify when the QML flow option is used. For product built in accordance with A.3.2.2 of

MIL-PRF-38535, or as modified in the manufacturer’s QM plan, the “QD” certification mark shall be used in place of the "Q" or

"QML" certification mark.

STANDARD

MICROCIRCUIT DRAWING

SIZE

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TABLE I. Electrical performance characteristics.

Test Symbol Conditions

-55°C ≤ TC ≤ +125°C

+4.5 V≤ VCC ≤ +5.5 V

unless otherwise specified

Device

types Group A

subgroups

Limits Unit

Min Max

Output high voltage

VOH

VCC = minimum, IOH = -2.0 mA

VIN = VIH or VIL All 1, 2, 3 2.4 V

Output low voltage

VOL

VCC = minimum, IOL = 16 mA

VIN = VIH or VIL All 1, 2, 3 0.5 V

Input high level

VIH

Guaranteed input logical high

voltage for all inputs All 1, 2, 3 2 V

Input low level

VIL

Guaranteed input logical low

voltage for all inputs All 1, 2, 3 0.8 V

Input clamp voltage

VI

VCC = minimum, IIN = - 18 mA All 1, 2, 3 -1.5 V

Input low current

IIL

VCC = maximum, VIN = 0.5 V All 1, 2, 3 -0.36 mA

Input high current

IIH

VCC = maximum, VIN = 2.7 V All 1, 2, 3 20 µA

II

VCC = maximum, VIN = 5.5 V All 1, 2, 3 0.1 mA

Off state (high impedance)

output current

IO

VCC = maximum

VIN = VIH or VIL VO = 2.4 V All 1, 2, 3 20 µA

VO = 0.5 V -20

Output short circuit current

1/

IOS

VCC maximum + .5 V,

VO = 0.5 V All 1, 2, 3 -30 -85 mA

Power supply current

ICC

VCC = maximum

(Worst case ICC is

at minimum

temperature) 2/

TC = -55°C to

+125°C All 1, 2, 3 210 mA

TC = +125°C150

Functional tests

See 4.3.1c All 7,8A,8B

See footnotes at end of table.

STANDARD

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TABLE I. Electrical performance characteristics - Continued.

Test Symbol Conditions

-55°C ≤ TC ≤ +125°C

+4.5 V≤ VCC ≤ +5.5 V

unless otherwise specified

Device

types Group A

subgroups

Limits Unit

Min Max

Access time from: A address stable or

B address stable to: YA stable or YB

stable

tAA See figure 4 and 5

CL = 50 pF, LE = high 01 9, 10, 11 30 ns

02 35

Turn-on time from: AOE− or BOE−

low to: YA or YB stable

tON See figure 4 and 5

CL = 50 pF All 9, 10, 11 20 ns

Turn-off time from: AOE− or BOE−

high to: YA or YB off

tOFF See figure 4 and 5

CL = 5 pF 3/ All 9, 10, 11 20 ns

Reset time from: LOA − low

to: YA low

tRES See figure 4 and 5

CL = 50 pF All 9, 10, 11 20 ns

Latch enable time from: LE high

to: YA and YB stable

tEN See figure 4 and 5

CL = 50 pF 01 9, 10, 11 22 ns

02 30

Transparency 1 from: WE 1 and WE 2

low to: YA or YB

tPD1 See figure 4 and 5

CL = 50 pF, LE = high 01 9, 10, 11 35 ns

02 40

Transparency 2 from: D

to: YA or YB

tPD2 See figure 4 and 5

CL = 50 pF, LE = high 01 9, 10, 11 35 ns

02 40

Data setup time from: D stable

to: Either WE high

tS1 See figure 4 and 5

CL = 50 pF All 9, 10, 11 15 ns

Data hold time from: Either WE high

to: D changing

tH1 See figure 4 and 5

CL = 50 pF All 9, 10, 11 0 ns

See footnotes at end of table.

STANDARD

MICROCIRCUIT DRAWING

SIZE

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TABLE I. Electrical performance characteristics - Continued.

Test Symbol Conditions

-55°C ≤ TC ≤ +125°C

+4.5 V≤ VCC ≤ +5.5 V

unless otherwise specified

Device

types Group A

subgroups

Limits Unit

Min Max

Address setup time from: B stable

to: Both WE low

tS2 See figure 4 and 5

CL = 50 pF All 9, 10, 11 8 ns

Address hold time from: Either WE

high to: B changing

tH2 See figure 4 and 5

CL = 50 pF All 9, 10, 11 0 ns

Latch close before write begin 1 from:

LE low to: WE 1 low

tPD3 CL = 50 pF, WE 2 low

See figure 4 and 5

All 9, 10, 11 0 ns

Latch close before write begin 2 from:

LE low to: WE 2 low

tPD4 CL = 50 pF, WE 1 low

See figure 4 and 5

All 9, 10, 11 0 ns

Address set up before latch closes

from: A or B stable to : LE low

tS3 See figure 4 and 5

CL = 50 pF All 9, 10, 11 15 ns

Write pulse width 1

Input: WE ,

Pulse: High-low-high

tPW1 CL = 50 pF, WE 2 low

See figure 4 and 5

All 9, 10, 11 15 ns

Write pulse width 2

Input: WE 2,

Pulse: High-low-high

tPW2 CL = 50 pF, WE 1 low

See figure 4 and 5

All 9, 10, 11 15 ns

A latch reset pulse

Input: LOA −,

Pulse: High-low-high

tPW3 See figure 4 and 5

CL = 50 pF All 9, 10, 11 15 ns

Latch data capture

Input: LE

Pulse: Low-high-low

tPW4 See figure 4 and 5

CL = 50 pF All 9, 10, 11 18 ns

1/ Not more than one output should be shorted at a time. Duration of the sort circuit test should not exceed 1 second.

2/ All inputs grounded except AOE− and BOE− = 2.4 V

3/ Measured from 1.5V at the input to 0.5V change in the output level.

STANDARD

MICROCIRCUIT DRAWING

SIZE

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DLA LAND AND MARITIME

COLUMBUS, OHIO 43218-3990 REVISION LEVEL

F SHEET 7

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Device

type All

Case

outline X, Y, 3

Terminal

number Terminal symbol

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

D1

D0

WE 1

B0

B1

B2

B3

LOA −

LE

YB0

YA0

YB1

YA1

GND

YB2

YA2

YB3

YA3

BOE−

AOE−

A3

A2

A1

A0

WE 2

D3

D2

VCC

FIGURE 1. Terminal connections.

STANDARD

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Write control

WE 1

WE 2

Function RAM outputs at latch inputs

A-port B-port

L

X

H

L

H

X

Write D into B

No write

A data (A ≠ B)

(A = B) Input data

A data

Input data

B data

H = High L = Low X = Don't care

YA READ

Inputs

YA output

Function

AOE− LOA −LE

H

L

X

L

H

X

H

L

Z

L

A-port RAM data

NC

High impedance

Force YA low

Latches transparent

Latches retain data

H = High X = Don't care NC = No Change

L = Low Z = High impedance

YB READ

Inputs

YB output

Function

BOE− LE

H

L

X

H

L

Z

B-port RAM data

NC

High impedance

Latches transparent

Latches retain data

H = High X = Don't care NC = No Change

L = Low Z = High impedance

FIGURE 2. Truth tables.

STANDARD

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FIGURE 3. Logic diagram.

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THREE-STAT E OUTPUT

5.0 - VBE - VOL

R1 =

IOL + VOL/1K

NOTES:

1. CL = 50 pF includes scope probe, wiring and stray capacitances without device in text fixture.

2. S1, S2, and S3 are closed during function tests and all ac tests except output enable tests.

3. S1 and S3 are closed while S2 is open for ten high test.

S1 and S2 are closed while S3 is open for ten low test.

4. CL = 5 pF for output disable test (see table I, tOFF).

Pin label Test

circuit R1 R2

YA0 -YA3,

YB0 - YB3 A 230Ω 1 kΩ

FIGURE 4. Test output load configuration.

STANDARD

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Write Timing

FIGURE 5. Timing waveforms.

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Address access, reset timing

FIGURE 5. Timing waveforms - Continued.

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Read timing

Data to output timing

FIGURE 5. Timing waveforms - Continued.

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Three-state enable,disable timing

FIGURE 5. Timing waveforms - Continued.

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3.6 Certificate of compliance. A certificate of compliance shall be required from a manufacturer in order to be listed as an

approved source of supply in MIL-HDBK-103 (see 6.6 herein). The certificate of compliance submitted to DLA Land and

Maritime -VA prior to listing as an approved source of supply shall affirm that the manufacturer's product meets the

requirements of MIL-PRF-38535, appendix A and the requirements herein.

3.7 Certificate of conformance. A certificate of conformance as required in MIL-PRF-38535, appendix A shall be provided

with each lot of microcircuits delivered to this drawing.

3.8 Notification of change. Notification of change to DLA Land and Maritime -VA shall be required for any change that

affects this drawing.

3.9 Verification and review. DLA Land and Maritime, DLA Land and Maritime's agent, and the acquiring activity retain the

option to review the manufacturer's facility and applicable required documentation. Offshore documentation shall be made

available onshore at the option of the reviewer.

4. VERIFICATION

4.1 Sampling and inspection. Sampling and inspection procedures shall be in accordance with MIL-PRF-38535, appendix A.

4.2 Screening. Screening shall be in accordance with method 5004 of MIL-STD-883, and shall be conducted on all devices

prior to quality conformance inspection. The following additional criteria shall apply:

a. Burn-in test, method 1015 of MIL-STD-883.

(1) T est condition C or D. The test circuit shall be maintained by the manufacturer under document revision level control

and shall be made available to the preparing or acquiring activity upon request. The test circuit shall specify the

inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in method 1015

of MIL-STD-883.

(2) TA = +125°C, minimum.

b. Interim and final electrical test parameters shall be as specified in table II herein, except interim electrical parameter

tests prior to burn-in are optional at the discretion of the manufacturer.

4.3 Quality conformance inspection. Quality conformance inspection shall be in accordance with method 5005 of MIL-STD-

883 including groups A, B, C, and D inspections. The following additional criteria shall apply.

4.3.1 Group A inspection.

a. Tests shall be as specified in table II herein.

b. Subgroups 4, 5, and 6 in table I, method 5005 of MIL-STD-883 shall be omitted.

c. Subgroup 7 and 8 shall include verification of the truth table.

4.3.2 Groups C and D inspections.

a. End-point electrical parameters shall be as specified in table II herein.

b. Steady-state life test conditions, method 1005 of MIL-STD-883.

(1) Test condition C or D. The test circuit shall be maintained by the manufacturer under document revision level

control and shall be made available to the preparing or acquiring activity upon request. The test circuit shall

specify the inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in

method 1005 of MIL-STD-883.

(2) TA = +125°C, minimum.

(3) Test duration: 1,000 hours, except as permitted by method 1005 of MIL-STD-883.

STANDARD

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TABLE II. Electrical test requirements.

MIL-STD-883 test requirements Subgroups

(in accordance with

MIL-STD-883, method 5005,

table I)

Interim electrical parameters

( method 5004) ---

Final electrical test parameters

( method 5004) 1*, 2, 3, 7, 8, 9, 10, 11

Group A test requirements

( method 5005) 1, 2, 3, 7, 8, 9, 10, 11

Groups C and D end-point electrical

parameters ( method 5005)

1, 2, 3

* PDA applies to subgroup 1.

5. PACKAGING

5.1 Packaging requirements. The requirements for packaging shall be in accordance with MIL-PRF-38535, appendix A.

6. NOTES

6.1 Intended use. Microcircuits conforming to this drawing are intended for use for Government microcircuit applications

(original equipment), design applications, and logistics purposes.

6.2 Replaceability. Microcircuits covered by this drawing will replace the same generic device covered by a contractor-

prepared specification or drawing.

6.3 Configuration control of SMD's. All proposed changes to existing SMD's will be coordinated with the users of record for

the individual documents. This coordination will be accomplished using DD Form 1692, Engineering Change Proposal.

6.4 Record of users. Military and industrial users shall inform DLA Land and Maritime when a system application requires

configuration control and the applicable SMD. DLA Land and Maritime will maintain a record of users and this list will be used

for coordination and distribution of changes to the drawings. Users of drawings covering microelectronics devices (FSC 5962)

should contact DLA Land and Maritime -VA, telephone (614) 692-0544.

6.5 Comments. Comments on this drawing should be directed to DLA Land and Maritime -VA, Columbus, Ohio 43218-3990,

or telephone (614) 692-0540.

6.6 Approved sources of supply. Approved sources of supply are listed in MIL-HDBK-103. The vendors listed in MIL-

HDBK-103 have agreed to this drawing and a certificate of compliance (see 3.6 herein) has been submitted to and accepted by

DLA Land and Maritime -VA.

STANDARD MICROCIRCUIT DRAWING BULLETIN

DATE: 11-03-08

Approved sources of supply for SMD 86025 are listed below for immediate acquisition only and shall be added to MIL-

HDBK-103 and QML-38535 during the next revision. MIL-HDBK-103 and QML-38535 will be revised to include the

addition or deletion of sources. The vendors listed below have agreed to this drawing and a certificate of compliance

has been submitted to and accepted by DLA Land and Maritime -VA. This information bulletin is superseded by the

next dated revision of MIL-HDBK-103 and QML-38535. DLA Land and Maritime maintains an online database of all

current sources of supply at http://www.dscc.dla.mil/Programs/Smcr/.

Standard microcircuit

drawing PIN 1/ Vendor

CAGE number Vendor

similar PIN 2/

8602501XA 3/

0C7V7

3V146

AM29705A/BXA

29705/XA

29705/BXA

8602501YA 3/

0C7V7

3V146

AM29705A/BYA

29705/YA

29705/BYA

86025013A 3/

3V146 AM29705A/B3A

29705/B3A

8602502XA 0DKS7 GEM10702QXA

8602502YA 0DKS7 GEM10702QYA

86025023A 0DKS7 GEM10702Q3A

8602502XC 0DKS7 GEM10702QXC

8602502YC 0DKS7 GEM10702QYC

86025023C 0DKS7 GEM10702Q3C

1/ The lead finish shown for each PIN representing a hermetic package is

the most readily available from the manufacturer listed for that part. If the

desired lead finish is not listed contact the vendor to determine its availability.

2/ Caution. Do not use this number for item acquisition. Items acquired to this

number may not satisfy the performance requirements of this drawing.

3/ Not available from an approved source.

Vendor CAGE Vendor name

number and address

0DKS7 Sarnoff, David Research Center

201 Washington Road

Princeton, NJ 08540-6449

0C7V7 E2V Aerospace and Defense, Inc.

dba QP Semiconductor, Inc.

2945 Oakmead Village Court

Santa Clara, CA 95051

3V146 Rochester Electronics Inc.

16 Malcolm Hoyt Drive

Newburyport, MA 01950

The information contained herein is disseminated for convenience only and the

Government assumes no liability whatsoever for any inaccuracies in the

information bulletin.