256-Position, Two-Time Programmable,
I2C Digital Potentiometer
AD5170
Rev. G
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FEATURES
256-position digital potentiometer
Two-time programmable (TTP) set-and-forget resistance
setting allows second-chance permanent programming
Unlimited adjustments prior to one-time programming
(OTP) activation
OTP overwrite allows dynamic adjustments with user-
defined preset
End-to-end resistance: 2.5 kΩ, 10 kΩ, 50 kΩ, 100 kΩ
Compact 10-lead MSOP: 3 mm × 4.9 mm package
Fast settling time: tS = 5 μs typical in power-up
Full read/write of wiper register
Power-on preset to midscale
Extra package address decode pins: AD0 and AD1
Single supply: 2.7 V to 5.5 V
Low temperature coefficient: 35 ppm/°C
Low power: IDD = 6 μA maximum
Wide operating temperature: −40°C to +125°C
Evaluation board and software are available
Software replaces MicroConverter® in factory programming
applications
APPLICATIONS
Systems calibration
Electronics level setting
Mechanical trimmers replacement in new designs
Permanent factory PCB settings
Transducer adjustment of pressure, temperature, position,
chemical, and optical sensors
RF amplifier biasing
Automotive electronics adjustments
Gain control and offset adjustments
FUNCTIONAL BLOCK DIAGRAM
V
DD
GND
SDA
SCL
AD0
AD1
W
RDAC
REGISTER
ADDRESS
DECODE
SERIAL INPUT
REGISTER
B
A
FUSE
LINKS
12
8
04104-0-001
Figure 1.
GENERAL DESCRIPTION
The AD5170 is a 256-position, two-time programmable, digital
potentiometer1 that employs fuse link technology, giving users
two opportunities to permanently program the resistance setting.
For users who do not need to program the digital potentiometer
setting in memory more than once, the OTP feature is a cost-
effective alternative to EEMEM. The AD5170 performs the same
electronic adjustment function as mechanical potentiometers or
variable resistors with enhanced resolution, solid-state reliability,
and superior low temperature coefficient performance.
The AD5170 is programmed using a 2-wire, I2C®-compatible
digital interface. Unlimited adjustments are allowed before
permanently setting the resistance value, and there are two
opportunities for permanent programming. During OTP
activation, a permanent blow fuse command freezes the wiper
position (analogous to placing epoxy on a mechanical trimmer).
Unlike traditional OTP digital potentiometers, the AD5170 has
a unique temporary OTP overwrite feature that allows for new
adjustments even after the fuse is blown. However, the OTP setting
is restored during subsequent power-up conditions. This feature
allows users to treat these digital potentiometers as volatile poten-
tiometers with a programmable preset.
For applications that program the AD5170 at the factory, Analog
Devices, Inc., offers device programming software that runs on
Windows NT®, Windows® 2000, and Windows XP operating
systems. This software effectively replaces any external I2C con-
trollers, thus enhancing the time-to-market of the user’s systems.
1 The terms digital potentiometer, VR, and RDAC are used interchangeably.
AD5170
Rev. G | Page 2 of 24
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description......................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 4
Electrical Characteristics: 2.5 kΩ ............................................... 4
Electrical Characteristics: 10 kΩ, 50 kΩ, and 100 kΩ ............. 5
Timing Characteristics: 2.5 kΩ, 10 kΩ, 50 kΩ, and 100 kΩ... 7
Absolute Maximum Ratings............................................................ 8
ESD Caution.................................................................................. 8
Pin Configuration and Function Descriptions............................. 9
Typical Performance Characteristics ........................................... 10
Test Circuits..................................................................................... 14
Theory of Operation ...................................................................... 15
One-Time Programming (OTP) .............................................. 15
Programming the Variable Resistor and Voltage—Rheostat
Operation..................................................................................... 15
Programming the Potentiometer Divider—Voltage Output
Operation .................................................................................... 16
ESD Protection ........................................................................... 17
Terminal Voltage Operating Range ......................................... 17
Power-Up Sequence ................................................................... 17
Power Supply Considerations................................................... 17
Layout Considerations............................................................... 18
Controlling the AD5170................................................................ 19
Software Programming ............................................................. 19
Device Programming................................................................. 19
I2C Controller Programming.................................................... 21
I2C-Compatible, 2-Wire Serial Bus.......................................... 21
Level Shifting for Different Voltage Operation ...................... 22
Outline Dimensions ....................................................................... 23
Ordering Guide .......................................................................... 23
REVISION HISTORY
5/11—Rev. F to Rev. G
Changes to Equation 1 and Equation 2 ....................................... 16
Updated Outline Dimensions....................................................... 23
Changes to Ordering Guide .......................................................... 23
Changes to I2C Notice.................................................................... 24
5/09—Rev. E to Rev. F
Changes to Resistor Integral Nonlinearity, Table 1...................... 3
Changes to Full-Scale Error, Table 1.............................................. 3
Changes to Zero-Scale Error, Table 1............................................. 3
Changes to Table 10........................................................................ 19
Changes to Figure 46...................................................................... 20
12/08—Rev. D to Rev. E
Changes to Resistor Integral Nonlinearity, Table 1...................... 3
Changes to OTP Supply Voltage Parameter, Table 1.................... 3
Changes to OTP Voltage Parameter, Table 2 ................................ 5
Changes to Table 5............................................................................ 8
Changes to One-Time Programming (OTP) Section................ 14
Changes to Power Supply Considerations Section..................... 16
Change to Caption, Figure 49 ....................................................... 22
Changes to Ordering Guide .......................................................... 22
7/08—Rev. C to Rev. D
Changes to Power Supplies Parameter in Table 1 and Table 2 ... 3
Updated Fuse Blow Condition to 400 ms Throughout ............... 5
1/08—Rev. B to Rev. C
Updated Format..................................................................Universal
Changes to Table 1.............................................................................3
Changes to Table 2.............................................................................4
Changes to Table 3.............................................................................6
Changes to Table 5.............................................................................8
Inserted Figure 25........................................................................... 12
Changes to One-Time Programming (OTP) Section................ 14
Changes to Power Supply Considerations Section .................... 16
Deleted Figure 38 and Figure 39 .................................................. 17
Updated Outline Dimensions....................................................... 21
Changes to Ordering Guide.......................................................... 21
5/05—Rev. A to Rev. B
Changes to Table 1.............................................................................3
Changes to Table 2.............................................................................5
Changes to Pin Function Descriptions...........................................9
Changes to Figure 28...................................................................... 14
Changes to Power Supply Considerations Section .................... 17
Changes to I2C-Compatible 2-Wire Serial Bus Section............ 21
Added Level Shifting for Different Voltage Operation
Section.............................................................................................. 23
Added Figure 48 ............................................................................. 23
Updated Outline Dimensions....................................................... 24
Changes to Ordering Guide.......................................................... 24
AD5170
Rev. G | Page 3 of 24
11/04—Rev. 0 to Rev. A
Changes to Electrical Characteristics Table 1................................3
Changes to Electrical Characteristics Table 2................................4
Changes to One-Time Programming ..........................................12
Changes to Figure 37, Figure 38, and Figure 39 .........................14
Changes to Power Supply Considerations ...................................14
Changes to Figure 40 ......................................................................15
Changes to Layout Considerations ...............................................15
11/03—Revision 0: Initial Version
AD5170
Rev. G | Page 4 of 24
SPECIFICATIONS
ELECTRICAL CHARACTERISTICS: 2.5 kΩ
VDD = 5 V ± 10% or 3 V ± 10%, VA = VDD, VB = 0 V, −40°C < TA < +125°C, unless otherwise noted.
Table 1.
Parameter Symbol Conditions Min Typ1 Max Unit
DC CHARACTERISTICS—RHEOSTAT MODE
Resistor Differential Nonlinearity2 R-DNL RWB, VA = no connect −2 ±0.1 +2 LSB
Resistor Integral Nonlinearity2 R-INL RWB, VA = no connect −14 ±2 +14 LSB
Nominal Resistor Tolerance3 ∆RAB T
A = 25°C −20 +55 %
Resistance Temperature Coefficient (∆RAB/RAB)/∆T 35 ppm/°C
RWB (Wiper Resistance) RWB Code = 0x00, VDD = 5 V 160 200 Ω
DC CHARACTERISTICS—POTENTIOMETER DIVIDER
MODE (SPECIFICATIONS APPLY TO ALL VRs)
Differential Nonlinearity4 DNL −1.5 ±0.1 +1.5 LSB
Integral Nonlinearity4 INL −2 ±0.6 +2 LSB
Voltage Divider Temperature Coefficient (∆VW/VW)/∆T Code = 0x80 15 ppm/°C
Full-Scale Error VWFSE Code = 0xFF −14 −5.5 0 LSB
Zero-Scale Error VWZSE Code = 0x00 0 4.5 12 LSB
RESISTOR TERMINALS
Voltage Range5 V
A, VB, VW GND VDD V
Capacitance A, Capacitance B6 C
A, CB f = 1 MHz, measured to GND,
code = 0x80
45 pF
Capacitance W6 C
W f = 1 MHz, measured to GND,
code = 0x80
60 pF
Shutdown Supply Current7 I
A_SD V
DD = 5.5 V 0.01 1 μA
Common-Mode Leakage ICM V
A = VB = VDD/2 1 nA
DIGITAL INPUTS AND OUTPUTS
Input Logic High (SDA and SCL)8 V
IH V
DD = 5 V 0.7 VDD V
DD + 0.5 V
Input Logic Low (SDA and SCL)8 VIL V
DD = 5 V −0.5 +0.3 VDD V
Input Logic High (AD0 and AD1) VIH V
DD = 3 V 2.1 V
Input Logic Low (AD0 and AD1) VIL V
DD = 3 V 0.6 V
Input Current IIL V
IN = 0 V or 5 V ±1 μA
Input Capacitance6 C
IL 5 pF
POWER SUPPLIES
Power Supply Range VDD RANGE 2.7 5.5 V
OTP Supply Voltage8, 9 V
DD_OTP T
A = 25°C 5.6 5.7 5.8 V
Supply Current IDD V
IH = 5 V or VIL = 0 V 3.5 6 μA
OTP Supply Current8, 10, 11 I
DD_OTP V
DD_OTP = 5 V, TA = 25°C 100 mA
Power Dissipation12 P
DISS V
IH = 5 V or VIL = 0 V, VDD = 5 V 33 μW
Power Supply Sensitivity PSS VDD = 5 V ± 10%, code =
midscale
±0.02 ±0.08 %/%
AD5170
Rev. G | Page 5 of 24
Parameter Symbol Conditions Min Typ1 Max Unit
DYNAMIC CHARACTERISTICS13
–3 dB Bandwidth BW_2.5k Code = 0x80 4.8 MHz
Total Harmonic Distortion THDW V
A = 1 V rms, VB = 0 V, f = 1 kHz 0.1 %
VW Settling Time tS VA = 5 V, VB = 0 V, ±1 LSB error
band
1 μs
Resistor Noise Voltage Density eN_WB R
WB = 1.25 kΩ, f = 1 kHz 3.2 nV/√Hz
1 Typical specifications represent average readings at 25°C and VDD = 5 V.
2 Resistor position nonlinearity error, R-INL, is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper
positions. R-DNL measures the relative step change from the ideal between successive tap positions. Parts are guaranteed monotonic.
3 VAB = VDD, wiper (VW) = no connect.
4 INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output DAC. VA = VDD and VB = 0 V. DNL specification limits
of ±1 LSB maximum are guaranteed monotonic operating conditions.
5 The A, B, and W resistor terminals have no limitations on polarity with respect to each other.
6 Guaranteed by design and not subject to production test.
7 Measured at the A terminal. The A terminal is open circuited in shutdown mode.
8 The minimum voltage requirement on the VIH is 0.7 V × VDD. For example, VIH minimum = 3.5 V when VDD = 5 V. It is typical for the SCL and SDA resistors to be pulled
up to VDD. However, care must be taken to ensure that the minimum VIH is met when the SCL and SDA are driven directly from a low voltage logic controller without
pull-up resistors.
9 Different from operating power supply; power supply for OTP is used one time only.
10 Different from operating current; supply current for OTP lasts approximately 400 ms for use one time only.
11 See Figure 26 for the energy plot during OTP program.
12 PDISS is calculated from (IDD × VDD). CMOS logic level inputs result in minimum power dissipation.
13 All dynamic characteristics use VDD = 5 V.
ELECTRICAL CHARACTERISTICS: 10 kΩ, 50 kΩ, AND 100 kΩ
VDD = 5 V ± 10% or 3 V ± 10%, VA = VDD, VB = 0 V, −40°C < TA < +125°C, unless otherwise noted.
Table 2.
Parameter Symbol Conditions Min Typ1 Max Unit
DC CHARACTERISTICS—RHEOSTAT MODE
Resistor Differential Nonlinearity2 R-DNL RWB, VA = no connect −1 ±0.1 +1 LSB
Resistor Integral Nonlinearity2 R-INL RWB, VA = no connect −2.5 ±0.25 +2.5 LSB
Nominal Resistor Tolerance3 ∆RAB T
A = 25°C −20 +20 %
Resistance Temperature Coefficient (∆RAB/RAB)/∆T 35 ppm/°C
RWB (Wiper Resistance) RWB Code = 0x00, VDD = 5 V 160 200 Ω
DC CHARACTERISTICS—POTENTIOMETER DIVIDER
MODE (SPECIFICATIONS APPLY TO ALL VRs)
Differential Nonlinearity4 DNL −1 ±0.1 +1 LSB
Integral Nonlinearity4 INL −1 ±0.3 +1 LSB
Voltage Divider Temperature Coefficient (∆VW/VW)/∆T Code = 0x80 15 ppm/°C
Full-Scale Error VWFSE Code = 0xFF −2.5 −1 0 LSB
Zero-Scale Error VWZSE Code = 0x00 0 1 2.5 LSB
RESISTOR TERMINALS
Voltage Range5 V
A, VB, VW GND VDD V
Capacitance A, Capacitance B6 C
A, CB f = 1 MHz, measured to GND,
code = 0x80
45 pF
Capacitance W6 C
W f = 1 MHz, measured to GND,
code = 0x80
60 pF
Shutdown Supply Current7 I
A_SD V
DD = 5.5 V 0.01 1 μA
Common-Mode Leakage ICM V
A = VB = VDD/2 1 nA
DIGITAL INPUTS AND OUTPUTS
Input Logic High (SDA and SCL)8 V
IH V
DD = 5 V 0.7 VDD V
DD + 0.5 V
Input Logic Low (SDA and SCL)8 V
IL V
DD = 5 V −0.5 +0.3 VDD V
Input Logic High (AD0 and AD1) VIH V
DD = 3 V 2.1 V
Input Logic Low (AD0 and AD1) VIL V
DD = 3 V 0.6 V
Input Current IIL V
IN = 0 V or 5 V ±1 μA
Input Capacitance6 C
IL 5 pF
AD5170
Rev. G | Page 6 of 24
Parameter Symbol Conditions Min Typ1 Max Unit
POWER SUPPLIES
Power Supply Range VDD RANGE 2.7 5.5 V
OTP Supply Voltage8, 9 V
DD_OTP 5.6 5.7 5.8 V
Supply Current IDD V
IH = 5 V or VIL = 0 V 3.5 6 μA
OTP Supply Current8, 10, 11 I
DD_OTP V
DD_OTP = 5 V, TA = 25°C 100 mA
Power Dissipation12 P
DISS V
IH = 5 V or VIL = 0 V, VDD = 5 V 33 μW
Power Supply Sensitivity PSS VDD = 5 V ± 10%, code =
midscale
±0.02 ±0.08 %/%
DYNAMIC CHARACTERISTICS13
–3 dB Bandwidth BW RAB = 10 kΩ, code = 0x80 600 kHz
R
AB = 50 kΩ, code = 0x80 100 kHz
R
AB = 100 kΩ, code = 0x80 40 kHz
Total Harmonic Distortion THDW VA =1 V rms, VB = 0 V, f = 1 kHz,
RAB = 10 kΩ
0.1 %
VW Settling Time (10 kΩ/50 kΩ/100 kΩ) tS VA = 5 V, VB = 0 V, ±1 LSB error
band
2 μs
Resistor Noise Voltage Density eN_WB R
WB = 5 kΩ, f = 1 kHz 9 nV/√Hz
1 Typical specifications represent average readings at 25°C and VDD = 5 V.
2 Resistor position nonlinearity error, R-INL, is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper
positions. R-DNL measures the relative step change from the ideal between successive tap positions. Parts are guaranteed monotonic.
3 VAB = VDD, wiper (VW) = no connect.
4 INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output DAC. VA = VDD and VB = 0 V. DNL specification limits
of ±1 LSB maximum are guaranteed monotonic operating conditions.
5 The A, B, and W resistor terminals have no limitations on polarity with respect to each other.
6 Guaranteed by design and not subject to production test.
7 Measured at the A terminal. The A terminal is open circuited in shutdown mode.
8 The minimum voltage requirement on the VIH is 0.7 V × VDD. For example, VIH minimum = 3.5 V when VDD = 5 V. It is typical for the SCL and SDA resistors to be pulled up
to VDD. However, care must be taken to ensure that the minimum VIH is met when the SCL and SDA are driven directly from a low voltage logic controller without pull-
up resistors.
9 Different from operating power supply, power supply OTP is used one time only.
10 Different from operating current, supply current for OTP lasts approximately 400 ms for use one time only.
11 See Figure 26 for the energy plot during OTP program.
12 PDISS is calculated from (IDD × VDD). CMOS logic level inputs result in minimum power dissipation.
13 All dynamic characteristics use VDD = 5 V.
AD5170
Rev. G | Page 7 of 24
TIMING CHARACTERISTICS: 2.5 kΩ, 10 kΩ, 50 kΩ, AND 100 kΩ
VDD = 5 V ± 10% or 3 V ± 10%, VA = VDD; VB = 0 V, −40°C < TA < +125°C, unless otherwise noted.
Table 3.
Parameter Symbol Conditions Min Typ Max Unit
I2C INTERFACE TIMING CHARACTERISTICS1 (SPECIFICATIONS
APPLY TO ALL PARTS)
SCL Clock Frequency fSCL 400 kHz
tBUF Bus Free Time Between Stop and Start t1 1.3 μs
tHD;STA Hold Time (Repeated Start) t2 After this period, the first clock
pulse is generated
0.6 μs
tLOW Low Period of SCL Clock t3 1.3 μs
tHIGH High Period of SCL Clock t4 0.6 μs
tSU;STA Setup Time for Repeated Start Condition t5 0.6 μs
tHD;DAT Data Hold Time2 t
6 0.9 μs
tSU;DAT Data Setup Time t7 100 ns
tF Fall Time of Both SDA and SCL Signals t8 300 ns
tR Rise Time of Both SDA and SCL Signals t9 300 ns
tSU;STO Setup Time for Stop Condition t10 0.6 μs
OTP Program Time t11 400 ms
1 See Figure 2 for locations of measured values.
2 The maximum tHD;DAT must be met only if the device does not stretch the low period (tLOW) of the SCL signal.
Timing Diagram
04104-044
t
1
t
2
t
3
t
8
t
8
t
9
t
9
t
6
t
4
t
7
t
5
t
2
t
10
PS S
SCL
SDA
P
Figure 2. I2C Interface Detailed Timing Diagram
AD5170
Rev. G | Page 8 of 24
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 4.
Parameter Rating
VDD to GND −0.3 V to +7 V
VA, VB, VW to GND VDD
Terminal Current, A to B, A to W, B to W1
Pulsed ±20 mA
Continuous ±5 mA
Digital Inputs and Output Voltage to GND 0 V to 7 V
Operating Temperature Range −40°C to +125°C
Maximum Junction Temperature (TJMAX) 150°C
Storage Temperature Range −65°C to +150°C
Lead Temperature (Soldering, 10 sec) 300°C
Thermal Resistance2
θJA: 10-Lead MSOP 230°C/W
1 Maximum terminal current is bound by the maximum current handling of
the switches, maximum power dissipation of the package, and maximum
applied voltage across any two of the A, B, and W terminals at a given
resistance.
2 Package power dissipation = (TJMAX − TA)/θJA.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
AD5170
Rev. G | Page 9 of 24
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
B
1
A
2
AD0
3
G
ND
4
V
DD 5
W
10
NC
9
AD1
8
SDA
7
SCL
6
AD5170
TOP VIEW
(Not to Scale)
04104-048
Figure 3. Pin Configuration
Table 5. Pin Function Descriptions
Pin No. Mnemonic Description
1 B B Terminal. GND ≤ VB ≤ VDD.
2 A A Terminal. GND ≤ VA ≤ VDD.
3 AD0 Programmable Address Bit 0 for Multiple Package Decoding.
4 GND Digital Ground.
5 VDD Positive Power Supply. Specified for operation from 2.7 V to 5.5 V. For OTP programming, the VDD supply must be
within the 5.6 V to 5.8 V range and capable of driving 100 mA.
6 SCL Serial Clock Input. Positive edge triggered. Requires a pull-up resistor. If it is driven directly from a logic controller
without the pull-up resistor, ensure that VIH minimum is 0.7 V × VDD.
7 SDA Serial Data Input/Output. Requires a pull-up resistor. If it is driven directly from a logic controller without the
pull-up resistor, ensure that VIH minimum is 0.7 V × VDD.
8 AD1 Programmable Address Bit 1 for Multiple Package Decoding.
9 NC No Connect.
10 W W Terminal. GND ≤ VW ≤ VDD.
AD5170
Rev. G | Page 10 of 24
TYPICAL PERFORMANCE CHARACTERISTICS
–2.0
–1.5
–1.0
–0.5
0
0.5
RHEOST
A
T MODE INL (LSB)
1.0
1.5
2.0
1289632 640 160 192 224 256
CODE (DECIMAL)
04104-002
V
DD
= 5.5V
T
A
= 25°C
R
AB
= 10kΩ
V
DD
= 2.7V
Figure 4. R-INL vs. Code vs. Supply Voltages
–0.5
–0.4
–0.3
–0.2
–0.1
0
0.1
0.2
0.3
0.4
0.5
RHEOST
A
T MODE DNL (LSB)
1289632 640 160 192 224 256
CODE (DECIMAL)
04104-003
T
A
= 25°C
R
AB
= 10kΩ
V
DD
= 2.7V
V
DD
= 5.5V
Figure 5. R-DNL vs. Code vs. Supply Voltages
–0.5
–0.4
–0.3
–0.2
–0.1
0
0.1
0.2
0.3
0.4
0.5
POTENTIOMETER MODE INL (LSB)
1289632 640 160 192 224 256
CODE (DECIMAL)
04104-004
R
AB
= 10kΩ
V
DD
= 2.7V
T
A
= –40°C, +25°C, +85°C, +125°C
V
DD
= 5.5V
T
A
= –40°C, +25°C, +85°C, +125°C
Figure 6. INL vs. Code vs. Temperature
–0.5
–0.4
–0.3
–0.2
–0.1
0
0.1
0.2
0.3
0.4
0.5
POTENTIOMETER MODE DNL (LSB)
1289632 640 160 192 224 256
CODE (DECIMAL)
04104-005
V
DD
= 2.7V; T
A
= –40°C, +25°C, +85°C, +125°C
R
AB
= 10kΩ
Figure 7. DNL vs. Code vs. Temperature
–1.0
–0.8
–0.6
–0.4
–0.2
0
0.2
0.4
0.6
0.8
1.0
POTENTIOMETER MODE INL (LSB)
1289632 640 160 192 224 256
CODE (DECIMAL)
04104-006
T
A
= 25°C
R
AB
= 10kΩ
V
DD
= 2.7V
V
DD
= 5.5V
Figure 8. INL vs. Code vs. Supply Voltages
–0.5
–0.4
–0.3
–0.2
–0.1
0
0.1
0.2
0.3
0.4
0.5
POTENTIOMETER MODE DNL (LSB)
1289632 640 160 192 224 256
CODE (DECIMAL)
04104-007
T
A
= 25°C
R
AB
= 10kΩ
V
DD
= 2.7V
V
DD
= 5.5V
Figure 9. DNL vs. Code vs. Supply Voltages
AD5170
Rev. G | Page 11 of 24
–2.0
–1.5
–1.0
–0.5
0
0.5
RHEOST
A
T MODE INL (LSB)
1.0
1.5
2.0
1289632 640 160 192 224 256
CODE (DECIMAL)
04104-008
R
AB
= 10kΩ
V
DD
= 2.7V
T
A
= –40°C, +25°C, +85°C, +125°C
V
DD
= 5.5V
T
A
= –40°C, +25°C, +85°C, +125°C
Figure 10. R-INL vs. Code vs. Temperature
–0.5
–0.4
–0.3
–0.2
–0.1
0
0.1
0.2
0.3
0.4
0.5
RHEOST
A
T MODE DNL (LSB)
1289632 640 160 192 224 256
CODE (DECIMAL)
04104-009
V
DD
= 2.7V, 5.5V; T
A
= –40°C, +25°C, +85°C, +125°C
R
AB
= 10kΩ
Figure 11. R-DNL vs. Code vs. Temperature
–2.0
–1.5
–1.0
–0.5
0
0.5
FSE, FULL-SCALE ERROR (LSB)
1.0
1.5
2.0
TEMPERATURE (°C)
–40 –25 –10 5 20 35 50 65 80 95 110 125
04104-010
V
DD
= 5.5V, V
A
= 5.0V
R
AB
= 10kΩ
V
DD
= 2.7V, V
A
= 2.7V
Figure 12. Full-Scale Error vs. Temperature
0
0.75
1.50
2.25
3.00
3.75
4.50
ZSE, ZERO-SCALE ERROR (LSB)
TEMPERATURE (°C)
–40 –25 –10 5 20 35 50 65 80 95 110 125
04104-011
V
DD
= 5.5V, V
A
= 5.0V
R
AB
= 10kΩ
V
DD
= 2.7V, V
A
= 2.7V
Figure 13. Zero-Scale Error vs. Temperature
I
DD
, SUPPLY CURRENT (µA)
0.1
1
10
–40 –7 26 59 92 125
TEMPERATURE (°C)
04104-012
V
DD
= 5V
V
DD
= 3V
Figure 14. IDD, Supply Current vs. Temperature
–20
0
20
40
60
80
100
120
RHEOST
A
T MODE TEMPCO (ppm/°C)
1289632 640 160 192 224 256
CODE (DECIMAL)
04104-013
R
AB
= 10kΩ
V
DD
= 2.7V
T
A
= –40°C TO +85°C, –40°C TO +125°C
V
DD
= 5.5V
T
A
= –40°C TO +85°C, –40°C TO +125°C
Figure 15. Rheostat Mode Tempco ΔRWB/ΔT vs. Code
AD5170
Rev. G | Page 12 of 24
–30
–20
–10
0
10
20
POTENTIOMETER MODE TEMPCO (ppm/°C)
30
40
50
1289632 640 160 192 224 256
CODE (DECIMAL)
04104-014
RAB = 10kΩ
VDD = 2.7V
TA = –40°C TO +85°C, –40°C TO +125°C
VDD = 5.5V
TA = –40°C TO +85°C, –40°C TO +125°C
Figure 16. Potentiometer Mode Tempco ΔVWB/ΔT vs. Code
–60
–54
–48
–42
–36
–30
–24
–18
–12
–6
0
GAIN (dB)
FREQUENCY (Hz)
10k 1M100k 10M
04104-015
0x80
0x40
0x20
0x10
0x08
0x04
0x010x02
Figure 17. Gain vs. Frequency vs. Code, RAB = 2.5 kΩ
–60
–54
–48
–42
–36
–30
–24
–18
–12
–6
0
GAIN (dB)
FREQUENCY (Hz)
1k 100k10k 1M
04104-016
0x80
0x40
0x20
0x10
0x08
0x04
0x01
0x02
Figure 18. Gain vs. Frequency vs. Code, RAB = 10 kΩ
–60
–54
–48
–42
–36
–30
–24
–18
–12
–6
0
GAIN (dB)
FREQUENCY (Hz)
1k 100k10k 1M
04104-017
0x80
0x40
0x20
0x10
0x08
0x04
0x01
0x02
Figure 19. Gain vs. Frequency vs. Code, RAB = 50 kΩ
–60
–54
–48
–42
–36
–30
–24
–18
–12
–6
0
GAIN (dB)
FREQUENCY (Hz)
1k 100k10k 1M
04104-018
0x80
0x40
0x20
0x10
0x08
0x04
0x01
0x02
Figure 20. Gain vs. Frequency vs. Code, RAB = 100 kΩ
–60
–54
–48
–42
–36
–30
–24
–18
–12
–6
0
GAIN (dB)
FREQUENCY (Hz)
10k1k 100k 1M 10M
04104-019
100kΩ
60kHz 50kΩ
120kHz
10kΩ
570kHz
2.5kΩ
2.2MHz
Figure 21. −3 dB Bandwidth at Code = 0x80
AD5170
Rev. G | Page 13 of 24
IDD, SUPPLY CURRENT (mA)
0.01
1
0.1
10
0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
DIGITAL I NPUT VOLTAGE (V)
04104-020
TA = 25°C
VDD = 2.7V
VDD = 5.5V
04104-023
SCL
V
W
Figure 22. IDD, Supply Current vs. Digital Input Voltage
Figure 25. Large Signal Settling Time
04104-033
CH1 20.0mAΩM 200ns A CH1 32.4mA
1
T 588.000ns
CH1 MAX
103mA
CH1 MIN
–1.98mA
SCL
V
W
04104-021
Figure 23. Digital Feedthrough
Figure 26. OTP Program Energy Plot for Single Fuse
V
W
04104-025
Figure 24. Midscale Glitch, Code 0x80 to Code 0x7F
AD5170
Rev. G | Page 14 of 24
TEST CIRCUITS
Figure 27 to Figure 32 illustrate the test circuits that define the test conditions used in the product specification tables.
0
4104-026
V
MS
AW
B
DUT
V+
V
+ = V
DD
1LSB = V+/2
N
Figure 27. Test Circuit for Potentiometer Divider Nonlinearity Error (INL, DNL)
04104-027
NO CONNECT
I
W
V
MS
AW
B
DUT
Figure 28. Test Circuit for Resistor Position Nonlinearity Error
(Rheostat Operation; R-INL, R-DNL)
04104-028
V
MS2
V
MS1
V
W
A
W
B
DUT
I
W
= V
DD
/R
NOMINAL
R
W
= [V
MS1
– V
MS2
]/I
W
Figure 29. Test Circuit for Wiper Resistance
04104-029
∆V
MS
%
DUT
( )
A
W
B
V+ ∆V
DD
%
∆V
MS
∆V
DD
∆V
DD
V
A
V
MS
V+ = V
DD
± 10%
PSRR (dB) = 20 LOG
PSS (%/%) =
Figure 30. Test Circuit for Power Supply Sensitivity (PSS, PSRR)
04104-030
+5V
–5V
W
A
2.5V
BV
OUT
OFFSET
GND
DUT
V
IN
AD8610
Figure 31. Test Circuit for Gain vs. Frequency
W
BV
CM
I
CM
A
NC
GND
NC
V
DD
DUT
NC = NO CONNECT
04104-032
Figure 32. Test Circuit for Common-Mode Leakage Current
AD5170
Rev. G | Page 15 of 24
THEORY OF OPERATION
04104-022
SDA
SCL A
W
B
COMPARATOR
MUX DECODER
FUSES
EN
FUSE
REG.
DAC
REG.
I
2
C INTERFACE
ONE-TIME
PROGRAM/TEST
CONTROL BLOCK
Figure 33. Detailed Functional Block Diagram
The AD5170 is a 256-position, digitally controlled, variable
resistor (VR) that employs fuse link technology to achieve
memory retention of the resistance setting.
An internal power-on preset places the wiper at midscale during
power-on. If the OTP function is activated, the device powers
up at the user-defined permanent setting.
ONE-TIME PROGRAMMING (OTP)
Prior to OTP activation, the AD5170 presets to midscale during
initial power-on. After the wiper is set at the desired position,
the resistance can be permanently set by programming the T bit
high along with the proper coding (see Table 9 and Table 10) and
one-time VDD_OTP. Note that fuse link technology of the AD517x
family of digital potentiometers requires that VDD_OTP between 5.6 V
and 5.8 V blow the fuses to achieve a given nonvolatile setting. On
the other hand, VDD can be 2.7 V to 5.5 V during operation. For
system supplies that are lower than 5.6 V, an external supply for
one-time programming is required. Note that the user is allowed
only one attempt in blowing the fuses. If the user fails to blow the
fuses at the first attempt, the structures of the fuses may have
changed such that they can never be blown, regardless of the
energy applied at subsequent events. For details, see the Power
Supply Considerations section.
The device control circuit has two validation bits, E1 and E0,
that can be read back to check the programming status (see
Table 6). Users should always read back the validation bits to
ensure that the fuses are properly blown. After the fuses are
blown, all fuse latches are enabled upon subsequent power-on;
therefore, the output corresponds to the stored setting. Figure 33
shows a detailed functional block diagram.
Table 6. Validation Status
E1 E0 Status
0 0 Ready for programming.
1 0 Fatal error. Some fuses are not blown. Do not retry.
Discard this unit.
1 1 Successful. No further programming is possible.
PROGRAMMING THE VARIABLE RESISTOR AND
VOLTAGE—RHEOSTAT OPERATION
The nominal resistance (RAB) between Terminal A and Terminal B
is available in 2.5 kΩ, 10 kΩ, 50 kΩ, and 100 kΩ. The nominal
resistance of the VR has 256 contact points that are accessed by
the wiper terminal, plus the B terminal contact. The 8-bit data
in the RDAC latch is decoded to select one of the 256 possible
settings.
A
W
B
A
W
B
A
W
B
0
4104-024
Figure 34. Rheostat Mode Configuration
Assuming that a 10 kΩ part is used, the first connection of the
wiper starts at Terminal B for Data 0x00. Because there is a 50 Ω
wiper contact resistance, such a connection yields a minimum of
100 Ω (2 × 50 Ω) resistance between Terminal W and Terminal B.
The second connection is the first tap point, which corresponds
to 139 Ω (RWB = RAB/256 + 2 × RW = 39 Ω + 2 × 50 Ω) for Data
0x01. The third connection is the next tap point, representing
178 Ω (2 × 39 Ω + 2 × 50 Ω) for Data 0x02, and so on. Each LSB
data value increase moves the wiper up the resistor ladder until
the last tap point is reached at 10,100 Ω (RAB + 2 × RW).
AD5170
Rev. G | Page 16 of 24
D5
D4
D3
D7
D6
D2
D1
D0
RDAC
LATCH
AND
DECODER
R
S
R
S
R
S
R
S
A
W
B
SD BIT
04104-034
Figure 35. Equivalent RDAC Circuit
The general equation that determines the digitally programmed
output resistance between Terminal W and Terminal B is
W
AB
WB RR
D
(D)R ×+×= 2
256 (1)
where:
D is the decimal equivalent of the binary code loaded in the
8-bit RDAC register.
RAB is the end-to-end resistance.
RW is the wiper resistance contributed by the on resistance of
the internal switch.
In summary, if RAB = 10 kΩ and Terminal A is open-circuited,
the output resistance, RWB, is set for the RDAC latch codes, as
shown in Table 7.
Table 7. Codes and Corresponding RWB Resistance
D (Dec) RWB (Ω) Output State
255 9961 Full scale (RAB − 1 LSB + RW)
128 5060 Midscale
1 139 1 LSB
0 100 Zero scale (wiper contact resistance)
Note that in the zero-scale condition, a finite wiper resistance of
100 Ω is present. Care should be taken to limit the current flow
between Terminal W and Ter mi nal B in t his state to a maximum
pulse current of no more than 20 mA. Otherwise, degradation
or possible destruction of the internal switch contact can occur.
Similar to the mechanical potentiometer, the resistance of the
RDAC between the wiper (Terminal W) and Terminal A also
produces a digitally controlled, complementary resistance, RWA .
When these terminals are used, Terminal B can be opened.
Setting the resistance value for RWA starts at a maximum value
of resistance and decreases as the data loaded in the latch
increases in value. The general equation for this operation is
W
ABWA RR
D
(D)R ×+×= 2
256
–256 (2)
For RAB = 10 kΩ and Terminal B open circuited, Table 8 shows
some examples of the output resistance (RWA ) vs. the RDAC
latch codes.
Table 8. Codes and Corresponding RWA Resistance
D (Dec) RWA (Ω) Output State
255 139 Full scale
128 5060 Midscale
1 9961 1 LSB
0 10,060 Zero scale
Typical device-to-device matching is process-lot dependent
and can vary by up to ±30%. Because the resistance element is
processed using thin film technology, the change in RAB with
temperature has a very low 35 ppm/°C temperature coefficient.
PROGRAMMING THE POTENTIOMETER DIVIDER—
VOLTAGE OUTPUT OPERATION
The digital potentiometer easily generates a voltage divider at
wiper to B and wiper to A proportional to the input voltage at
A to B. Unlike the polarity of VDD to GND, which must be
positive, voltage across A to B, W to A, and W to B can be at
either polarity.
A
W
B
V
I
V
O
0
4104-035
Figure 36. Potentiometer Mode Configuration
If ignoring the effect of the wiper resistance for approximation,
connecting Terminal A to 5 V and Terminal B to ground pro-
duces an output voltage at the wiper to B starting at 0 V up to
1 LSB less than 5 V. Each LSB of voltage is equal to the voltage
applied across Terminal A and Terminal B divided by the 256
positions of the potentiometer divider. The general equation
defining the output voltage at VW with respect to ground for any
valid input voltage applied to Terminal A and Terminal B is
B
A
WV
D
V
D
DV 256
256
256
)(
−
+= (3)
For a more accurate calculation, which includes the effect of
wiper resistance, VW, the following equation can be used:
B
AB
WA
A
AB
WB
WV
R
DR
V
R
DR
DV )(
)(
)( += (4)
Operation of the digital potentiometer in divider mode results
in a more accurate operation over temperature. Unlike rheostat
mode, the output voltage is dependent mainly on the ratio of
the internal resistors, RWA and RWB, and not the absolute values.
Therefore, the temperature drift reduces to 15 ppm/°C.
AD5170
Rev. G | Page 17 of 24
ESD PROTECTION
All digital inputs, SDA, SCL, AD0, and AD1, are protected with
a series input resistor and parallel Zener ESD structures, as shown
in Figure 37 and Figure 38.
LOGIC
340
Ω
GND
04104-037
Figure 37. ESD Protection of Digital Pins
A, B, W
GND
04104-038
Figure 38. ESD Protection of Resistor Terminals
TERMINAL VOLTAGE OPERATING RANGE
The AD5170 VDD-to-GND power supply defines the boundary
conditions for proper 3-terminal digital potentiometer opera-
tion. Supply signals present on Terminal A, Terminal B, and
Terminal W that exceed VDD or GND are clamped by the internal
forward-biased diodes (see Figure 39).
GND
A
W
B
V
DD
04104-039
Figure 39. Maximum Terminal Voltages Set by VDD and GND
POWER-UP SEQUENCE
Because the ESD protection diodes limit the voltage compliance
at Termina l A, Termina l B, and Ter minal W, it i s important to
power VDD/GND before applying any voltage to Terminal A,
Ter minal B, a nd Terminal W (s ee Figure 39). Otherwise, the
diode is forward-biased such that VDD is powered unintentionally
and may affect the rest of the user’s circuit. The ideal power-up
sequence is GND, VDD, the digital inputs, and then VA/VB/VW.
The relative order of powering VA, VB, VW, and the digital inputs
is not important as long as they are powered up after GND/VDD.
POWER SUPPLY CONSIDERATIONS
To minimize the package pin count, both the one-time pro-
gramming and normal operating voltage supplies share the
same VDD terminal of the AD5170. The AD5170 employs fuse
link technology that requires 5.6 V to 5.8 V for blowing the
internal fuses to achieve a given setting, but normal VDD can be
anywhere between 2.7 V and 5.5 V after the fuse programming
process. As a result, dual voltage supplies and isolation are needed if
system VDD is lower than the required VDD_OTP. The fuse program-
ming supply (either an on-board regulator or rack-mount power
supply) must be rated at 5.6 V to 5.8 V and be able to provide a
100 mA current for 400 ms for successful OTP.
When the fuse programming is complete, the VDD_OTP supply
must be removed to allow normal operation at 2.7 V to 5.5 V,
and the device consumes current in the μA range.
V
DD
2.7V
5.7V
P1
P1 = P2 = FDV302P, NDS0610
R1
10kΩ
P2
C1
10µF
C2
0.1µF
A
PPLY FOR OTP ONLY
AD5170
0
4104-0-51
Figure 40. Isolate 5.7 V OTP Supply from 2.7 V Normal Operating Supply
For example, for those who operate their systems at 2.7 V, use of
the bidirectional, low threshold, P-Channel MOSFETs is recom-
mended for the isolation of the supply. As shown in Figure 40,
this assumes that the 2.7 V system voltage is applied first, and
the P1 and P2 gates are pulled to ground, thus turning on P1 and,
subsequently, P2. As a result, VDD of the AD5170 approaches 2.7 V.
When the AD5170 setting is found, the factory tester applies the
VDD_OTP to both the VDD and the MOSFETs gates, turning off P1
and P2. The OTP command is executed at this time to program the
AD5170 while the 2.7 V source is protected. When the fuse pro-
gramming is complete, the tester withdraws the VDD_OTP and the
setting for the AD5170 is permanently fixed.
The AD5170 achieves the OTP function by blowing internal
fuses. Users should always apply the 5.6 V to 5.8 V one-time-
program voltage requirement at the first fuse programming
attempt. Failure to comply with this requirement can lead to a
change in the fuse structures, rendering programming inoperable.
Care should be taken when SCL and SDA are driven from a low
voltage logic controller. Users must ensure that the logic high
level is between 0.7 V × VDD and VDD + 0.5 V. Refer to the Level
Shifting for Different Voltage Operation section.
Poor PCB layout introduces parasitics that can affect the fuse
programming. Therefore, it is recommended to add a 10 μF
tantalum capacitor in parallel with a 1 nF ceramic capacitor as
close as possible to the VDD pin. The type and value chosen for
both capacitors are important. This combination of capacitor
values provides both a fast response and larger supply current
handling with minimum supply droop during transients. As a
result, these capacitors increase the OTP programming success
by not inhibiting the proper energy needed to blow the internal
fuses. Additionally, C1 minimizes transient disturbance and low
frequency ripple, and C2 reduces high frequency noise during
normal operation.
AD5170
Rev. G | Page 18 of 24
V
DD
V
DD
GND
C2
1nF
C1
10µF
+
AD5170
04104-040
LAYOUT CONSIDERATIONS
It is good practice to employ compact, minimum lead length,
layout design. The leads to the inputs should be as direct as
possible, with a minimum conductor length. Ground paths
should have low resistance and low inductance.
Note that the digital ground should also be joined remotely to
the analog ground at one point to minimize the ground bounce.
Figure 41. Power Supply Bypassing
AD5170
Rev. G | Page 19 of 24
CONTROLLING THE AD5170
There are two ways of controlling the AD5170. Users can program the device with either computer software or external I2C controllers.
04104-041
Figure 42. AD5170 Computer Software Interface
SOFTWARE PROGRAMMING
Due to the advantages of the one-time programmable feature,
consider programming the device in the factory before shipping
the final product to the end users. Analog Devices offers device
programming software that can be implemented in the factory
on PCs running Windows 95 or later. As a result, external con-
trollers are not required, significantly reducing development time.
The program is an executable file that does not require knowledge
of programming languages or programming skills, and it is easy to
set up and to use. Figure 42 shows the software interface. The
software can be downloaded from the AD5170 product page.
Write
The AD5170 starts at midscale after power-up prior to OTP
programming. To increment or decrement the resistance, move
the scroll bars on the left. To write any specific value, use the bit
pattern in the upper screen and click Run. The format of writing
data to the device is shown in Table 9. Once the desired setting
is found, click Program Permanent: First Fuse Link to blow
the internal fuse links.
Read
To read the validation bits and data from the device, click Read.
The format of the read bits is shown in Table 10.
DEVICE PROGRAMMING
To apply the device programming software in the factory, modify
a parallel port cable and configure Pin 2, Pin 3, Pin 15, and Pin 25
for SDA_write, SCL, SDA_read, and DGND, respectively, for
the control signals (see Figure 43). Also, lay out the PCB of the
AD5170 with SCL and SDA pads, as shown in Figure 44, such
that pogo pins can be inserted for factory programming.
13
25
12
24
11
23
10
22
9
21
8
20
7
19
6
18
5
17
4
16
3
15
2
14
1
SCL
R3
100Ω
R2
100Ω
R1
100Ω
SDA
READ
WRITE
0
4104-042
Figure 43. Parallel Port Connection
(Pin 2 = SDA_write, Pin 3 = SCL, Pin 15 = SDA_read, and Pin 25 = DGND)
AD5170
B
A
AD0
GND
VDD
W
NC
AD1
SDA
SCL
04104-043
Figure 44. Recommended AD5170 PCB Layout
AD5170
Rev. G | Page 20 of 24
Table 9. Write Mode
S 0 1 0 1 1 AD1 AD0 W A 2T SD T 0 OW X X X A D7 D6 D5 D4 D3 D2 D1 D0 A P
Slave Address Byte Instruction Byte Data Byte
Table 10. Read Mode
S 0 1 0 1 1 AD1 AD0 R A D7 D6 D5 D4 D3 D2 D1 D0 A E1 E0 X X X X X X A P
Slave Address Byte Data Byte Validation Byte
Table 11. SDA Bit Definitions and Descriptions
Bit Description
S Start condition.
P Stop condition.
A Acknowledge.
AD0, AD1 Package pin-programmable address bits.
X Don’t care.
W Write.
R Read.
2T Second fuse link array for two-time programming. Logic 0 corresponds to first trim. Logic 1 corresponds to
second trim. Note that blowing Trim 2 before Trim 1 effectively disables Trim 1 and, in turn, allows only one-time
programming.
SD Shutdown connects wiper to Terminal B and open circuits Terminal A. It does not change the contents of the wiper register.
T OTP programming bit. Logic 1 permanently programs the wiper.
OW Overwrite the fuse setting and program the digital potentiometer to a different setting. Note that upon power-up,
the digital potentiometer presets to either midscale or fuse setting, depending on whether the fuse link is blown.
D7, D6, D5, D4, D3,
D2, D1, and D0
Data bits.
E1, E0 OTP validation bits:
0, 0 = ready to program.
1, 0 = fatal error. Some fuses are not blown. Do not retry. Discard this unit.
1, 1 = programmed successfully. No further adjustments are possible.
AD5170
Rev. G | Page 21 of 24
I2C CONTROLLER PROGRAMMING
Write Bit Patterns
04104-045
SCL
S
TART BY
MASTER
SDA 01
1
FRAME 1
SLAVE ADDRESS BYTE
0 1 1 AD1 AD0
FRAME 2
INSTRUCTION BYTE
ACK BY
AD5170
R/W A0 SD 0 OW XXX
19
D7 D6 D5 D4 D3
ACK BY
AD5170
FRAME 3
DATA BYTE
19
T
STOP BY
MASTER
9
D2 D1 D0
ACK BY
AD5170
Figure 45. Writing Data to the RDAC Register
Read Bit Pattern
04104-046
SCL
S
TART BY
MASTER
SDA 01
1
FRAME 1
SLAVE ADDRESS BYTE
0 1 1 AD1 AD0
FRAME 2
DATA BYTE
ACK BY
AD5170
R/W D7 D6 D4 D3 D2 D1 D0
19
E1 E0 X X X
ACK BY
MASTER
FRAME 3
VALIDATION BYTE
19
D5
STOP BY
MASTER
9
XXX
NO ACK
BY MASTER
Figure 46. Reading Data from the RDAC Register
The third MSB, T, is the OTP programming bit. A logic high
blows the polyfuses and programs the resistor setting perma-
nently. For example, if the user wants to blow the first array
of fuses, the instruction byte is 00100XXX. To blow the second
array of fuses, the instruction byte is 10100XXX. A logic low of
the T bit simply allows the device to act as a typical volatile digital
potentiometer.
I2C-COMPATIBLE, 2-WIRE SERIAL BUS
The following section describes how the 2-wire, I2C serial bus
protocol operates (see Figure 45 and Figure 46).
The master initiates a data transfer by establishing a start con-
dition, which is when a high-to-low transition on the SDA line
occurs while SCL is high (see Figure 45). The following byte is
the slave address byte, which consists of the slave address followed
by an R/W bit (this bit determines whether data is read from or
written to the slave device). AD0 and AD1 are configurable address
bits that allow up to four devices on one bus (see ). Table 9
The fourth MSB must always be Logic 0.
The fifth MSB, OW, is an overwrite bit. When raised to a logic
high, OW allows the RDAC setting to be changed even after the
internal fuses are blown. However, when OW is returned to
Logic 0, the position of the RDAC returns to the setting prior to
the overwrite. Because OW is not static, if the device is powered
off and on, the RDAC presets to midscale or to the setting at
which the fuses were blown, depending on whether the fuses
are permanently set.
The slave address corresponding to the transmitted address bits
responds by pulling the SDA line low during the ninth clock
pulse (this is called the acknowledge bit). At this stage, all other
devices on the bus remain idle while the selected device waits
for data to be written to, or read from, its serial register. If the
R/W bit is high, the master reads from the slave device. If the
R/W bit is low, the master writes to the slave device. The remainder of the bits in the instruction byte are don’t care
bits (see Figure 45).
In write mode, the second byte is the instruction byte. The first
MSB of the instruction byte, 2T, is the second trim enable bit.
A logic low selects the first array of the fuses, and a logic high
selects the second array of the fuses. This means that after blowing
the fuses with Trim 1, the user still has another chance to blow
them again with Trim 2. Note that using Trim 2 before Trim 1
effectively disables Trim 1 and, in turn, allows only one-time
programming.
After acknowledging the instruction byte, the last byte in write
mode is the data byte. Data is transmitted over the serial bus in
sequences of nine clock pulses (eight data bits followed by an
acknowledge bit). The transitions on the SDA line must occur
during the low period of SCL and remain stable during the high
period of SCL (see Figure 2).
In read mode, the data byte follows immediately after the
acknowledgment of the slave address byte. Data is transmitted
over the serial bus in sequences of nine clock pulses (a slight
difference from write mode, with eight data bits followed by an
acknowledge bit). Similarly, transitions on the SDA line must
occur during the low period of SCL and remain stable during
the high period of SCL (see Figure 46).
The second MSB, SD, is a shutdown bit. A logic high causes an
open circuit at Terminal A and shorts the wiper to Terminal B.
This operation yields almost 0 Ω in rheostat mode or 0 V in
potentiometer mode. Note that the shutdown operation does
not disturb the contents of the register. When brought out of
shutdown, the previous setting is applied to the RDAC. In
addition, new settings can be programmed during shutdown.
When the part is returned from shutdown, the corresponding
VR setting is applied to the RDAC.
Following the data byte, the validation byte contains two valida-
tion bits, E0 and E1. These bits signify the status of the one-time
programming (see Figure 46).
AD5170
Rev. G | Page 22 of 24
After all the data bits are read or written, a stop condition is
established by the master. A stop condition is defined as a low-
to-high transition on the SDA line while SCL is high. In write
mode, the master pulls the SDA line high during the 10th clock
pulse to establish a stop condition (see Figure 45).
In read mode, the master issues a no acknowledge for the 9th
clock pulse (that is, the SDA line remains high). The master brings
the SDA line low before the 10th clock pulse and then brings the
SDA line high to establish a stop condition (see Figure 46).
A repeated write function gives the user flexibility to update the
RDAC output a number of times after addressing and instructing
the part only once. For example, after the RDAC has acknowledged
its slave address and instruction bytes in write mode, the RDAC
output updates on each successive byte. If different instructions
are needed, the write/read mode has to start again with a new
slave address, instruction, and data byte. Similarly, a repeated
read function of the RDAC is also allowed.
Multiple Devices on One Bus
Figure 47 shows four AD5170s on the same serial bus. Each has
a different slave address because the states of their AD0 and
AD1 pins are different, which allows each device on the bus to
be written to or read from independently. The master device
output bus line drivers are open-drain pull-downs in a fully
I2C-compatible interface.
SDA
SDA
AD1
AD0
MASTER
SCL
SCL
AD5170
SDA
AD1
AD0
SCL
AD5170
SDA
AD1
AD0
SCL
AD5170
SDA
5V
R
P
R
P
5V
5V
5V
AD1
AD0
SCL
AD5170
04104-047
Figure 47. Multiple AD5170s on One I2C Bus
LEVEL SHIFTING FOR DIFFERENT VOLTAGE
OPERATION
If the SCL and SDA signals come from a low voltage logic con-
troller and are below the minimum VIH level (0.7 V × VDD), level
shift the signals for read/write communications between the
AD5170 and the controller. Figure 48 shows one of the implemen-
tations. For example, when SDA1 is at 2.5 V, M1 turns off and
SDA2 becomes 5 V. When the SDA1 is at 0 V, M1 turns on and
the SDA2 approaches 0 V. As a result, proper level shifting is
established. M1 and M2 should be low threshold, N-channel
power MOSFETs, such as the FDV301N.
0
4104-052
2.5V
CONTROLLER
2.7V TO 5.5V
AD5170
Rp Rp Rp Rp
V
DD1
= 2.5
V
V
DD2
= 5
V
G
G
SD
M1 SD
M2
S
DA1
S
CL1
SDA2
SCL2
Figure 48. Level Shifting for Different Voltage Operation
AD5170
Rev. G | Page 23 of 24
OUTLINE DIMENSIONS
COMPLIANT TO JEDEC STANDARDS MO-187-BA
091709-A
6°
0°
0.70
0.55
0.40
5
10
1
6
0.50 BSC
0.30
0.15
1.10 MAX
3.10
3.00
2.90
COPLANARITY
0.10
0.23
0.13
3.10
3.00
2.90
5.15
4.90
4.65
PIN 1
IDENTIFIER
15° MAX
0.95
0.85
0.75
0.15
0.05
Figure 49. 10-Lead Mini Small Outline Package [MSOP]
(RM-10)
Dimensions shown in millimeters
ORDERING GUIDE
Model1 R
AB (kΩ) Temperature Range Package Description Package Option Branding
AD5170BRM2.5 2.5 –40°C to +125°C 10-Lead MSOP RM-10 DD2
AD5170BRM2.5-RL7 2.5 –40°C to +125°C 10-Lead MSOP RM-10 DD2
AD5170BRMZ2.5 2.5 –40°C to +125°C 10-Lead MSOP RM-10 DD7
AD5170BRM10 10 –40°C to +125°C 10-Lead MSOP RM-10 DD3
AD5170BRM10-RL7 10 –40°C to +125°C 10-Lead MSOP RM-10 DD3
AD5170BRMZ10 10 –40°C to +125°C 10-Lead MSOP RM-10 DD4
AD5170BRMZ10-RL7 10 –40°C to +125°C 10-Lead MSOP RM-10 DD4
AD5170BRM50 50 –40°C to +125°C 10-Lead MSOP RM-10 DD0
AD5170BRM50-RL7 50 –40°C to +125°C 10-Lead MSOP RM-10 DD0
AD5170BRMZ50 50 –40°C to +125°C 10-Lead MSOP RM-10 DD6
AD5170BRM100 100 –40°C to +125°C 10-Lead MSOP RM-10 DD1
AD5170BRM100-RL7 100 –40°C to +125°C 10-Lead MSOP RM-10 DD1
AD5170BRMZ100 100 –40°C to +125°C 10-Lead MSOP RM-10 DD5
1 Z = RoHS Compliant Part.
AD5170
Rev. G | Page 24 of 24
NOTES
I2C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors).
©2003–2011 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D04104-0-5/11(G)
