512Kx36/32 & 1Mx18 Synchronous SRAM
- 1 - Rev 0.2
Dec. 2001
K7A161801A
K7A163201A PRELIMINARY
K7A163601A
Document Title
512Kx36/32 & 1Mx18-Bit Synchronous Pipelined Burst SRAM
The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the
specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters of this device. If you have any ques-
tions, please contact the SAMSUNG branch office near your office, call or contact Headquarters.
Revision History
Rev. No.
0.0
0.1
0.2
Remark
Preliminary
Preliminary
Preliminary
History
1. Initial draft
1. Add x32 org and industrial temperature .
1. Speed bin merge.
From K7A1636(32/18)08A to K7A1636(32/18)01A.
2. AC parameter change.
tOH(min)/tHZC(min) from 0.8 to 1.5 at -25
tOH(min)/tHZC(min) from 1.0 to 1.5 at -22
tOH(min)/tHZC(min) from 1.0 to 1.5 at -20
Draft Date
Feb. 23. 2001
Aug. 30. 2001
Dec.26. 2001
512Kx36/32 & 1Mx18 Synchronous SRAM
- 2 - Rev 0.2
Dec. 2001
K7A161801A
K7A163201A PRELIMINARY
K7A163601A
16Mb SB/SPB Synchronous SRAM Ordering Information
Org. Part Number Mode VDD Speed
SB ; Access Time(ns)
SPB ; Cycle Time(MHz) PKG Temp
1Mx18
K7B161825A-Q(H/F)C(I)65/75/85 SB 3.3 6.5/7.5/8.5ns
Q :100TQFP
H : 119BGA
F : 165FBGA
C
(Commercial
Temperature
Range)
I
(Industrial
Temperature
Range)
K7A161880A-QC(I)25/22/20/16/14 SPB(2E1D) 1.8 250/225/200/167/138MHz
K7A161800A-Q(H/F)C(I)25/22/20/16/14 SPB(2E1D) 3.3 250/225/200/167/138MHz
K7A161801A-QC(I)25/22/20/16/14 SPB(2E2D) 3.3 250/225/200/167/138MHz
512Kx32
K7B163225A-QC(I)65/75/85 SB 3.3 6.5/7.5/8.5ns
K7A163280A-QC(I)25/22/20/16/14 SPB(2E1D) 1.8 250/225/200/167/138MHz
K7A163200A-QC(I)25/22/20/16/14 SPB(2E1D) 3.3 250/225/200/167/138MHz
K7A163201A-QC(I)25/22/20/16/14 SPB(2E2D) 3.3 250/225/200/167/138MHz
512Kx36
K7B163625A-Q(H/F)C(I)65/75/85 SB 3.3 6.5/7.5/8.5ns
K7A163680A-QC(I)25/22/20/16/14 SPB(2E1D) 1.8 250/225/200/167/138MHz
K7A163600A-Q(H/F)C(I)25/22/20/16/14 SPB(2E1D) 3.3 250/225/200/167/138MHz
K7A163601A-QC(I)25/22/20/16/14 SPB(2E2D) 3.3 250/225/200/167/138MHz
512Kx36/32 & 1Mx18 Synchronous SRAM
- 3 - Rev 0.2
Dec. 2001
K7A161801A
K7A163201A PRELIMINARY
K7A163601A
512Kx36/32 & 1Mx18-Bit Synchronous Pipelined Burst SRAM
The K7A163601A , K7A163201A and K7A161801A are
18,874,368-bit Synchronous Static Random Access Memory
designed for high performance second level cache of Pentium
and Power PC based System.
It is organized as 512K(1M) words of 36(32/18) bits and inte-
grates address and control registers, a 2-bit burst address
counter and added some new functions for high performance
cache RAM applications; GW, BW, LBO, ZZ. Write cycles are
internally self-timed and synchronous.
Full bus-width write is done by GW, and each byte write is per-
formed by the combination of WEx and BW when GW is high.
And with CS1 high, ADSP is blocked to control signals.
Burst cycle can be initiated with either the address status pro-
cessor(ADSP) or address status cache controller(ADSC)
inputs. Subsequent burst addresses are generated internally in
the system′s burst sequence and are controlled by the burst
address advance(ADV) input.
LBO pin is DC operated and determines burst sequence(linear
or interleaved).
ZZ pin controls Power Down State and reduces Stand-by cur-
rent regardless of CLK.
The K7A163601A, K7A163201A and K7A161801A are fabri-
cated using SAMSUNG′s high performance CMOS technology
and is available in a 100pin TQFP package. Multiple power and
ground pins are utilized to minimize ground bounce.
GENERAL DESCRIPTIONFEATURES
LOGIC BLOCK DIAGRAM
• Synchronous Operation.
• 2 Stage Pipelined operation with 4 Burst.
• On-Chip Address Counter.
• Self-Timed Write Cycle.
• On-Chip Address and Control Registers.
• VDD= 3.3V +0.165V/-0.165V Power Supply.
• I/O Supply Voltage 3.3V +0.165V/-0.165V for 3.3V I/O
or 2.5V+0.4V/-0.125V for 2.5V I/O.
• 5V Tolerant Inputs Except I/O Pins.
• Byte Writable Function.
• Global Write Enable Controls a full bus-width write.
• Power Down State via ZZ Signal.
• LBO Pin allows a choice of either a interleaved burst or a linear
burst.
• Three Chip Enables for simple depth expansion with No Data
Contention ; 2cycle Enable, 2cycle Disable.
• Asynchronous Output Enable Control.
• ADSP, ADSC, ADV Burst Control Pins.
• TTL-Level Three-State Output.
• 100-TQFP-1420A Package
• Operating in commeical and industrial temperature range.
CLK
LBO
ADV
ADSC
ADSP
CS1
CS2
CS2
GW
BW
WEx
OE
ZZ
DQa0 ~ DQd7 or DQa0 ~ DQb7
BURST CONTROL
LOGIC BURST 512Kx36/32 , 1Mx18
ADDRESS
CONTROL OUTPUT
DATA-IN
ADDRESS
COUNTER
MEMORY
ARRAY
REGISTER
REGISTER
BUFFER
LOGIC
CONTROL
REGISTER
CONTROL
REGISTER
A′0~A′1
A0~A1
or A2~A19
or A0~A19
REGISTER
DQPa ~ DQPd
A0~A18 A2~A18
(x=a,b,c,d or a,b)
DQPa,DQPb
FAST ACCESS TIMES
PARAMETER Symbol -25 -22 -20 -16 -14 Unit
Cycle Time tCYC 4.0 4.4 5.0 6.0 7.2 ns
Clock Access Time tCD 2.6 2.8 3.1 3.5 4.0 ns
Output Enable Access Time tOE 2.6 2.8 3.1 3.5 4.0 ns
512Kx36/32 & 1Mx18 Synchronous SRAM
- 4 - Rev 0.2
Dec. 2001
K7A161801A
K7A163201A PRELIMINARY
K7A163601A
PIN CONFIGURATION(TOP VIEW)
PIN NAME
Note : 1. A0 and A1 are the two least significant bits(LSB) of the address field and set the internal burst counter if burst is desired.
SYMBOL PIN NAME TQFP PIN NO. SYMBOL PIN NAME TQFP PIN NO.
A0 - A18
ADV
ADSP
ADSC
CLK
CS1
CS2
CS2
WEx(x=a,b,c,d)
OE
GW
BW
ZZ
LBO
Address Inputs
Burst Address Advance
Address Status Processor
Address Status Controller
Clock
Chip Select
Chip Select
Chip Select
Byte Write Inputs
Output Enable
Global Write Enable
Byte Write Enable
Power Down Input
Burst Mode Control
32,33,34,35,36,37,42
43,44,45,46,47,48,49
50,81,82,99,100
83
84
85
89
98
97
92
93,94,95,96
86
88
87
64
31
VDD
VSS
N.C.
DQa0~a7
DQb0~b7
DQc0~c7
DQd0~d7
DQPa~Pd
or N.C
VDDQ
VSSQ
Power Supply(+3.3V)
Ground
No Connect
Data Inputs/Outputs
Output Power Supply
(3.3V or 2.5V)
Output Ground
15,41,65,91
17,40,67,90
14,16,38,39,66
52,53,56,57,58,59,62,63
68,69,72,73,74,75,78,79
2,3,6,7,8,9,12,13
18,19,22,23,24,25,28,29
51,80,1,30
4,11,20,27,54,61,70,77
5,10,21,26,55,60,71,76
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
100 Pin TQFP
(20mm x 14mm)
NC/DQPc
DQc0
DQc1
VDDQ
VSSQ
DQc2
DQc3
DQc4
DQc5
VSSQ
VDDQ
DQc6
DQc7
N.C.
VDD
N.C.
VSS
DQd0
DQd1
VDDQ
VSSQ
DQd2
DQd3
DQd4
DQd5
VSSQ
VDDQ
DQd6
DQd7
NC/DQPd
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
DQPb/NC
DQb7
DQb6
VDDQ
VSSQ
DQb5
DQb4
DQb3
DQb2
VSSQ
VDDQ
DQb1
DQb0
VSS
N.C.
VDD
ZZ
DQa7
DQa6
VDDQ
VSSQ
DQa5
DQa4
DQa3
DQa2
VSSQ
VDDQ
DQa1
DQa0
DQPa/NC
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
A6
A7
CS1
CS2
WEd
WEc
WEb
WEa
CS2
VDD
VSS
CLK
GW
BW
OE
ADSC
ADSP
ADV
A8
81 A9
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
A15
A14
A13
A12
A11
A10
A17
A18
VDD
VSS
N.C.
N.C.
A0
A1
A2
A3
A4
A5
31
LBO
A16
K7A163601A(512Kx36)
K7A163201A(512Kx32)
512Kx36/32 & 1Mx18 Synchronous SRAM
- 5 - Rev 0.2
Dec. 2001
K7A161801A
K7A163201A PRELIMINARY
K7A163601A
PIN CONFIGURATION(TOP VIEW)
PIN NAME
Note : 1. A0 and A1 are the two least significant bits(LSB) of the address field and set the internal burst counter if burst is desired.
SYMBOL PIN NAME TQFP PIN NO. SYMBOL PIN NAME TQFP PIN NO.
A0 - A19
ADV
ADSP
ADSC
CLK
CS1
CS2
CS2
WEx(x=a,b)
OE
GW
BW
ZZ
LBO
Address Inputs
Burst Address Advance
Address Status Processor
Address Status Controller
Clock
Chip Select
Chip Select
Chip Select
Byte Write Inputs
Output Enable
Global Write Enable
Byte Write Enable
Power Down Input
Burst Mode Control
32,33,34,35,36,37,42
43,44,45,46,47,48,49
50 80,81,82,99,100
83
84
85
89
98
97
92
93,94
86
88
87
64
31
VDD
VSS
N.C.
DQa0 ~ a7
DQb0 ~ b7
DQPa, Pb
VDDQ
VSSQ
Power Supply(+3.3V)
Ground
No Connect
Data Inputs/Outputs
Output Power Supply
(3.3V or 2.5V)
Output Ground
15,41,65,91
17,40,67,90
1,2,3,6,7,14,16,25,28,29
30,38,39,51,52,53,56,57
66,75,78,79,95,96
58,59,62,63,68,69,72,73
8,9,12,13,18,19,22,23
74,24
4,11,20,27,54,61,70,77
5,10,21,26,55,60,71,76
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
100 Pin TQFP
(20mm x 14mm)
N.C.
N.C.
N.C.
VDDQ
VSSQ
N.C.
N.C.
DQb0
DQb1
VSSQ
VDDQ
DQb2
DQb3
N.C.
VDD
N.C.
VSS
DQb4
DQb5
VDDQ
VSSQ
DQb6
DQb7
DQPb
N.C.
VSSQ
VDDQ
N.C.
N.C.
N.C.
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
N.C.
N.C.
VDDQ
VSSQ
N.C.
DQPa
DQa7
DQa6
VSSQ
VDDQ
DQa5
DQa4
VSS
N.C.
VDD
ZZ
DQa3
DQa2
VDDQ
VSSQ
DQa1
DQa0
N.C.
N.C.
VSSQ
VDDQ
N.C.
N.C.
N.C.
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
A6
A7
CS1
CS2
N.C.
N.C.
WEb
WEa
CS2
VDD
VSS
CLK
GW
BW
OE
ADSC
ADSP
ADV
A8
81 A9
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
A15
A14
A13
A12
A11
A18
A19
VDD
VSS
N.C.
N.C.
A0
A1
A2
A3
A4
A5
31
LBO
A16
A17
A10
K7A161801A(1Mx18)
512Kx36/32 & 1Mx18 Synchronous SRAM
- 6 - Rev 0.2
Dec. 2001
K7A161801A
K7A163201A PRELIMINARY
K7A163601A
FUNCTION DESCRIPTION
The K7A163601A , K7A163201A and K7A161801A are synchronous SRAM designed to support the burst address accessing
sequence of the Power PC based microprocessor. All inputs (with the exception of OE, LBO and ZZ) are sampled on rising clock
edges. The start and duration of the burst access is controlled by ADSC, ADSP and ADV and chip select pins.
The accesses are enabled with the chip select signals and output enabled signals. Wait states are inserted into the access with
ADV.
When ZZ is pulled high, the SRAM will enter a Power Down State. At this time, internal state of the SRAM is preserved. When ZZ
returns to low, the SRAM normally operates after 2cycles of wake up time. ZZ pin is pulled down internally.
Read cycles are initiated with ADSP(regardless of WEx and ADSC)using the new external address clocked into the on-chip address
register whenever ADSP is sampled low, the chip selects are sampled active, and the output buffer is enabled with OE. In read oper-
ation the data of cell array accessed by the current address, registered in the Data-out registers by the positive edge of CLK, are car-
ried to the Data-out buffer by the next positive edge of CLK. The data, registered in the Data-out buffer, are projected to the output
pins. ADV is ignored on the clock edge that samples ADSP asserted, but is sampled on the subsequent clock edges. The address
increases internally for the next access of the burst when WEx are sampled High and ADV is sampled low. And ADSP is blocked to
control signals by disabling CS1.
All byte write is done by GW(regaedless of BW and WEx.), and each byte write is performed by the combination of BW and WEx
when GW is high.
Write cycles are performed by disabling the output buffers with OE and asserting WEx. WEx are ignored on the clock edge that sam-
ples ADSP low, but are sampled on the subsequent clock edges. The output buffers are disabled when WEx are sampled
Low(regaedless of OE). Data is clocked into the data input register when WEx sampled Low. The address increases internally to the
next address of burst, if both WEx and ADV are sampled Low. Individual byte write cycles are performed by any one or more byte
write enable signals(WEa, WEb, WEc or WEd) sampled low. The WEa control DQa0 ~ DQa7 and DQPa, WEb controls DQb0 ~ DQb7
and DQPb, WEc controls DQc0 ~ DQc7 and DQPc, and WEd control DQd0 ~ DQd7 and DQPd. Read or write cycle may also be initi-
ated with ADSC, instead of ADSP. The differences between cycles initiated with ADSC and ADSP as are follows;
ADSP must be sampled high when ADSC is sampled low to initiate a cycle with ADSC.
WEx are sampled on the same clock edge that sampled ADSC low(and ADSP high).
Addresses are generated for the burst access as shown below, The starting point of the burst sequence is provided by the external
address. The burst address counter wraps around to its initial state upon completion. The burst sequence is determined by the state
of the LBO pin. When this pin is Low, linear burst sequence is selected. When this pin is High, Interleaved burst sequence is
selected.
BURST SEQUENCE TABLE (Interleaved Burst)
LBO PIN HIGH Case 1 Case 2 Case 3 Case 4
A1A0A1A0A1A0A1A0
First Address
Fourth Address
0
0
1
1
0
1
0
1
0
0
1
1
1
0
1
0
1
1
0
0
0
1
0
1
1
1
0
0
1
0
1
0
BQ TABLE (Linear Burst)
Note : 1. LBO pin must be tied to High or Low, and Floating State must not be allowed.
LBO PIN LOW Case 1 Case 2 Case 3 Case 4
A1A0A1A0A1A0A1A0
First Address
Fourth Address
0
0
1
1
0
1
0
1
0
1
1
0
1
0
1
0
1
1
0
0
0
1
0
1
1
0
0
1
1
0
1
0
ASYNCHRONOUS TRUTH TABLE
OPERATION ZZ OE I/O Status
Sleep Mode HXHigh-Z
Read L L DQ
LHHigh-Z
Write LXDin, High-Z
Deselected LXHigh-Z
Notes
1. X means "Don′t Care".
2. ZZ pin is pulled down internally
3. For write cycles that following read cycles, the output buffers must be
disabled with OE, otherwise data bus contention will occur.
4. Sleep Mode means power down state of which stand-by current does
not depend on cycle time.
5. Deselected means power down state of which stand-by current
depends on cycle time.
512Kx36/32 & 1Mx18 Synchronous SRAM
- 7 - Rev 0.2
Dec. 2001
K7A161801A
K7A163201A PRELIMINARY
K7A163601A
SYNCHRONOUS TRUTH TABLE
Notes : 1. X means "Don′t Care". 2. The rising edge of clock is symbolized by ↑.
3. WRITE = L means Write operation in WRITE TRUTH TABLE.
WRITE = H means Read operation in WRITE TRUTH TABLE.
4. Operation finally depends on status of asynchronous input pins(ZZ and OE).
CS1CS2CS2ADSP ADSC ADV WRITE CLK ADDRESS ACCESSED Operation
HXXXLX X ↑N/A Not Selected
L L XLX X X ↑N/A Not Selected
LXHLX X X ↑N/A Not Selected
L L X X LX X ↑N/A Not Selected
LXHXLX X ↑N/A Not Selected
LHL L X X X ↑External Address Begin Burst Read Cycle
LHLHLXL↑External Address Begin Burst Write Cycle
LHLHLXH↑External Address Begin Burst Read Cycle
XXXH H LH↑Next Address Continue Burst Read Cycle
HXXXHLH↑Next Address Continue Burst Read Cycle
XXXH H L L ↑Next Address Continue Burst Write Cycle
HXXXHL L ↑Next Address Continue Burst Write Cycle
XXXH H H H ↑Current Address Suspend Burst Read Cycle
HXXXH H H ↑Current Address Suspend Burst Read Cycle
XXXHHH L↑Current Address Suspend Burst Write Cycle
HXXXH H L↑Current Address Suspend Burst Write Cycle
TRUTH TABLES
WRITE TRUTH TABLE(x36 / x32)
Notes : 1. X means "Don′t Care".
2. All inputs in this table must meet setup and hold time around the rising edge of CLK(↑).
GW BW WEaWEbWEcWEdOPERATION
H H XXXX READ
HLHHHH READ
HL L HHH WRITE BYTE a
HLHLH H WRITE BYTE b
HLH H LLWRITE BYTE c and d
HLLLLL WRITE ALL BYTEs
LXXXXX WRITE ALL BYTEs
WRITE TRUTH TABLE(x18)
Notes : 1. X means "Don′t Care".
2. All inputs in this table must meet setup and hold time around the rising edge of CLK(↑).
GW BW WEaWEbOPERATION
HHX X READ
HLH H READ
HL L HWRITE BYTE a
HLHLWRITE BYTE b
HL L L WRITE ALL BYTEs
LX X X WRITE ALL BYTEs
512Kx36/32 & 1Mx18 Synchronous SRAM
- 8 - Rev 0.2
Dec. 2001
K7A161801A
K7A163201A PRELIMINARY
K7A163601A
CAPACITANCE*(TA=25°C, f=1MHz)
*Note : Sampled not 100% tested.
PARAMETER SYMBOL TEST CONDITION Min Max Unit
Input Capacitance CIN VIN=0V -5pF
Output Capacitance COUT VOUT=0V -7pF
OPERATING CONDITIONS at 3.3V I/O(0°C ≤ TA ≤ 70°C)
* The above parameters are also guaranteed at industrial temperature range.
PARAMETER SYMBOL MIN Typ. Max Unit
Supply Voltage VDD 3.135 3.3 3.465 V
VDDQ 3.135 3.3 3.465 V
Ground VSS 0 0 0 V
OPERATING CONDITIONS at 2.5V I/O(0°C ≤ TA ≤ 70°C)
* The above parameters are also guaranteed at industrial temperature range.
PARAMETER SYMBOL MIN Typ. Max Unit
Supply Voltage VDD 3.135 3.3 3.465 V
VDDQ 2.375 2.5 2.9 V
Ground VSS 000V
ABSOLUTE MAXIMUM RATINGS*
*Note : Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
PARAMETER SYMBOL RATING UNIT
Voltage on VDD Supply Relative to VSS VDD -0.3 to 4.6 V
Voltage on VDDQ Supply Relative to VSS VDDQ VDD V
Voltage on Input Pin Relative to VSS VIN -0.3 to VDD+0.3 V
Voltage on I/O Pin Relative to VSS VIO -0.3 to VDDQ+0.3 V
Power Dissipation PD1.6 W
Storage Temperature TSTG -65 to 150 °C
Operating Temperature Commercial TOPR 0 to 70 °C
Industrial TOPR -40 to 85 °C
Storage Temperature Range Under Bias TBIAS -10 to 85 °C
512Kx36/32 & 1Mx18 Synchronous SRAM
- 9 - Rev 0.2
Dec. 2001
K7A161801A
K7A163201A PRELIMINARY
K7A163601A
VSS
VIH
VSS-1.0V
20% tCYC(MIN)
TEST CONDITIONS
* The above parameters are also guaranteed at industrial temperature range.
Parameter Value
Input Pulse Level(for 3.3V I/O) 0 to 3.0V
Input Pulse Level(for 2.5V I/O) 0 to 2.5V
Input Rise and Fall Time(Measured at 20% to 80% for 3.3V I/O) 1.0V/ns
Input Rise and Fall Time(Measured at 20% to 80% for 2.5V I/O) 1.0V/ns
Input and Output Timing Reference Levels for 3.3V I/O 1.5V
Input and Output Timing Reference Levels for 2.5V I/O VDDQ/2
Output Load See Fig. 1
(V
DD
=3.3V+0.165V/-0.165V,V
DDQ
=3.3V+0.165/-0.165V or V
DD
=3.3V+0.165V/-0.165V,V
DDQ
=2.5V+0.4V/-0.125V, T
A
=0to70
°
C)
DC ELECTRICAL CHARACTERISTICS(VDD=3.3V+0.165V/-0.165V, TA=0°C to +70°C)
Notes : 1. The above parameters are also guaranteed at industrial temperature range.
2. Reference AC Operating Conditions and Characteristics for input and timing.
3. Data states are all zero.
4. In Case of I/O Pins, the Max. VIH=VDDQ+0.3V.
PARAMETER SYMBOL TEST CONDITIONS MIN MAX UNIT NOTES
Input Leakage Current(except ZZ) IIL VDD = Max ; VIN=VSS to VDD -2 +2 µA
Output Leakage Current IOL Output Disabled, VOUT=VSS to VDDQ -2 +2 µA
Operating Current ICC Device Selected, IOUT=0mA,
ZZ≤VIL , Cycle Time ≥ tCYC Min
-25 -440
mA 1,2
-22 -400
-20 -370
-16 -340
-14 -280
Standby Current
ISB
Device deselected, IOUT=0mA,
ZZ≤VIL, f=Max,
All Inputs≤0.2V or ≥ VDD-0.2V
-25 -120 mA
-22 -110
-20 -100
-16 -90 mA
-14 -90
ISB1 Device deselected, IOUT=0mA, ZZ≤0.2V,
f = 0, All Inputs=fixed (VDD-0.2V or 0.2V) -70 mA
ISB2 Device deselected, IOUT=0mA, ZZ≥VDD-
0.2V, f=Max, All Inputs≤VIL or ≥VIH -60 mA
Output Low Voltage(3.3V I/O) VOL IOL=8.0mA -0.4 V
Output High Voltage(3.3V I/O) VOH IOH=-4.0mA 2.4 -V
Output Low Voltage(2.5V I/O) VOL IOL=1.0mA -0.4 V
Output High Voltage(2.5V I/O) VOH IOH=-1.0mA 2.0 -V
Input Low Voltage(3.3V I/O) VIL -0.3* 0.8 V
nput High Voltage(3.3V I/O) VIH 2.0 VDD+0.3** V3
Input Low Voltage(2.5V I/O) VIL -0.3* 0.7 V
Input High Voltage(2.5V I/O) VIH 1.7 VDD+0.3** V3
512Kx36/32 & 1Mx18 Synchronous SRAM
- 10 - Rev 0.2
Dec. 2001
K7A161801A
K7A163201A PRELIMINARY
K7A163601A
Output Load(B),
(for tLZC, tLZOE, tHZOE & tHZC)
Dout
353Ω / 1538Ω5pF*
+3.3V for 3.3V I/O
319Ω / 1667Ω
Fig. 1
* Including Scope and Jig Capacitance
Output Load(A)
Dout
Zo=50Ω
RL=50ΩVL=1.5V for 3.3V I/O
VDDQ/2 for 2.5V I/O
/+2.5V for 2.5V I/O
30pF*
AC TIMING CHARACTERISTICS(VDD=3.3V+0.165V/-0.165V, TA=0°C to +70°C)
Notes : 1. The above parameters are also guaranteed at industrial temperature range.
2. All address inputs must meet the specified setup and hold times for all rising clock edges whenever ADSC and/or ADSP is sampled low and
CS is sampled low. All other synchronous inputs must meet the specified setup and hold times whenever this device is chip selected.
3. Both chip selects must be active whenever ADSC or ADSP is sampled low in order for the this device to remain enabled.
4. ADSC or ADSP must not be asserted for at least 2 Clock after leaving ZZ state.
Parameter Symbol -25 -22 -20 -16 -14 Unit
MIN MAX Min Max MIN MAX Min Max Min Max
Cycle Time tCYC 4.0 -4.4 -5.0 -6.0 -7.2 -ns
Clock Access Time tCD -2.6 -2.8 -3.1 -3.5 -4.0 ns
Output Enable to Data Valid tOE -2.6 -2.8 -3.1 -3.5 -4.0 ns
Clock High to Output Low-Z tLZC 0-0-0-0-0-ns
Output Hold from Clock High tOH 1.5 -1.5 -1.5 -1.5 -1.5 -ns
Output Enable Low to Output Low-Z tLZOE 0-0-0-0-0-ns
Output Enable High to Output High-Z tHZOE -2.6 -2.8 -3.0 -3.0 -3.5 ns
Clock High to Output High-Z tHZC 1.5 2.6 1.5 2.8 1.5 3.0 1.5 3.0 1.5 3.5 ns
Clock High Pulse Width tCH 1.7 -1.8 -2.0 -2.1 -2.5 -ns
Clock Low Pulse Width tCL 1.7 -1.8 -2.0 -2.1 -2.5 -ns
Address Setup to Clock High tAS 1.2 -1.4 -1.4 -1.5 -1.5 -ns
Address Status Setup to Clock High tSS 1.2 -1.4 -1.4 -1.5 -1.5 -ns
Data Setup to Clock High tDS 1.2 -1.4 -1.4 -1.5 -1.5 -ns
Write Setup to Clock High (GW, BW, WEX)tWS 1.2 -1.4 -1.4 -1.5 -1.5 -ns
Address Advance Setup to Clock High tADVS 1.2 -1.4 -1.4 -1.5 -1.5 -ns
Chip Select Setup to Clock High tCSS 1.2 -1.4 -1.4 -1.5 -1.5 -ns
Address Hold from Clock High tAH 0.3 -0.4 -0.4 -0.5 -0.5 -ns
Address Status Hold from Clock High tSH 0.3 -0.4 -0.4 -0.5 -0.5 -ns
Data Hold from Clock High tDH 0.3 -0.4 -0.4 -0.5 -0.5 -ns
Write Hold from Clock High (GW, BW, WEX)tWH 0.3 -0.4 -0.4 -0.5 -0.5 -ns
Address Advance Hold from Clock High tADVH 0.3 -0.4 -0.4 -0.5 -0.5 -ns
Chip Select Hold from Clock High tCSH 0.3 -0.4 -0.4 -0.5 -0.5 -ns
ZZ High to Power Down tPDS 2-2-2-2-2-cycle
ZZ Low to Power Up tPUS 2-2-2-2-2-cycle
512Kx36/32 & 1Mx18 Synchronous SRAM
- 11 - Rev 0.2
Dec. 2001
K7A161801A
K7A163201A PRELIMINARY
K7A163601A
CLOCK
ADSP
ADSC
ADDRESS
WRITE
CS
ADV
OE
Data Out
TIMING WAVEFORM OF READ CYCLE
NOTES : WRITE = L means GW = L, or GW = H, BW = L, WEx = L
CS = L means CS1 = L, CS2 = H and CS2 = L
CS = H means CS1 = H, or CS1 = L and CS2 = H, or CS1 = L, and CS2 = L
tCH tCL
tSS tSH
tSS tSH
tAS tAH
A1 A2 A3
BURST CONTINUED WITH
NEW BASE ADDRESS
tWS tWH
tCSS tCSH
tADVS tADVH
tOE tHZOE
tLZOE
tCD
tOH
(ADV INSERTS WAIT STATE)
tHZC
Q3-4Q3-3Q3-2Q3-1Q2-4Q2-3Q2-2Q2-1
Q1-1
Don′t Care
Undefined
tCYC
512Kx36/32 & 1Mx18 Synchronous SRAM
- 12 - Rev 0.2
Dec. 2001
K7A161801A
K7A163201A PRELIMINARY
K7A163601A
TIMING WAVEFORM OF WRTE CYCLE
CLOCK
ADSP
ADSC
ADDRESS
WRITE
CS
ADV
Data In
tCH tCL
tSS tSH
tAS tAH
A1 A2 A3
(ADSC EXTENDED BURST)
tHZOE
D2-1D1-1
tCSS tCSH
(ADV SUSPENDS BURST)
D2-2 D2-3 D2-4 D3-1 D3-2 D3-3D2-2 D3-4
Q0-3 Q0-4
OE
Data Out
tSS tSH
tWS tWH
tADVS tADVH
tDS tDH
Don′t Care
Undefined
tCYC
512Kx36/32 & 1Mx18 Synchronous SRAM
- 13 - Rev 0.2
Dec. 2001
K7A161801A
K7A163201A PRELIMINARY
K7A163601A
TIMING WAVEFORM OF COMBINATION READ/WRTE CYCLE(ADSP CONTROLLED , ADSC=HIGH)
CLOCK
ADSP
ADDRESS
WRITE
CS
ADV
OE
Data Out
tCH tCL
tDS tDH
Q3-2
Data In
tOH
A1 A2 A3
D2-1
Q3-1 Q3-3
tSS tSH
tAS tAH
tWS tWH
tADVS tADVH
tLZOE
tHZOE
tCD
tHZC
Q3-4
tLZC
Q1-1
Don′t Care
Undefined
tCYC
512Kx36/32 & 1Mx18 Synchronous SRAM
- 14 - Rev 0.2
Dec. 2001
K7A161801A
K7A163201A PRELIMINARY
K7A163601A
TIMING WAVEFORM OF SINGLE READ/WRITE CYCLE(ADSC CONTROLLED , ADSP=HIGH)
CLOCK
ADSC
ADDRESS
WRITE
CS
ADV
OE
Data In
tCH tCL
tHZOE
D6-1
Data Out
tWS tWH
tLZOE tOH
tOE
D5-1 D7-1
tWS tWH
tLZOE
tDHtDS
A1 A2 A3 A4 A5 A6 A7 A8 A9
Q3-1Q1-1 Q2-1 Q4-1 Q8-1
tCSS tCSH
tSS tSH
Q9-1
Don′t Care
Undefined
tCYC
512Kx36/32 & 1Mx18 Synchronous SRAM
- 15 - Rev 0.2
Dec. 2001
K7A161801A
K7A163201A PRELIMINARY
K7A163601A
TIMING WAVEFORM OF POWER DOWN CYCLE
CLOCK
ADSP
ADDRESS
WRITE
CS
ADV
Data In
tCH tCL
D2-2
OE
tHZOE
D2-1
A1
tSS tSH
Data Out
tPUS
ADSC
ZZ
tAS tAH
tCSS tCSH
Sleep State
Normal Operation Mode
ZZ Recovery Cycle
A2
tWS tWH
tLZOE
Q1-1
tOE
tHZC
tPDS
ZZ Setup Cycle
Don′t Care
Undefined
tCYC
512Kx36/32 & 1Mx18 Synchronous SRAM
- 16 - Rev 0.2
Dec. 2001
K7A161801A
K7A163201A PRELIMINARY
K7A163601A
APPLICATION INFORMATION
The Samsung 512Kx36 Synchronous Pipelined Burst SRAM has two additional chip selects for simple depth expansion.
DEPTH EXPANSION
This permits easy secondary cache upgrades from 512K depth to 1M depth without extra logic.
Data
Address
CLK
ADS
CS
2
CS
2
CLK
ADSC
WEx
OE
CS
1
Address Data
ADV ADSP
512Kx36
SPB
SRAM
(Bank 0)
CS
2
CS
2
CLK
ADSC
WEx
OE
CS
1
Address Data
ADV ADSP
512Kx36
SPB
SRAM
(Bank 1)
CLK
Address
Cache
Controller
A
[0:19]
A
[19]
A
[0:18]
A
[19]
A
[0:18]
I/O
[0:71]
Microprocessor
Clock
ADSP
ADDRESS
Data Out
OE
Data Out
WRITE
CS1
An+1*
ADV
(Bank 0)
(Bank 1)
[0:n*]
INTERLEAVE READ TIMING (Refer to non-interleave write timing for interleave write timing)
Bank 0 is selected by CS2, and Bank 1 deselected by CS2
Q1-1 Q1-2 Q1-4Q1-3
tSS tSH
A1
Q2-2 Q2-4Q2-3
tWS tWH
tADVS tADVH
tOE
tLZOE tHZC
Bank 0 is deselected by CS2, and Bank 1 selected by CS2
tCSS tCSH
tCD
tLZC Q2-1
A2
tAS tAH
Don′t Care Undefined
(ADSP CONTROLLED , ADSC=HIGH)
*Notes : n = 14 32K depth , 15 64K depth
16 128K depth , 17 256K depth
18 512K depth , 19 1M depth
512Kx36/32 & 1Mx18 Synchronous SRAM
- 17 - Rev 0.2
Dec. 2001
K7A161801A
K7A163201A PRELIMINARY
K7A163601A
APPLICATION INFORMATION
DEPTH EXPANSION
Data
Address
CLK
ADS
Microprocessor
CS
2
CS
2
CLK
ADSC
WEx
OE
CS
1
Address Data
ADV ADSP
1Mx18
SPB
SRAM
(Bank 0)
CS
2
CS
2
CLK
ADSC
WEx
OE
CS
1
Address Data
ADV ADSP
1Mx18
SPB
SRAM
(Bank 1)
CLK
Address
Cache
Controller
A
[0:20]
A
[20]
A
[0:19]
A
[20]
A
[0:19]
I/O
[0:71]
The Samsung 1Mx18 Synchronous Pipelined Burst SRAM has two additional chip selects for simple depth expansion.
This permits easy secondary cache upgrades from 1M depth to 2M depth without extra logic.
Clock
ADSP
ADDRESS
Data Out
OE
Data Out
WRITE
CS1
An+1*
ADV
(Bank 0)
(Bank 1)
[0:n*]
INTERLEAVE READ TIMING (Refer to non-interleave write timing for interleave write timing)
Bank 0 is selected by CS2, and Bank 1 deselected by CS2
Q1-1 Q1-2 Q1-4Q1-3
tSS tSH
A1
Q2-2 Q2-4Q2-3
tWS tWH
tADVS tADVH
tOE
tLZOE tHZC
Bank 0 is deselected by CS2, and Bank 1 selected by CS2
tCSS tCSH
tCD
tLZC Q2-1
A2
tAS tAH
Don′t Care Undefined
(ADSP CONTROLLED , ADSC=HIGH)
*Notes : n = 14 32K depth , 15 64K depth
16 128K depth , 17 256K depth
18 512K depth , 19 1M depth
20 2M depth
512Kx36/32 & 1Mx18 Synchronous SRAM
- 18 - Rev 0.2
Dec. 2001
K7A161801A
K7A163201A PRELIMINARY
K7A163601A
PACKAGE DIMENSIONS
0.10 MAX
0~8
°
22.00
±
0.30
20.00
±
0.20
16.00
±
0.30
14.00
±
0.20
1.40
±
0.10
1.60 MAX
0.05 MIN
(0.58)
0.50
±
0.10
#1
(0.83) 0.50
±
0.10
100-TQFP-1420A
0.65 0.30
±
0.10
0.10 MAX
+ 0.10
- 0.05
0.127
Units ; millimeters/Inches
