2K x 8 Reprogrammable Registered PROM
CY7C245A
Cypress Semiconductor Corporation • 3901 North F irs t Street • San Jos e • CA 95134 • 408-943-2 600
Document #: 38-04007 Rev. *B Revised December 27, 2002
1CY7C245A
Features
• Window ed for reprogramm abi lity
• CMOS for optimum speed/power
• High speed
—15-ns address set-up
—10-ns clock to output
• Low power
—330 mW (commercial) for -25 ns
—660 mW (military)
• Programmable synchronous or asynchronous output
enable
• On-chip edge-triggered registers
• Programmable asynchronous register (INIT)
• EPROM technology, 100% programmable
• Slim, 300-mil, 24-pin plastic or hermetic DIP
•5V ±10% VCC, commercial and military
• TTL-c ompatib le I/O
• Direct replacement for bipolar PROMs
• Capable of withstanding greater than 2001V static
discharge
Functional Descri p tion
The CY7C245A is a high-performance, 2K x 8, electrically
progra mma b le, read o nly memory p a ck ag ed i n a slim 300 -mi l
plastic or hermetic DIP. The ceramic package may be
equipped with an erasure window; when exposed to UV light
the PROM is erased and can then be reprogrammed. The
memory cells utilize proven EPROM floating-gate technology
and byte-wide intelligent programming algorithms.
The CY7C245A replaces bipolar devices and offers the advan-
tages of lower power, reprogrammability, superior perfor-
mance and high programming yield. The EPROM cell requires
only 12.5 V for the superv oltag e, and low current requir ements
allow gang programming. The EPROM cells allow each
memory lo ca tion to b e te sted 100 %, bec au se each lo cation i s
written into, erased, and repeatedly exercised prior to encap-
sulation. Each PROM is also tested for AC performance to
guarantee that after customer programming the product will
meet AC specification limits.
The CY7C245A has an asynchronous initial ize function (INI T).
This function acts as a 2049th 8-bit word loaded into the
on-chip register. It is user programmable with any desired
word, or may b e used as a PRESET or CLEAR f unction on the
outputs. INIT is triggered by a low level, not an edge.
Logic Block Diagram PinConfigurations
1
2
3
4
5
6
7
8
9
10
11
12
16
17
18
19
20
24
23
22
21
13
14
A7
A6
A5
A4
A3
A2
A1
A0
O0
O1
O2
GND
VCC
A8
A9
INIT
CP
O7
O6
O4
O5
O3
PROGRAMMABLE
ARRAY MULTIPLEXER
15
8-BIT
EDGE-
REGISTER
TRIGGERED
O7
O6
O5
O4
O3
O2
O1
O0
CP
CP
E/E S
E/ES
28
4
5
6
7
8
9
10
321 27
1314151617
26
25
24
23
22
21
20
11
12 19
A5
V
CC
GND A6
A7
O3
O1
O018
O4
O5
NC
A0
A4
A3A10
NC
NC
NC
INIT
E/ES
O7
O6
A2
A1CP
O2
A8
INIT
INITIALIZE WORD
PROGRAMMABLE
A9
PROGRAMMABLE
MULTIPLEXER
DQ
C
A10
ADDRESS
DECODER
A0
A1
A2
A3
A4
A5
A6
A8
A9
A10
A7
COLUMN
ADDRESS
ROW
ADDRESS
DIP
Top View
LCC/PLCC (Opaque only)
Top View
Selection Guide
7C245A-15 7C245A-18 7C245A-25 7C245A-35 Unit
Minimum Address Set-Up Time 15 18 25 35 ns
Maxim um C loc k to Out put 10 12 12 15 ns
Maximum Operating
Current Standard Commercial 120 120 90 90 mA
Military 120 120 120 mA
CY7C245A
Document #: 38-04007 Rev. *B Page 2 of 11
Maximum Ratings[1]
(Above which the useful life may be impaired. For user guide-
lines, not tes ted .)
Storage Temperature .....................................−65°C to +150°C
Ambient Temperature with
Power Applied..................................................−55°C to +125°C
Supply Voltage to Ground Potential
(Pin 24 to Pin 12).................................................−0.5V to +7.0V
DC Voltage Applied to Outputs
in High Z State .....................................................−0.5V to +7.0V
DC Input Voltage.................................................−3.0V to +7.0V
DC Program Voltage (Pins 7, 18, 20)...........................13.0V
UV Erasure...................................................7258 Wsec/cm2
Static Discha rge Voltage..... ................. ...... ................> 200 1V
(per MIL-STD-883, Method 3015)
Latch-Up Current.....................................................>200 mA
]
Operating Range
Range Ambient
Temperature VCC
Commercial 0°C to +70°C 5V ±10%
Military[2] −55°C to +125°C 5V ±10%
Electrical Characteristi cs Ov er the Operating Ran ge [3,4]
7C245A-15 7C245A-18
7C245A-25
7C245A-35
7C245A-45
Parameter Description Test Conditions Min. Max. Min. Max. Min. Max. Unit
VOH Output HIGH Voltage VCC = Min., IOH = −4.0 mA
VIN = VIH or VIL 2.4 2.4 2.4 V
VOL Output LOW Voltage VCC = Min., IOL = 16 mA
VIN = VIH or VIL 0.4 0.4 0.4 V
VIH Input HIGH Level Guaranteed Input Logical
HIGH Voltage for All Inputs 2.0 VCC 2.0 VCC 2.0 VCC V
VIL Input LOW Level Guaranteed Input Logical
LOW Voltage for All Inputs 0.8 0.8 0.8 V
IIX Input Leakage Current GND < VIN < VCC −10 +10 −10 +10 −10 +10 µA
VCD Input Clamp Diode
Voltage Note 4
IOZ Output Leakage
Current GND < VO < VCC
Output Disabled[5] −10 +10 −10 +10 −10 +10 µA
IOS Output Short
Circuit Current VCC = Max.,
VOUT = 0.0V[6] −20 −90 −20 −90 −20 −90 mA
ICC Power Su ppl y Cu rrent VCC = Max.,
IOUT = 0 mA Com’l 120 120 90 mA
Mil 120 120
VPP Programming Supply
Voltage 12 13 12 13 12 13 V
IPP Programming Supply
Current 50 50 50 mA
VIHP Input HIGH
Program ming Voltage 3.0 3.0 3.0 V
VILP Input LOW
Program ming Voltage 0.4 0.4 0.4 V
Capacitance[4]
Parameter Description Test Conditions Max. Unit
CIN Input Capa citance TA = 25°C, f = 1 MHz,
VCC = 5.0V 10 pF
COUT Output Capacitance 10 pF
Notes:
1. The voltage on any input or I/O pin cannot exceed the power pin during power-up.
2. TA is t he “inst ant on” c ase te mperatur e.
3. See the last page of this specification for Group A subgroup testing information.
4. See the “Introduction to CMOS PROMs” section of the Cypress Data Book for general information on testing.
5. For devices using the synchronous enable, the device must be clocked after applying these voltages to perform this measurement.
6. For test purposes, not more than one output at a time should be shorted. Short circuit test duration should not exceed 30 seconds.
CY7C245A
Document #: 38-04007 Rev. *B Page 3 of 11
Operating Modes
The CY7C245A is a CMOS electrically programmable read
only memory organized as 2048 words x 8 bits and is a
pin-for-pin replacement for bipolar TTL fusible link PROMs.
The CY7C245A incorporates a D-type, master-slave register
on chip, reducing the cost and size of pipelined micropro-
grammed systems and applications where accessed PROM
data is stored temporarily in a register. Additional flexibility is
provided with a programmable synchronous (ES) or
asynchronous (E) output enable and asynchronous initialization
(INIT).
Upon power-up the state of the outputs will depend on the
programmed state of the enable function (ES or E). If the
synchronous enable (ES) has been programmed, the register will be
in the set condition causing the outputs (O0–O7) to be in the OFF or
high-impedance state. If the asynchronous enable (E) is being used,
the outputs will come up in the OFF or high-impedance state only if
the enable (E) input is at a HIGH logic level. Data is read by applying
the memory location to the address inputs (A0–A10) and a logic LOW
to the enable input. The stored data is accessed and loaded into the
master flip-flops of the data regist er during the address set-up time.
At the next LOW-to-HIGH transition of the clock (CP), data is trans-
ferred to the slave flip- flops, whic h drive the outpu t buffers, and th e
accessed data will appear at the outputs (O0–O7).
If the asynchro nous ena ble (E ) is being used, the outputs may be
disabled at any time by switching the enable to a logic HIGH, and may
be returned to the active state by switching the enable to a logic LOW.
If the synchronous enable (ES) is being used, the outputs will go
to the OFF or high-impedance state upon the next positive clock edge
after the synchronous enable input is switched to a HIGH level. If the
synchronous enable pin is switched to a logic LOW , the subsequent
positive clock edge will return the output to the active state. Following
a positive clock edg e, the addre ss and synchronous en able inputs
are free to change since no change in the output will occur until the
next LOW-to-HIGH transition of the clock. This unique feature allows
the CY7C245A decoders and sense amplifiers to access the next
location while previously addressed data remains stable on
the outputs.
AC Test Loads and Waveforms[3 , 4]
3.0V
5V
OUTPUT
R1 250Ω
R2
167Ω
50 pF
INCLUDING
JIG AND
SCOPE
GND 90%
10%
90%
10%
5ns 5ns
5V
OUTPUT
5pF
INCLUDING
JIG AND
SCOPE
(b) HighZ Load
OUTPUT 2.0V
Equivalent to: TH ÉVENINEQUIVALENT
100Ω
R1 250Ω
(a) Normal Load
R2
167Ω
ALL INPUT PULSES
≤≤
Switching Characteristics Over Operating Range[3 , 4]
7C245A-15 7C245A-18 7C245A-35 7C245A-25 7C245A-35
Parameter Description Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Unit
tSA Address Set-Up to Clock HIGH 15 18 25 35 45 ns
tHA Address Hold from Clock HIGH 0 0 0 0 0 ns
tCO Clock HIGH to Valid Output 10 12 12 15 25 ns
tPWC Clock Pulse Width 10 12 15 20 20 ns
tSES ES Set-Up to Clock HIGH 10 10 12 15 15 ns
tHES ES Hold from Clock HIGH 5 5 5 5 5 ns
tDI Delay from INIT to V alid Output 15 20 20 20 35 ns
tRI INIT Recovery to Clock HIGH 10 12 15 20 20 ns
tPWI INIT Pulse Width 10 12 15 20 25 ns
tCOS Valid Output from Clock HIGH[7] 15 15 15 20 30 ns
tHZC Inactive Output from Clock
HIGH[7] 15 15 15 20 30 ns
tDOE Valid Output from E LOW[8] 12 15 15 20 30 ns
tHZE Inactive Output from E HIGH[8] 15 15 15 20 30 ns
Notes:
7. Applies only when the synchronous (ES) function i s used.
8. Applies only when the asynchronous (E) funct ion is used.
CY7C245A
Document #: 38-04007 Rev. *B Page 4 of 11
Operating Modes (Continued)
System timing is simplified in that the on-chip edge triggered
register allow s t he PROM clo ck to b e d erived d irectl y from the
system cloc k without i ntroduc ing r ace con dition s. The on- chip
register timing requirements are similar to those of discrete
registers available in the mar ket.
The CY7C245A has an asynchronous initialize input (INIT).
The initialize function is useful during power-up and time-out
sequences and can facilitate implementati on of other sophi sticated
functions such as a built-in “jump start” address. When activated, the
initialize control input causes the contents of a user-programmed
2049th 8-bit word to be loaded int o the on-chip register. Each bit is
programmable and the initialize function can be used to load any
desired combination of 1s and 0s into the register. In the unpro-
grammed state , activati ng INIT will gener ate a r egister CLEAR (all
outputs LOW). If all the bits of the in itialize word are pr ogrammed,
acti vatin g IN IT performs a register PRESET (all outputs HIGH).
Applyin g a LOW to the I N IT input causes an immediate load of the
programmed initialize word into the master and slave flip-flops of the
register, independent of all other inputs, including the clock (CP). The
initialize data w ill app ear at the d evice out puts af ter t he outputs are
enabled by bringing the asynchronous enable (E) LOW .
Erasure Characteri stics
W ave lengths o f light l ess than 4000 Ang stroms b egin to e rase
the 7C245A. For this reason, an opaque label should be
placed ov er the w i ndo w i f th e PR OM i s ex posed to s un lig ht or
fluorescent lighting for extended periods of time.
The recommended dose for erasure is ultraviolet light with a
wavelength of 2537 Angstroms for a minimum dose (UV
intensity multiplied by exposure time) of 25 Wsec/cm2. For an
ultraviole t lamp with a 12 mW/cm2 power rating the e xposure time
would be approximately 35 minutes. The 7C245A needs to be within
1 inch of the lamp during erasure. Permanent damage may result if
the PROM is exposed to high-intensity UV light for an extended
period of time. 7258 Wsec/cm2 is the recommended maximum
dosage.
Programming Informati on
Programming support is available from Cypress as well as
from a number of third-party software vendors. For detailed
programming information, including a listing of software
packages, please see the PROM Programming Information
located at the end of this section. Programming algorithms can
be obtained from any Cypress representative.
Control Byte
00............Asynchro no us output enable (defau lt st at e)
01.....................................Synchronous output enable
Switching Waveforms[4]
tDI
tCO tDOE
tHZE
tHZC
tSA tHA
tHES
tSES
C245A-7
tPWC tPWC
tPWC tPWC
tPWC tPWC
tHA
tCO tCOS
O0−O7
A0−A10
INIT
CP
ES
E
tRI
tPWI
tHES
tSES
tHES
tSES
Bit Map Data
Programmer Address RAM Dat a
Decimal Hex Contents
0 0 Data
.
.
.
.
.
.
.
.
.
2047 7FF Data
2048 800 Init Byte
2049 801 Control Byte
CY7C245A
Document #: 38-04007 Rev. *B Page 5 of 11
Table 1. Mode Selection
Pin Function[9]
Read or Output Disable A10–A4A3A2–A1A0CP E, ESINIT O7–O0
Mode Other A10–A4A3A2–A1A0PGM VFY VPP D7–D0
Read A10–A4A3A2–A1A0VIL/VIH VIL VIH O7–O0
Output Disable A10–A4A3A2–A1A0X VIH VIH High Z
Initialize A10–A4A3A2–A1A0X VIL VIL Init. Byte
Program A10–A4A3A2–A1A0VILP VIHP VPP D7–D0
Program Verify A10–A4A3A2–A1A0VIHP VILP VPP O7–O0
Program Inhibit A10–A4A3A2–A1A0VIHP VIHP VPP High Z
Intellig ent Program A10–A4A3A2–A1A0VILP VIHP VPP D7–D0
Program Synchronous Enable A10–A4VIHP A2–A1VPP VILP VIHP VPP High Z
Program Initialization Byte A10–A4VILP A2–A1VPP VILP VIHP VPP D7–D0
Blank Check Zeros A10–A4A3A2–A1A0VIHP VILP VPP Zeros
Note:
9. X = “don’t care” but not to exceed VCC +5%.
Figure 1. Programming Pinouts
1
2
3
4
5
6
7
8
9
10
11
12
16
17
18
19
20
24
23
22
21
13
14
A8
A7
A6
A5
A4
A3
A2
A1
A0
D0
D1
D2
GND
VCC
D7
D6
D4
D5
D3
15
A9
A10
VPP
VFY
PGM
28
4
5
6
7
8
9
10
321 27
1314151617
26
25
24
23
22
21
20
1112 19
A5
VCC
GND A6
A7
D3
D1
D018
D4
D5
NC
A0
A4
A3
A8
NC
NC
D7
D6
A2
A1
D2
A10
VPP
VFY
PGM
NC
A9
DIP LCC/PLCC (Opaque Only)
Top View Top View
CY7C245A
Document #: 38-04007 Rev. *B Page 6 of 11
Typical DC and AC Characteristics
1.4
1.6
1.0
0.8
4.0 4.5 5.0 5.5 6.0 −55 25 125
1.2
1.1
1.6
4.0 4.5 5.0 5.5 6.0
NORMALIZED CLOCK -TO-OUTPUT TIME
SUPPLY VOLTAGE (V)
NORMALIZED SUPPLY CURRENT
vs. SUP PLY VOLTAGE NORMALIZED SUPPLY CURRENT
vs. AMBIENT TEMPERAT URE
AMBI EN T TEMPERATURE (°C) SUPPLY V O LTAGE (V)
CLOCK TO OUTPUT TIME
vs. VCC
0.6
1.2
1.6
1.4
1.2
1.0
0.8
−55 125
NORMALIZED SET-UP TIME
AMBI EN T TEMPERATURE (°C)
CLOCK TO OUTPUT TIME
vs. TEMPERATURE
150
175
125
75
50
25
0.0 1.0 2.0 3.0
OUTPUT SINK CURRENT (mA)
0
100
OUTPUT VOLTAGE (V)
OUTPUT SINK CURRENT
vs. OUTPUT VOLTAGE
1.0
0.9
0.8
NORMALIZED I CC
NORMALIZED I
CC
VCC =5.0V
TA=25°C
TA=25°C
0.6
0.6
1.02
1.00
0.98
0.96
0.94
0.92
025 5075
CLOCK PERIOD (ns)
30.0
25.0
20.0
15.0
10.0
5.0
0 200 400 600 800
DELTA t (ns)
AA
CAPACITANCE (pF)
TYPICAL ACCESS TIME CHANGE
vs. OUTPUT LOADING
100 0.0 1000
TA=25°C
VCC =4.5V
TA=25°C
f= f
MAX
25
0.88
NORMALIZED SUPPLY CURRENT
vs. CLOCK PERIOD
4.0
1.4
1.2
1.0
0.8
1.6
1.4
1.2
1.0
0.8
−55 125
NORMALIZED SET-UP TIME
0.6 25
AMBIENT TEMPERATURE (°C)
NORMALIZED SET-UP TIME
vs. TEMPERATURE
1.2
4.0 4.5 5.0 5.5 6.0
NORMALIZED CLOCK-TO-OUTPUT TIME
0.4
SUPPLY VOLTAGE (V)
NORMALIZED SET-UP TIME
vs. SUPPLYVOLTAGE
TA=25°C
1.0
0.8
0.6
NORMALIZED I
CC
0.90
VCC =5.5V
TA=25°C
CY7C245A
Document #: 38-04007 Rev. *B Page 7 of 11
MILITARY SPECIFICATIONS
Group A Subgroup Testing
Ordering Information
Speed (ns) ICC
(mA) Ordering
Code Package
Type Package Type Operating
RangetSA tCO
15 10 120 CY7C245A-15JC J64 28-Lead Plastic Leaded Chip Carrier Commercial
18 12 120 CY7C245A-18JC J64 28-Lead Plastic Leaded Chip Carrier Commercial
CY7C245A-18PC P13 24-Lead (300-Mil) Molded DIP
CY7C245A-18WC W14 24-Lead (300-Mil) Windowed CerDIP
18 12 120 CY7C245A-18DMB D14 24-Lead (300-Mil) CerDIP Military
CY7C245A-18QMB Q64 28-Pin Win dowe d Lead les s Chip Carri er
CY7C245A-18WMB W14 24-Lead (300-Mil) Windowed CerDIP
25 15 60 CY7C245A-25PC P13 24-Lead (300-Mil) Molded DIP Commercial
CY7C245A-25WC W14 24-Lead (300-Mil) Windowed CerDIP
90 CY7C245A-25JC J64 28-Lead Plastic Leaded Chip Carrier
CY7C245A-25SC S13 24-Lead Molded SOIC
35 20 60 CY7C245A-35WC W14 24-Lead (300-Mil) Windowed CerDIP Commercial
90 CY7C245A-35JC J64 28-Lead Plastic Leaded Chip Carrier
120 CY7C245A-35DMB D14 24-Lead (300-Mil) CerDIP Military
CY7C245A-35QMB Q64 28-Pin Win dowe d Lead les s Chip Carri er
DC Characteristics
Parameter Subgroups
VOH 1, 2, 3
VOL 1, 2, 3
VIH 1, 2, 3
VIL 1, 2, 3
IIX 1, 2, 3
IOZ 1, 2, 3
ICC 1, 2, 3
Switching Characteristics
Parameter Subgroups
tSA 7, 8, 9, 10, 11
tHA 7, 8, 9, 10, 11
tCO 7, 8, 9, 10, 11
SMD Cross Reference
SMD
Number Suffix Cypress
Number
5962-88735 033X CY7C245A-25LMB
5962-88735 04LX CY7C245A-25DMB
CY7C245A
Document #: 38-04007 Rev. *B Page 8 of 11
Package Diagrams
24-Lead (300-Mil) CerDIP D14
MIL-STD-1835 D- 9 Config.A
51-80031-**
28-Lead Plastic Leaded Chip Carrier J64
51-85001-*A
CY7C245A
Document #: 38-04007 Rev. *B Page 9 of 11
Package Diagrams (continued)
51-85013-*A
24-Lead (300-Mil) Molded DIP P13
28-Pin Windowed Leadless Chip Carrier Q64
MIL–STD–1835 C–4
51-80102-**
CY7C245A
Document #: 38-04007 Rev. *B Page 10 of 11
© Cypress Semiconductor Corporation, 2002. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any ci rcuitry other th an circuitry embod ied in a Cypr ess Semiconductor pr oduct. Nor does it convey or imply any licen se under p atent or other ri ghts. Cypre ss Semiconductor does not autho rize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
All product and company names mentioned in this document may be the trademarks of their respective holders.
Package Diagrams (continued)
24-Lead (300-Mil) Molded SOIC S13
51-85025-*A
51-80086-**
24-Lead (300-Mil) Windowed CerDIP W14
MIL-STD-1835 D-9 Config. A
CY7C245A
Document #: 38-04007 Rev. *B Page 11 of 11
Document History Page
Document Title: CY7C245A 2K x 8 Reprogrammable Registered PROM
Document Number: 38-04007
REV. ECN NO. Issue
Date Orig. of
Change Description of Change
** 113863 3/6/02 DSG Change from Spec number: 38-00074 to 38-04007
*A 11889 4 10/09/02 GBI Update orde ring inform ati on
*B 122248 12/27/02 RBI Add power up requirements to Operating Conditions information
