1.2 A Programmable Device Power Supply
with Integrated 16-Bit Level Setting DACs
AD5560
Rev. C
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FEATURES
Programmable device power supply (DPS)
FV, MI, MV, FNMV functions
5 internal current ranges (on-chip RSENSE)
±5 µA, ±25 µA, ±250 µA, ±2.5 mA, ±25 mA
2 external high current ranges (external RSENSE)
EXTFORCE1: ±1.2 A maximum
EXTFORCE2: ±500 mA maximum
Integrated programmable levels
All 16-bit DACs: force DAC, comparator DACs, clamp DACs,
offset DAC, OSD DAC, DGS DAC
Programmable Kelvin clamp and alarm
Offset and gain correction registers on-chip
Ramp mode on force DAC for power supply slewing
Programmable slew rate feature, 1 V/s to 0.3 V/s
DUTGND Kelvin sense and alarm
25 V FV span with asymmetrical operation within −22 V/+25 V
On-chip comparators
Gangable for higher current
Guard amplifier
System PMU connections
Current clamps
Die temperature sensor and shutdown feature
On-chip diode thermal array
Diagnostic register allows access to internal nodes
Open-drain alarm flags (temperature, current clamp, Kelvin
alarm)
SPI-/MICROWIRE-/DSP-compatible interface
64-lead (10 mm × 10 mm) TQFP with exposed pad (on top)
APPLICATIONS
Automatic test equipment (ATE)
Device power supply
GENERAL DESCRIPTION
The AD5560 is a high performance, highly integrated device
power supply consisting of programmable force voltages and
measure ranges. This part includes the required DAC levels to
set the programmable inputs for the drive amplifier, as well as
clamping and comparator circuitry. Offset and gain correction
is included on-chip for DAC functions. A number of program-
mable measure current ranges are available: five internal fixed
ranges and two external customer-selectable ranges (EXTFORCE1
and EXTFORCE2) that can supply currents up to ±1.2 A and
±500 mA, respectively. The voltage range possible at this high
current level is limited by headroom and the maximum power
dissipation. Current ranges in excess of ±1.2 A or at high
current and high voltage combinations can be achieved by
paralleling or ganging multiple DPS devices. Open-drain
alarm outputs are provided in the event of overcurrent,
overtemperature, or Kelvin alarm on either the SENSE or
DUTGND line.
The DPS functions are controlled via a simple 3-wire serial
interface compatible with SPI, QSPI™, MICROWIRE™, and DSP
interface standards running at clock speeds of up to 50 MHz.
AD5560
Rev. C | Page 2 of 60
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications....................................................................................... 1
General Description......................................................................... 1
Revision History ............................................................................... 3
Functional Block Diagram .............................................................. 4
Specifications..................................................................................... 5
Timing Characteristics .............................................................. 13
Timing Diagrams........................................................................ 13
Absolute Maximum Ratings.......................................................... 15
Thermal Resistance .................................................................... 15
ESD Caution................................................................................ 15
Pin Configuration and Function Descriptions........................... 16
Typical Performance Characteristics ........................................... 18
Terminology .................................................................................... 26
Theory of Operation ...................................................................... 27
Force Amplifier........................................................................... 27
DAC Reference Voltage (VREF)............................................... 27
Open-Sense Detect (OSD) Alarm and Clamp ....................... 27
Device Under Test Ground (DUTGND)................................. 27
GPO.............................................................................................. 28
Comparators................................................................................ 28
Current Clamps .......................................................................... 28
Short-Circuit Protection............................................................ 28
Guard Amplifier ......................................................................... 28
Compensation Capacitors......................................................... 28
Current Range Selection............................................................ 29
High Current Ranges ................................................................. 29
Ideal Sequence for Gang Mode................................................. 30
Compensation for Gang Mode ................................................. 30
System Force/Sense Switches .................................................... 30
Die Temperature Sensor and Thermal Shutdown ................. 31
Measure Output (MEASOUT) ................................................. 31
VMID Voltage ................................................................................ 31
Force Amplifier Stability............................................................ 34
Poles and Zeros in a Typical System ........................................ 35
Minimizing the Number of External Compensation
Components................................................................................ 35
Extra Poles and Zeros in the AD5560...................................... 35
Compensation Strategies........................................................... 36
Optimizing Performance for a Known Capacitor Using
Autocompensation Mode.......................................................... 36
Adjusting the Autocompensation Mode................................. 37
Dealing with Parallel Load Capacitors .................................... 37
DAC Levels.................................................................................. 37
Force and Comparator DACs ................................................... 37
Clamp DACs ............................................................................... 37
OSD DAC.................................................................................... 38
DUTGND DAC.......................................................................... 38
Offset DAC.................................................................................. 38
Offset and Gain Registers.......................................................... 38
Reference Selection .................................................................... 39
Choosing AVDD/AVSS Power Supply Rails............................... 39
Choosing HCAVSSx and HCAVDDx Supply Rails ................... 39
Power Dissipation....................................................................... 39
Package Composition and Maximum Vertical Force............ 40
Slew Rate Control....................................................................... 40
Serial Interface ................................................................................ 42
SPI Interface................................................................................ 42
SPI Write Mode .......................................................................... 42
SDO Output ................................................................................ 42
RESET Function ......................................................................... 42
BUSY Function........................................................................... 42
LOAD Function.......................................................................... 42
Register Update Rates................................................................ 43
Control Registers............................................................................ 44
DPS and DAC Addressing ........................................................ 44
Readback Mode .......................................................................... 55
DAC Readback............................................................................ 55
Power-On Default ...................................................................... 55
Using the HCAVDDx and HCAVSSx Supplies .......................... 57
Power Supply Sequencing ......................................................... 57
Required External Components............................................... 58
Power Supply Decoupling......................................................... 59
Outline Dimensions ....................................................................... 60
Ordering Guide .......................................................................... 60
AD5560
Rev. C | Page 3 of 60
REVISION HISTORY
10/10—Rev. B to Rev. C
Changes to Force Output Voltage Parameter and Load Transient
Response Parameter, Table 1............................................................5
Changes to Figure 52 ......................................................................29
Changes to Table 9 ..........................................................................32
9/09—Rev. A to Rev. B
Changes to Table 1, Measure Current and Measure Voltage
Parameters..........................................................................................6
Changes to Die Temperature Sensor and Thermal
Shutdown Section............................................................................31
Changes to Table 10 and Table 11 .................................................32
Changes to Table 18, Bit 15 ............................................................45
Changes to Table 23, Bits[15:12] ...................................................50
Changes to Table 25 ........................................................................54
12/08—Rev. 0 to Rev. A
Changes to Figure 1 ..........................................................................4
Changes to Table 1 ............................................................................4
Changes to Table 2 ..........................................................................13
Changes to Table 3 ..........................................................................15
Changes to Open-Sense Detect (OSD) Alarm and Clamp .......27
Changes to Figure 53 ......................................................................30
Change to gm Maximum Rating, Table 13..................................34
Changes to Table 19 ........................................................................46
Changes to Bit 7, Bit 8 Functions, Table 21 .................................48
Changes to Power Supply Decoupling Section ...........................59
11/08—Revision 0: Initial Version
AD5560
Rev. C | Page 4 of 60
FUNCTIONAL BLOCK DIAGRAM
R
Z
: 500Ω
TO 1.6M Ω
R
P
: 200Ω
TO 1M Ω
100kΩ
25kΩ
6kΩ
GPORESET
AVSS AVDD
HW_INH/LOAD
DGND CLALM
TMPALM
VREF
DVCC
REFGND
AGND CLEN/
LOAD
8pF
RCLK
KELALM
SW16
GUARD
AMP
×1 REG
C REG
M REG
16
16
16 16
×1
16-BIT
CLAMP
CO NTR OL
DAC
OFFSET
CLH
×2 REG
×1 REG
C REG
M REG
16
16
16 16
×1
16-BIT
DAC
OFFSET
OFFSET
CLH
×2 REG
16
16
16
16 16-BIT
DAC
OFFSET
CPH
×2 REG
16
16
×8
×8
16-BIT
DAC
OSD
DAC
DGS
DAC
AD5560
OFFSET
DIAGNOST IC B
DIAGNOST IC A
DUTGND SENSE
TSENSE
MUX
AND
GAIN
×1/×0.2
CPL
SW3 SW2
SW1
A
B
×2 REG
×1 REG
C REG
M REG
16
16
16
16 16
×1
16-BIT
DAC
FIN
R3
×2 REG
RAM P REG
MUX
g
m
16-BIT
CLH DAC
CLH
OFFSET DAC R4
R1
AGND S/W I NH
THERMAL SHUTDOWN
R2
×1 REG
C REG
M REG
16
16
16
×1 REG
C REG
M REG
KSENSE
VSENSE
ISENSE
CPOH/
CPO
CPOL
MEASOUT
POWER-ON
RESET
DIE TE MP
SENSOR AND
THERMAL
SHUTDOWN
OPEN
SENSE
DETECT
SW7
SW13
SW14
SW15
SW17
SW18
SERIAL SPI INTERFACE
SCLK SYNCSDI BUSYSDO
–
–
–
–
+
+
–
+
–
+
+
+
×10
OR ×20
×1
AGND
V
SENSE
I
SENSE
DAC MID CODE
VOLTAGE TO
CENTER I
RANGE
LO CAL FEEDBACK
EXTFORCE1
EXTFORCE2
VREF
VREF
AC
B
A
C
B
16
16
ALARM BL OCK
KSENSE
DUTGND SENSE
GUARD
DUTGND SENSE
AND ALARM
SW5a
40µA/V
80µA/V
400µA/V
1000µA/V
INHIBIT
SLEW RAT E
CONTROL
HCAVDD1x
C
C0
C
C1
C
C2
C
C3 HCAVDD2x
SENSE
EXTFORCE1
UP TO ±1.2A
UP TO ±500mA EXTFORCE2
SLAVE_IN
MASTER_OUT
C
F0
TO C
F4
C
F0
TO C
F4
DUT
07779-001
EXTMEASIH1
SYS_SENSE
SYS_FORCE
SW8
SW9
EXTMEASIH2
EXTMEASIL
EXT
R
SENSE
1
EXT
R
SENSE
2
DUTGND
GUARD/
SYS_DUTGND
SW6
SW5b
SW11
10kΩ
HCAVSS1x HCAVSS2x
100kΩ
20kΩ
2kΩ
200Ω
20Ω2.5mA
250µA
25µA
5µA
25mA
R
SENSE
FORCE
SW4
Figure 1.
AD5560
Rev. C | Page 5 of 60
SPECIFICATIONS
HCAVDDx ≤ (AVSS + 33 V), HCAVDDx ≤ AVDD, HCAVSSx ≥ AVSS, AVDD ≥ 8 V, AVSS ≤ −5 V, |AVDD − AVSS| ≥ 16 V and ≤ 33 V, DVCC =
2.3 V to 5.5 V, VREF = 5 V, gain (m), offset (c), and DAC offset registers are at default values; AGND = DGND = 0 V; TJ = 25°C to 90°C,
maximum specifications, unless otherwise noted. FSV is full-scale voltage, FSVR is full-scale voltage range, FSC is full-scale current, FSCR is
full-scale current range.
Table 1.
Parameter Min Typ Max Unit Test Conditions/Comments
FORCE VOLTAGE
Force Output Voltage1
EXTFORCE1 AVSS + 2.25 AVDD − 2.25 V Allow ±500 mV for external RSENSE voltage drop.
HCAVSS1x + 1.75 HCAVSS1x − 1.75 V Allow ±500 mV for external RSENSE voltage drop.
HCAVSS1x + 1.25 HCAVDD1x − 1.25 V Allow ±500 mV for external RSENSE voltage drop.
Reduced headroom/footroom, clamps must be
enabled.2
EXTFORCE2 AVSS + 2.25 AVDD − 2.25 V Allow ±500 mV for external RSENSE voltage drop
HCAVSS2x + 1.75 HCAVDD2x − 1.75 V Allow ±500 mV for external RSENSE voltage drop
HCAVSS2x + 1.25 HCAVDD2x − 1.25 V Allow ±500 mV for external RSENSE voltage drop.
Reduced headroom/footroom, clamps must be
enabled.2
FORCE AVSS + 2.75 AVDD − 2.75 V Internal current ranges, includes ±500 mV for
internal RSENSE voltage drop
Headroom/Footroom1 −2.75 +2.75 V Internal current ranges to AVDD/AVSS, includes
±500 mV for internal RSENSE voltage drop.
Headroom/Footroom1 −2.25 +2.25 V External current ranges, EXTFORCE1/
EXTFORCE2 to HCAVDDx and HCAVSSx supplies;
includes ±500 mV for external RSENSE voltage drop.
Force Output Voltage Span −22 +25 V May be a skewed range but within headroom
requirements and maximum power dissipation
for current range.
Forced Voltage Linearity Error −2 +2 mV
Forced Voltage Offset Error −50 +50 mV Uncalibrated, use c register to calibrate, meas-
ured at midscale.
Forced Voltage Offset Error Tempco1 27 V/°C Standard deviation = 23 V/°C.
Forced Voltage Gain Error −25 +25 mV Uncalibrated, use m register to calibrate.
Forced Voltage Gain Error Tempco1 4 ppm/°C Standard deviation = 3 ppm/°C.
Short-Circuit Current Limit3 Clamps off.
EXTFORCE1 −3.5 ±2.7 +3.5 A Positive and negative dc short-circuit current.
EXTFORCE2 −1.25 ±0.9 +1.25 A Positive and negative dc short-circuit current.
FORCE −75 ±50 +75 mA ±25 mA range, positive and negative dc short-
circuit current.
−20 ±10 +20 mA All other ranges, positive and negative dc
short-circuit current.
Active CFx Buffer −64 +64 mA
DC Load Regulation1 −1 +1 mV EXTFORCE1 range, ±1 A load current change.
−0.4 +0.4 mV EXTFORCE2 range, ±0.5 A load current change.
Load Transient Response1 70 mV 1.2 A load step into 100 F DUT capacitance
(10 mΩ ESR), autocompensation mode.
140 mV 1.2 A load step into 30 µF DUT capacitance
(10 mΩ ESR), autocompensation mode.
NSD1 350 nV/√Hz Measured at 1 kHz, at output of FORCE.
MEASURE CURRENT RANGES Sense resistors are trimmed to within 1%,
nominal ±500 mV VRSENSE.
Internal Sense Resistors1 100 kΩ ±5 µA current range.
20 kΩ ±25 µA current range.
2 kΩ ±250 µA current range.
200 Ω ±2.5 mA current range.
20 Ω ±25 mA current range.
AD5560
Rev. C | Page 6 of 60
Parameter Min Typ Max Unit Test Conditions/Comments
Measure Current Ranges Specified current ranges with VREF = 5 V and MI
gain = 20, or with VREF = 2.5 V and MI gain = 5.
±5 µA Set using internal sense resistor.
±25 µA Set using internal sense resistor.
±250 µA Set using internal sense resistor.
±2.5 mA Set using internal sense resistor.
±25 mA Set using internal sense resistor.
±500 mA EXTFORCE2, set by user with external sense
resistor, limited by headroom requirements
and maximum power dissipation.
±120
0
mA EXTFORCE1, set by user with external sense
resistor, limited by headroom requirements
and maximum power dissipation.
MEASURE CURRENT All offset DAC/supply combinations settings, all
gain settings are measure current = (IDUT ×
RSENSE × MI gain), unless otherwise noted.
Differential Input Voltage Range1 −0.64 +0.64 V Maximum voltage across RSENSE, MI gain = 20.
−0.7 +0.7 V Maximum voltage across RSENSE, MI gain = 10.
Output Voltage Span1 25 V Measure current block alone (internal node).
Offset Error −1 +1 % FSC At 0 A, MI gain = 20, MEASOUT gain = 1.
Offset Error Tempco1 −1 ppm of FSC/°C Standard deviation = 13 ppm/°C.
Offset Error −1.5 +1.5 % FSC At 0 A, MI gain = 10, MEASOUT gain = 1.
Offset Error Tempco1 −1 ppm of FSC/°C Standard deviation = 13 ppm/°C.
Offset Error −1.5 +1.5 % FSC At 0 A, MI gain = 20, MEASOUT gain = 0.2.
Offset Error Tempco1 3 ppm of FSC/°C Standard deviation = 13 ppm/°C.
Offset Error −3 +3 % FSC At 0 A, MI gain = 10, MEASOUT gain = 0.2.
Offset Error Tempco1 8 ppm of FSC/°C Standard deviation = 15 ppm/°C.
Gain Error −2 +2 % FSC Internal current ranges, all gain settings.
Gain Error1 −1 +1 % FSC External current ranges, excluding RSENSE.
Gain Error Tempco1 20 ppm/°C Standard deviation = 5 ppm/°C.
MEASOUT Gain = 1 All supply conditions.
Linearity Error −0.01 +0.01 % FSCR MI gain = 20 and 10.
MEASOUT Gain = 0.2 Nominal supply (±16.5 V, 0x8000 offset DAC).
Linearity Error −0.06 +0.06 % FSCR MI gain = 20.
Linearity Error −0.05 +0.05 % FSCR MI gain = 10.
MEASOUT Gain = 0.2 Low supply (−25 V/+8 V, 0xD4EB offset DAC).
Linearity Error −0.125 +0.125 % FSCR MI gain = 20.
Linearity Error −0.175 +0.175 % FSCR MI gain = 10.
MEASOUT Gain = 0.2 High supply (−5 V/+28 V, 0xD1D offset DAC).
Linearity Error −0.0875 +0.0875 % FSCR MI gain = 20.
Linearity Error −0.1 +0.1 % FSCR MI gain = 10.
Common-Mode Error −0.005 +0.005 %FSVR/V % of FS change at measure output per volts
change in DUT voltage.
NSD1 900 nV/√Hz MI gain = 20, MEASOUT gain = 1, measured at
MEASOUT @ 1 kHz, inputs grounded.
550 nV/√Hz MI gain = 10, MEASOUT gain = 1, measured at
MEASOUT @ 1 kHz, inputs grounded.
170 nV/√Hz MI gain = 20, MEASOUT gain = 0.2, measured at
MEASOUT @ 1 kHz, inputs grounded.
110 nV/√Hz MI gain = 10, MEASOUT gain = 0.2, measured at
MEASOUT @ 1 kHz, inputs grounded.
MEASURE VOLTAGE MEASOUT Gain 1 and MEASOUT Gain 0.2.
Measure Voltage Range1 AVSS + 2.75 AVDD − 2.75 V All voltage ranges.
Gain Error −0.1 +0.1 % FS
Gain Error Tempco1 3 ppm/°C Standard deviation = 2 ppm/°C.
MEASOUT Gain = 1
Linearity Error −2 +2 mV
Offset Error −12 +12 mV
Offset Error Tempco1 2 µV/°C Standard deviation = 12 µV/°C.
NSD1 100 nV/√Hz @ 1 kHz, at MEASOUT, inputs grounded.
AD5560
Rev. C | Page 7 of 60
Parameter Min Typ Max Unit Test Conditions/Comments
MEASOUT Gain = 0.2
Linearity Error −5.5 +5.5 mV Referred to MV input, nominal supply (±16.5 V,
0x8000 offset DAC).
−9 +24 mV Referred to MV input, low supply (−25 V/+8 V,
0xD4EB offset DAC).
−4 +13 mV Referred to MV input, high supply (−5 V/+28 V,
0xD1D offset DAC).
Offset Error −30 +20 mV Referred to MV output.
Offset Error Tempco1 10 µV/°C Standard deviation = 12 µV/°C, referred to MV
output.
NSD1 50 nV/√Hz @ 1 kHz, at MEASOUT, inputs grounded.
COMBINED LEAKAGE Includes SYS_SENSE, SYS_FORCE, EXTFORCE1,
EXTFORCE2, EXTMEASIH1, EXTMEASIH2,
EXTMEASIL, FORCE, and SENSE; measured with
PD = 1, SW-INH = 0 (power up and tristate).
Leakage Current −37.5 +37.5 nA
−30 +30 nA TJ = 25°C to 70°C.
Leakage Current Tempco1 ±0.1 ±0.4 nA/°C
SENSE INPUT
Leakage Current −2.5 +2.5 nA Measured with PD = 1, SW-INH = 0 (power-up
and tristate).
Leakage Current Tempco1 ±0.0
1
nA/°C
Pin Capacitance1 10 pF
EXTMEASIH1, EXTMEASIH2, EXTMEASIL
Leakage Current −2.5 +2.5 nA Measured with PD = 1, SW-INH = 0 (power-up
and tristate).
Leakage Current Tempco1 ±0.0
1
nA/°C
Pin Capacitance1 5 pF
FORCE OUTPUT, FORCE
Maximum Current Drive1 −30 +30 mA
Leakage Current −10 +10 nA Measured with PD = 1, SW-INH = 0 (power-up
and tristate).
Leakage Current Tempco1 ±0.0
3
nA/°C
Pin Capacitance1 120 pF
EXTFORCE1 OUTPUTS
Maximum Current Drive1 −1200 +1200 mA Set with external sense resistor, limited by
headroom and power dissipation.
Leakage Current −7.5 +7.5 nA Measured with PD = 1, SW-INH = 0 (power-up
and tristate).
Leakage Current Tempco1 ±0.0
3
±0.06 nA/°C
Pin Capacitance1 275 pF
EXTFORCE2 OUTPUTS
Maximum Current Drive1 −500 +500 mA Set with external sense resistor, limited by
headroom and power dissipation.
Leakage Current −5 +5 nA Measured with PD = 1, SW-INH = 0 (power-up
and tristate).
Leakage Current Tempco1 ±0.0
2
±0.05 nA/°C
Pin Capacitance1 100 pF
SYS_SENSE
Voltage Range AVSS AVDD V
Leakage Current −2.5 +2.5 nA SYS_SENSE high-Z, force amplifier inhibited.
Leakage Current Tempco1 ±0.0
05
±0.025 nA/°C
Path On Resistance 280 Ω AVDD = 16.5 V, AVSS = −16.5 V.
Pin Capacitance1 5 pF
AD5560
Rev. C | Page 8 of 60
Parameter Min Typ Max Unit Test Conditions/Comments
SYS_FORCE
Voltage Range AVSS AVDD V
Current Carrying Capability1 −25 +25 mA
Leakage Current −2.5 +2.5 nA SYS_FORCE high-Z, force amplifier inhibited.
Leakage Current Tempco1 ±0.00
5
±0.025 nA/°C
Path On Resistance 35 Ω AVDD = 16.5 V, AVSS = −16.5 V.
Pin Capacitance1 5 pF
SYS_DUTGND
Voltage Range AVSS AVDD V
Path On Resistance 300 400 Ω AVDD = 16.5 V, AVSS = −16.5 V.
CURRENT CLAMP
Clamp Accuracy Programmed
clamp value
Programmed clamp
value + 10
% of FS MI gain = 20, with clamp separation of 2 V, and
1 V separation from AGND/0 A.
Programmed
clamp value
Programmed clamp
value + 20
% of FS MI gain = 10, with clamp separation of 2 V, and
1 V separation from AGND/0 A.
VCLL to VCLH1 2 V 10% of FSCR (MI gain = 20), 20% of FSCR (MI
gain = 10), restriction to prevent both clamps
activating together.
VCLL to 0 A1 1 V 5% of FSCR (MI gain = 20), 10% of FSCR (MI gain
= 10), restriction to avoid impinging on FV
before programmed level.
VCLH to 0 A1 1 V 5% of FSCR (MI gain 20), 10% of FSCR (MI gain =
10), restriction to avoid impinging on FV before
programmed level.
Clamp Activation Response Time1 20 100 s Measured from BUSY going low to visible
clamping.
Clamp Recovery1 2 5 s
Measured from BUSY going low to visible
recovery.
Alarm Delay 1 50 s
Time for CLALM to flag.
FORCE AMPLIFER
Slew Rate1 1 V/µs Fastest slew rate, controlled via serial interface.
0.312 V/µs Slowest slew rate, controlled via serial interface.
Maximum Stable Load Capacitance1 160 µF
Voltage Overshoot/Undershoot1 5 % Of programmed value (≥1 V).
SETTLING TIME (FORCE AMPLIFER) Compensation Register 1 = 0x4880 (229 nF to
380 nF, ESR 74 to 140 mΩ)
To within 10 mV of programmed value.
FV (1200 mA EXTFORCE1 Range)1 16 25 µs 3.7 V step, RDUT = 2.4 Ω, CDUT = 0.22 µF, full dc load.
FV (900 mA EXTFORCE1 Range)1 18 30 µs 8 V step, RDUT = 8.8 Ω, CDUT = 0.22 µF, full dc
load.
FV (500 mA EXTFORCE2 Range)1 34 53 µs 15 V step, RDUT = 30 Ω, CDUT = 0.22 µF, full dc
load.
FV (300 mA EXTFORCE2 Range)1 25 50 µs 10 V step, RDUT = 33.3 Ω, CDUT = 0.22 µF, full dc load.
FV (25 mA Range)1, 3 125 180 µs 20 V step, RDUT = 800 Ω, CDUT = 0.22 µF, full dc load.
FV (2.5 mA Range)1, 3 300 500 µs 10 V step, RDUT = 4 kΩ, CDUT = 0.22 µF, full dc load.
FV (250 µA Range)1, 3 300 500 µs 10 V step, RDUT = 40 kΩ, CDUT = 0.22 µF, full dc load.
FV (25 µA Range)1, 3 400 600 µs 10 V step, RDUT = 400 kΩ, CDUT = 0.22 µF, full dc load.
FV (5 µA Range)1, 3 20 40 µs 1 V step, RDUT = 200 kΩ, CDUT = 0.22 µF, full dc load.
Compensation Register 1 = 0x8880 (1.7 F to
2.9 F, ESR 74 to 140 mΩ)
FV (180 mA EXTFORCE1 Range)1 16 25 µs 3 V step, CDUT = 2.2 µF, full dc load.
FV (100 mA EXTFORCE2 Range)1 60 80 µs 8 V step, CDUT = 2.2 µF, full dc load.
Compensation Register 1 = 0xB880 (7.9F to
13 F, ESR 74 to 140 mΩ)
FV (180 mA EXTFORCE1 Range)1 55 70 µs 3 V step, CDUT = 10 µF, full dc load.
FV (100 mA EXTFORCE2 Range)1 210 260 µs 8 V step, CDUT = 10 µF, full dc load.
Compensation Register 1 = 0xC880 (13 F to
22 F, ESR 74 to 140 mΩ)
FV (180 mA EXTFORCE1 Range)1 65 80 µs 3 V step, CDUT = 20 µF, full dc load.
FV (100 mA EXTFORCE2 Range)1 310 370 µs 8 V step, CDUT = 20 µF, full dc load.
AD5560
Rev. C | Page 9 of 60
Parameter Min Typ Max Unit Test Conditions/Comments
SETTLING TIME (FV, MEASURE CURRENT) Compensation Register 1 = 0x4880 (229 nF to
380 nF, ESR 74 to 140 mΩ)
To within 10 mV of programmed value.
MI (1200 mA EXTFORCE1 Range)1 30 40 µs 3.7 V step, RDUT = 2.4 Ω, CDUT = 0.22 µF, full dc load.
MI (900 mA EXTFORCE1 Range)1 32 42 µs 8 V step, RDUT = 8.8 Ω, CDUT = 0.22 µF, full dc load.
MI (500 mA EXTFORCE2 Range)1 69 95 µs 15 V step, RDUT = 30 Ω, CDUT = 0.22 µF, full dc
load.
MI (300 mA EXTFORCE2 Range)1 70 100 µs 10 V step, RDUT = 33.3 Ω, CDUT = 0.22 µF, full dc load.
MI (25 mA Range)1, 3 650 µs 20 V step, RDUT = 800 Ω, CDUT = 0.22 µF, full dc load.
MI (2.5 mA Range)1, 3 6400 µs 10 V step, RDUT = 4 kΩ, CDUT = 0.22 µF, full dc
load.
MI Buffer Alone1 10 15 µs 0.5 V step using MEASOUT high-Z to within
10 mV of final value.
SETTLING TIME (FV, MEASURE VOLTAGE) Compensation Register 1 = 0x4880 (229 nF to
380 nF, ESR 74 to 140 mΩ)
To within 10 mV of programmed value.
MV (1200 mA Range)1 16 µs 3.7 V step, RDUT = 2.4 Ω, CDUT = 0.22 µF, full dc load.
MV (900 mA Range)1 20 µs 8 V step, RDUT = 8.8 Ω, CDUT = 0.22 µF, full dc load.
MV (500 mA Range)1 34 µs 15 V step, RDUT = 30 Ω, CDUT = 0.22 µF, full dc
load.
MV (300 mA Range)1 25 µs 10 V step, RDUT = 33.3 Ω, CDUT = 0.22 µF, full dc load.
MV (25 mA Range)1, 3 125 180 µs 20 V step, RDUT = 800 Ω, CDUT = 0.22 µF, full dc load.
MV (2.5 mA Range)1, 3 300 500 µs 10 V step, RDUT = 4 kΩ, CDUT = 0.22 µF, full dc
load.
MV (250 µA Range)1, 3 300 500 µs 10 V step, RDUT = 40 kΩ, CDUT = 0.22 µF, full dc load.
MV Buffer Alone1 2 5 µs 10 V step using MEASOUT high-Z to within
10 mV of final value.
SETTLING TIME (FV) SAFE MODE To within 100 mV of programmed value.
FV (1200 mA EXTFORCE1 Range1 25 µs 3.7 V step, RDUT = 3.1 Ω, CDUT = 0.22 µF, full dc load.
FV (180 mA EXTFORCE1 Range)1 303 µs 3 V step, RDUT = 16 Ω, CDUT = 0. 22 µF to 20 F, full
dc load.
FV (100 mA EXTFORCE2 Range)1 660 µs 8 V step, RDUT = 33.3 Ω, CDUT = 0. 22 µF to 20 F,
full dc load.
FV (25 mA Range)1, 3 760 1000 µs 20 V step, RDUT = 400 Ω, CDUT = 0.22 µF, full dc load.
SWITCHING TRANSIENTS
Range Change Transient1 0.5 % of FV CDUT = 10 F, changing from higher to adjacent
lower ranges (except EXTFORCE1 to EXTFORCE2).
20 mV CDUT = 10 F, changing from lower (5 µA) to
higher range (EXTFORCE1).
0.5 % of FV CDUT = 100 F, changing between all ranges.
DAC SPECIFICATIONS
Force/Comparator/Offset DACs
Resolution 16 Bits
Voltage Output Span −22 +25 V VREF = 5 V, minimum and maximum values set
by offset DAC.
Differential Nonlinearity1 −1 +1 LSB Guaranteed monotonic.
Offset DAC
Gain Error −20 +20 mV
Clamp DAC CLL < CLH.
Resolution 16 Bits
Voltage Output Span −22 +25 V VREF = 5 V, minimum and maximum values set
by offset DAC.
Differential Nonlinearity1 −1 +1 LSB Guaranteed monotonic.
OSD DAC
Resolution 16 Bits
Voltage Output Span 0.62 5 V VREF = 5 V.
Differential Nonlinearity1 1 1 LSB Guaranteed monotonic.
DGS DAC
Resolution 16 Bits
Voltage Output Span 0 5 V VREF = 5 V.
Differential Nonlinearity1 −1 +1 LSB Guaranteed monotonic.
AD5560
Rev. C | Page 10 of 60
Parameter Min Typ Max Unit Test Conditions/Comments
Comparator DAC Dynamic
Output Voltage Settling Time1 3.5 6 µs 1 V change to 1 LSB.
Slew Rate1 1 V/µs
Digital-to-Analog Glitch Energy1 10 nV-s
Glitch Impulse Peak Amplitude1 40 mV
REFERENCE INPUT
VREF DC Input Impedance 1 MΩ Typically 100 MΩ.
VREF Input Current −10 +10 µA Per input; typically ±30 nA.
VREF Range1 2 5 V
COMPARATOR Measured directly at comparator; does not
include measure block errors.
Error −7 +7 mV Uncalibrated.
VOLTAGE COMPARATOR With respect to the measured voltage.
Propagation Delay1 0.25 µs
Error1 −12 +12 mV Uncalibrated.
CURRENT COMPARATOR
Propagation Delay1 0.25 1 µs
Error1 −1.5 +1.5 % Of programmed current range, uncalibrated.
MEASURE OUTPUT, MEASOUT
Measure Output Voltage Span1 −12.81 +12.81 V MEASOUT gain = 1, VREF = 5 V, offset DAC =
0x8000.
Measure Output Voltage Span1 −6.405 +6.405 V MEASOUT gain = 1, VREF = 2.5 V.
Measure Output Voltage Span1 0 5.125 V MEASOUT gain = 0.2, VREF = 5 V, offset DAC =
0x8000.
Measure Output Voltage Span1 0 2.56 V MEASOUT gain = 0.2, VREF = 2.5 V.
Measure Pin Output Impedance 115 Ω
Output Leakage Current −100 +100 nA When HW_INH is low.
Output Capacitance1 5 pF
Short-Circuit Current1 −10 +10 mA
OPEN-SENSE DETECT/CLAMP/ALARM
Measurement Accuracy −200 +200 mV
Clamp Accuracy 600 900 mV
Alarm Delay1 50 s
DUTGND
Voltage Range1 −1 +1 V
Pull-Up Current +50 +70 A Pull-up for purpose of detecting open circuit on
DUTGND, can be disabled.
Leakage Current −1 +1 A When pull-up disabled, DGS DAC = 0x3333 (1 V
with VREF = 5 V). If DUTGND voltage is far away
from one of comparator thresholds, more
leakage may be present.
Trip Point Accuracy −30 +10 mV
Alarm Delay1 50 s
GUARD AMPLIFIER
Voltage Range1 AVSS + 2.25 AVDD − 2.25 V
Voltage Span1 25 V
Output Offset −10 +10 mV
Short-Circuit Current1 −20 +20 mA
Load Capacitance1 100 nF
Output Impedance 100 Ω
Alarm Delay1 200 s If it moves 100 mV away from input level.
DIE TEMPERATURE SENSOR
Accuracy1 −10 +10 % Relative to a temperature change.
Output Voltage at 25°C 1.54 V
Output Scale Factor1 4.7 mV/°C
Output Voltage Range1 1 2 V
AD5560
Rev. C | Page 11 of 60
Parameter Min Typ Max Unit Test Conditions/Comments
SPI INTERFACE LOGIC
Logic Inputs
Input High Voltage, VIH 1.7/2.0 V (2.3 V to 2.7 V)/(2.7 V to 5.5 V) JEDEC-compliant
input levels.
Input Low Voltage, VIL 0.7/0.8 V (2.3 V to 2.7 V)/(2.7 V to 5.5 V) JEDEC-compliant
input levels.
Input Current, IINH, IINL −1 +1 µA
Input Capacitance, CIN1 10 pF
CMOS Logic Outputs SDO, CPOL, CPOH, GPO, CPO.
Output High Voltage, VOH DVCC − 0.4 V
Output Low Voltage, VOL 0.4 V IOL = 500 µA.
Tristate Leakage Current −1 +1 A SDO, CPOL, CPOH, CPO.
Output Capacitance1 10 10 10 pF SDO, CPOL, CPOH, CPO.
Open-Drain Logic Outputs BUSY, TMPALM, CLALM, KELALM.
Output Low Voltage, VOL 0.4 V IOL = 500 µA, CL = 50 pF, RPULLUP = 1 kΩ.
Output Capacitance1 10 pF
POWER SUPPLIES
HCAVDD1x 4 28 V |HCAVDDx – HCAVSSx| < 33 V, HCAVSSx ≥ AVSS,
HCAVDDx ≤ AVDD.
HCAVSS1x −25 −5 V
HCAVDD2x 4 28 V |HCAVDDx – HCAVSSx| < 33 V, HCAVSSx ≥ AVSS,
HCAVDDx ≤ AVDD.
HCAVSS2x −25 −5 V
AVDD 8 28 V |AVDD – AVSS| < 33 V.
AVSS −25 −5 V
DVCC 2.3 5.5 V
AIDD 4 30 mA All ranges.
AISS4 −30 mA All ranges.
DICC 3 mA
AIDD4 27 mA
Channel inhibited/tristate, HW_INH or
SW-INH low.
AISS4 −27 mA
Channel inhibited/tristate, HW_INH or
SW-INH low.
HCAVDDx and HCAVSSx supply currents shown
are excluding load currents; however, for
power budget calculations, the supply currents
here are consumed by the load.
HCAIDD1 20 mA When enabled, excluding load conditions.
HCAIDD1 0.5 mA When disabled.
HCAISS1 −20 mA When enabled, excluding load condition.
HCAISS1 −0.5 mA When disabled.
HCAIDD2 15 mA When enabled, excluding load conditions.
HCAIDD2 0.25 mA When disabled.
HCAISS2 −15 mA When enabled, excluding load conditions.
HCAISS2 −0.25 mA When disabled.
POWER-DOWN CURRENTS Supply currents on power-up or during a
power-down condition.
HCAIDD 250 A
HCAISS −250 A
HCAIDD 250 A
HCAISS −250 A
AIDD 5 mA
AISS −5 mA
DICC 3 mA
Maximum Power Dissipation
EXTFORCE1 10 W
EXTFORCE2 5 W
Power-Up Overshoot1 5 % Of programmed value.
AD5560
Rev. C | Page 12 of 60
Parameter Min Typ Max Unit Test Conditions/Comments
Power Supply Sensitivity1 DC to 1 kHz.
∆Forced Voltage/∆AVDD −65 dB −30 dB at 100 kHz.
∆Forced Voltage/∆AVSS −65 dB −25 dB at 100 kHz.
∆Forced Voltage/∆HCAVDDx −90 dB −60 dB at 100 kHz.
∆Forced Voltage/∆HCAVSSx −90 dB −62 dB at 100 kHz.
∆Measured Current/∆AVDD −50 dB −25 dB at 100 kHz.
∆Measured Current/∆AVSS −43 dB −20 dB at 100 kHz.
∆Measured Current/∆HCAVDDx −90 dB −60 dB at 100 kHz.
∆Measured Current/∆HCAVSSx −90 dB −60 dB at 100 kHz.
∆Measured Voltage/∆AVDD −65 dB −30 dB at 100 kHz.
∆Measured Voltage/∆AVSS −65 dB −25 dB at 100 kHz.
∆Measured Voltage/∆HCAVDDx −90 dB −60 dB at 100 kHz.
∆Measured Voltage/∆HCAVSSx −90 dB −65 dB at 100 kHz.
∆Forced Voltage/∆DVCC −80 dB −46 dB at 100 kHz.
∆Measured Current/∆DVCC −80 dB −36 dB at 100 kHz.
∆Measured Voltage/∆DVCC −80 dB −46 dB at 100 kHz.
1 Guaranteed by design and characterization, not subject to production test.
2 Programmable clamps must be enabled if taking advantage of reduced headroom/footroom.
3 Clamps disabled.
4 Not including internal pull-up current between AVDD/AVSS and HCAVDDx/HCAVSSx pins.
AD5560
Rev. C | Page 13 of 60
TIMING CHARACTERISTICS
HCAVDDx ≤ AVSS + 33 V, HCAVSSx ≥ AVSS, AVDD ≥ 8 V, AVSS ≤ −5 V, |AVDD − AVSS| ≥ 16 V and ≤ 33 V, VREF = 5 V (TJ = 25°C to 90°C,
maximum specifications, unless otherwise noted).
Table 2. SPI Interface
Parameter1, 2, 3
DVCC = 2.3 V
to 2.7 V
DVCC = 2.7 V
to 3.3 V
DVCC = 4.5 V
to 5.5 V Unit Description
tUPDATE 600 600 600 ns max Channel update cycle time
t1 25 20 20 ns min SCLK cycle time; 60/40 duty cycle
t2 10 8 8 ns min SCLK high time
t3 10 8 8 ns min SCLK low time
t4 10 10 10 ns min SYNC falling edge to SCLK falling edge setup time
t5 15 15 15 ns min
Minimum SYNC high time
t6 5 5 5 ns min
24th SCLK falling edge to SYNC rising edge
t7 5 5 5 ns min Data setup time
t8 4.5 4.5 4.5 ns min Data hold time
t94 40 35 30 ns max
SYNC rising edge to BUSY falling edge
t10 1.5 1.5 1.5 s max BUSY pulse width low for DAC x1 write
280 280 280 ns max
BUSY pulse width low for other register write
t11 25 20 10 ns min
RESET pulse width low
t12 400 400 400 µs max
RESET time indicated by BUSY low
t13 250 250 250 ns min
Minimum SYNC high time in readback mode
t145, 6 45 35 25 ns max SCLK rising edge to SDO valid
t15 30 30 30 ns max
SYNC rising edge to SDO high-Z
LOAD TIMING
t16 20 20 20 ns min
LOAD pulse width low
t17 150 150 150 ns min
BUSY rising edge to force output response time
t18 0 0 0 ns min
BUSY rising edge to LOAD falling edge
t19 150 150 150 ns min
LOAD rising edge to FORCE output response time
150 150 150 ns min
LOAD rising edge to current range response
1 Guaranteed by design and characterization, not production tested.
2 All input signals are specified with tR = tF = 2 ns (10% to 90% of DVCC) and timed from a voltage level of 1.2 V.
3 See Figure 4 and Figure 5.
4 This is measured with the load circuit shown in Figure 2.
5 This is measured with the load circuit shown in Figure 3.
6 Longer SCLK cycle time is required for correct operation of readback mode; consult timing diagrams and timing specifications.
TIMING DIAGRAMS
TO OUTPUT
PIN
DV
CC
R
LOAD
2.2kΩ
C
LOAD
50pF
V
OL
07779-002
Figure 2. Load Circuit for Open Drain
07779-003
V
OH
(MIN) – V
OL
(MAX)
2
200µA I
OL
200µA I
OL
TO OUTPUT
PINC
LOAD
50pF
Figure 3. Load Circuit for CMOS
AD5560
Rev. C | Page 14 of 60
SYNC
SCLK
SDI
BUSY
RESET
12
t
3
t
2
24
t
4
t
6
t
1
t
7
t
8
t
9
DB23 DB0
t
10
t
11
t
12
BUSY
t
5
1
LOAD ACTIVE DURING BUSY.
2
LOAD ACTIVE AFTER BUSY.
3
LO AD FUNCTION IS AVAIL ABLE VIA CLE N OR HW_INH AS DETERMINED BY DP S RE GIS TER 2.
LOAD
1,3
FORCE
EXTFORCE1
EXTFORCE2
1
FORCE
EXTFORCE1
EXTFORCE2
2,3
LOAD
2,3
t16
t17
t18 t16
t19
07779-004
Figure 4. SPI Write Timing
SCLK
S
YN
C
SDI
SDO
24 48
D0BDB23 DB0
DB0
INPUT WORD SPECIF I ES
REGIST E R TO BE RE AD NOP COND I TI ON
SELECTED REG I ST ER DATA
CLO CKED OUT
t13
t14
t15
DB23
DB23
07779-005
Figure 5. SPI Read Timing
AD5560
Rev. C | Page 15 of 60
ABSOLUTE MAXIMUM RATINGS
THERMAL RESISTANCE
Table 3.
Parameter Rating
AVDD to AVSS 34 V
AVDD to AGND −0.3 V to +34 V
AVSS to AGND −34 V to +0.3 V
HCAVDDx to HCAVSSx 34 V
HCAVDDx to AGND −0.3 V to +34 V
HCAVSSx to AGND −34 V to +0.3 V
HCAVDDx to AVSS −0.3 V to AVSS + 34 V
HCAVDDx to AVDD −0.3 V to AVDD + 0.3 V
HCAVSSx to AVSS +0.3 V to AVSS − 0.3 V
DVCC to DGND −0.3 V to +7 V
AGND to DGND −0.3 V to +0.3 V
REFGND to AGND −0.3 V to +0.3 V
Digital Inputs to DGND −0.3 V to DVCC + 0.3 V
Analog Inputs to AGND AVSS − 0.3 V to AVDD + 0.3 V
EXTFORCE1 and EXTFORCE2 to
AGND1
AVDD − 28 V
Storage Temperature −65°C to +125°C
Operating Junction Temperature 25°C to 90°C
Reflow Profile J-STD 20 (JEDEC)
Junction Temperature 150°C max
Power Dissipation 10 W max (EXTFORCE1 stage)
5 W max (EXTFORCE2 stage)
ESD
HBM 1500 V
FICDM 500 V
Table 4.1
Cooling
Airflow
(LFPM) θJA
θJC
(Uniform
Heating)
θJC
(Local
Heating) Unit
0 42 °C/W
200 37.2 °C/W
No Heat
Sink2
400 35.7
1 4.91
°C/W
0 12.2 °C/W
200 11.1 °C/W
Heat
Sink3
400 9.5
1 4.91
°C/W
Cold
Plate4
N/A N/A 1 4.91 °C/W
1 TA = 30°C, TCOLD PLATE = 30°C, total power = 8.5 W (1 W distributed, 7.5 W in
power stages − local heating), 0.5 mm TIM, 2.56 W/m/k.
2 No heat sink attached; thermal performance of the package depends on
environmental conditions. All numbers are simulated and assume a JEDEC
4-layer test board.
3 Heat sink attached with a rated performance of θCA ~6.2°C/W giving ~TJ =
111°C at 400 LFM. Thermal performance of the package depends on the heat
sink and environmental conditions. All numbers are simulated and assume a
JEDEC 4-layer test board.
4 Attached infinite cold plate should be ≤ 30°C to maintain TJ < 90°C. Thermal
performance of the package depends on the heat sink and environmental
conditions. All numbers are simulated and assume a JEDEC 4-layer test
board.
ESD CAUTION
1 When an EXTFORCE1 or EXTFORCE2 stage is enabled and the supply
differential |AVDD − AVSS| > 28 V, care should be taken to ensure that these
pins are not directly shorted to AVSS voltage at any time because this can
cause damage to the device.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
AD5560
Rev. C | Page 16 of 60
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
NC
C
F4
C
F3
C
F2
C
F1
C
F0
DUTGND
SENSE
EXTMEASIL
GUARD/SYS_DUTGND
AGND
AV
SS
AV
DD
EXTMEASIH1
EXTMEASIH2
AV
DD
EXTFORCE1A
HCAV
SS
1A
HCAV
SS
2A
EXTFORCE2A
HCAV
DD
2A
HCAV
DD
1B
EXTFORCE1B
HCAV
SS
1B
HCAV
SS
2B
EXTFORCE2B
HCAV
DD
2B
HCAV
DD
1C
EXTFORCE1C
HC_V
SS
1C
GPO
HCAV
DD
1A
PIN 1
NOTES
1. NC = NO CO NNE CT.
2
. EXPOS E D P AD ON TOP O F PACKAG E . EXP OSED P AD IS I NTERNALLY CONNECTED TO
MOST NEGATIVE POINT , A
V
SS
.
AD5560
TOP VIEW
(No t t o S cale)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49505152535455565758596061626364
07779-006
BUSY
CPOL
SDO
DV
CC
DGND
SCLK
SDI
CPOH/CPO
CLEN/LOAD
RCLK
TMPALM
KELALM
CLALM
RESET
HW_INH/LOAD
SYNC
MEASOUT
AV
DD
C
C3
C
C0
C
C1
C
C2
SLAVE_IN
AV
SS
SYS_FORCE
SYS_SENSE
AGND
VREF
REFGND
AV
SS
FORCE
MASTER_OUT
EXPOSED PAD ON TOP
Figure 6. Pin Configuration
Table 5. Pin Function Descriptions
Pin No. Mnemonic Description
1 CLALM Clamp Alarm Output. Open-drain output, active low; this pin can be programmed to be either latched or
unlatched.
2 KELALM Kelvin Alarm Pin for SENSE and DUTGND, Open-Drain Active Low. This pin can be programmed to be either
latched or unlatched.
3 TMPALM Temperature Alarm Flag. Open-drain output, active low; this pin can be programmed to be either latched or
unlatched.
4 CPOH/CPO Comparator High Output (CPOH) or Window Comparator Output (CPO).
5 CPOL Comparator Low Output.
6 BUSY Open-Drain Active Low Output. This pin indicates the status of the calibration engine for the DAC channels.
7 SDO Serial Data Output. This pin is used for reading back DAC and DPS register information for diagnostic
purposes.
8 DVCC Digital Supply Voltage.
9 DGND Digital Ground Reference Point.
10 SCLK Clock Input, Active Falling Edge.
11 SDI Serial Data Input.
12 SYNC Frame Sync, Active Low.
13 RCLK Ramp Clock Logic Input. If the ramp function is used, a clock signal of 833 kHz maximum should be applied to
this input to drive the ramp circuitry. Tie RCLK low if it is unused.
14 RESET Logic Input. This pin is used to reset all internal nodes on the device to their power-on reset value.
15 CLEN/LOAD Clamp Enable. This input allows the user to enable or disable the clamp circuitry. This pin can be configured
as a LOAD function to allow synchronization of multiple devices. Either CLEN or HW_INH can be chosen as
LOAD input (see the system control register, Address 0x1).
16 HW_INH/LOAD Hardware Inhibit Input to Disable Force Amplifier. This pin can be configured as a LOAD function to allow
synchronization of multiple devices. Either CLEN or HW_INH can be chosen as a LOAD input (see the system
control register, Address 0x1).
17 REFGND Accurate Ground Reference for Applied Voltage Reference.
AD5560
Rev. C | Page 17 of 60
Pin No. Mnemonic Description
18 VREF Reference Input for DAC Channels, Input Range 2 V to 5 V.
19, 44 AGND Analog Ground.
20, 30, 45 AVSS Negative Analog Supply Voltage. These pins supply DACs and other high voltage circuitry, such as
measure blocks.
21, 33, 46 AVDD Positive Analog Supply Voltage. These pins supply DACs and other high voltage circuitry, such as
measure blocks.
22 MEASOUT Multiplexed DUT voltage sense, DUT current sense, Kelvin sense, or temperature output; refer to AGND.
23 CC3 Compensation Capacitor Input 3.
24 CC0 Compensation Capacitor Input 0.
25 CC1 Compensation Capacitor Input 1.
26 CC2 Compensation Capacitor Input 2.
27 SLAVE_IN Slave Input When Ganging Multiple DPS Devices.
28 MASTER_OUT Master Output When Ganging Multiple DPS Devices.
29 SYS_SENSE External Sense Signal Output.
31 SYS_FORCE External Force Signal Input.
32 FORCE Output Force Pin for Internal Current Ranges.
34 NC No Connect.
35 CF4 Feedforward Capacitor 4.
36 CF3 Feedforward Capacitor 3.
37 CF2 Feedforward Capacitor 2.
38 CF1 Feedforward Capacitor 1.
39 CF0 Feedforward Capacitor 0.
40 DUTGND Device Under Test Ground.
41 SENSE Input Sense Line.
42 EXTMEASIL Low Side Measure Current Line for External High Current Ranges.
43 GUARD/SYS_DUTGND
Guard Amplifier Output Pin or System Device Under Test Ground Pin. See the DPS Register 2 in Table 19
for addressing details.
47 EXTMEASIH1 Input High Measure Line for External High Current Range 1.
48 EXTMEASIH2 Input High Measure Line for External High Current Range 2.
49, 55, 61 HCAVDD1A,
HCAVDD1B,
HCAVDD1C
High Current Positive Analog Supply Voltage, for EXTFORCE1 Range.
50, 56, 62 EXTFORCE1A,
EXTFORCE1B,
EXTFORCE1C
Output Force. This pin is used for high Current Range 1, up to a maximum of ±1.2 A.
51, 57, 63 HCAVSS1A,
HCAVSS1B,
HCAVSS1C
High Current Negative Analog Supply Voltage, for EXTFORCE1 Range.
52, 58 HCAVSS2A, HCAVSS2B High Current Negative Analog Supply Voltage, for EXTFORCE2 Range.
53, 59 EXTFORCE2A,
EXTFORCE2B
Output Force. This pin is used for high Current Range 2, up to a maximum of ±500 mA.
54, 60 HCAVDD2A,
HCAVDD2B
High Current Positive Analog Supply Voltage, for EXTFORCE2 Range.
64 GPO Extra Logic Output Bit. Ideal for external functions such as switching out a decoupling capacitor at DUT.
65 EP The exposed pad is internally connected to AVSS.
AD5560
Rev. C | Page 18 of 60
TYPICAL PERFORMANCE CHARACTERISTICS
–4
–2
0
2
4
6
8
10
12
MEASOUT GAIN = 1
MEASOUT GAIN = 0.2
07779-034
CODE
MV L INEARI TY (mV)
0 10,000 20,000 30,000 40,000 50,000 60,000
T
J
= 25°C
AV
DD
= 8V
AV
SS
= –25V
V
REF
= 5V
OFFSET DAC = 0
xD4EB
07779-026
CODE
LINEARITY (mV )
–0.2
0
0.2
0.4
0.6
0.8
1.0
1.2
0 10,000 20,000 30,000 40,000 50,000 60,000
Figure 7. Force Voltage Linearity vs. Code, VREF = 5 V, No Load Figure 10. Measure Voltage Linearity vs. Code (MEASOUT Gain 1,
MEASOUT Gain = 0.2, Negative Skew Supply)
07779-027
CODE
MV L INEARI TY ERRO R (mV)
10,0000 20,000
2.0
1.5
0.5
0
–0.5
–1.0
1.0
–1.5
–2.0 30,000 40,000 50,000 60,000
T
J
= 25°C
AV
DD
= 16. 25V
AV
SS
= –16.25V
V
REF
= 5V
MEASOUT GAIN = 1
MEASOUT GAIN = 0.2
07779-035
CODE
0 10,000 20,000 30,000 40,000 50,000 60,000 70,000
LOW SUPPLIES
HIGH SUPP LIES
HI GH: A V DD = 28V, AVSS = –5V, OFF SET DAC = 0xD1D
LOW: AVDD = 5V, AVSS = –25V OFFSE T DAC = 0xD4E B
NO M : AV DD/AVSS = ± 16.25V, OFF S ET DAC = 0x8000
VREF = 5V
NOMINAL SUPPLIES
LINEARITY (%)
–0.0100
0.0100
–0.0075
–0.0050
–0.0025
0.0025
0
0.0050
0.0075
Figure 8. Measure Voltage Linearity vs. Code (MEASOUT Gain = 1,
MEASOUT Gain = 0.2, Nominal Supplies)
Figure 11. Measure Current Linearity vs. Code (MEASOUT Gain = 1,
MI Gain = 20), TJ = 25°C
07779-036
CODE
MI LINEARITY (%)
0 10,000 20,000 30,000 40,000 50,000 60,000 70,000
–0.010
–0.005
0.005
0
0.010
HIGH SUPP L IES
NOMI NAL SUP PLI ES
HIG H: AV
DD
= 28V, AV
SS
= –5V, OFF SET DAC = 0xD1D
LOW: AV
DD
= 5V, AV
SS
= –25V OF FSET DAC = 0xD4EB
NOM: AV
DD
/AV
SS
= ±16.25V, OF FSE T DAC = 0x8000
V
REF
= 5V
LOW SUPPLIES
MEASOUT GAIN = 1
07779-033
CODE
MV LINEARIT Y ( mV )
–2
–1
0
1
2
3
4
5
0 10,000 20,000 30,000 40,000 50,000 60,000
T
J
= 25°C
AV
DD
= 28V
AV
SS
= –5V
V
REF
= 5V
OFFSET DAC = 0xD1D
MEASOUT GAIN = 0.2
Figure 9. Measure Voltage Linearity vs. Code (MEASOUT Gain = 1,
MEASOUT Gain = 0.2, Positive Skew Supply)
Figure 12. Measure Current Linearity vs. Code (MEASOUT Gain = 1,
MI Gain = 10)
AD5560
Rev. C | Page 19 of 60
07779-037
CODE
0 10,000 20,000 30,000 40,000 50,000 60,000 70,000
HIGH SUPPLIES
NOMINAL SUPPL IES
HIGH: AVDD = 28V, AVSS = –5V, OFFSET DAC = 0xD1D
LOW : AVDD = 5V, AVSS = –25V OFFSET DAC = 0xD4EB
NO M: AVDD/AVSS = ±16.25V, O FFSET DAC = 0x8000
VREF = 5V
±25 mA R ANGE
LOW SUPPLIES
LINEARITY ( %)
–0.0500
0.0500
–0.0375
–0.0250
–0.0125
0.0125
0
0.0250
0.0375
Figure 13. Measure Current Linearity vs. Code (MEASOUT Gain = 0.2,
MI Gain = 20)
07779-038
CODE
0 10,000 20,000 30,000 40,000 50,000 60,000 70,000
HIGH SUPPLIES
HIGH: AVDD = 28V, AVSS = –5V, OFFSET DAC = 0xD1D
LOW : AVDD = 5V, AVSS = –25V OFFSET DAC = 0xD4EB
NO M : AVDD/AVSS = ±16.25V, OFFSET DAC = 0x8000
VREF = 5V ±25mA RANGE
LOW SUPPLIES
NOM INAL S UPP LIE S
LINEARITY ( %)
–0.100
0.100
–0.075
–0.050
–0.025
0.025
0
0.050
0.075
Figure 14. Measure Current Linearity vs. Code (MEASOUT Gain = 0.2,
MI Gain = 10)
07779-039
CODE
LINEARITY (%)
0 10,000 20,000 30,000 40,000 50,000 60,000
–0.0100
0.0100
–0.0075
–0.0050
–0.0025
0.0025
0
0.0050
0.0075
AV
DD
= +16.25V
AV
SS
= –16. 25V
V
REF
= 5V
OF FSE T DAC = 0x8000
MI GAIN = 20
MEASOUT GAIN = 1
25mA RANGE
25µ A RANGE
2.5mA
Figure 15. Measure Current Linearity vs. IRANGE (MEASOUT Gain = 1,
MI Gain = 20)
07779-040
CODE
LINEARITY ( %)
0 10,000 20,000 30,000 40,000 50,000 60,000
–0.0500
0.0500
–0.0375
–0.0250
–0.0125
0.0125
0
0.0250
0.0375
AV
DD
= +16.25V
AV
SS
= –16. 25V
V
REF
= 5V
OFFSET DAC = 0x8 000
MI GAIN = 20
MEASOUT GAIN = 0.2
25mA RANGE
25µ A RANGE
2.5mA
Figure 16. Measure Current Linearity vs. IRANGE (MEASOUT Gain = 0.2,
MI Gain = 20)
07779-030
STRESS VOLTAGE (V)
LEAKAG E CURRENT (n A)
T
J
= 25°C
–3.0
–2.5
–2.0
–1.5
–1.0
–0.5
0
0.5
1.0
1.5
–10 5 0 5 10
EXTFORCE1A
EXTFORCE2B
FORCE
EXTFORCE1B
EXTMEASIH1
SENSE
EXTFORCE1C
EXTMEASIH2
SYS_FORCE
EXTFORCE2A
EXTMEASIL
SYS_SENSE
COM BINED L EAKAGE
Figure 17. Leakage Current vs. Stress Voltage (Force and Combined Leakage)
0
1
2
3
4
5
6
7
07779-031
LEAKAGE CURRENT ( nA)
EXTFORCE1A
EXTFORCE2B
FORCE
EXTFORCE1B
EXTMEASIH1
SENSE
EXTFORCE1C
EXTMEASIH2
SYS_FORCE
EXTFORCE2A
EXTMEASIL
SYS_SENSE
COM BINED L EAKAGE
V
STRESS
= 9V
25 35 45 55 65 75 85 95
TEMPERATURE (°C)
Figure 18. Leakage Current vs. Temperature (Force and Combined Leakage),
VSTRESS = 9 V
AD5560
Rev. C | Page 20 of 60
07779-032
STRESS VOLTAGE (V)
LEAKAGE CURRENT ( nA)
T
J
= 25°C
–0.20
–0.15
–0.10
–0.05
0.05
0
0.10
0.15
–10 5 0 5 10
EXTFORCE1A
EXTFORCE2B
EXTFORCE1B
EXTMEASIH1
SENSE
EXTFORCE1C
EXTMEASIH2
SYS_FORCE
EXTFORCE2A
EXTMEASIL
SYS_SENSE
Figure 19. Leakage Current vs. Stress Voltage
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
EXTFORCE1A
EXTFORCE2B
EXTFORCE1B
EXTMEASIH1
SENSE
EXTFORCE1C
EXTMEASIH2
SYS_FORCE
EXTFORCE2A
EXTMEASIL
SYS_SENSE
25 35 45 55 65 75 85 95
07779-061
TEMPERATURE (°C)
LEAKAG E CURRE NT (n A)
V
STRESS
=9V
Figure 20. Leakage Current vs. Temperature, VSTRESS = 9 V
–0.20
–0.15
–0.10
–0.05
0
0.05
0.10
25 35 45 55 65 75 85
07779-047
TEMPERATURE (°C)
OFFS E T ERROR (% )
HIGH
HIG H 0.2
NOMINAL
LOW
NOMINAL 0.2
LOW 0.2
HIGH: AV
DD
= 28V, AVSS = –5V, OFFSET DAC = 0xD1D
LOW : AV
DD
= 5V, AVSS = –25V OFFSET DAC = 0xD4EB
NO M : AV
DD
/AV
SS
= ±16.25V, O FFSET DAC = 0x8000
V
REF
= 5V
LOW0.2/HIGH0.2/NOM0.2 MEAN FOR MEASOUT GAIN = 0.2
Figure 21. MI Offset Error vs. Temperature, MI Gain = 20,
MEASOUT Gain = 1 and 0.2
–0.12
–0.10
–0.08
–0.06
–0.04
–0.02
0
25 35 45 55 65 75 85
07779-48
TEMPERATURE (°C)
GAI N E RROR (%)
HIGH
NOMINAL
LOW
Figure 22. MI Positive Gain Error vs. Temperature, MI Gain = 20,
MEASOUT Gain = 1
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
–2.5
–2.0
–1.5
–1.0
–0.5
0
25 35 45 55 65 75 85
07779-043
TEMPERATURE (°C)
POSI TIV E GAIN ERROR (mV)
NEGATIV E GAIN E RROR (mV)
AV
DD
= ±16.25V
AV
SS
= –16. 25V
V
REF
= 5V
OFFSET DAC = 0x8000
Figure 23. FV Gain Error vs. Temperature
20.0
20.5
21.0
21.5
22.0
22.5
23.0
25 35 45 55 65 75 85
07779-041
TEMPERATURE (°C)
OFFS E T ERRO R (m V)
Figure 24. FV Offset Error vs. Temperature
AD5560
Rev. C | Page 21 of 60
–0.007
–0.006
–0.005
–0.004
–0.003
–0.002
–0.001
0
25 35 45 55 65 75 85
07779-045
TEMPERATURE (°C)
GAIN ERROR (%)
HIGH
NOMINAL LOW
Figure 25. MV Gain Error vs. Temperature, MEASOUT Gain = 1
25 35 45 55 65 75 85
LOW
HIGH
07779-042
TEMPERATURE (°C)
OF FSET ERRO R ( mV)
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
NOMINAL
Figure 26. MV Offset Error vs. Temperature, MEASOUT Gain = 1
0
0.005
0.010
0.015
0.020
0.025
0.030
25 35 45 55 65 75 85
07779-046
TEMPERATURE (°C)
GA IN E R ROR (%)
HIGH
NOMINAL
LOW
Figure 27. MV Gain Error vs. Temperature, MEASOUT Gain = 0.2
–5
–4
–3
–2
–1
0
1
2
3
4
5
25 35 45 55 65 75 85
07779-044
TEMPERATURE (°C)
OFFS E T ERROR (m V)
HIGH
NOMINAL
LOW
Figure 28. MV Offset Error vs. Temperature, MEASOUT Gain = 0.2
07779-015
CH1 50mV
CH3 5V M 200µ s A CH3 1.5V
1
3
T 10.4%
CH1 p - p
27mV
CH1 AREA
10.92µVs
BW
BW
FORCE
SYNC
Figure 29. Range Change 2.5 mA to 25 mA, Safe Mode, 2.5 mA ILOAD, 10 F Load
07779-016
CH1 50mV
CH3 5V M200µs A CH3 1.5V
1
3
T 10.4%
CH1 p-p
16mV
CH1 AREA
–5.336µVs
BW
BW
FORCE
SYNC
Figure 30. Range Change 25 mA to 2.5 mA, Safe Mode, 2.5 mA ILOAD, 10 F Load
AD5560
Rev. C | Page 22 of 60
07779-017
CH1 50mV
CH3 5V M 200µ s A CH3 1.5V
1
3
T 10.4%
CH1 p-p
159mV
CH1 AREA
14.31µVs
BW
BW
FORCE
SYNC
Figure 31. Range Change 25 mA to EXTFORCE2, Safe Mode,
25 mA ILOAD, 10 F Load
07779-018
CH1 50m V
CH3 5V M 200µ s A CH3 1.5V
1
3
T 10.4%
CH1 p- p
36mV
CH1 AREA
–9.738µVs
FORCE
SYNC
Figure 32. Range Change EXTFORCE2 to 25 mA, Safe Mode,
25 mA ILOAD, 10 µF Load
07779-019
PEAK-T O-PEAK (mV)
0
50
100
150
200
250
300
350
SAFE
MODE AUTO
COMP SAFE
MODE AUTO
COMP SAFE
MODE AUTO
COMP
EXT RANGE 1 EXT RANGE 2 25mA RANG E
10µ F LOAD
30µ F LOAD
100 µ F LOAD
Figure 33. Kick/Droop Response vs. IRANGE, Compensation, and CLOAD,,
10% to 90% to 10% ILOAD Change
07779-020
CH1 100m V CH2 5 V M40µs A CH2 1.6V
1
2
T 120.4µs
CH1 p- p
84mV
BW
TRIGGER
FORCE
Figure 34. Autocompensation Mode 90% to 10% ILOAD Change,
EXTFORCE2 Range, 10 µF Load
07779-021
CH1 100m V CH2 5V M40µs A CH2 4V
1
2
T 120.4µs
CH1 p- p
86mV
BW
TRIGGER
FORCE
Figure 35. Autocompensation Mode 10% to 90% ILOAD Change,
EXTFORCE2 Range, 10 µF Load
07779-022
CH1 100m V CH2 5V M40µs A CH2 1.6V
1
2
T 120.4µs
CH1 p- p
172mV
BW
TRIGGER
FORCE
Figure 36. Safe Mode 80% to 10%, EXTFORCE2 Range, 10 µF Load
AD5560
Rev. C | Page 23 of 60
CH2 5V
07779-023
CH1 100mV M40 µs A CH2 4.6V
1
2
T 120.4µs
CH1 p- p
174mV
BW
TRIGGER
FORCE
Figure 37. Safe Mode 10% to 90%, EXTFORCE2 Range, 10 µF Load
07779-024
FO RCED T EM P ERAT URE ( ° C)
MEASOUT VOLT AG E ( V)
1.4
1.5
1.6
1.7
1.8
1.9
2.0
25 35 45 55 65 75 85
AV
DD
= +16.5V
AV
SS
= –16.5V
Figure 38. MEASOUT TSENSE Temperature Sensor vs. Temperature
(Multiple Devices)
07779-054
CH1 5V
CH3 5V M 400µs A CH3 2.9V
1
2
3
4
T 10.2%
BW
CH2 2V
CH4 10V
T
A
= 25°C
AV
DD
= +16.25V
AV
SS
= –16.25V
V
REF
= 5V
OF F S E T DAC = 0x8000
I
RANGE
/I
LOAD
= 250µA
0 TO 10V ST E P
R
LOAD
= 40kΩ
C
LOAD
= 220n F
AUTOCOM P M ODE 0x4880
MEASOUT GAI N 1, MI GAIN 20
FORCE
MEASOUT – MI
BUSY
Figure 39. Transient Response FVMI Mode, ±250 µA Range,
Autocompensation Mode
07779-055
CH1 5V
CH3 5V M20µs A CH3 2.9V
1
2
3
4
T 1.4%
BW
CH2 2V
CH4 10V
T
A
= 25°C
AV
DD
= +16.25V
AV
SS
= –16.25V
V
REF
= 5V
OFFSET DAC = 0x8000
I
RANGE
/I
LOAD
= 25mA
0 TO 10V STEP
R
LOAD
= 40kΩ
C
LOAD
= 220n F
AUTOCOM P MO DE 0x44 80
MEASOUT GAIN 1, MI GAIN 20
FORCE
MEASOUT – MI
BUSY
Figure 40. Transient Response FVMI Mode, 25 mA Range,
Autocompensation Mode
07779-056
CH1 5V
CH3 5V M 100µ s A CH3 2.9V
1
2
3
4
T 7.2%
BW
CH2 2V
CH4 10V
T
A
= 25°C
AV
DD
= +16.25V
AV
SS
= –16. 25V
V
REF
= 5V
OF FSE T DAC = 0x80 00
I
RANGE
/I
LOAD
= 250 µA
0 TO 10V S TEP
R
LOAD
= 40k Ω
C
LOAD
= 220nF
SAFE MODE
MEASOUT GAIN 1, MI GAIN 20
FORCE
MEASOUT – MI
BUSY
Figure 41. Transient Response FVMI Mode, 25mA Range, Safe Mode
07779-057
CH1 5V
CH3 5V M4µs A CH3 2.9V
1
2
3
4
T 3%
BW
CH2 1V
CH4 10V
T
A
= 25°C
AV
DD
= +16.25V
AV
SS
= –16. 25V
V
REF
= 5V
OF FSE T DAC = 0x80 00
I
RANGE
/I
LOAD
= EX TFORCE1/1.2A
0 TO 3. 7V STE P
C
LOAD
= 10µF CERAMIC
AUTOCOM P M ODE 0x 9680
MEASOUT GAIN 1, MI GAIN 20
FORCE
MEASOUT – MI
BUSY
Figure 42. Transient Response FVMI Mode, EXTFORCE1 Range,
Autocompensation Mode
AD5560
Rev. C | Page 24 of 60
07779-058
CH1 5V
CH3 5V M20µs A CH3 2.9V
1
2
4
T 4.6%
BW
CH2 1V
CH4 10V
T
A
= 25°C
AV
DD
= +16 .25V
AV
SS
= –16. 2 5V
V
REF
= 5V
OFFSET DAC = 0x 8000
I
RANGE
/I
LOAD
= EXT F ORCE1/1. 2A
0 TO 3. 7V ST EP
C
LOAD
= 10µF CERAMIC
SAFE MODE
MEASOUT GAIN 1, MI GAIN 20
3
FORCE
MEASOUT – MI
BUSY
Figure 43. Transient Response FVMI Mode, EXTFORCE1 Range, Safe Mode
07779-059
CH1 5V
CH3 5V M10µs A CH3 2.9V
1
2
3
4
T 9.8%
BW
CH2 2V
CH4 10V
T
A
= 25°C
AV
DD
= +16.25V
AV
SS
= –16. 25 V
V
REF
= 5V
OFFSET DAC = 0x8 000
I
RANGE
/I
LOAD
= EX TFORCE2/
300mA
0 TO 10V S TEP
C
LOAD
= 220nF
AUTO COMP M ODE 0x4880
MEASOUT GAIN 1, MI GAIN 20
FORCE
MEASOUT – MI
BUSY
Figure 44. Transient Response FVMI Mode, EXTFORCE2 Range,
Autocompensation Mode
3
07779-060
CH1 5V
CH3 5 V M100µ s A CH3 2.9V
1
2
4
T 9.8%
BW
FORCE
CH2 2V
CH4 10V
T
A
= 25°C
AV
DD
= +16.25V
AV
SS
= –16.25V
V
REF
= 5V
OFFSET DAC = 0x8000
I
RANGE
/I
LOAD
= EXTFORCE2/300mA
0 TO 10V STEP
C
LOAD
= 220n F
SAFE MODE
MEASOUT GAIN 1, MI GAIN 20
MEASOUT – MI
BUSY
Figure 45. Transient Response FVMI Mode, EXTFORCE2 Range, Safe Mode
07779-025
NSD (nV/√Hz)
0
100
200
300
400
500
600
700
800
900
1000 PART H1
PART H2
PART H3
G
AIN = 00
G
AIN = 10
G
AIN = 00
G
AIN = 10
G
AIN = 00
G
AIN = 01
G
AIN = 10
G
AIN = 11
FVMN FVMV FNMV FVMI
Figure 46. NSD vs. Amplifier Stage and Gain Setting at 1 kHz
–100
–80
–60
–40
–20
20
0
10 100 1k 10k 100k 1M 10M
07779-049
FREQUENCY (Hz)
ACPSRR (dB)
DV
CC
= +5.25V, AV
DD
= +16.5V, AV
SS
= –16. 5 V
FOH
MV: GAIN 0
MV: GAIN 1
MV: GAIN 2
MV: GAIN 3
MI: GAIN 0
MI: G AIN 1
MI: GAIN 2
MI: GAIN 3
Figure 47. ACPSRR of AVDD vs. Frequency
–100
–120
–140
–80
–60
–40
–20
0
10 100 1k 10k 100k 1M 10M
07779-050
FREQUENCY (Hz)
ACPSRR (dB)
DV
CC
= +5.25V, AV
DD
= +16.5V, AV
SS
= –16. 5V
FOH
MV: GAIN 0
MV: GAIN 1
MV: GAIN 2
MV: GAIN 3
MI: GAIN 0
MI: G AIN 1
MI: GAIN 2
MI: GAIN 3
Figure 48. ACPSRR of AVSS vs. Frequency
AD5560
Rev. C | Page 25 of 60
–120
–100
–80
–60
–40
–20
0
10 100 1k 10k 100k 1M 10M
07779-051
FREQUENCY (Hz )
ACPSRR (dB)
MV: GAIN 0
FOH
MI: GAIN 0
DV
CC
= +5.25V, AV
DD
= +16.5V, AV
SS
= –16. 5 V
–140
–120
–100
–80
–60
–40
–20
0
10 100 1k 10k 100k 1M 10M
07779-053
FREQUENCY (Hz )
ACPSRR (dB)
MI: GAIN 0
DV
CC
= +5.25V, AV
DD
= +16.5V, AV
SS
= –16. 5V
FOH
MV: GAIN 0
Figure 49. ACPSRR of DVCC vs. Frequency Figure 51. ACPSRR of HCAVSSx vs. Frequency
–140
–120
–100
–80
–60
–40
–20
0
10 100 1k 10k 100k 1M 10M
07779-052
FREQUENCY (Hz )
ACPSRR (d B)
MI: GAIN 0
FOH
DV
CC
= +5.25V, AV
DD
= +16.5V, AV
SS
= –16. 5V
MV: GAIN 0
Figure 50. ACPSRR of HCAVDDx vs. Frequency
AD5560
Rev. C | Page 26 of 60
TERMINOLOGY
Offset Error
Offset error is a measure of the difference between the actual
voltage and the ideal voltage at midscale or at zero current
expressed in millivolts (mV) or percentage of full-scale range
(%FSR).
Gain Error
Gain error is the difference between full-scale error and zero-
scale error. It is expressed in percentage of full-scale range
(%FSR).
Gain Error = Full-Scale Error − Zero-Scale Error
where:
Full-Scale Error is the difference between the actual voltage and
the ideal voltage at full scale.
Zero-Scale Error is the difference between the actual voltage and
the ideal voltage at zero scale.
Linearity Error
Linearity error, or endpoint linearity, is a measure of the
maximum deviation from a straight line passing through the
endpoints of the full-scale range. It is measured after adjusting
for offset error and gain error and is expressed in millivolts (mV).
Common-Mode (CM) Error
CM error is the error at the output of the amplifier due to the
common-mode input voltage. It is expressed in percentage of
full-scale voltage range per volt (%FSVR/V).
Clamp Limit
Clamp limit is a measure of where the clamps begin to function
fully and limit the clamped voltage or current.
Leakage Current
Leakage current is the current measured at an output pin when
the circuit connected to that pin is in high impedance state.
Slew Rate
The slew rate is the rate of change of the output voltage
expressed in volts per microsecond (V/s).
Differential Nonlinearity (DNL)
DNL is the difference between the measured change and the
ideal 1 LSB change between any two adjacent codes. A specified
DNL of ±1 LSB maximum ensures monotonicity.
Output Voltage Settling Time
Output voltage settling time is the amount of time it takes for
the output of a DAC to settle to a specified level for a full-scale
input change.
Digital-to-Analog Glitch Energy
Digital-to-analog glitch energy is the amount of energy that is
injected into the analog output at the major code transition. It
is specified as the area of the glitch in nanovolts per second
(nV-sec). It is measured by toggling the DAC register data
between 0x7FFF and 0x8000.
AC Power Supply Rejection Ratio (ACPSRR)
ACPSRR is a measure of the part’s ability to avoid coupling
noise and spurious signals that appear on the supply voltage
pin to the output of the switch. The dc voltage on the device
is modulated by a sine wave of 0.2 V p-p. The ratio of the
amplitude of the signal on the output to the amplitude of the
modulation is the ACPSRR. It is expressed in decibels (dB).
VSTRESS
VSTRESS is the stress voltage applied to each pin during leakage
testing.
AD5560
Rev. C | Page 27 of 60
THEORY OF OPERATION
The AD5560 is a single-channel, device power supply for use
in semiconductor automatic test equipment. All the DAC levels
required to operate the device are available on chip.
This device contains programmable modes to force a pin vol-
tage and measure the corresponding current (FVMI) covering
a wide current measure range of up to ±1.2 A. A voltage sense
amplifier allows measurement of the DUT voltage. Measured
current or voltage is available on the MEASOUT pin.
FORCE AMPLIFIER
The force amplifier is a unity gain amplifier forcing voltage
directly to the device under test (DUT). This high bandwidth
amplifier allows suppression of load transient induced glitching
on the amplifier output. Headroom and footroom requirements
for the amplifier are 2.25 V and an additional ±500 mV dropped
across the selected sense resistor with full-scale current flowing.
The amplifier is designed to drive high currents up to ±1.2 A
with the capability of ganging together outputs of multiple
AD5560 devices for currents in excess of ±1.2 A.
The force amplifier can be compensated to ensure stability
when driving DUT capacitances of up to 160 F.
The device is capable of supplying transient currents in excess
of ±1.2 A when powering a DUT with a large decoupling
capacitor. A clamp enable pin (CLEN) allows disabling of the
clamp circuitry to allow the amplifier to quickly charge this
large capacitance.
An extra control bit (GPO) is available to switch out DUT
decoupling when making low current measurements.
HW_INH Function
A hardware inhibit pin (HW_INH/LOAD) allows disabling of
the force amplifier, making the output high impedance. This
function is also available through the serial interface (see the
SW-INH bit in the DPS Register 1, Address 0x2).
This pin can also be configured as a LOAD function to allow
multiple devices to be synchronized. Note that either CLEN
or HW_INH can be chosen as a LOAD function.
DAC REFERENCE VOLTAGE (VREF)
One analog reference input, VREF, supplies all DAC levels with
the necessary reference voltage to generate the required dc levels.
OPEN-SENSE DETECT (OSD) ALARM AND CLAMP
The open-sense detect (OSD) circuitry protects the DUT from
overvoltage when the force and sense lines of the force
amplifier becoming disconnected from each other.
This block performs three functions related to the force and
sense lines.
• It clamps the sense line to within a programmable
threshold level (plus a VBE) of the force line, where the
programmable threshold is set by the OSD DAC voltage
level. This limits the maximum or minimum voltage that
can appear on the FORCE pin; it can be driven no higher
than [V(FIN DAC) + threshold + VBE] and no lower than
[V(FIN DAC) − threshold − VBE].
• It triggers an alarm on KELALM if the force line goes more
than the threshold voltage away (OSD DAC level) from the
sense line.
• It translates the V(force − sense) voltage to a level
relative to AGND so that it can be measured through
the MEASOUT pin.
The open-sense detect level is programmable over the range
0.62 V to 5 V (16-bit OSD DAC plus one diode drop). The 5 V
OSD DAC can be accessed through the serial interface (see the
DAC register addressing portion of Table 24). There is a 10 kΩ
resistor that can be connected between the FORCE and SENSE
pins by use of SW11. This 10 kΩ resistor is intended to
maintain a force/sense connection when a DUT is not in place.
It is not intended to be connected when measurements are
being made because this defeats the purpose of the OSD circuit
in identifying an open circuit between FORCE and SENSE. In
addition, the sense path has a 2.5 kΩ resistor in series; there-
fore, if the 10 kΩ switch is closed, errors may become apparent
when in high current ranges.
DEVICE UNDER TEST GROUND (DUTGND)
DUTGND is the ground level of the DUT.
DUTGND Kelvin Sense
KELALM flags when the voltage at the DUTGND pin moves
too far away from the AGND line (>1 V default setting of the
DGS DAC). This alarm trigger is programmable via the serial
interface. The threshold for the alarm function is program-
mable using the DUTGND SENSE DAC (DGS DAC) (see
). Table 24
The DUTGND pin has a 50 A pull-up resistor that allows
the alarm function to detect whether DUTGND is open. Setting
the disable DUTALM bit high (Register 0x6, Bit 10) disables the
50 A pull-up resistor and also disables the alarm feature. The
alarm feature can also be set to latched or unlatched (Register 0x6,
Bit 11).
Kelvin Alarm (KELALM)
The open-drain active low Kelvin alarm pin flags the user when
an open occurs in either the sense or DUTGND line; it can be
programmed to be either latched or unlatched (Register 0x6,
Bit 13, Bit 11, Bit 7). The delay in the alarm flag is 50 s.
AD5560
Rev. C | Page 28 of 60
GPO
The GPO pin can be used as an extra control bit for external
switching functions, such as for switching out DUT decoupling
when making low current measurements.
The GPO pin is also internally connected to an array of thermal
diodes scattered across the AD5560. The diagnostic register
(Address 0x7) details the addressing and location of the diodes.
These can be used for diagnostic purposes to determine the
thermal gradients across the die and across a board containing
many AD5560 devices. When selected, the anode of these
diodes is connected to GPO and the cathode to AGND. The
AD5560 evaluation board uses the ON Semiconductor®
ADT7461 temperature sensor for the purpose of analyzing the
temperature at different points across the die.
COMPARATORS
The DUT measured value is monitored by two comparators
(CPOL, CPOH). These comparators give the advantage of
speed for go-no-go testing.
Table 6. Comparator Output Function
Test Condition CPOL CPOH
(VDUT or IDUT) > CPH 0
(VDUT or IDUT) < CPH 1
(VDUT or IDUT) > CPL 1
(VDUT or IDUT) < CPL 0
CPH > (VDUT or IDUT) > CPL 1 1
To minimize the number of comparator output lines routed
back to the controller, it is possible to change the comparator
function to a window comparator that outputs on one single
pin, CPO. This pin is shared with CPOH and, when configured
through the serial interface, it provides information on whether
the measured DUT current or voltage is inside or outside the
window set by the CPL and CPH DAC levels (see Table 24).
Table 7. Comparator Output Function in CPO Mode
Test Condition CPO Output
(VDUT or IDUT) > CPL and < CPH 1
(VDUT or IDUT) < CPL or > CPH 0
CURRENT CLAMPS
High and low current clamps are included on chip. These protect
the DUT in the event of a short circuit. The CLH and CLL
levels are set by the 16-bit DAC levels. The clamp works to
limit the current supplied by the force amplifier to within the
set levels. The clamp circuitry compares the voltage across the
sense resistor (multiplied by an in-amp gain of 10 or 20) to
compare to the programmed clamp limit and activates the
clamp circuit if either the high level or low level is exceeded,
thus ensuring that the DUT current can never exceed the
programmed clamp limit + 10% of full-scale current.
If a clamp level is exceeded, this is flagged via the latched open-
drain CLALM pin, and the resulting alarm information can be
read back via the SPI interface.
The clamp levels should not be set to the same level; instead,
they should be set a minimum of 2 V apart (irrespective of the
MI gain setting). This equates to 10% of FSCR (MI gain = 20)
(20% of FSCR, MI gain of 10) apart. They should also be 1 V
away from the 0 A level.
The clamp register limits the CLL clamp to the range 0x0000 to
0x7FFF; any code in excess of this is seen as 0x7FFF. Similarly,
the CLH clamp registers are limited to the range 0x8000 to
0xFFFF (see Table 24).
Clamp Alarm Function (CLALM)
The CLALM open-drain output flags the user when a clamp
limit has been hit; it can be programmed to be either latched or
unlatched.
Clamp Enable Function (CLEN/LOAD)
Pin 15 (CLEN) allows the user to disable the clamping function
when powering a device with large DUT capacitance, thus allowing
increased current drive to the device and, therefore, speeding
up the charging time of the load capacitance. CLEN is active high.
This pin can also be configured as LOAD to allow multiple devices
to be synchronized. Note that either CLEN or HW_INH can be
chosen as a LOAD function.
SHORT-CIRCUIT PROTECTION
The AD5560 force amplifier stage has built-in short-circuit
protection per stage as noted in the Specifications section.
When the current clamps are disabled, the user must minimize
the duration of time that the device is left in a short-circuit
condition (for all current ranges).
GUARD AMPLIFIER
A guard amplifier allows the user to force the shield of the
coaxial cable to be driven to the same forced voltage at the
DUT, ensuring minimal voltage drops across the cable to
minimize errors from cable insulation leakage.
The guard amplifier also has an alarm function that flags the
open-drain KELALM pin when the guard output is shorted.
The delay in the alarm flag is 200 s.
The guard amplifier output (GUARD/SYS_DUTGND, Pin 43)
can also be configured to function as a SYS_DUTGND pin; to
do this, the guard amplifier must be tristated via software (see
DPS Register 2, Table 19).
COMPENSATION CAPACITORS
The force amplifier is capable of driving DUT capacitances up
to 160 F. Four external compensation capacitor (CCx) inputs
are provided to ensure stability into the maximum load capacit-
ance while ensuring that settling time is optimized. In addition,
five CFx capacitor inputs are provided to switch across the sense
AD5560
Rev. C | Page 29 of 60
resistors to further optimize stability and settling time perform-
ance. The AD5560 has three compensation modes: safe mode,
autocompensation mode, and manual compensation mode, all
of which are described in more EFUBJMJOUIF'PSDF"NQMJGJFS
Stability section.
The range of suggested compensation capacitors allows
optimum performance for any capacitive load from 0 pF
to 160 F using one of the modes previously listed.
Although there are four compensation input pins and five feed-
forward capacitor inputs pins, all capacitor inputs may be used
only if the user intends to drive large variations of DUT load
capacitances. If the DUT load capacitance is known and does
not change for all combinations of voltage ranges and test
conditions, then it is possible only one set of CCx and CFx
capacitors may be required.
Table 8. Suggested Compensation Capacitor Selection
Capacitor Value
CC0 100 pF
CC1 100 pF
CC2 330 pF
CC3 3.3 nF
CF0 4.7 nF
CF1 22 nF
CF2 100 nF
CF3 470 nF
CF4 2.2 F
The voltage range for the CCx and CFx pins is the same as the
voltage range expected on FORCE; therefore, choice of capa-
citors should take this into account. CFx capacitors can have
10% tolerance; this extra variation directly affects settling
times, especially when measuring current in the low current
ranges. Selection of CCx should be at ≤5% tolerance.
CURRENT RANGE SELECTION
Integrated thin film resistors minimize external components
and allow easy selection of current ranges from ±5 µA to
±25 mA. Using external current sense resistors, two higher
current ranges are possible: EXTFORCE1 can drive currents
up to ±1.2 A, while EXTFORCE2 is designed to drive currents
up to ±500 mA. The voltage drop across the selected sense resistor
is ±500 mV when full-scale current is flowing through it.
The measure current amplifier has two gain settings, 10 and
20. The two gain settings allow users to achieve the quoted/
specified current ranges with large or small voltage swings.
The gain of 20 setting is intended for use with a 5 V reference,
and the gain of 10 setting is for use with a 2.5 V reference. Both
combinations ensure the specified current ranges. Other
VREF/gain setting combinations should only be used to
achieve smaller current ranges. Attempting to achieve greater
current ranges than the specified ranges is outside the intended
operation of the AD5560. The maximum guaranteed voltage
across RSENSE is ±0.64 V (gain of 20) or ±0.7 V (gain of 10).
HIGH CURRENT RANGES
For currents in excess of 1200 mA, a gang mode is available
whereby multiple devices are ganged together for higher currents.
There are two methods of ganging channels together; these are
discussed in the following two sections.
Master and Slaves in Force Voltage (FV) Mode
All devices are placed in force voltage (FV) mode. One device
acts as the master device and the other devices act as slaves. By
connecting in this manner, any device can be configured as the
master. Here, the MASTER_OUT pin of the master device is
connected to the output of the force amplifier, and it feeds the
inputs of each slave force amplifier (via the SLAVE_IN pin ).
All devices are connected externally to the DUT. For current
to be shared equally, there must be good matching between
each of the paths to the DUT. Settings for DPS Register 2 are
master = 0x0000, slave = 0x0400. Clamps should be disabled in
the slave devices.
EXTMEASIL
SENSE
MASTER DPS
EXTMEASIH1
SW5-a
FIN
DAC
×1
SW5-a
SW16
R
SENSE
LOCAL
FEEDBACK
SW5-b
SW6
MASTER OUT
EXTFORCE1
EXTFORCE2
SLAVE IN
R
SENSE
R
SENSE
DUT
DUTGND
EXTMEASIL
SENSE
SLAVE DPS 1
EXTMEASIH1
SW5-a
FIN
DAC
×1
×20
OR
×W
×20
OR
×W
×20
OR
×W
SW5-a
SW16
LOCAL
FEEDBACK
SW5-b
SW6
MASTER OUT
EXTFORCE1
EXTFORCE2
SLAVE IN
EXTMEASIL
SENSE
SLAVE DPS 2
EXTMEASIH1
SW5-a
FIN
DAC
I
SENSE
AMP
V
SENSE
AMP
I
SENSE
AMP
V
SENSE
AMP
I
SENSE
AMP
V
SENSE
AMP
×1
SW5-a
SW16
LOCAL
FEEDBACK
SW5-b
SW6
MASTER OUT
EXTFORCE1
EXTFORCE2
SLAVE IN
07779-007
Figure 52. Simplified Block Diagram of High Current Ganging Mode
AD5560
Rev. C | Page 30 of 60
Master in FV Mode, Slaves in Force Current (FI) Mode
The master device is placed into FV mode, and all slave devices
into force current (FI) mode. The measured current of the
master device (MASTER_OUT) is applied to the input of all
slave devices (SLAVE_IN), and the slaves act as followers. All
channels work to share the current equally among all devices
in the gang. Because the slaves force current, matching the
DUT paths is not so critical. Settings for DPS Register 2 are
master = 0x0200, slave = 0x0600. Clamps should be disabled in
the slave devices.
EXTMEASIL
MASTER DPS
EXTMEASIH1
SW5-a
FIN
DAC
MEASOUT
BUFFER
AND GAIN I
SENSE
AMP
SENSE
SW5-a
SW16 SW5-b
SW6
MASTER OUT
EXTFORCE1
EXTFORCE2
SLAVE IN
EXTMEASIL
SLAVE DPS 1
EXTMEASIH1
SW5-a
FIN
DAC
MEASOUT
BUFFER
AND GAIN I
SENSE
AMP
SENSE
SW5-a
SW16 SW5-b
SW6
MASTER OUT
EXTFORCE1
EXTFORCE2
SLAVE IN
EXTMEASIL
SLAVE DPS 2
EXTMEASIH1
SW5-a
FIN
DAC
MEASOUT
BUFFER
AND GAIN I
SENSE
AMP
SENSE
SW5-a
SW16 SW5-b
SW6
MASTER OUT
EXTFORCE1
EXTFORCE2
SLAVE IN
DUT
DUTGND
×20
×20
×20
07779-008
R
SENSE
R
SENSE
R
SENSE
Figure 53. Simplified Block Diagram of Gang Mode,
Using an FV/FI Combination
The EXTFORCE1, EXTFORCE2, or ±25 mA ranges can be
used for the gang mode. Therefore, it is possible to gang devices
to get a high voltage/high current combination, or a low
voltage/high current combination.
For example, ganging five 25 V/25 mA devices using the 25 mA
range achieves a 25 V/625 mA range, whereas five 15 V/200 mA
devices using the EXTFORCE2 path can achieve a 15 V/1 A
range. Similarly, ganging four 3.5 V/1.2 A devices using the
EXTFORCE1 path results in a 3.5 V/4.8 A DPS.
IDEAL SEQUENCE FOR GANG MODE
Use the following steps to bring devices into and out of gang mode:
1. Choose the master device and force 0 V output, corres-
ponding to zero current.
2. Select slave DPS 1 and place it in slave mode (keep slaves in
high-Z mode via SW-INH or HW_INH until ready to gang).
3. Select to gang in either current or voltage mode.
4. Repeat Step 2 and Step 3 one at a time through the chain of
slaves.
5. Load the required voltage to the master device. The other
devices copy either voltage or current as programmed.
To remove devices from the gang, the master device should
be programmed to force 0 V out again. The procedure for
removing devices should be the reverse of Step 1 through Step 5.
Note that this may not always be possible in practice; therefore,
it is also possible to gang and ungang while driving a load. Just
ensure that the slave devices are in high-Z mode while confi-
guring them into the required range and gang setting.
Gang mode extends only to the ±25 mA range and the two high
current ranges, EXTFORCE1 and EXTFORCE2. Therefore, where
an accurate measurement is required at a low current, the user
should remove slaves from the gang to move to the appropriate
lower current range to make the measurement. Similarly, slaves
can be brought back into the gang if needed.
COMPENSATION FOR GANG MODE
When ganging, the slave devices should be set to the fastest
response.
When slaves are in FI mode, the AD5560 force amplifier over-
rides other compensation settings to enforce CFx = 0, RZ = 0,
and gmx ≤ 1. This is done internally to the force amplifier;
therefore, readback will not show that the signals inside the
force amplifier actually change.
SYSTEM FORCE/SENSE SWITCHES
System force/sense switches allow easy connection of a central
or system parametric measurement unit (PMU) for calibration
or additional measurement purposes.
The system device under test ground (SYS_DUTGND) switch
is shared with the GUARD/SYS_DUTGND pin (Pin 43). See
the DPS Register 2 in Table 19 for addressing details.
AD5560
Rev. C | Page 31 of 60
DIE TEMPERATURE SENSOR AND THERMAL
SHUTDOWN
There are three types of temperature sensors in the AD5560.
• The first is a temperature sensor available on the MEASOUT
pin and expressed in voltage terms. Nominally at 25°C, this
sensor reads 1.54 V. It has a temperature coefficient of
4.7 mV/°C. This sensor is active during power-down mode.
Die Temp = (VMEASOUT(TSENSE) − 1.54)/0.0047 + 25°C
Based on typical temperature sensor output voltage at
25°C and output scaling factor.
• The second type of temperature sensor is related to the
thermal shutdown feature in the device. Here, there are
sensors located in the middle of the enabled power stage,
which are used to trip the thermal shutdown. The thermal
shutdown feature senses only the power stages, and the power
stage that it senses is determined by the active stage.
If ranges of <25 mA are selected, the EXTFORCE1 sensor is
monitored. The EXTFORCE1 power stage itself is made
up of three identical stages, but the thermal shutdown is
activated by only one stage (EXTFORCE1B). Similarly, the
EXTFORCE2 stage is made up of two identical output
stages, but the thermal shutdown can be activated by only
one stage (EXTFORCE2A).
The thermal shutdown circuit monitors these sensors and,
in the event of the die temperature exceeding the program-
mable threshold temperature (100°C, 110°C, 120°C, 130°C
(default)), the device protects itself by inhibiting the force
amplifier stage, clearing SW-INH in DPS Register 1 and
flagging the overtemperature event via the open-drain
TMPALM pin, which can be programmed to be either
latched or unlatched. These temperature sensors can be
read via the MEASOUT pin by selecting them in the
diagnostic register ( , VPTAT low and VPTAT
high). They are expressed in voltage and to scale to
temperature. They must be referred to the VTSD reference
voltage levels (see ) also available on MEASOUT.
This set of sensors is not active in power-down mode.
Table 23
Table 23
Die Temp_y = {(VPTAT_x − VTSD_low)/[(VTSD_high −
VTSD_low)/(Temp_high – Temp_low)]} + Temp_low
where:
x, y are (high, NPN) and (low, PNP).
Temp_low = −273°C.
Temp_high = +130°C.
• The third set of temperature sensors is an array of thermal
diodes scattered across the die. These diodes allow the user
to evaluate the temperature of different parts of the die and
are of great use to determine the temperature gradients
across the die and the temperature of the accurate portions
of the die when the device is dissipating high power. For
further details on the thermal array and locations, see the
diagnostic register section in Table 23.
These diodes can be muxed out onto the GPO pin. The
diagnostic register (Address 0x7) details the addressing and
location of the diodes. These can be used for diagnostic
purposes to determine the thermal gradients across the die
and across a board containing many AD5560 devices. When
selected, the anode of each diode is connected to GPO and
the cathode to AGND. The AD5560 evaluation board uses
the ON Semiconductor ADT7461 temperature sensor for
the purpose of analyzing the temperature at different
points across the die.
Note that, when a thermal shutdown occurs, as the force
amplifier is inhibited or tristated, user intervention is required
to reactivate the device. It is necessary to clear the temperature
alarm flag by issuing a read command of Register Address 0x44
(alarm status and clear alarm status register, Table 25), and
then issuing a new write to the DPS Register 1 (SW-INH = 1)
to reenable the force amplifier.
MEASURE OUTPUT (MEASOUT)
The measured DUT voltage, current (voltage representation
of DUT current), KSENSE, or die temperature is available on
MEASOUT with respect to AGND. The default MEASOUT
range is the forced voltage range for voltage measure and
current measure (nominally ±12.81 V, depending on reference
voltage and offset DAC) and includes overrange to allow for
system error correction.
The serial interface allows the user to select another MEASOUT
range of (1.025 × VREF) to AGND; this range is suitable for use
with an ADC with a smaller input range.
To allow for system error correction, there is additional gain
for the force function. If this overrange is used as intended,
the output range on MEASOUT scales accordingly.
The MEASOUT line can be tristated via the serial interface.
When using low supply voltages, ensure that there is sufficient
headroom and footroom for the required force voltage range.
VMID VOLTAGE
The midcode voltage (VMID) is used in the measure current
amplifier block to center the current ranges at about 0 A.
This is required to ensure that the quoted current ranges can
be achieved when using offset DAC settings other than the
default. VMID corresponds to 0x8000 or the DAC midcode
value, that is, the middle of the voltage range set by the offset
DAC setting (see Table 15 and Figure 54).
VMID = 5.125 × VREF × (32,768/216) − (5.125 × VREF ×
(OFFSET_DAC_CODE/216))
or
VMID = 5.125 × VREF × ((32,768 − Offset DAC)/216)
AD5560
Rev. C | Page 32 of 60
VMIN is another inportant voltage level that is used in other
parts of the circuit. When using a MEASOUT gain of 0.2, the
VMIN level is used to scale the voltage range; therefore, when
choosing supply rails, it is very important to ensure that there
is sufficient footroom so that the VMIN level is not impinged
on (the high voltage DAC amplifiers used here require
approximately 2 V footroom to AVSS). See the Choosing
AVDD/AVSS Power Supply Rails section for more information.
VMIN = −5.125 × VREF × (OFFSET_DAC_CODE/216)
Table 9. MEASOUT Output Ranges
Output Voltage Range1
MEASOUT Function
GAIN1 = 0, MEASOUT Gain = 1 Transfer Function
Offset DAC =
0x0 Offset DAC = 0x8000 Offset DAC = 0xE000
Measure Voltage (MV) ±VDUT 0 V to 25.62 V ±12.81 V −22.42 V to +3.2 V
GAIN0 = 0 MI gain = 20 (IDUT × RSENSE × 20) + VMID 0 V to 25.62 V ±12.81 V −22.42 V to +3.2 V
Measure
Current
(MI) GAIN0 = 1 MI gain = 10 (IDUT × RSENSE × 10) + VMID 0 V to 12.81 V
(VREF = 2.5 V)
±6.4 V
(VREF = 2.5 V)
−11.2 V to +1.6 V
(VREF = 2.5 V)
1 VREF = 5 V, unless otherwise noted.
Table 10.
MEASOUT Function
GAIN1 = 1, MEASOUT Gain = 0.2 Transfer Function Output Voltage Range1, 2
Measure Voltage (MV) MV = 0.2 × (VDUT − VMIN) 0 V to 5.12 V (±2.56 V centered around 2.56 V)
(includes overrange)
GAIN0 = 0 MI gain = 20 (IDUT × RSENSE × 20 × 0.2) + 0.5125 × VREF 0 V to 5.12 V (±2.56 V centered around 2.56 V)
(includes overrange)
GAIN0 = 1 MI gain = 10 (IDUT × RSENSE × 10 × 0.2) + 0.5125 × VREF 1.28 V to 3.84 V (±1.28 V, centered around 2.56 V)
Measure
Current
(MI)
0 V to 2.56 V (±1.28 V, centered around 1.28 V)
(VREF = 2.5 V)
1 VREF = 5 V, unless otherwise noted.
2 The offset DAC setting has no effect on the output voltage range.
Table 11. Possible ADCs and ADC Drivers for Use with AD55601
Part
No. Resolution
Sample
Rate Channels AIN Range2 Interface ADC Driver Multiplexer3 Package
AD7685 16 250 kSPS 1 0 to VREF Serial, SPI ADA4841-x ADG704, ADG708 MSOP,
LFCSP
AD7686 16 500 kSPS 1 0 to VREF Serial, SPI ADA4841-x ADG704, ADG708 MSOP,
LFCSP
AD7693 16 500 kSPS 1 −VREF to +VREF Serial, SPI ADA4841-x,
ADA4941-1
ADG1404,
ADG1408,
ADG1204
MSOP,
LFCSP
AD7610 16 250 kSPS 1
Bipolar 10 V, bipolar
5 V, unipolar 10 V,
unipolar 5 V
Serial, parallel AD8021 AD1404, ADG1408,
ADG1204
LFCSP,
LQFP
AD7655 16 1 MSPS 4 0 V to 5 V Serial, SPI ADA4841-x/
AD8021
LQFP,
LFCSP
1 Subset of the possible ADCs, ADC drivers, and multiplexers suitable for use with the AD5560. Visit http://www.analog.com for more options.
2 Do not allow the MEASOUT output range to exceed the AIN range of the ADC.
3 For the purposes of sharing ADCs among multiple DPS channels, note that the multiplexer is not absolutely necessary because the AD5560 MEASOUT path has a
tristate mode.
AD5560
Rev. C | Page 33 of 60
att
att
5R
R
1kΩ
5R
mi
mv
att
att
tri
DAC
att
1kΩ
5R
R
OS D DA C I N
MEASURE
VOLTAGE
MEASURE
CURRENT
MEASOUT
5R
NOTES
1. at t : ATTENUAT IO N FOR E XTE RNAL MEAS OUT × 0.20 F OR OUTPUT VO LT AGE RANGE 0V TO 5.125V ( WI TH O VERRANGE ) ( VREF = 5V ) .
tri: TRISTATE MODE
mv: ME ASURE V OLTAG E
mi: M E ASURE CURRE NT
mi_gain: MEASURE I GAIN SELECTION
MI_x10
MI_x20
INTERNAL
MEASI HIGH
ISENSE AM P
R10R
R10R
2R 2R
-
SENSE
DUTGND
VSENSE AMP
5R
5R
5R
5R
VREF
REFGND
VMID = (VTO P – VBOT)/2
VBOT
LOW VOLTAGE
OFFSET DAC HV DAC AMP
VMIN
VMID
VOS = ( 1 + 2/8. 25) × ( OF FSE T DAC VOLTAG E )
8.25R 8.25R
mi_gain
VTOP
INTERNAL
MEASI LOW
2R 2R
8.25R
2R
07779-009
Figure 54. MI, MV, and MEASOUT Block Showing Gain Settings and Offset DAC Influence
AD5560
Rev. C | Page 34 of 60
FORCE AMPLIFIER STABILITY
There are three modes for configuring the force amplifier: safe
mode, autocompensation mode, and manual compensation mode.
Manual compensation mode has highest priority, followed by safe
mode, then autocompensation mode.
Safe Mode
Selected through Compensation Register 1 (see Table 20), this
mode guarantees stability of the force amplifier under all
conditions. Where the load is unknown, this mode is useful but
results in a slow response. This is the power-on default of the
AD5560.
Autocompensation Mode
Using this mode, the user inputs the CR and ESR values, and
the AD5560 decides the most appropriate compensation
scheme for these load conditions. The compensation chosen
is for an optimum tradeoff between ac response and stability.
Manual Compensation Mode
This mode allows access to all of the internal programmable
parameters to configure poles/zeros, which affect the dynamic
performance of the loop. These variables are outlined in
Table 12 and Table 13.
Figure 55 shows more details of the force amplifier block.
Table 12. External Variables
Name Description Min Max
CR DUT capacitance with contributing
ESR
10 nF 160 µF
RC ESR in series with CR 1 mΩ 10 Ω
CD DUT capacitance with negligible ESR 100 pF 10 nF
RD Loading resistance at the DUT ~2 Ω Infinity
IR Current range ±5 A ±1.2 A
Table 13. Internal Variables
Name Description Min Max
RZ Resistor in series with CC0, which
contributes a zero.
500 Ω 1.6 MΩ
RP Resistor to 8 pF to contribute an
additional pole
200 Ω 1 MΩ
CC0:CC3 Capacitors to ensure unconditional
stability
100 pF 100 nF
CF0:CF4 Capacitors to optimize ac
performance into different CR, CD
4.7 nF 10 F
gmx Transconductance of force
amplifier input stage
40 A/V 900 A/
V
DUTGND
FORCE
SENSE
V
SENSE
–
–+
+×1
C
F0
4.7nF
R
Z
:
500Ω TO
1.6MΩ
C
F1
22nF
C
F2
100nF
C
F3
470nF
C
F4
2.2µF
R
SENSE
2
R
SENSE
1
AD5560
FO RCE V O L T AG E L O O P
EXTFORCE1
EXTFORCE2
100kΩ25kΩ
20Ω
200Ω
2kΩ
20kΩ
100kΩ
6kΩ
100pF 100pF 330pF 3.3nF
C
C0
C
C1
C
C2
C
C3
FORCE
DAC
g
m
R
P
:
200Ω TO 1MΩ
8pF
AGND
+
–
+
–
C
D
C
R
R
D
R
C
07779-010
Figure 55. Block Diagram of a Force Amplifier Loop
AD5560
Rev. C | Page 35 of 60
POLES AND ZEROS IN A TYPICAL SYSTEM
Typical closed loop systems have one dominant pole in the
feedback path, providing −20 dB/decade gain roll off and 90°
of phase shift so that the gain decreases to 0 dB where there
is a conservative 90° of phase margin.
The AD5560 has compensation options to help cope with the
various load conditions that a DPS is presented with.
MINIMIZING THE NUMBER OF EXTERNAL
COMPENSATION COMPONENTS
Note that, depending on the range of load conditions, not all
external capacitors are required.
CFx Pins
There are five external CFx pins. All five pins are used
in the autocompensation mode to choose a suitable capacitor,
depending on the load being driven. To reduce component
count, it is possible to connect just one capacitor, for instance,
CF2 to the CF2, CF1, and CF0 pins. Therefore, when any of the
smallest three external capacitors are selected, the same physical
capacitor is used because it is connected to all three pins. A
disadvantage here is that the larger CF2 capacitor should be
bigger than optimal and may increase settling time of the
whole circuit (particularly the measure current).
CCx Pins
To make the AD5560 stable with any unknown capacitor
from 0 pF to 160 F, all four CCx capacitors are required.
However, if the range of load is from 0 pF to 20 µF, then
CC3 can be omitted. Similarly, if the load range is from 0 pF to
2.2 µF, then CC2 and CC3 can be omitted. Only CC0 is required
in autocompensation mode.
Note that safe mode, which makes the device stable in any
load from 0 pF to 160 F, simply switches in all of the four
CCx capacitors. Stability into 160 F is assured only if all four
capacitors are present; otherwise, the maximum capacitor for
stability is reduced to 20 F, 2.2 F, or 220 nF, depending on
how many capacitors are missing.
EXTRA POLES AND ZEROS IN THE AD5560
The Effect of CCx
CC0 is switched on at all times. CC3, CC2, and CC1 can be con-
nected in addition to CC0 to slow down the force amplifier loop.
In the ±500 mA range looking into a small load capacitor, with
only CC0 connected, the ac gain vs. phase response results in
~90° of phase margin and a unity gain bandwidth (UGB) of
~400 kHz.
The Effect of CFx
The output of the AD5560 passes through a sense resistor to
the DUT. Coupled with the load capacitor, this sense resistor
can act as a low-pass filter that adds phase shift and decreases
phase margin (particularly in the low current ranges where the
sense resistors are large).
Placing a capacitor in parallel with this sense resistor provides
an ac feedforward path to the DUT. Therefore, at high frequen-
cies, the DUT is driven through the CFx capacitor rather than
through the sense resistor.
Note that each CFx output has an output impedance of about
3 . This is very small compared to the sense resistors of the
low current ranges but not so for the highest current ranges.
Therefore, the CFx capacitors are most effective in the low current
ranges but are of lesser benefit in higher current ranges.
As shown in the force amplifier diagram (see Figure 55), there
is a pole at 1/( RSENSE × [CFx + CR]) and a zero at 1/[ RSENSE × CFx].
Therefore, the output impedance of each CFx output, at around
1 , limits the improvement available by using the CFx capaci-
tors. For a large load capacitance, there is still a pole at −1/[1
× CR] above which the phase improvement is lost. If there is
also a cable resistance to the DUT, or if CFx has significant ESR,
this should be added to the 1 to calculate the pole frequency.
If CFx is chosen to be bigger than the load capacitance, it can
dominate the settling time and slow down the settling of the
whole circuit. Also, it directly affects the time taken to measure
a current (RSENSE × CFx).
The Effect of RZ
When the load capacitance is known, RZ can be used to optim-
ize the response of the AD5560. Because the CFx buffers have
some output impedance of about 1 , there is likely to be some
additional resistance to the DUT. There can still be an output
pole associated with this resistance and the load capacitance,
CR, 1/[R0 × CR] (where R0 = the series/parallel combination of
the sense resistor, the CFx output impedance, the CFx capacitor
ESR, and the cable to DUT). This is particularly significant for
larger load capacitances in any current range. By programming
a zero into the loop response by setting RZ (in series with CC0),
it is possible to cancel this pole. Above the frequency 1/[CC0 ×
RZ], the series resistance and capacitance begin to look resistive
rather than capacitive, and the 90° phase shift and 20 dB/decade
contributed by CC0 no longer apply. Note that, to cancel the
load pole with the RZ zero, the load pole must be known to
exist. Adding a zero to cancel a pole that does not exist causes
an oscillation (perhaps the expected load capacitor is not
present). Also, it is recommended to avoid creating a zero
frequency lower than the pole frequency; instead, allow the zero
frequency to be 2× or 3× higher than the calculated pole
frequency.
The Effect of RP
RP can be used to ensure circuit stability when a poor load
capacitor with significant ESR is present. Above the frequency,
1/[CR × RC], the DUT begins to look resistive. The ESR of the
DUT capacitor, RC, contributes a zero at this frequency. The
load capacitor, CR, is counted on to stabilize the system when
the user has cancelled the load pole with the RZ zero. Just as the
absence of CR under these circumstances can cause oscillations,
the presence of ESR RC while nonzero RZ is used can cause
AD5560
Rev. C | Page 36 of 60
stability problems. This is most likely to be the case when there
are both a large CR and large RC.
The RP resistor is intended to solve this problem. Again, it is
prudent not to cancel exact pole/zero cancellation with RZ and
instead allow the zero to be 2× to 3× the frequency of the pole.
It is best to be very conservative when using RZ to cancel the
load pole. Choose a high zero frequency to avoid flat spots in
the gain curve that extend bandwidth, and be conservative when
choosing RP to create a pole. Aim to place the RZ zero at 5× the
exact cancellation frequency and the RP pole at around 2× the
exact cancellation frequency. The best solution here is to avoid
this complexity by using a high quality capacitor with low ESR.
COMPENSATION STRATEGIES
Ensuring Stability into an Unknown Capacitor Up to a
Maximum Value
If the AD5560 has to be stable in a range of load capacitance
from no load capacitance to an upper limit, then select manual
compensation mode and, in Compensation Register 2, set the
parameters according to the maximum load capacitance listed
in Table 14.
Table 14. Suggested Compensation Settings for Load Capa-
citance Range of Unknown Value to Some Maximum Value
Capacitor
Min Max gm[1:0] R
P[2:0] R
Z[2:0] C
C[3:1] C
F[2:0]
0 0.22 F 2 0 0 000 2
0 2.2 F 2 0 0 001 3
0 10 F 2 0 0 010 4
0 20 F 2 0 0 011 4
0 160 F 2 0 0 111 4
Table 14 assumes that the CCx and CFx capacitor values are those
suggested in Table 8.
Making a circuit stable over a range of load capacitances for
no load capacitance or greater means that the circuit is over-
compensated for small load capacitances, undercompensated
for high load capacitances, or both. The previous choice settings,
along with the suggested capacitor values, is a compromise
between both. By compromising phase margin into the largest
load capacitors, the system bandwidth can be increased, which
means better performance under load current transient condi-
tions. The disadvantage is that there is more overshoot during a
large DAC step. To reduce this at the expense of settling time, it
may be desirable to temporarily switch a capacitor range 5× or
10× larger before making a large DAC step.
OPTIMIZING PERFORMANCE FOR A KNOWN
CAPACITOR USING AUTOCOMPENSATION MODE
The autocompensation mode decides what values of gmx, CCx
CFx, RZ, and RP should be chosen for good performance in a
particular capacitor. Both the capacitance and its ESR need to
be known. To avoid creating an oscillator, the capacitance should
not be overestimated and the ESR should not be underesti-
mated. Use the following steps to determine compensation
settings when using the manual compensation register (this
algorithm is what the autocompensation method is based upon):
1. Use CR (the load capacitance with a series ESR) and RC (the
ESR of that load capacitance) as inputs.
2. Assume that CR has not been overestimated and that RC has
not been underestimated. (Although, when the ESR RC is
shown to have a frequency dependence, the lowest RC that
occurs near the resonant frequency is probably a better
guide. However, do not underestimate this ESR).
a. CC0 is the suggested 100 pF.
b. CFx capacitor values are as suggested, and they extend
up to 2.2 µF (CF4). For faster settling into small
capacitive loads, include smaller CFx values such as CF3
and CF2. If a capacitor is not included, then short the
corresponding CFx pin to one that is.
c. There is approximately 1 of parasitic resistance, RC,
from the AD5560 to the DUT (for example, the cable);
RC = 1 .
3. Select gm[1:0] = 2, CC[3:1] = 000. This makes the input stage of
the force amplifier; have gmx = 300 µA/V; deselect the
compensation capacitors, CC1, CC2, CC3, so that only CC0 is
active.
4. Choose a CF[2:0] value from 0 to 4 to select the largest CFx
capacitor that is smaller than CR.
5. If CR < 100 nF, then set RZ[2:0] = 0, RP[2:0] = 0. This ends the
algorithm.
6. Calculate R0, the resistive impedance to the DUT, using the
following steps:
a. Calculate RS, the sense resistor, from the selected
current range using RS = 0.5 V/IRANGE.
b. Calculate RF, the output impedance, through the CFx
capacitor, by using
RF = 1.2 + (ESR of CFx capacitor)
c. Calculate RFM, a modified version of RF, which takes
account of frequency dependent peaking, through the
CFx buffers into a large capacitive load, by using
RFM = RF/(1 + [2 × (CFx/2.2 F)])
That is, RFM is up to 3× smaller than RF, when the
selected CFx capacitor is large compared to 2.2 F.
Then calculate
R0 = RC + (RS ||RFM)
where RC takes its value from the assumptions in Step 2.
7. If RC > (R0/5), then the ESR is large enough to make the
DUT look resistive. Choose RZ[2:0] = 0, RP[2:0] = 0. This ends
the algorithm
8. Calculate the unity gain frequency (Fug), the ideal unity
gain frequency of the force amplifier, from Fug =
gmx/2πCC0. Using the previously suggested values (gm[1:0] = 2
gives gmx = 300 µA/V and CC0 = 100 pF), Fug calculates to
480 kHz.
9. Calculate FP, the load pole frequency, using FP =
1/(2πR0CC0).
AD5560
Rev. C | Page 37 of 60
10. Calculate FZ, the ESR zero frequency, using FZ =
1/(2πRcCr).
11. If FP > Fug, the load pole is above the bandwidth of the
AD5560. Ignore it with RZ[2:0] = 0, RP[2:0] = 0. This ends the
algorithm
12. If RC < (R0/25), then the ESR is negligible. Attempt to
cancel the load pole with RZ zero. Choose an ideal zero
frequency of 2 × FP for some safety margin and then
choose the RZ[2:0] value that gives the closest frequency on a
logarithmic scale. This ends the algorithm
13. Otherwise, this is a troublesome window in which a load
pole and a load zero can’t be ignored. Use the following
steps:
• To cancel the load pole at FP, choose an ideal zero
frequency of 6 × FP (this is more conservative than the
2 × FP suggested earlier, but there is more that can go
wrong with miscalculation). Then choose the RZ[2:0]
value that gives the closest zero to this ideal frequency
of 6 × FP on a logarithmic scale.
• To cancel the ESR zero at FZ, choose an ideal pole
frequency of 2 × FZ.
• Then choose the RP[2:0] value that gives the closest pole
to this ideal frequency of 2 × FZ on a logarithmic scale.
This ends the algorithm
ADJUSTING THE AUTOCOMPENSATION MODE
The autocompensation algorithm assumes that there is 1 of
resistance (RC) from the AD5560 to the DUT. If a particular
application has resistance that differs greatly from this, then
it is likely that the autocompensation algorithm is nonoptimal.
If using the autocompensation algorithm as a starting point,
consider that overstating the CR capacitance and understating
the ESR RC is likely to give a faster response but could cause
oscillations. Understating CR and overstating RC is more likely
to slow things down and reduce phase margin but not create
an oscillator.
It is often advisable to err on the side of simplicity. Rather than
insert a pole and zero at similar frequencies, it may be better to
add none at all. Set RP[2:0] = RZ[2:0] = 0 to push them beyond the
AD5560 bandwidth.
DEALING WITH PARALLEL LOAD CAPACITORS
In the event that the load capacitance consists of two parallel
capacitors with different ESRs, it is highly likely that the overall
complex impedance at the unity gain bandwidth is dominated
by the larger capacitor and its ESR. Assuming that the smaller
capacitor does not exist normally is a safer simplifying assump-
tion.
A more complex alternative is to calculate the overall impedance
at the expected unity gain bandwidth and use this to calculate
an equivalent series CR and RC that have the same complex
impedance at that particular frequency.
DAC LEVELS
This device contains all the dedicated DAC levels necessary
for operation: a 16-bit DAC for the force amplifier, two 16-bit
DACs for the clamp high and low levels, two 16-bit DACs for
the comparator high and low levels, a 16-bit DAC to set a
programmable open sense voltage, and a 16-bit offset DAC
to bias or offset a number of DACs on chip (FORCE, CLL,
CLH, CPL, CPH).
FORCE AND COMPARATOR DACS
The architecture of the main force amplifier DAC consists of
a 16-bit R-2R DAC, whereas the comparator DACs are resistor-
string DACs followed by an output buffer amplifier. This
resistor-string architecture guarantees DAC monotonicity.
The 16-bit binary digital code loaded to the DAC register
determines at what node on the string the voltage is tapped
off before being fed to the output amplifier.
The comparator DAC is similarly arranged. The force and
comparator DACs have a 25.62 V span, including overrange
to enable offset and gain errors to be calibrated out.
The transfer function for these 16-bit DACs is
DUTGND
CODEDACOFFSET
VREF
CODEDAC
VREFVOUT
+
⎟
⎠
⎞
⎜
⎝
⎛
××−
⎟
⎠
⎞
⎜
⎝
⎛
××=
16
16
2__
125.5
2
125.5
where DAC CODE is X2 (see the Offset and Gain Registers
section).
CLAMP DACS
The architecture of the clamp DAC consists of a 16-bit resistor-
string DAC followed by an output buffer amplifier. This resistor-
string architecture guarantees DAC monotonicity. The 16-bit
binary digital code loaded to the DAC register determines at
what node on the string the voltage is tapped off before being
fed to the output amplifier.
The clamp DACs have a 25.62 V span, including overrange, to
enable offset and gain errors to be calibrated out.
AD5560
Rev. C | Page 38 of 60
The transfer function for these 16-bit DACs is
DUTGND
CODEDACOFFSET
V
CODEDAC
VVCLLVCLH REFREF
+
⎟
⎠
⎞
⎜
⎝
⎛
××−
⎟
⎟
⎠
⎞
⎜
⎜
⎝
⎛
××=
16
16
2
__
125.5
2
125.5,
The transfer function for the clamp current value is
GAINAMPMIR
CODEDAC
V
ICLHICLL
SENSE
REF
__
2
32768
125.5
,
16
×
⎟
⎟
⎠
⎞
⎜
⎜
⎝
⎛−
××
=
where:
RSENSE is the sense resistor.
MI_AMP_GAIN is the gain of the MI amp (either 10 or 20).
OSD DAC
The OSD DAC is a 16-bit DAC function, again a resistor string
DAC guaranteeing monotonicity. The 16-bit binary digital
code loaded to the DAC register determines at what node on
the string the voltage is tapped off before being fed to the
output amplifier. The OSD function is used to program the
voltage difference needed between the force and sense lines
before the alarm circuit flags an error. The OSD DAC has a
range of 0.62 V to 5 V. The transfer function is as follows:
⎟
⎠
⎞
⎜
⎝
⎛
×= 16
2CODEDAC
VREFVOUT (1)
The offset DAC does not affect the OSD DAC output range.
DUTGND DAC
Similarly, the DUTGND DAC (DGS) is a 16-bit DAC and uses
a resistor string DAC to guarantee monotonicity. The 16-bit
binary digital code loaded to the DAC register determines at
what node on the string the voltage is tapped off before being
fed to the output amplifier. This function is used to program
the voltage difference needed between the DUTGND and
AGND lines before the alarm circuit flags an error.
The DUTGND DAC has a range of 0 V to 5 V. The transfer
function for this 16-bit DAC is shown in Equation 1.
The offset DAC does not affect the OSD DAC output range.
OFFSET DAC
In addition to the offset and gain trim, there is also a 16-bit
offset DAC that offsets the output of each DAC on chip. There-
fore, depending on headroom available, the input to the force
amplifier can be arranged either symmetrically or asymmetrically
about DUTGND but always within a voltage span of 25 V. Some
extra gain is included to allow for system error correction using
the m (gain) and c (offset) registers.
The usable voltage range is −22 V to +25 V. Full scale loaded
to the offset DAC does not give a useful output voltage range
because the output amplifiers are limited by available footroom.
Table 15 shows the effect of the offset DAC on other DACs in
the device (clamp, comparator, and force DACs).
Table 15. Offset DAC Relationship with Other DACs, VREF = 5 V
Offset DAC Code DAC Code1 DAC Output Voltage Range
0 0 0.00
0 32,768 12.81
0 65,535
25.62
… …
…
32,768 0
−12.81
32,768 32,768
0.00
32,768 65,535
12.81
… …
…
57,344 0
−22.42
57,344 32,768
−9.61
57,344 65,535
3.20
… …
…
65,355 … Footroom limitations
1 DAC code shown for 16-bit force DAC.
OFFSET AND GAIN REGISTERS
Each DAC level contains independent offset and gain control
registers that allow the user to digitally trim offset and gain.
These registers give the user the ability to calibrate out errors
in the complete signal chain (including the DAC) using the
internal m and c registers, which hold the correction factors.
The digital input transfer function for the DACs can be
represented as
x2 = [x1 × (m + 1)/2n] + (c – 2n – 1)
where:
x2 is the data-word loaded to the resistor string DAC.
x1 is the 16-bit data-word written to the DAC input register.
m is the code in the gain register (default code = 216 – 1).
n is the DAC resolution (n = 16).
c is the code in the offset register (default code = 215).
Offset and Gain Registers for the Force Amplifier DAC
The force amplifier input (FIN) DAC level contains independent
offset and gain control registers that allow the user to digitally
trim offset and gain. There is one set of registers for the force
voltage range: x1, m, and c.
Offset and Gain Registers for the Comparator DACs
The comparator DAC levels contain independent offset and
gain control registers that allow the user to digitally trim offset
and gain. There are seven sets of registers consisting of a combi-
nation of x1, m, and c, one set each for the five internal force
current ranges and one set each for the two external high
current ranges.
Offset and Gain Registers for the Clamp DACs
The clamp DAC levels contain independent offset and gain
control registers that allow the user to digitally trim offset
and gain. One set of registers covers the VSENSE range, the five
internal force current ranges, and the two external high current
ranges. Both clamp DAC x1 registers and their associated offset
and gain registers are 16 bit.
AD5560
Rev. C | Page 39 of 60
REFERENCE SELECTION
The voltage applied to the VREF pin determines the output
voltage range and span applied to the force amplifier, clamp,
and comparator inputs and the current ranges.
This device can be used with a reference input ranging from
2 V to 5 V. However, for most applications, a reference input
of 5 V is able to meet all voltage range requirements. The DAC
amplifier gain is 5.125, which gives a DAC output span of
25.625 V. The DACs have gain and offset registers that can
be used to calibrate out system errors. In addition, the gain
register can be used to reduce the DAC output range to the
desired force voltage range.
Using a 5 V reference and setting the m (gain) register to one-
fourth scale or 0x4000 gives an output voltage span of 6.25 V.
Because the force DAC has 18 bits of resolution even with only
one-fourth of the output voltage span, it is still possible to
achieve 16-bit resolution in this 6.25 V range.
The measure current amplifier has two gain settings, 10 and 20.
The two gain settings allow users to achieve the quoted/speci-
fied current ranges with large or small voltage swings. The 20
gain setting is intended for use with a 5 V reference, and the 10
gain setting is for use with a 2.5 V reference. Both combinations
ensure the specified current ranges. Other VREF/gain setting
combinations should be used only to achieve smaller current
ranges. See Table 27 for suggested references for use with the
AD5560.
CHOOSING AVDD/AVSS POWER SUPPLY RAILS
As noted in the Specifications section, the minimum supply
variation across the part is |AVDD − AVSS| ≥ 16 V and ≤ 33 V,
AVDD ≥ 8 V, and AVSS ≤ −5 V. For the AD5560 circuits to
operate correctly, the supply rails must take into account not
only the force voltage range but also the internal DAC
minimum voltage level, as well as headroom/footroom.
The DAC amplifier gains VREF by 5.125, and the offset DAC
centers that range about some chosen point. Because the DAC
minimum voltage (VMIN) is used in other parts of the circuit
(MEASOUT gain of 0.2), it is important that AVSS be chosen
based on the following:
AVSS ≤ −5.125 × (VREF × (OFFSET_DAC_CODE/216)) −
AVSS_Headroom − VDUTGND − (RCABLE × ILOAD)
where:
AVSS_Headroom is the 2.75 V headroom (includes the RSENSE
voltage drop).
VDUTGND is the voltage range anticipated at DUTGND.
RCABLE is the cable/path resistance.
ILOAD is the maximum load current.
When choosing AVDD, remember to take into account the
specified current ranges. The measure current block has either
a gain of 20 or 10 and must have sufficient headroom/
footroom to operate correctly.
As the nominal, VRSENSE is ±0.5 V for the full-scale specified
current flowing for all ranges. If this is gained by 20, the
measure current amplifier output (internal node) voltage
range is ±10 V with full-scale current and the default offset
DAC setting. The measure current block needs ±2.25 V
footroom/headroom for correct operation in addition to
the ±0.5 V VRSENSE.
For simplicity, when VREF = 5 V, minimum |AVDD − AVSS| =
31.125 V (VREF × 5.125 + headroom + footroom); otherwise,
there can be unanticipated effects resulting from headroom/
footroom issues. This does not take into account cable loss or
DUTGND contributions.
Similarly, when VREF = 2.5 V, minimum |AVDD − AVSS| = 18.3 V
and, when VREF = 2 V, minimum |AVDD − AVSS| = 16 V.
The AD5560 is designed to settle fast into large capacitive loads;
therefore, when slewing, the device draws 2× to 3× the current
range from the AVDD/AVSS supplies. When supply rails are
chosen, they should be capable of supplying each DPS channel
with sufficient current to slew.
CHOOSING HCAVSSx AND HCAVDDx SUPPLY RAILS
Selection of HCAVSSx and HCAVDDx supplies is determined by
the EXTFORCE1 and EXTFORCE2 output ranges. The supply
rails chosen must take into account headroom and footroom,
DUTGND voltage range, cable loss, supply tolerance, and
VRSENSE. If diodes are used in series with the HCAVSSx and
HCAVDDx supplies pins (shown in Figure 57), the diode voltage
drop should also be factored into the supply rail calculation.
The AD5560 is designed to settle fast into large capacitive loads
in high current ranges; therefore, when slewing, the device draws
2× to 3× the current range from the HCAVSSx and HCAVDDx
supplies. When choosing supply rails, ensure that they are
capable of supplying each DPS channel with sufficient current
to slew.
All output stages of the AD5560 are symmetrical; they can
source and sink the rated current. Supply design/bypassing
should account for this.
POWER DISSIPATION
The maximum power dissipation allowed in the EXTFORCE1
stage is 10 W, whereas in the EXTFORCE2 stage, it is 5 W.
Take care to ensure that the device is adequately cooled to
remove the heat. The quiescent current is ~0.8 W with an
internal current range enabled and ~1 W with external current
ranges, EXTFORCE1 or EXTFORCE2, enabled. This device is
specified for performance up to 90°C junction temperature (TJ).
AD5560
Rev. C | Page 40 of 60
PACKAGE COMPOSITION AND MAXIMUM
VERTICAL FORCE
The exposed pad and leads of the TQFP package have a 100%
tin finish. The exposed paddle is connected internally to AVSS.
The simulated maximum allowable force for a single lead is
0.18 lbs; total allowable force for the package is 11.5 lbs. The
quoted maximum force may cause permanent lead bending.
Other package failure (die, mold, board) may occur first at
lower forces.
SLEW RATE CONTROL
There are two methods of achieving different slew rates using
the AD5560. One method is using the programmable slew rate
feature that gives eight programmable rates. The second
method is using the ramp feature and an external clock.
Programmable Slew Rate
Eight programmable modes of slew rates are available to choose
from through the serial interface, enabling the user to choose
different rates to power up the DUT. The different slew rates
are achieved by variation in the internal compensation of the
force DAC output amplifier. The slew rates available are
1.000 V/µs, 0.875 V/µs, 0.750 V/µs, 0.625 V/µs, 0.5 V/µs,
0.4375 V/µs, 0.35V µs, and 0.313 V/µs.
Ramp Function
Included in the AD5560 is a ramp function that enables the
user to apply a rising or falling voltage ramp to the DUT. The
user supplies a clock, RCLK, to control the timing.
This function is controlled via the serial interface and requires
programming of a number of registers to determine the end
value, the ramp size, and the clock divider register to determine
the update rate.
The contents of the FIN DAC x1 register are the ramp start
value. The user must load the end code register and the step
size register. The sign is now generated from the difference
between the FIN DAC x1 register and the end code; then the
step size value is added to or subtracted from FIN DAC x1,
calibrated and stored. The user must supply a clock to the RCLK
pin to load the new code to the DAC. The output settles in 1.2 µs
for a step of 10 mV with CDUT in the lowest range of <0.2 µF.
While the output is settling, the next step is calculated to be
ready for the next ramp clock. The calibration engine is used
here; therefore, there is a calibration delay of 1.2 µs.
The ramp timing is controlled in two ways: by a user-supplied
clock (RCLK) and by a clock divider register. This gives the
user much flexibility over the frequency of the ramp steps. The
ramp typically starts after (2 × clock divider + 2) clocks,
although there can be a ±1 clock delay due to the asynchronous
nature of RCLK. The external clock can be a maximum of 833
kHz when using clock divider = 1. Faster RCLK speeds can be
used, but the fastest ramp rate is linked into the DAC
calibration engine.
For slower ramp rates, an even slower RCLK can be used.
The step sizes are in multiples of 16 LSBs. If the code previous
to the end code is not a multiple of this step size, the last step is
smaller. If the ramp function must be interrupted at any stage
during the ramp, write the interrupt ramp command. The FIN
DAC x1 stops ramping at the current value and returns to
normal operation.
The fastest ramp rate is 0.775 V/µs (for a 5 V reference and an
833 kHz clock using a 2032 LSB step size and divider = 1).
The slowest ramp rate is 24 µV/µs (for a 5 V reference and an
833 kHz clock using a 16 LSB step size and divider = 255).
Even slower ramps can be achieved with slower SCLK. The
ramp continues until any of the following occurs:
• It reaches the end code.
• An interrupt ramp is received from the user.
• If any enabled alarm triggers, the ramp stops to allow
the user to service the activated alarm.
While the device is in ramp mode, the only command that the
interface accepts is an interrupt ramp. No other commands should
be written to the device while ramping because they are ignored.
AD5560
Rev. C | Page 41 of 60
NO
WRITE NEW
FIN ×1 DAC VAL UE
UPDATE DAC
CODE?
NO
YES
NO
CHANG E RA MP
START?
NEW RAM P
YES
CHANGE
STEP SI ZE?
SEL E CT RAMP S IZE
PROGRAM
CLO CK DIVI DER
CHANGE
CLOCK
DIVISION?
YES
NO
YES
NO
YES
YES
NO
WRI TE RAMP E ND CODE
RAMP M ODE ENABL E RAM P
CALCULATE
NEXT DAC CODE
LOAD DAC
DO NO T LOAD DAC.
RETAIN PREVIOUS
VALUE
TE R M I N ATE RA M P
RAMP
COMPLETE?
INTERRUPT
RAMP?
ALARM?
RETURN TO
NORMAL MO DE
07779-011
Figure 56. Flow Chart for Ramp Function
AD5560
Rev. C | Page 42 of 60
SERIAL INTERFACE
The AD5560 contains an SPI-compatible interface operating at
clock frequencies of up to 50 MHz. To minimize both the
power consumption of the device and on-chip digital noise, the
interface powers up fully only when the device is being written
to, that is, on the falling edge of SYNC.
SPI INTERFACE
The serial interface is 2.5 V LVTTL-compatible when operating
from a 2.3 V to 3.6 V DVCC supply. It is controlled by the
following four pins:
• SYNC (frame synchronization input)
• SDI (serial data input pin)
• SCLK (clocks data in and out of the device)
• SDO (serial data output pin for data readback)
SPI WRITE MODE
The AD5560 allows writing of data via the serial interface to
every register directly accessible to the serial interface, which
is all registers except the DAC registers.
The serial word is 24 bits long. The serial interface works with
both a continuous and a burst (gated) serial clock. Serial data
applied to SDI is clocked into the AD5560 by clock pulses applied
to SCLK. The first falling edge of SYNC starts the write cycle.
At least 24 falling clock edges must be applied to SCLK to clock
in 24 bits of data before SYNC is taken high again.
The input register addressed is updated on the rising edge of
SYNC. For another serial transfer to take place, SYNC must be
taken low again.
SDO OUTPUT
The SDO output in the AD5560 is a weak/slow output driver.
If using readback or the daisy-chain function, the frequency of
SCLK must be reduced so that SDO can operate properly. The
SCLK frequency is dependent on the DVCC supply voltage used;
see Table 2 for details and the following example:
Maximum SCLK = 12 MHz, then DVCC = 2.3 V to 2.7 V
Maximum SCLK = 15 MHz, then DVCC = 2.7 V to 3.3 V
Maximum SCLK = 20 MHz, then DVCC = 4.5 V to 5.5 V
RESET FUNCTION
RESET is a level-sensitive input. Bringing the RESET line low
resets the contents of all internal registers to their power-on
reset state. The falling edge of RESET initiates the reset process;
BUSY goes low for the duration, returning high when the
RESET process is complete. This sequence takes 300 µs
maximum. Do not write to the serial interface while BUSY
is low handling a RESET command. When BUSY returns high,
normal operation resumes, and the status of the RESET pin is
ignored until it goes low again.
BUSY FUNCTION
BUSY is a digital open-drain output that indicates the status of
the AD5560. All writes drive the BUSY output low for some
period of time; however, events that use the calibration engine,
such as all DAC x1 writes, drive it lower for a longer period of
time while the calculations are completed.
For the DACs, the value of the internal data (x2) loaded to the
DAC data register is calculated each time the user writes new
data to the corresponding x1 register. During the calculation
of x2, the BUSY output goes low and x2 writes are pipelined;
therefore, x2 writes can still be presented to the device while
BUSY is still low (see the section). The
DAC outputs update immediately after
Register Update Rates
BUSY goes high.
Writes to other registers must be handled differently and
should either watch the BUSY pin or be timed. While BUSY
is low, the user can continue writing new data to any control
register, m register, or c register but should not complete the
writing process (SYNC returning high) until the BUSY signal
has returned high.
BUSY also goes low during power-on reset, as well as when a
low level is detected on the RESET pin.
BUSY writes to the system control register, compensation
register, alarm register, and diagnostic register; m or c registers
do not involve the calibration engine, thus speeding up writing
to the device.
LOAD FUNCTION
The AD5560 device contains a function with which updates
to multiple devices can be synchronized using the LOAD
function. There is not a dedicated pin available for this
function; however, either the CLEN or HW_INH pin can
be used as a LOAD input (selection is made in the system
control register, Address 0x1, Bits[8:7]).
When selected as the LOAD function, the pin no longer
operates in its previous function (power-on default for each
of these pins is a CLEN or HW_INH function).
The LOAD function controls the following registers:
• 0x8 FIN DAC x2 register
• 0xD CLL DAC x2 register
• 0x10 CLH DAC x2 register
• 0x4 Compensation Register 1
• 0x5 Compensation Register2
• 0x2 DPS Register1 (only current ranges, Bits[13:11])
There is, however, an alternate method for updating and using
the CLEN and HW_INH pins in their normal function.
AD5560
Rev. C | Page 43 of 60
If Bits[8:7] of the system control register (Address 0x1) are
high, then the CLEN and HW_INH operate as normal, and the
update waits until BUSY goes high (this way multiple channels
can still be synchronized by simply tying BUSY pins together).
REGISTER UPDATE RATES
As mentioned previously, the value of the x2 register is
calculated each time the user writes new data to the
corresponding x1 register. The calculation is performed by a
three stage process. The first two stages take 600 ns each, and
the third stage takes 300 ns. When the write to one of the x1
registers is complete, the calculation process begins. The user
is free to write to another register provided that the write
operation does not finish until the first stage calculation is
complete, that is, 600 ns after the completion of the first write
operation.
AD5560
Rev. C | Page 44 of 60
CONTROL REGISTERS
DPS AND DAC ADDRESSING
The serial word assignment consists of 24 bits, as shown in
Table 16. All write-to registers can be read back. There are
some read-only registers (Address 0x43 and Address 0x44).
DAC x2 registers are not available for readback.
A no operation (NOP) command performs no function within
the device. This code may be useful when performing a
readback function where a change of DAC or DPS register is
not required.
Table 16. Serial Word Assignment
B23 [B22:B16] [B15:B0]
R/W Address bits Data bits
Table 17. Read or Write Register Addressing
Address Register Default Data Bits, MSB First
0x0 NOP 0x0000 NOP command; performs no operation.
Bit Name Function
Thermal shutdown bits. TMP1, TMP0 allow the user to program the thermal
shutdown temperature of operation.
TMP Action
0 Shutdown at a TJ of 130°C (power-on default)
1 Shutdown at a TJ of 120°C
2 Shutdown at a TJ of 110°C
0x1 System
control
register
0x0000
15
14
TMP[1:0]
3 Shutdown at a TJ of 100°C
MEASOUT output range. The MEASOUT range defaults to the voltage force span for
voltage and current measurements (this is ±12.81 V), which includes some overrange
to allow for error correction. The MEASOUT range can be reduced by using the gain
bits. This allows for use of asymmetrical supplies or for use of a smaller input range ADC.
MEASOUT gain settings do not translate the low voltage temperature sensor signal
(TSENSE).
Gain MEASOUT Gain MI Gain
0 1 20
1 1 10
2 0.2 20
3 0.2 10
13
12
Gain[1:0]
To allow for system error correction, there is an additional gain of 0.125 for the force
function if this error correction is used as intended; then the output range on
MEASOUT scales accordingly (see Table 9).
11 FINGND
Writing a 1 to FINGND switches the positive input of the force amplifier to GND; when
0, the input of the force amplifier is connected to the output of the force DAC.
10 CPO
Write a 1 to the CPO bit to enable a simple window comparator function. In this
mode, only one comparator output is available (CPOH/CPO). This provides two bits of
information. The compared value is either inside or outside the window and enables
the user to bring only one line back to the controller per DPS device.
9
PD This bit powers down the force amplifier block. Note that the amplifier must be
powered up but inhibited (SW-INH or HW_INH), to meet leakage specifications. A 0
powers this block down (default).
Updates to registers listed in the following LOAD function column do not occur until
the active LOAD pin is brought low (or in the case of LOAD 3, until BUSY goes high).
LOAD LOAD Function
0 Default operation, CLEN and HW_INH function normally.
1 The CLEN pin is a LOAD input.
2 The HW_INH pin is a LOAD input.
8
7
LOAD
3 The device senses the BUSY open-drain pin and doesn't update until that
goes high. No LOAD hardware pin. CLEN and HW_INH function normally.
6:0 Unused Set to 0.
AD5560
Rev. C | Page 45 of 60
Table 18. DPS Register 1
Address Default Data Bits, MSB First
0x2 0x0000
Bit Name Function
15
SW-INH This bit enables the force amplifier when high and disables the amplifier when low. This bit is AND’d with the
HW_INH hardware inhibit pin.
14 Reserved Reserved, set to 0.
13 I[2:0] Current range addressing. These bits allow selection of the required current range.
12
I Action
0 ±5 µA current range.
1 ±25 µA current range.
2 ±250 µA current range.
3 ±2.5 mA current range.
4 ±25 mA current range.
5 External Range 2.
6 External Range 1.
11
7 Reserved.
10 CMP[1:0] Comparator function. CMP1 acts as a comparator output enable, whereas CMP0 selects between a
comparing DUT current or voltage; by default, the comparators are high-Z on power-on.
CMP Action
0 Comparator outputs high-Z.
1 Comparator outputs high-Z.
2 Compare DUT current.
9
3 Compare DUT voltage.
8
7
6
Bits ME[3:0] allow selection of the required measure mode, allowing the MEASOUT line to be disabled;
connect to the temperature sensor or enable it for measurement. ME3 is MEASOUT enable/disable; when
high, MEASOUT is enabled, and ME[2:0] can be used to preselect the measuring parameter. Where a
number of MEASOUT lines are connected together and passed to a common ADC, this function can allow
for much faster measurement time between channels because the slew time of the measurement buffer is
reduced. For details on diagnostic functions, see Address 0x7, the diagnostic register.
ME[2:0] Action
0 MEASOUT high-Z.
1 Connect MEASOUT to ISENSE.
2 Connect MEASOUT to VSENSE.
3 Connect MEASOUT to KSENSE.
4 Connect MEASOUT to TSENSE.
5 Connect MEASOUT to DUTGND SENSE.
6 Connect MEASOUT to diagnostic functions: DIAG A (see Address 0x7).
5
ME[3:0]
7 Connect MEASOUT to diagnostic functions: DIAG B (see Address 0x7).
4 CLEN Clamp enable; set high to enable the clamp; set low to disable the clamp. This bit is OR’d with the
hardware CLEN pin.
3:0 Unused Set to 0.
AD5560
Rev. C | Page 46 of 60
Table 19. DPS Register 2
Address Default Data Bits, MSB First
Bit Name Function
System force and sense line addressing, SF0. Bit SF0 addresses each of the different
combinations of switching the system force and sense lines to the force and sense pins at the
DUT.
Guard High-Z
(Bit 7) SFO SYS_SENSE Pin SYS_FORCE Pin GUARD/SYS_DUTGND Pin
0 0 Open Open Guard
0 1 Sense Force Guard
1 0 Open Open Open
0x3 0x0000
15 SF0
1 1 Sense Force DUTGND
Slew rate control, SR2, SR1, SR0. Selects the slew rate for the main DAC output amp.
SR Action
0 1 V/s
1 0.875 V/s
2 0.75 V/s
3 0.62 V/s
4 0.5 V/s
5 0.43 V/s
6 0.35 V/s
14
13
12
SR[2:0]
7 0.3125 V/s
11 GPO General purpose output bit. The GPO bit can be used for any function, such as disconnecting
the decoupling capacitor to help speed up low current testing.
Ganging multiple devices increases the current drive available. Use these bits to enable
selection of the ganging mode and place the device in slave or master mode. In default
operation, each device is a master (gang of one). Figure shows how the device is configured
in this mode.
SLAVE Action
0 Master: MASTER_OUT = internally connects to active EXTFORCE1/
EXTFORCE2 output
1 Master: MASTER_OUT = master MI
2 SLAVE FV to EXTFORCE1/EXTFORCE2 connected internally to close the
FVAMP loop
10
9
SLAVE,
GANGIMODE
3 SLAVE FI
8 INT10K
Setting this bit high allows the user to connect an internal sense short resistor of 10 kΩ
between the force and the sense lines (closes SW11). This resistor is actually made up of series
4 kΩ resistors followed by a 2 kΩ switch and another 4 kΩ resistor. There is a 10 kΩ resistor that
can be connected between the FORCE and SENSE pins by use of SW11. This 10 kΩ resistor is
intended to maintain a force/sense connection when a DUT is not in place. It is not intended
to be connected when measurements are being made because this defeats the purpose of the
OSD circuit in identifying an open circuit between FORCE and SENSE. In addition, the sense
path has a 2.5 kΩ resistor in series; therefore, if the 10 kΩ switch is closed, errors may become
apparent when in high current ranges.
7 Guard high-Z
Set this bit high to high-Z the guard amplifier. This is required if using the GUARD/
SYS_DUTGND pin in the SYS_DUTGND function.
6:0 Unused Set to 0.
AD5560
Rev. C | Page 47 of 60
The AD5560 has three compensation modes. The power-on default mode is SAFEMODE enabled. This ensures that the device is stable
into any load. Use Compensation Register 1 to configure the device for autocompensation, where the user inputs the CDUT and ESR
bits, and the AD5560 chooses the most appropriate compensation scheme for these load conditions.
Table 20. Compensation Register 1
Address Default Data Bits, MSB First
0x4 0x0000
Bit Name Function
Use these control bits to tell the device how much capacitive load there is so that the device can
optimize the compensation used. Do not overestimate CDUT because this can cause oscillations.
Underestimating CDUT gives suboptimal but stable performance.
CDUT CDUT Min CDUT Max
0 0 nF 50 nF
1 50 nF 83 nF
2 83 nF 138 nF
3 138 nF 229 nF
4 229 nF 380 nF
5 380 nF 630 nF
6 630 nF 1.1 µF
7 1.1 µF 1.7 µF
8 1.7 µF 2.9 µF
9 2.9 µF 4.8 µF
10 4.8 µF 7.9 µF
11 7.9 µF 13 µF
12 13 µF 22 µF
13 22 µF 36 µF
14 36 µF 60 µF
15
14
13
12
CDUT[3:0]
15 60 µF 160 µF
Use these control bits to tell the device how much ESR there is in series with CDUT so that the device can
optimize the compensation used. Do not underestimate ESR because this can cause oscillations.
Overestimating ESR gives suboptimal but stable performance.
ESR ESR Min ESR Max
0 0 mΩ 1 mΩ
1 1 mΩ 1.8 mΩ
2 1.8 mΩ 3.4 mΩ
3 3.4 mΩ 6.3 mΩ
4 6.3 mΩ 12 mΩ
5 12 mΩ 21 mΩ
6 21 mΩ 40 mΩ
7 40 mΩ 74 mΩ
8 74 mΩ 140 mΩ
9 140 mΩ 250 mΩ
10 250 mΩ 460 mΩ
11 460 mΩ 860 mΩ
12 860 mΩ 1500 mΩ
13 1500 mΩ 2900 mΩ
14 2900 mΩ 5400 mΩ
11
10
9
8
ESR[3:0]
15 6400 mΩ 10,000 mΩ
7
SAFEMODE SAFEMODE = 0 overrides values in Compensation Register 1 to make the force amplifier stable under
most load conditions. This mode is useful if it is unknown what the DPS is driving, but it does result in an
extremely slow response. The default operation on power-on or reset is SAFEMODE.
SAFEMODE settings are always gm[1:0] = 2, RP[2:0] = 0, RZ[2:0] = 0, CC[3:1] = 111, CF[2:0] = 5, and CC0 = 1.
Set this bit high to enable autocompensation.
6:0 Reserved Set to 0.
AD5560
Rev. C | Page 48 of 60
Table 21. Compensation Register 2
Address Default Data Bits, MSB First
0x5 0x0110 Bit Name Function
15 Manual
compensation
The AD5560 can be manually configured to compensate the force amplifier into a wide range of load
conditions. When this bit is high, manual compensation mode is active, and it overrides the settings of
Compensation Register 1. Readback when in manual compensation mode returns the compensation
settings loaded to the force amplifier and loaded to this register. Similarly, when in autocompensation
mode, readback of this register address returns the compensation settings of the force amplifier. However,
readback of this register address when in safe mode does not reflect SAFEMODE settings. SAFEMODE
settings are gm[1:0] = 2, RP[2:0] = 0, RZ[2:0] = 0, CC[3:1] = 111, CF[2:0] = 5, and CC0 = 1.
Set the value of RZ to add a zero at the following frequencies. This calculation assumes that CC0 = 100 pF.
RZ R
Zx(Ω) FZ (Hz)
01 500 3.2 M
1 1.6 k 1 M
2 5 k 320 k
3 16 k 100 k
4 50 k 32 k
5 160 k 10 k
6 500 k 3.2 k
14
13
12
RZ[2:0]
7 1.6 M 1 k
Set the value of RP to add an additional pole. There is an internal 8 pF capacitor to provide an RC filter,
creating a pole at one of the following frequencies.
RP[2:0] R
P (Ω) FP (Hz)
01 200 100 M
1 675 29 M
2 2280 8.7 M
3 7700 2.6 M
4 26 k 760 k
5 88 k 220 k
6 296 k 67 k
11
10
9
RP[2:0]
7 1 M 20 k
Set the transconductance of the force amplifiers input stage. The gain bandwidth (GBW) of the force
voltage loop is equal to gmx/CC0. The following values assume CC0 = 100 pF.
gmx g
mx (µA/V) GBW (Hz)
0 40 64 k
1 80 130 k
21 300 480 k (default)
8
7
gm[1:0]
3 900 1.3 M
These bits determine which feedforward capacitor CFx is switched in.
CFx Action
0 None
1 CF0
2 CF1
3 CF2
4 CF3
51 CF4
6 None
6
5
4
CF[2:0]
7 None
3 CC3 Connect CC3 in series with 100 kΩ1
2 CC2 Connect CC2 in series with 25 kΩ1
1 CC1 Connect CC1 in series with 6 kΩ1
0 Reserved 0
1 This item corresponds to a SAFEMODE setting (SAFEMODE is the power-on default setting).
AD5560
Rev. C | Page 49 of 60
Register 0x6 allows the user to enable or disable any of the alarm flags that are not required. If disabled, that particular alarm no longer
flags on the appropriate open-drain pin; however, the alarm status is still available in both of the alarm status registers (Address 0x43 and
Address 0x44).
Table 22. Alarm Setup Register
Address Default Data Bits, MSB First
0x6 0x0000 Bit Name Function
15 Latched
TMPALM
Set this latched bit high to program the open-drain TMPALM alarm pin as a latched output;
leave low for an unlatched alarm pin (default).
14 Disable
TMPALM
Set this bit high to disable the open-drain TMPALM alarm pin; leave low to leave enabled (default).
13 Latched
OSALM
Set this latched bit high to program the OSALM as a latched alarm on the open-drain KELALM
pin; leave low for an unlatched alarm pin (default).
12 Disable
OSALM
Set this bit high to disable the OSALM alarm function flagging the open-drain KELALM pin;
leave low to remain enabled (default). The disable GRDALM, DUTALM, and OSALM alarm
functions share one open-drain KELALM alarm pin. These bits allow users to choose if they wish
to have all or selected information flagged to the alarm pin.
11 Latched
DUTALM
Set this latched bit high to program the DUTALM as a latched alarm on the open-drain KELALM
pin; leave low for an unlatched alarm pin (default).
10 Disable
DUTALM
Set this bit high to disable the DUTALM alarm function flagging the open-drain KELALM pin.
Leave low to leave enabled (default). The disable GRDALM, DUTALM, and OSALM alarm
functions share one open drain KELALM alarm pin. These bits allow users to choose if they wish
to have all or any information flagged to the alarm pin. The DUTGND pin has a 50 µA pull-up to
allow for detection of an error in the DUTGND path. Setting this bit high also disables the 50 µA
pull-up.
9 Latched
CLALM
Set this latched bit high to program the open-drain CLALM clamp alarm pin as a latched
output; leave low for an unlatched alarm pin (default).
8 Disable
CLALM
Set this bit high to disable the open drain CLALM alarm pin; leave low to leave enabled (default).
7 Latched
GRDALM
Set this latched bit high to program the GRDALM as a latched alarm on the open-drain KELALM
pin; leave low for an unlatched alarm pin (default).
6 Disable
GRDALM
Set this bit high to disable the GRDALM alarm function flagging the open-drain KELALM pin;
leave low to leave enabled (default). The disable GRDALM, DUTALM and OSALM alarm functions
share one open-drain KELALM alarm pin. These bits allow users to choose if they wish to have
all or any information flagged to the KELALM alarm pin.
5:0 Unused Set to 0.
AD5560
Rev. C | Page 50 of 60
Table 23. Diagnostic Register
Address Default Data Bits, MSB First
0x7 0x0000
Bit Name Function
DIAG select selects the set of diagnostic signals that can be made available on MEASOUT. First, use MEASOUT
addressing (DPS Register 1) to select either the DIAG A or the DIAG B node to be made available on MEASOUT.
DIAG Select
Selected
Measure Block DIAG A DIAG B
0:3 Disabled Disabled Disabled
4 Disabled Disabled
5 EXTFORCE1A EXTFORCE2A
6 FINP FINM
7
Force amplifier
Output 2.5 mA Output 25 mA
8 VPTAT low VPTAT high
9 VTSD low (ref V
for −273°C)
VTSD high (ref V for +130°C)
10 MI VMID Code
11
Measure block
MV VMIN Code
12 FORCE DAC VOS DAC
13 CLL DAC CLH DAC
14 CPL DAC CPH DAC
15
DAC block
OSD DAC DGS DAC
VPTAT low/VPTAT high are temperature sensor devices in the middle of the enabled power stage, which gives a
voltage level that can be mapped back to the VTSD low and VTSD high reference points to get a temperature
value. These sensors are used in the thermal shutdown feature. See the%JF5FNQFSBUVSF4FOTPSBOE5IFSNBM
4IVUEPXOsection.
VMID code is the midscale voltage of the DACs; the offset DAC has a direct effect on this voltage level.
15
14
13
12
DIAG
select[3:0]
VMIN code is the zero-scale voltage of the DACs; again the offset DAC has a direct effect.
11
10
9
8
7
TSENSE
select[3:0]
The following codes allow selection of one of three sets of eight thermal diodes. The D+ of the selected thermal
diode is available on the GPO pin; the D− is on the AGND.
These thermal diodes are located across the die, in the cool parts and in the power stages. Diodes [16:23] are located
in the force amplifier NPNs (power output devices for supplying current). Similarly, Diodes [24:31] are located in
the force amplifier PNP devices (output devices for sinking current).
TSENSE Select
Selected
Thermal Block Connected Sensor
0:7 N/A—normal
GPO operation
No sensor connected
8 Cool end of high current drivers, hot side of digital
block
9 25 mA output stage
10 Hottest part of sensitive measurement circuitry
and cool part of force amplifier
11 Coolest end of force amplifier block
12 Coolest end of DACs
13 Beside TSENSE available on MEASOUT
14 Hottest part of DACs
15
Cool block
Cool side of digital block
16 1A-1
17 1A-2
18 2A (similar location to VPTAT low for EXTFORCE2
range)
19 1B-1 (similar location to VPTAT low for EXTFORCE1
range)
20 1B-2
21 2B
22 1C-1
23
Force amplifier
PNPs
1C-2
AD5560
Rev. C | Page 51 of 60
Address Default Data Bits, MSB First
0x7 0x0000
Bit Name Function
24 1A-1
25 1A-2
26 2A (similar location to VPTAT high for EXTFORCE2
range)
27 1B-1 (similar location to VPTAT high for EXTFORCE1
range)
28 1B-2
29 2B
30 1C-1
31
Force amplifier
NPNs
1C-2
These register bits allow disabling of stages of the force amplifier. They can be used to ensure connectivity in
each parallel stage. The enabled stage depends also on which current range is selected.
Current Range
Test Force
Amplifier Enabled Stage
EXTFORCE1 0 All stages
EXTFORCE1 1 EXTFORCE1C
EXTFORCE1 2 EXTFORCE1B
EXTFORCE1 3 EXTFORCE1A
EXTFORCE2 0 All stages
EXTFORCE2 1 Reserved
EXTFORCE2 2 EXTFORCE2B
6
5
Test Force
AMP[1:0]
EXTFORCE2 3 EXTFORCE2A
4:0 Reserved Set to 0.
AD5560
Rev. C | Page 52 of 60
Table 24. Other Registers
Address Register Default Data Bits, MSB First
0x8 FIN DAC x1 0x8000 x1 DAC register; D15 to D0, MSB first.
0x9 FIN DAC m 0xFFFF m register; D15 to D0, MSB first.
0xA FIN DAC c 0x8000 c register; D15 to D0, MSB first.
0xB Offset DAC x 0x8000 D15 to D0.
0xC OSD DAC x 0x1FFF D15 to D0.
0xD CLL DAC x1 0x0000 D15 to D0; the low clamp level can only be negative; the MSB is always 0 to ensure this.
0xE CLL DAC m 0xFFFF D15 to D0.
0xF CLL DAC c 0x8000 D15 to D0.
0x10 CLH DAC x1 0xFFFF D15 to D0; the high clamp level can only be positive; the MSB is always 1 to ensure this.
0x11 CLH DAC m 0xFFFF D15 to D0.
0x12 CLH DAC c 0x8000 D15 to D0.
0x13 CPL DAC x1 5 A range 0x0000 D15 to D0.
0x14 CPL DAC m 5 A range 0xFFFF D15 to D0.
0x15 CPL DAC c 5 A range 0x8000 D15 to D0.
0x16 CPL DAC x1 25 A range 0x0000 D15 to D0.
0x17 CPL DAC m 25 A range 0xFFFF D15 to D0.
0x18 CPL DAC c 25 A range 0x8000 D15 to D0.
0x19 CPL DAC x1 250 A range 0x0000 D15 to D0.
0x1A CPL DAC m 250 A range 0xFFFF D15 to D0.
0x1B CPL DAC c 250 A range 0x8000 D15 to D0.
0x1C CPL DAC x1 2.5 mA range 0x0000 D15 to D0.
0x1D CPL DAC m 2.5 mA range 0xFFFF D15 to D0.
0x1E CPL DAC c 2.5 mA range 0x8000 D15 to D0.
0x1F CPL DAC x1 25 mA range 0x0000 D15 to D0.
0x20 CPL DAC m 25 mA range 0xFFFF D15 to D0.
0x21 CPL DAC c 25 mA range 0x8000 D15 to D0.
0x22 CPL DAC x1 EXT Range 2 0x0000 D15 to D0.
0x23 CPL DAC m EXT Range 2 0xFFFF D15 to D0.
0x24 CPL DAC c EXT Range 2 0x8000 D15 to D0.
0x25 CPL DAC x1 EXT Range 1 0x0000 D15 to D0.
0x26 CPL DAC m EXT Range 1 0xFFFF D15 to D0.
0x27 CPL DAC c EXT Range 1 0x8000 D15 to D0.
0x28 CPH DAC x 1 5 A range 0xFFFF D15 to D0.
0x29 CPH DAC m 5 A range 0xFFFF D15 to D0.
0x2A CPH DAC c 5 A range 0x8000 D15 to D0.
0x2B CPH DAC x1 25 A range 0xFFFF D15 to D0.
0x2C CPH DAC m 25 mA range 0xFFFF D15 to D0.
0x2D CPH DAC c 25 A range 0x8000 D15 to D0.
0x2E CPH DAC x1 250 A range 0xFFFF D15 to D0.
0x2F CPH DAC m 250 A range 0xFFFF D15 to D0.
0x30 CPH DAC c 250 A range 0x8000 D15 to D0.
0x31 CPH DAC x1 2.5 mA range 0x0000 D15 to D0.
0x32 CPH DAC m 2.5 mA range 0xFFFF D15 to D0.
0x33 CPH DAC c 2.5 mA range 0x8000 D15 to D0.
0x34 CPH DAC x1 25 mA range 0xFFFF D15 to D0.
0x35 CPH DAC m 25 mA range 0xFFFF D15 to D0.
0x36 CPH DAC c 25 mA range 0x8000 D15 to D0.
0x37 CPH DAC x1 EXT Range 2 0xFFFF D15 to D0.
0x38 CPH DAC m EXT Range 2 0xFFFF D15 to D0.
0x39 CPH DAC c EXT Range 2 0x8000 D15 to D0.
0x3A CPH DAC x1 EXT Range 1 0xFFFF D15 to D0.
0x3B CPH DAC m EXT Range 1 0xFFFF D15 to D0.
AD5560
Rev. C | Page 53 of 60
Address Register Default Data Bits, MSB First
0x3C CPH DAC c EXT Range 1 0x8000 D15 to D0.
0x3D DGS DAC 0x3333 D15 to D0 DUTGND SENSE DAC, 0 V to 5 V range.
0x3E Ramp end code 0x0000 D15 to D0; this is the ramp end code. The ramp start code is the code that is in the FIN
DAC register.
0x3F Ramp step size 0x0001 0000 0000 D6 to D0.
D6:D0 set the ramp step size in increments of 16 LSB per code, with a 5 V reference,
16 LSB = 6.1 mV.
For example,
000 0000 = 16 LSBs (6.1 mV) step
000 0001 = 16 LSBs (6.1 mV) step
…
111 1111 = 2032 LSBs (775 mV) step.
0x40 RCLK divider 0x0001 0000 0000 D7 to D0.
D7:D0 set the RCLK divider.
0000 0000 = ÷ 1
0000 0001 = ÷ 1
0000 0010 = ÷ 2
0000 0011 = ÷ 3
…
1111 1111 = ÷ 255
0x41 Enable ramp 0x0000 0xFFFF to enable.
0x42 Interrupt ramp 0x0000 0x0000 to interrupt.
AD5560
Rev. C | Page 54 of 60
Table 25. Alarm Status and Clear Alarm Status Register
Address Register Default Data Bits, MSB first
This register is a read-only register providing information on the status of the alarm functions and
the comparator outputs.
Bit Name Function
15 LTMPALM Latched temperature alarm bit; if low, this bit indicates that an alarm event has
occurred.
14 TMPALM Unlatched alarm bit; if low, these bit indicates that an alarm event is still
present.
13 LOSALM Latched open-sense alarm bit; if low, indicates that an alarm event has
occurred.
12 OSALM Unlatched open-sense alarm bit; if low, indicates that an alarm event is still
present.
11 LDUTALM Latched DUTGND Kelvin sense alarm; if low, indicates that an alarm event has
occurred.
10 DUTALM Unlatched DUTGND Kelvin sense alarm; if low, indicates that an alarm event is still
present.
9 LCLALM Latched clamp alarm; if low, indicates that an alarm event has occurred.
8 CLALM Unlatched clamp alarm; if low, indicates that an alarm event is still present.
7 LGRDALM Latched guard alarm; if low, indicates that an alarm event has occurred.
6 GRDALM Unlatched guard alarm; if low, indicates that an alarm event is still present.
5 CPOL Comparator output low condition as per the comparator output pin.
4 CPOH Comparator output high condition as per the comparator output pin.
0x43 Alarm status 0x0000
3:0 Unused Must be zeros.
This register is a read-only register providing information on the status of the alarm functions and
the comparator outputs. Reading this register also automatically clears any latched alarm pins or bits.
Bit Name Function
15 LTMPALM Latched temperature alarm bit; if low, this bit indicates that an alarm event has
occurred.
14 TMPALM Unlatched alarm bit; if low, these bit indicates that an alarm event is still
present.
13 LOSALM Latched open-sense alarm bit; if low, indicates that an alarm event has
occurred.
12 OSALM Unlatched open-sense alarm bit; if low, indicates that an alarm event is still
present.
11 LDUTALM Latched DUTGND Kelvin sense alarm; if low, indicates that an alarm event has
occurred.
10 DUTALM Unlatched DUTGND Kelvin sense alarm; if low, indicates that an alarm event is still
present.
9 LCLALM Latched clamp alarm; if low, indicates that an alarm event has occurred.
8 CLALM Unlatched clamp alarm; if low, indicates that an alarm event is still present.
7 LGRDALM Latched guard alarm; if low, indicates that an alarm event has occurred.
6 GRDALM Unlatched guard alarm; if low, indicates that an alarm event is still present.
5 CPOL Comparator output low condition as per the comparator output pin.
4 CPOH Comparator output high condition as per the comparator output pin.
0x44 Alarm status
and clear alarm
0x0000
3:0 Unused Must be zeros.
0x45 CPL DAC x1 0x0000 D15 to D0.
0x46 CPL DAC m 0xFFFF D15 to D0.
0x47 CPL DAC c 0x8000 D15 to D0.
0x48 CPH DAC x1 0xFFFF D15 to D0.
0x49 CPH DAC m 0xFFFF D15 to D0.
0x4A CPH DAC c 0x8000 D15 to D0.
0x4B to
0x7F
Reserved Reserved.
AD5560
Rev. C | Page 55 of 60
READBACK MODE
The AD5560 allows data readback via the serial interface from
every register directly accessible to the serial interface, which is
all registers except the DAC register (x2 calibrated register). To
read back contents of a register, it is necessary to write a 1 to
the R/W bit, address the appropriate register, and fill the data
bits with all zeros.
After the write command has been written, data from the
selected register is loaded to the internal shift register and is
available on the SDO pin during the next SPI operation.
Address 0x43 and Address 0x44 are the only registers that are
read only. The read function gives the user details of the alarm
status and the comparator output result.
Alarm flags on latched alarm pins (Pin 1, Pin 2, Pin 3) and bits
are cleared after a read command of Register 0x44 (alarm status
and clear alarm register (see Table 25)).
SCLK frequency for readback does not operate at the full speed
of the SPI interface. See the Timing Characteristics section for
further details.
DAC READBACK
The DAC x1, DAC m, and DAC c registers are available to read
back via the serial interface. Access to the calibrated x2 register
is not available.
POWER-ON DEFAULT
During power-on, the power-on state machine resets all internal
registers to their default values, and BUSY goes low. A rising
edge on BUSY indicates that the power-on event is complete
and that the interface is enabled. The RESET pin has no
function in the power-on event.
During power-on, all DAC x1 registers corresponding to 0 V
are cleared; the calibration register default corresponds to m at
full scale and to c at zero scale.
The default conditions of the DPS and the system control
registers are as shown in the relevant tables (see Table 17
through Table 26).
During a RESET function, all registers are reset to the power-on
default.
AD5560
Rev. C | Page 56 of 60
Table 26. AD5560 Truth Table of Switches1
Reg Bit Name Bit SW1 SW2 SW3 SW4 SW7 SW13 SW14 SW15 SW5 SW6 SW8 SW9 SW11 SW16
System
Control
Register
Gain0,
Gain1
X X X X X X X X X X X X X X
0 B X X X X X X X X X X X X X FINGND
1 A X X X X X X X X X X X X X
CPO X X X X X X X X X X X X X X
PD2, 3 X X X X X X X X X X X X X On
04 X c X X X X X X X X X X X X DPS Register 1 SW-INH2
15 X a X X X X X X X X X X X X
000 X X X On On Off Off Off X X X X X X
001 X X X On On Off Off Off X X X X X X
010 X X X On On Off Off Off X X X X X X
011 X X X On On Off Off Off X X X X X X
100 X X X On On Off Off Off X X X X X X
101 X X X Off Off Off On On X X X X X X
I2, I1, I0
110 X X X Off Off On Off On X X X X X X
00 X X X X X X X X X X X X X X
01 X X X X X X X X X X X X X X
10 X X a X X X X X X X X X X X
CMP1, CMP0
11 X X b X X X X X X X X X X X
000 X X X X X X X X X X X X X Off
001 X X X X X X X X X X X X X On
010 X X X X X X X X X X X X X On
011 X X X X X X X X X X X X X On
100 X X X X X X X X X X X X X On
101 X X X X X X X X X X X X X On
110 X X X X X X X X X X X X X On
ME3, ME2,
ME1, ME0
111 X X X X X X X X X X X X X On
0 X X X X X X X X X X Off Off X X DPS Register 2 SF0
1 X X X X X X X X X X On On X X
006 b a X X X X X X a Off X X X X
017 b a X X X X X X b Off X X X X
108 c c X X X X X X Off On X X X X
Slave,
GANGIMODE
119 c b X X X X X X Off On X X X X
0 X X X X X X X X X X X X Off X INT10K
1 X X X X X X X X X X X X On X
HW_INH2 X c X X X X X X X X X X X X
Hardware Pins
CLEN X X X X X X X X X X X X X X
1 X = don’t care; the switch is unaffected by the particular bit condition.
2 Active low.
3 Power-down mode; used for low power consumption.
4 Force amplifier outputs tristate, low leakage mode; feedback made around amplifier.
5 FV mode.
6 Master: MASTER_OUT = internally connects to active EXTFORCE1/EXTFORCE2/25 mA output.
7 Master: MASTER_OUT = master MI.
8 Slave FV: EXTFORCE1/EXTFORCE2/25 mA connected internally to close the FVAMP loop.
9 Slave FI.
AD5560
Rev. C | Page 57 of 60
USING THE HCAVDDx AND HCAVSSx SUPPLIES
The first set of power supplies, AVDD and AVSS, provide power
to the DAC levels and associated circuitry. They also supply the
force amplifier stage for the low current ranges (ranges using
internal sense resistors up to 25 mA maximum).
The second set of power supplies, HCAVSS1 and HCAVDD1,
are intended to be used to minimize power consumption in
the AD5560 device for the EXTFORCE1 range (up to ±1.2 A).
Similarly, the HCAVSS2 and HCAVDD2 supplies are used for the
EXTFORCE2 range (up to ±500 mA). These supplies must be
less than or equal to the AVDD and AVSS supplies. When driving
high currents at low voltages, power can be greatly minimized
by ensuring that the supplies are at the lowest voltages.
Therefore, HCAVSSx and HCAVDDx can be switched externally
to different power rails as required by the set voltage range.
However, the design of the high current output stage means
that these supplies always have to be at a higher voltage than
the forced voltage, irrespective of the current range being used.
Therefore, depending on the level of supply switching, external
diodes may be required in series with each of the HCAVDDx
and HCAVSSx supplies, as shown in Figure 57. There are
internal pull-up resistors between the supplies (see Figure 57).
Using diodes here allows a more flexible use of supplies and
can minimize the amount of supply switching required. In the
example, the AVDD and AVSS supplies can support the high
voltage needs, whereas the HCAVDDx and HCAVSSx supplies
support the low voltage, higher current ranges. Diode selection
should take into account the current carrying requirements.
Supply selection for HCAVDDx and HCAVSSx supplies must
allow for this extra voltage drop.
POWER SUPPLY SEQUENCING
When the supplies are connected to the AD5560, it is important
that the AGND and DGND pins be connected to the relevant
ground plane before the positive or negative supplies are applied.
In most applications, this is not an issue because the ground
pins for the power supplies are connected to the ground pins of
the AD5560 via ground planes. The AVDD and AVSS supplies
must be applied to the device either before or at the same time
as the HCAVDDx and HCAVSSx supplies, as indicated in Table 3.
There are no known supply sequences surrounding the DVCC
supply, although it is recommended that it be applied as
indicated by the absolute maximum ratings (see Table 3).
AD5560
33kΩ
1200mA
RANGE
500mA
RANGE
FORCE
DUT RANGE
0V TO + 25 V
OUTPUT RANGE
0V TO + 2 5V
INT E RNAL RSENSE
±0.5V AT FULL CURRENT
INT E RNAL RANGE SELE CT
(5µA , 25µA, 250µA, 2.5mA, 25mA)
EXTFORCE1
DUT RANG E
–2V TO + 3 V
EXTFORCE2
DUT RANG E
0V TO + 6V
ALL OW ±0.5V
FOR EXT RSENSE
OUTPUT RANG E
–2.5V TO +3.5V
2. HIGHEST CURRENT
RANGE
1. LOW CURRENT,
HIGH VOLTAGE
3. MI DCU RRENT
RANG E
OUT P UT RANGE
–0.2V TO +6.5V
ALLOW ±0 . 5V F O R E X T RSENSE
+
10µF
+
0.1µF
10µF
0.1µF
HCAVDD2 = +9V
HCAVSS2 = –5V
HCAVDD1 = +6V
HCAVSS1 = –5V
++
+
10µF
+
0.1µF
10µF
0.1µF
++
AVDD = +28V
AVSS = –5V
+
10µF
+
0.1µF
DVCC = 3V/5V
+
0.1µF
10µF
0.1µF
++
33kΩ
100kΩ100kΩ
07779-012
Figure 57. Example of Using the Extra Supply Rails Within the AD5560 to Achieve Multiple Voltage/Current Ranges
AD5560
Rev. C | Page 58 of 60
REQUIRED EXTERNAL COMPONENTS
The minimum required external components are shown in the
block diagram in Figure 58. Decoupling is very dependent on
the type of supplies used, the board layout, and the noise in the
system. It is possible that less decoupling may be required as a
result. Although there are four compensation input pins and
five feedforward capacitor input pins, all capacitor inputs may
be used only if the user intends to drive large variations of DUT
load capacitances. If the DUT load capacitance is known and
doesn’t change for all combinations of voltage ranges and test
conditions, then it is possible only one set of CCx and CFx is
required.
SHARED
ADC
ADC
V
REF
AV
SS
AV
DD
VREFDV
CC
KELALM
CLALM
DV
CC
OR
OTHER
DIGITAL
SUPPLY
TMPALM
RESET
RPULLUP
DV
CC
OR
OTHER
DIGITAL
SUPPLY
RPULLUP
MEASOUT
C
C0
C
C1
C
C2
C
C3
EXTFORCE1
EXTFORCE2
CF4
CF3
CF2
CF1
DUT
07779-013
EXTMEASHI1
SENSE
EXTMEASHI2
R
SENSE
2
R
SENSE
1
EXTMEASIL
DUTGND
FORCE
+
10µF
+
0.1µF
10µF
0.1µF
HCAV
DD2
HCAV
SS2
REF
HCAV
DD1
HCAV
SS1
SHARED
REFERENCE
++
+
10µF
+
0.1µF
10µF
0.1µF
++
AV
DD
AV
SS
+
10µF
+
0.1µF
DV
CC
+
0.1µF
10µF
0.1µF
++
+
0.1µF
CF0
ADC
DRIVER
Figure 58. External Components Required for Use with the DPS
Table 27. References Suggested for Use with the AD55601
Part No. Voltage (V)
Initial
Accuracy %
Ref Out Tempco
(ppm/°C max)
A/B Grade
Ref Output
Current (mA)
Supply Voltage
Range (V) Package
ADR431 2.5 ±0.04 10/3 30 4.5 to 18 MSOP, SOIC
ADR435 5 ±0.04 10/3 30 7 to 18 MSOP, SOIC
ADR441 2.5 ±0.04 10/3 10 3 to 18 MSOP, SOIC
ADR445 5 ±0.04 10/3 10 5.5 to 18 MSOP, SOIC
1 Subset of the possible references suitable for use with the AD5560. See www.analog.com/references for more options.
AD5560
Rev. C | Page 59 of 60
POWER SUPPLY DECOUPLING
In any circuit where accuracy is important, careful consid-
eration of the power supply and ground return layout helps
to ensure the rated performance. The printed circuit board
on which the AD5560 is mounted should be designed so that
the analog and digital sections are separated and confined to
certain areas of the board. If the AD5560 is in a system where
multiple devices require an AGND-to-DGND connection, the
connection should be made at one point only. The star ground
point should be established as close as possible to the device.
The DGND connection in the AD5560 should be treated as
AGND and returned to the AGND plane. For more detail on
decoupling for mixed signal applications, refer to Analog
Devices Tutorial MT 031.
For supplies with multiple pins (AVSS, AVDD, DVCC), it is
recommended to tie these pins together and to decouple
each supply once.
The AD5560 should have ample supply decoupling of 10 µF
in parallel with 0.1 µF on each supply located as close to the
part as possible, ideally right up against the device. The 10 µF
capacitors are the tantalum bead type. The 0.1 µF capacitor
should have low effective series resistance (ESR) and effective
series inductance (ESL), such as the common ceramic capaci-
tors that provide a low impedance path to ground at high
frequencies to handle transient currents due to internal logic
switching.
Digital lines running under the device should be avoided because
these couple noise onto the device. The analog ground plane
should be allowed to run under the AD5560 to avoid noise
coupling. The power supply lines of the AD5560 should use as
large a trace as possible to provide low impedance paths and
reduce the effects of glitches on the power supply line. Fast
switching digital signals should be shielded with digital ground
to avoid radiating noise to other parts of the board and should
never be run near the reference inputs. It is essential to
minimize noise on all VREF lines. Avoid crossover of digital
and analog signals. Traces on opposite sides of the board
should run at right angles to each other. This reduces the effects
of feedthrough throughout the board. As is the case for all thin
packages, care must be taken to avoid flexing the package and
to avoid a point load on the surface of this package during the
assembly process.
Also note that the exposed paddle of the AD5560 is internally
connected to the negative supply AVSS.
AD5560
Rev. C | Page 60 of 60
OUTLINE DIMENSIONS
COM PLI ANT TO JE DE C STANDARDS MS - 0 26-ACD- HU
1.05
1.00
0.95
0.20
0.09
0.08 MAX
COPLANARITY
VIEW A
RO TAT ED 90
°
CCW
SEATING
PLANE
0° M IN
7°
3.5°
0°
0.15
0.05
49
64
1
17
16
32
33
48
1.20
MAX
0.675
0.872
0.75
0.60
0.45
VIEW A
TOP VI EW
(PINS DOWN)
49 64
17
1
16
32
33
48
0.50
BSC
LEAD PITCH
0.38
0.32
0.22
BOTTOM VIEW
(PINS UP)
7.50
BSC
7.50
BSC
EXPOSED
PAD
5.95
BSC
12.20
12.00 S Q
11.80
10.20
10.00 S Q
9.80
5.95 BSC
011708-A
FO R P ROPER CONNECT ION O F
THE EXPOSED PAD, REFER TO
THE PIN CO NFIGURATION AND
FUNCT I ON DESCRIPT IO NS
SECTION OF THIS DATA SHEET.
Figure 59. 64-Lead Thin Quad Flat Package, Exposed Pad [TQFP_EP]
(SV-64-3)
Dimensions shown in millimeters
ORDERING GUIDE
Model1 Temperature Range2 Package Description Package Option
AD5560JSVUZ TJ = 25°C to +90oC 64-Lead Thin Quad Flat Pack with Exposed Pad (TQFP_EP) SV-64-3
AD5560JSVUZ-REEL TJ = 25°C to +90oC 64-Lead Thin Quad Flat Pack with Exposed Pad (TQFP_EP) SV-64-3
EVAL-AD5560EBUZ Evaluation Kit
1 Z = RoHS Compliant Part.
2 TJ = junction temperature.
©2008-2010 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D07779-0-10/10(C)
