TE28F016B3BA90 - Intel - Product.Network

3-Volt Advanced Boot Block Flash

Memory

28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3

Datasheet

Product Features

The Intel®3-Volt Advanced Boot Block flash memory, manufactured on Intel’s latest 0.13 µm

and 0.18 µm technologies, represent a feature-rich solution at overall lower system cost. The 3-

Volt Advanced Boot Block Flash Memory products in x16 will be available in 48-lead TSOP and

48-ball CSP packages. The x8 option of this product family will be available only in 40-lead

TSOP and 48-ball µBGA* packages. Additional information on this product family can be

obtained by accessing Intel’s website at: http://www.intel.com/design/flash.

•Flexible SmartVoltage Technology

—2.7 V–3.6 V Read/Program/Erase

—12 V VPP Fast Production Programming

•1.65 V–2.5 V or 2.7 V–3.6 V I/O Option

— Reduces Overall System Power

•High Performance

—2.7 V–3.6 V: 70 ns Max Access Time

•Optimized Block Sizes

—Eight 8-KB Blocks for Data,Top or

Bottom Locations

—Up to One Hundred Twenty-Seven 64-

KB Blocks for Code

•Block Locking

—VCC-Level Control through WP#

•Low Power Consumption

—9 mA Typical Read Current

•Absolute Hardware-Protection

—VPP = GND Option

—VCC Lockout Voltage

•Extended Temperature Operation

—–40 °C to +85 °C

•Automated Program and Block Erase

—Status Registers

•Intel®Flash Data Integrator Software

—Flash Memory Manager

—System Interrupt Manager

—Supports Parameter Storage, Streaming

Data (e.g., Voice)

•Extended Cycling Capability

—Minimum 100,000 Block Erase Cycles

Guaranteed

•Automatic Power Savings Feature

—Typical ICCS after Bus Inactivity

•Standard Surface Mount Packaging

—48-Ball CSP Packages

—40- and 48-Lead TSOP Packages

•Density and Footprint Upgradeable for

common package

—8-, 16-, 32- and 64-Mbit Densities

•ETOX™ VIII (0.13 µm)Flash

Technology

—16 and 32-Mbit Densities

•ETOX™ VII (0.18 µm) Flash Technology

—16-, 32- and 64-Mbit Densities

•ETOX ™ VI (0.25µm) Flash Technology

—8-, 16-, and 32-Mbit Densities

•The x8 option not recommended for new

designs

Order Number: 290580-016

April 2002

Notice: This specification is subject to change without notice. Verify with your local Intel sales

office that you have the latest data sheet before finalizing a design.

Information in this document is provided in connection with Intel® products. No license, express or implied, by estoppel or otherwise, to any

intellectual property rights is granted by this document. Except as provided in Intel's Terms and Conditions of Sale for such products, Intel assumes no

liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties

relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are

not intended for use in medical, life saving, or life sustaining applications.

Intel may make changes to specifications and product descriptions at any time, without notice.

Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for

future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.

The 28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3 may contain design defects or errors known as errata which may cause the product to

deviate from published specifications. Current characterized errata are available on request.

Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.

Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 1-800-

548-4725 or by visiting Intel's website at http://developer.intel.com/design/flash.

*Other names and brands may be claimed as the property of others.

iii
28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3
Contents
0 Introduction ..................................................................................................................1
1 Product Overview ..................................................................................................2
0 Product Description ..................................................................................................3
1 Package Pinouts ...................................................................................................3
2 Block Organization ..............................................................................................10
2.1 Parameter Blocks ...................................................................................10
2.2 Main Blocks ............................................................................................10
0 Principles of Operation..........................................................................................10
1 Bus Operation .....................................................................................................10
1.1 Read.......................................................................................................11
1.2 Output Disable........................................................................................11
1.3 Standby ..................................................................................................11
1.4 Deep Power-Down / Reset .....................................................................11
1.5 Write .......................................................................................................12
2 Modes of Operation.............................................................................................12
2.1 Read Array .............................................................................................12
2.2 Read Identifier ........................................................................................14
2.3 Read Status Register .............................................................................14
2.3.1 Clearing the Status Register .....................................................14
2.4 Program Mode........................................................................................15
2.4.1 Suspending and Resuming Program ........................................15
2.5 Erase Mode ............................................................................................15
2.5.1 Suspending and Resuming Erase.............................................16
3 Block Locking ......................................................................................................17
3.1 WP# = VIL for Block Locking ..................................................................17
3.2 WP# = VIH for Block Unlocking ..............................................................18
4 VPP Program and Erase Voltages .......................................................................18
4.1 VPP =V
IL for Complete Protection .........................................................18
5 Power Consumption ............................................................................................18
5.1 Active Power ..........................................................................................19
5.2 Automatic Power Savings (APS)............................................................19
5.3 Standby Power .......................................................................................19
5.4 Deep Power-Down Mode .......................................................................19
6 Power and Reset Considerations........................................................................19
6.1 Power-Up/Down Characteristics ............................................................19
6.2 RP# Connected to System Reset...........................................................20
6.3 VCC,V
PP and RP# Transitions ...............................................................20
7 Power Supply Decoupling ...................................................................................20
0 Electrical Specifications........................................................................................21
1 Absolute Maximum Ratings.................................................................................21
2 Operating Conditions...........................................................................................22
3 Capacitance ........................................................................................................22
4 DC Characteristics ..............................................................................................23
5 AC Characteristics —Read Operations...............................................................27

28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3
iv
4.6 AC Characteristics —Write Operations............................................................... 32
4.7 Program and Erase Timings ............................................................................... 36
5.0 Reset Operations ..................................................................................................... 38
6.0 Ordering Information .............................................................................................. 39
7.0 Additional Information ........................................................................................... 41
Appendix A Write State Machine Current/Next States ................................................. 42
Appendix B Architecture Block Diagram........................................................................... 43
Appendix C Word-Wide Memory Map Diagrams............................................................. 44
Appendix D Byte-Wide Memory Map Diagrams .............................................................. 50
Appendix E Program and Erase Flowcharts .................................................................... 53

28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3

Revision History

Number Description

-001 Original version

-002

Section 3.4, VPP Program and Erase Voltages, added

Updated Figure 9: Automated Block Erase Flowchart

Updated Figure 10: Erase Suspend/Resume Flowchart (added program to table)

Updated Figure 16: AC Waveform: Program and Erase Operations (updated notes)

IPPR maximum specification change from ±25 µAto±50µA

Program and Erase Suspend Latency specification change

Updated Appendix A: Ordering Information (included8Mand4Minformation)

Updated Figure, Appendix D: Architecture Block Diagram (Block info. in words not bytes)

Minor wording changes

-003

Combined byte-wide specification (previously 290605) with this document

Improved speed specification to 80 ns (3.0 V) and 90 ns (2.7 V)

Improved 1.8 V I/O option to minimum 1.65 V (Section 3.4)

Improved several DC characteristics (Section 4.4)

Improved several AC characteristics (Sections 4.5 and 4.6)

Combined 2.7 V and 1.8 V DC characteristics (Section 4.4)

Added5VV

PP read specification (Section 3.4)

Removed 120 ns and 150 ns speed offerings

Moved Ordering Information from Appendix to Section 6.0; updated information

Moved Additional Information from Appendix to Section 7.0

Updated figure Appendix B, Access Time vs. Capacitive Load

Updated figure Appendix C, Architecture Block Diagram

Moved Program and Erase Flowcharts to Appendix E

Updated Program Flowchart

Updated Program Suspend/Resume Flowchart

Minor text edits throughout

-004

Added 32-Mbit density

Added 98H as a reserved command (Table 4)

A1–A20 = 0 when in read identifier mode (Section 3.2.2)

Status register clarification for SR3 (Table 7)

VCC and VCCQ absolute maximum specification = 3.7 V (Section 4.1)

Combined IPPW and ICCW into one specification (Section 4.4)

Combined IPPE and ICCE into one specification (Section 4.4)

Max Parameter Block Erase Time (tWHQV2/tEHQV2) reduced to 4 sec (Section 4.7)

MaxMainBlockEraseTime(t

WHQV3/tEHQV3) reduced to 5 sec (Section 4.7)

Erase suspend time @ 12 V (tWHRH2/tEHRH2) changed to 5 µs typical and 20 µs maximum

(Section 4.7)

Ordering Information updated (Section 6.0)

Write State Machine Current/Next States Table updated (Appendix A)

Program Suspend/Resume Flowchart updated (Appendix F)

Erase Suspend/Resume Flowchart updated (Appendix F)

Text clarifications throughout

-005

µBGA package diagrams corrected (Figures 3 and 4)

IPPD test conditions corrected (Section 4.4)

32-Mbit ordering information corrected (Section 6)

µBGA package top side mark information added (Section 6)

-006

VIH and VILSpecification change (Section 4.4)

ICCS test conditions clarification (Section 4.4)

Added Command Sequence Error Note (Table 7)

Data sheet renamed from Smart 3 Advanced Boot Block 4-Mbit, 8-Mbit, 16-Mbit Flash

Memory Family.

Added device ID information for 4-Mbit x8 device

Removed 32-Mbit x8 to reflect product offerings

Minor text changes

-007 Corrected RP# pin description in Table 2, 3VoltAdvancedBootBlockPinDescriptions

Corrected typographical error fixed in Ordering Information

28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3

-008 4-Mbit packaging and addressing information corrected throughout document

-009 Corrected 4-Mbit memory addressing tables in Appendices D and E

-010 Max ICCD changed to 25 µA

VCCMax on 32 M (28F320B3) changed to 3.3 V

-011 Added 64-Mbit density and faster speed offerings

Removed access time vs. capacitance load curve

-012

Changed references of 32Mbit 80ns devices to 70ns devices to reflect the faster product

offering.

Changed VccMax=3.3V reference to indicate the affected product is the 0.25µm32Mbit

device.

Minor text edits throughout document.

-013 Added New Pin-1 indicator information on 40 and 48Lead TSOP packages.

Minor text edits throughout document.

-014 Added specifications for 0.13 micron product offerings throughout document

-015 Minor text edits throughout document.

-016

Adjusted ordering information.

Adjusted specifications for 0.13 micron product offerings.

Revised and corrected DC Characteristics Table.

Adjusted package diagram information.

Minor text edits throughout document.

Number Description

28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3
1
1.0 Introduction
This datasheet contains the specifications for the 3-Volt Advanced Boot Block Flash Memory
family, which is optimized for portable, low-power, systems. This family of products features
1.65 V–2.5 V or 2.7 V–3.6 V I/Os, and a low VCC/VPP operating range of 2.7 V–3.6 V for Read,
Program, and Erase operations. In addition, this family is capable of fast programming at 12 V.
Throughout this document, the term “2.7 V” refers to the full voltage range 2.7 V–3.6 V (except
where noted otherwise) and “VPP =12V”refersto12V±5%.Section1.0and2.0providean
overview of the Flash Memory family including applications, pinouts, and pin descriptions.
Section 3.0 describes the memory organization and operation for these products. Sections 4.0 and
5.0 contain the operating specifications. Finally, Sections 6.0 and 7.0 provide ordering and other
reference information.
The 3-Volt Advanced Boot Block Flash Memory features the following:
•Enhanced blocking for easy segmentation of code and data or additional design flexibility
•Program Suspend to Read command
•VCCQ input of 1.65 V–2.5 V or 2.7 V–3.6 V on all I/Os. See Figures 1 through 4 for pinout
diagrams and VCCQ location
•Maximum program and erase time specification for improved data storage.
NOTES:
1. 32-Mbit and 64-Mbit densities not available in 40-lead TSOP.
2. 8-Mbit densities not available in µBGA* CSP.
3. VCCMaxis3.3Von0.25µm 32-Mbit devices.
Table 1. 3-Volt Advanced Boot Block Feature Summary
Feature 28F008B3, 28F016B3 28F800B3, 28F160B3,
28F320B3(3), 28F640B3 Reference
VCC Read Voltage 2.7 V– 3.6 V Section 4.2,
Section 4.4
VCCQ I/O Voltage 1.65 V–2.5 V or 2.7 V– 3.6 V Section 4.2, 4.4
VPP Program/Erase Voltage 2.7 V– 3.6 V or 11.4 V– 12.6 V Section 4.2, 4.4
Bus Width 8 bit 16 bit Table 3
Speed 70 ns, 80 ns, 90 ns, 100 ns, 110 ns Section 4.5
Memory Arrangement 1024 Kbit x 8 (8 Mbit),
2048Kbitx8(16Mbit)
512 Kbit x 16 (8 Mbit),
1024 Kbit x 16 (16 Mbit),
2048 Kbit x 16 (32 Mbit),
4096 Kbit x 16 (64 Mbit)
Section 2.2
Blocking (top or bottom)
Eight 8-Kbyte parameter blocks and
Fifteen 64-Kbyte blocks (8 Mbit) or
Thirty-one 64-Kbyte main blocks (16 Mbit)
Sixty-three 64-Kbyte main blocks (32 Mbit)
Onehundredtwenty-seven64-Kbytemainblocks(64Mbit)
Section 2.2
Appendix C
Locking WP# locks/unlocks parameter blocks
All other blocks protected using VPP
Section 3.3
Table 8
Operating Temperature Extended: –40 °Cto+85°C Section 4.2, 4.4
Program/Erase Cycling 100,000 cycles Section 4.2, 4.4
Packages 40-lead TSOP(1),
48-Ball µBGA* CSP(2)
48-Lead TSOP,
48-Ball µBGA CSP(2),
48-Ball VF BGA(4) Figure 4,Figure 5

28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3

1.1 Product Overview

Intel provides the most flexible voltage solution in the flash industry, providing three discrete

voltage supply pins: VCC for Read operation, VCCQ for output swing, and VPP for Program and

Erase operation. All 3-Volt Advanced Boot Block Flash Memory products provide program/erase

capability at 2.7 V or 12 V (for fast production programming), and read with VCC at2.7V.Since

many designs read from the flash memory a large percentage of the time, 2.7 V VCC operation can

provide substantial power savings.

The 3-Volt Advanced Boot Block Flash Memory products are available in either x8 or x16

packages in the following densities: (see Section 6.0, “Ordering Information” on page 39 for

availability.)

•8-Mbit (8, 388, 608-bit) flash memory organized as 512 Kwords of 16 bits each or 1024

Kbytes of 8-bits each

•16-Mbit (16, 777, 216-bit) flash memory organized as 1024 Kwords of 16 bits each or

2048 Kbytes of 8-bits each

•32-Mbit (33, 554, 432-bit) flash memory organized as 2048 Kwords of 16 bits each

•64-Mbit (67, 108, 864-bit) flash memory organized as 4096 Kwords of 16 bits each

The parameter blocks are located at either the top (denoted by -T suffix) or the bottom (-B suffix)

of the address map in order to accommodate different microprocessor protocols for kernel code

location. The upper two (or lower two) parameter blocks can be locked to provide complete code

security for system initialization code. Locking and unlocking is controlled by WP# (see Section

3.3, “Block Locking” on page 17 for details).

The Command User Interface (CUI) serves as the interface between the microprocessor or

microcontroller and the internal operation of the flash memory. The internal Write State Machine

(WSM) automatically executes the algorithms and timings necessary for Program and Erase

operations, including verification, thereby unburdening the microprocessor or microcontroller. The

status register indicates the status of the WSM by signifying block erase or word program

completion and status.

The 3-Volt Advanced Boot Block flash memory is also designed with an Automatic Power Savings

(APS) feature, which minimizes system current drain and allows for very low power designs. This

mode is entered following the completion of a read cycle (approximately 300 ns later).

The RP# pin provides additional protection against unwanted command writes that may occur

during system reset and power-up/down sequences due to invalid system bus conditions (see

Section 3.6, “Power-Up/Down Operation” on page 19).

Section 3.0, “Principles of Operation” on page 10 gives detailed explanation of the different modes

of operation. Section 4.4, “DC Characteristics” on page 23 provides complete current and voltage

specifications. Refer to Section 4.5, “AC Characteristics —Read Operations” on page 27 for read,

program, and erase performance specifications.

28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3

2.0 Product Description

This section explains device pin description and package pinouts.

2.1 Package Pinouts

The 3-Volt Advanced Boot Block flash memory is available in 40-lead TSOP (x8, Figure 1),

48-lead TSOP (x16, Figure 2), 48-ball µBGA(x8 and x16, Figure 4 and Figure 5, respectively), and

48-ball VF BGA (x16, Figure 5) packages. In all figures, pin changes necessary for density

upgrades have been circled.

0580_01

NOTES:

1. 40-Lead TSOP available for 8-Mbit and 16-Mbit densities only.

2. Lower densities will have NC on the upper address pins. For example, an 8-Mbit device will have NC on

Pin 38.

Figure 1. 40-Lead TSOP Package for x8 Configurations

GND

CCQ

OE#

GND

CE#

WE#

RP#

WP#

16 M

Advanced Boot Block

40-Lead TSOP

10 mm x 20 mm

TOP VIEW

28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3

0580_02

Figure 2. 48-Lead TSOP Package for x16 Configurations

Advanced Boot Block

48-Lead TSOP

12 mm x 20 mm

TOP VIEW

CCQ

GND

WE#

RP#

WP#

OE#

GND

CE#

32 M

16 M

64 M

28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3

Note: The topside marking on 8 Mb, 16 Mb, and 32 Mb Advanced & Advanced + Boot Block 40L and

48L TSOP products will convert to a white ink triangle as a Pin-1 indicator. Products without the

white triangle will continue to use a dimple as a Pin-1 indicator. There are no other changes in

package size, materials, functionality, customer handling, or manufacturability. Product will

continue to meet stringent Intel quality requirements.

Products Affected are Intel Ordering Codes:

Figure 3. New Mark for Pin-1 indicator for 40-Lead 8 Mb, 16 Mb TSOP and 48-Lead 8 Mb, 16

Mb and 32 Mb TSOP

Current Mark:

New Mark:

28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3

Ordering Information Valid Combinations

40-Lead TSOP 48-Lead TSOP

Ext. Temp. 32

Mbit

TE28F320B3TC70

TE28F320B3BC70

TE28F320B3TC90

TE28F320B3BC90

TE28F320B3TA100

TE28F320B3BA100

TE28F320B3TA110

TE28F320B3BA110

Ext. Temp. 16

Mbit

TE28F160B3TC70

TE28F160B3BC70

TE28F160B3TC80

TE28F160B3BC80

TE28F016B3TA90(3) TE28F160B3TA90(3)

TE28F016B3BA90(3) TE28F160B3BA90(3)

TE28F016B3TA110(3) TE28F160B3TA110(3)

TE28F016B3BA110(3) TE28F160B3BA110(3)

Ext. Temp. 8

Mbit

TE28F008B3TA90(3) TE28F800B3TA90(3)

TE28F008B3BA90(3) TE28F800B3BA90(3)

TE28F008B3TA110(3) TE28F800B3TA110(3)

TE28F008B3BA110(3) TE28F800B3BA110(3)

28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3

0580_04

NOTES:

1. Shaded connections indicate the upgrade address connections. Lower density devices will not have the

upper address solder balls. Routing is not recommended in this area. A20 is the upgrade address for the

16-Mbit device.

Figure 4. x8 48-Ball µBGA* Chip Size Package (Top View, Ball Down)

A14

A15

A16

A17

VCCQ

A12

A10

A13

A11

WE#

VPP

RP#

WP#

A19

A20

A18

CE#

GND

GND D7 NC D4 VCC NC D1 OE#

13254768

16M

28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3

0580_03

NOTES:

1. Shaded connections indicate the upgrade address connections. Lower density devices will not have the

upper address solder balls. Routing is not recommended in this area. A19 is the upgrade address for the

16-Mbit device. A20 is the upgrade address for the 32-Mbit device. A21 is the upgrade address for the 64-Mbit

device.

2. Table 2, “3-Volt Advanced Boot Block Pin Descriptions” on page 9 details the usage of each device pin.

Figure 5. x16 48-Ball Very Fine Pitch BGA and µBGA* Chip Size Package (Top View, Ball

Down)

13254768

A13

A14

A15

A16

VCCQ

A11

A10

A12

D14

D15

WE#

VPP

RP#

A21

D11

D12

WP#

A18

A20

A19

A17

CE#

Vss

Vss D7 D13 D4 VCC D10 D1 OE#

16M

32M64M

28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3

Table 2. 3-Volt Advanced Boot Block Pin Descriptions

Symbol Type Name and Function

A0–A21 INPUT

ADDRESS INPUTS for memory addresses. Addresses are internally latched during a program or

erase cycle.

28F008B3: A[0-19], 28F016B3: A[0-20],

28F800B3: A[0-18], 28F160B3: A[0-19],

28F320B3: A[0-20], 28F640B3: A[0-21]

DQ0–DQ7

INPUT/

OUTPUT

DATA INPUTS/OUTPUTS: Inputs array data on the second CE# and WE# cycle during a Program

command. Inputs commands to the Command User Interface when CE# and WE# are active. Data is

internally latched. Outputs array, identifier and status register data. The data pins float to tri-state when

the chip is de-selected or the outputs are disabled.

DQ8–

DQ15

INPUT/

OUTPUT

DATA INPUTS/OUTPUTS: Inputs array data on the second CE# and WE# cycle during a Program

command. Data is internally latched. Outputs array and identifier data. The data pins float to tri-state

when the chip is de-selected. Not included on x8 products.

CE# INPUT

CHIP ENABLE: Activates the internal control logic, input buffers, decoders and sense amplifiers. CE#

is active low. CE# high de-selects the memory device and reduces power consumption to standby

levels.

OE# INPUT OUTPUT ENABLE: Enables the device’s outputs through the data buffers during a Read operation.

OE#isactivelow.

WE# INPUT WRITE ENABLE: Controls writes to the Command Register and memory array. WE# is active low.

Addresses and data are latched on the rising edge of the second WE# pulse.

RP# INPUT

RESET/DEEP POWER-DOWN: Uses two voltage levels (VIL,V

IH) to control reset/deep power-down

mode.

WhenRP#isatlogiclow,thedeviceisinreset/deeppower-downmode, which drives the outputs

to High-Z, resets the Write State Machine, and minimizes current levels (ICCD).

When RP# is at logic high, the device is in standard operation. When RP# transitions from logic-

low to logic-high, the device defaults to the read array mode.

WP# INPUT

WRITE PROTECT: Provides a method for locking and unlocking the two lockable parameter blocks.

WhenWP#isatlogiclow,thelockableblocksarelocked, preventing Program and Erase

operations to those blocks. If a Program or Erase operation is attempted on a locked block, SR.1 and

either SR.4 [program] or SR.5 [erase] will be set to indicate the operation failed.

When WP# is at logic high, the lockable blocks are unlocked and can be programmed or erased.

See Section 3.3 for details on write protection.

VCCQ INPUT

OUTPUT VCC:Enables all outputs to be driven to 1.8 V – 2.5 V while the VCC is at 2.7 V–3.3 V. If the

VCC is regulated to 2.7 V–2.85 V, VCCQ canbedrivenat1.65V–2.5Vtoachievelowestpower

operation (see Section 4.4).

This input may be tied directly to VCC (2.7 V–3.6 V).

VCC DEVICE POWER SUPPLY: 2.7 V–3.6 V

VPP

PROGRAM/ERASE POWER SUPPLY: Supplies power for Program and Erase operations. VPP may

bethesameasV

CC (2.7 V–3.6 V) for single supply voltage operation. For fast programming at

manufacturing, 11.4 V–12.6 V may be supplied to VPP

. This pin cannot be left floating. Applying

11.4 V–12.6 V to VPP can only be done for a maximum of 1000 cycles on the main blocks and 2500

cycles on the parameter blocks. VPP may be connected to 12 V for a total of 80 hours maximum (see

Section 3.4 for details).

VPP <V

PPLK protects memory contents against inadvertent or unintended program and erase

commands.

GND GROUND: For all internal circuitry. All ground inputs must be connected.

NC NO CONNECT: Pin may be driven or left floating.

28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3

2.2 Block Organization

The 3-Volt Advanced Boot Block is an asymmetrically blocked architecture that enables system

integration of code and data within a single flash device. Each block can be erased independently

of the others up to 100,000 times. For the address locations of each block, see the memory maps in

Appendix C.

2.2.1 Parameter Blocks

The 3-Volt Advanced Boot Block flash memory architecture includes parameter blocks to facilitate

storage of frequently updated small parameters (i.e., data that would normally be stored in an

EEPROM). The word-rewrite functionality of EEPROMs can be emulated using software

techniques. Each device contains eight parameter blocks of 8 Kbytes/4 Kwords (8192 bytes/4,096

words) each.

2.2.2 Main Blocks

After the parameter blocks, the remainder of the array is divided into equal-size main blocks

(65,536 bytes/32,768 words) for data or code storage. The 8-Mbit device contains 15 main blocks;

16-Mbit flash has 31 main blocks; 32-Mbit has 63 main blocks; 64-Mbit has 127 main blocks.

3.0 Principles of Operation

Flash memory combines EEPROM functionality with in-circuit electrical program-and-erase

capability. The 3-Volt Advanced Boot Block Flash Memory family utilizes a Command User

Interface (CUI) and automated algorithms to simplify Program and Erase operations. The CUI

allows for 100% CMOS-level control inputs and fixed power supplies during erasure and

programming.

When VPP <V

PPLK, the device will execute only the following commands successfully: Read

Array, Read Status Register, Clear Status Register, and Read Identifier. The device provides

standard EEPROM read, standby, and Output-Disable operations. Manufacturer identification and

device identification data can be accessed through the CUI. All functions associated with altering

memory contents, namely program and erase, are accessible via the CUI. The internal Write State

Machine (WSM) completely automates Program and Erase operations, while the CUI signals the

start of an operation and the status register reports status. The CUI handles the WE# interface to the

data and address latches, as well as system status requests during WSM operation.

3.1 Bus Operation

3-Volt Advanced Boot Block flash memory devices read, program, and erase in-system via the

local CPU or microcontroller. All bus cycles to or from the flash memory conform to standard

microcontroller bus cycles. Four control pins dictate the data flow in and out of the flash

component: CE#, OE#, WE#, and RP#. Table 3 summarizes these bus operations.

28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3

NOTES:

1. 8-bit devices use only DQ[0:7], 16-bit devices use DQ[0:15].

2. X must be VIL,V

IH for control pins and addresses.

3. See DC Characteristics for VPPLK,V

PP1,V

PP2,V

PP3,V

PP4 voltages.

4. Manufacturer and device codes may also be accessed in read identifier mode (A1–A21 =0).SeeTable 5.

5. Refer to Table 6 for valid DIN during a Write operation.

6. To program or erase the lockable blocks, hold WP# at VIH.

7. RP# must be at GND ± 0.2 V to meet the maximum deep power-down current specified.

3.1.1 Read

The flash memory has four read modes available: read array, read identifier, read status, and read

query. These modes are accessible independent of the VPP voltage. The appropriate Read Mode

command must be issued to the CUI to enter the corresponding mode. Upon initial device power-

up or after exit from reset, the device automatically defaults to read-array mode.

CE# and OE# must be driven active to obtain data at the outputs. CE# is the device selection

control; when active, it enables the flash memory device. OE# is the data output control, and it

drives the selected memory data onto the I/O bus. For all read modes, WE# and RP# must be at

VIH.Figure 8 illustrates a read cycle.

3.1.2 Output Disable

With OE# at a logic-high level (VIH), the device outputs are disabled. Output pins are placed in a

high-impedance state.

3.1.3 Standby

Deselecting the device by bringing CE# to a logic-high level (VIH) places the device in standby

mode, which substantially reduces device power consumption without any latency for subsequent

read accesses. In standby, outputs are placed in a high-impedance state independent of OE#. If

deselected during Program or Erase operation, the device continues to consume active power until

the Program or Erase operation is complete.

3.1.4 Deep Power-Down / Reset

From read mode, RP# at VIL for time tPLPH deselects the memory, places output drivers in a high-

impedance state, and turns off all internal circuits. After return from reset, a time tPHQV is required

until the initial read-access outputs are valid. A delay (tPHWL or tPHEL) is required after return from

reset before a write can be initiated. After this wake-up interval, normal operation is restored. The

CUI resets to read-array mode, and the status register is set to 80H. Figure 10A illustrates this case.

Table 3. Bus Operations(1)

Mode Note RP# CE# OE# WE# DQ0–7 DQ8–15

Read (Array, Status, or Identifier) 2–4 VIH VIL VIL VIH DOUT DOUT

Output Disable 2 VIH VIL VIH VIH HighZ HighZ

Standby 2 VIH VIH X X HighZ HighZ

Reset 2, 7 VIL X X X HighZ HighZ

Write 2, 5–7 VIH VIL VIH VIL DIN DIN

28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3

If RP# is taken low for time tPLPH during a Program or Erase operation, the operation will be

aborted and the memory contents at the aborted location (for a program) or block (for an erase) are

no longer valid, since the data may be partially erased or written. The abort process goes through

the following sequence:

1. When RP# goes low, the device shuts down the operation in progress, a process that takes time

tPLRH to complete.

2. After this time tPLRH, the part will either reset to read-array mode (if RP# has gone high during

tPLRH,Figure 10B), or enter reset mode (if RP# is still logic low after tPLRH,Figure 10C).

3. In both cases, after returning from an aborted operation, the relevant time tPHQV or tPHWL/

tPHEL must be waited before a Read or Write operation is initiated, as discussed in the previous

paragraph. However, in this case, these delays are referenced to the end of tPLRH rather than

when RP# goes high.

As with any automated device, it is important to assert RP# during system reset. When the system

comes out of reset, the processor expects to read from the flash memory. Automated flash

memories provide status information when read during program or Block-Erase operations. If a

CPU reset occurs with no flash memory reset, proper CPU initialization may not occur because the

flash memory may be providing status information instead of array data. Intel®Flash memories

allow proper CPU initialization following a system reset through the use of the RP# input. In this

application, RP# is controlled by the same RESET# signal that resets the system CPU.

3.1.5 Write

A write occurs when both CE# and WE# are low and OE# is high. Commands are written to the

Command User Interface (CUI) using standard microprocessor write timings to control Flash

operations. The CUI does not occupy an addressable memory location. The address and data buses

are latched on the rising edge of the second WE# or CE# pulse, whichever occurs first. Figure 9

illustrates a Program and Erase operation. Table 6 shows the available commands, and Appendix A

provides detailed information on moving between the different modes of operation using CUI

commands.

Two commands modify array data: Program (40H), and Erase (20H). Writing either of these

commands to the internal Command User Interface (CUI) initiates a sequence of internally timed

functions that culminate in the completion of the requested task (unless that operation is aborted by

either RP# being driven to VIL for tPLRH or an appropriate Suspend command).

3.2 Modes of Operation

The flash memory has four read modes (read array, read identifier, read status, and read query; see

Appendix B), and two write modes (program and block erase). Three additional modes (erase

suspend to program, erase suspend to read, and program suspend to read) are available only during

suspended operations. Table 4 summarizes the commands used to reach these modes. Appendix A

is a comprehensive chart showing the state transitions.

3.2.1 Read Array

When RP# transitions from VIL (reset) to VIH, the device defaults to read-array mode and will

respond to the read-control inputs (CE#, address inputs, and OE#) without any additional CUI

commands.

28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3

When the device is in read-array mode, four control signals control data output.

•WE# must be logic high (VIH)

•CE# must be logic low (VIL)

•OE# must be logic low (VIL)

•RP# must be logic high (VIH)

In addition, the address of the preferred location must be applied to the address pins. If the device is

not in read-array mode, as would be the case after a Program or Erase operation, the Read Array

command (FFH) must be written to the CUI before array reads can occur.

NOTE: See Appendix A for mode transition information.

Table 4. Command Codes and Descriptions

Code Device Mode Description

00, 01,

60, 2F,

C0, 98

Invalid/

Reserved

Unassigned commands that should not be used. Intel reserves the right to redefine these

codes for future functions.

FF Read Array Places the device in read-array mode, such that array data will be output on the data pins.

40 Program Set-Up

This is a two-cycle command. The first cycle prepares the CUI for a program operation. The

second cycle latches addresses and data information and initiates the WSM to execute the

program algorithm. The flash outputs status register data when CE# or OE# is toggled. A Read

Array command is required after programming to read array data. See Section 3.2.4.

10 Alternate

Program Set-Up (See 40H/Program Set-Up)

20 Erase Set-Up

Prepares the CUI for the Erase Confirm command. If the next command is not an Erase

Confirm command, then the CUI will (a) set both SR.4 and SR.5 of the status register to a “1,”

(b) place the device into the read-status-register mode, and (c) wait for another command. See

Section 3.2.5.

Erase Confirm

Program / Erase

Resume

If the previous command was an Erase Set-Up command, then the CUI will close the address

and data latches, and begin erasing the block indicated on the address pins. During erase, the

device will only respond to the Read Status Register and Erase Suspend commands. The

device will output status-register data when CE# or OE# is toggled.

If a Program or Erase operation was previously suspended, this command will resume that

operation.

B0 Program / Erase

Suspend

Issuing this command will begin to suspend the currently executing Program/Erase operation.

The status register will indicate when the operation has been successfully suspended by

setting either the program suspend (SR.2) or erase suspend (SR.6), and the WSM status bit

(SR.7) to a “1” (ready). The WSM will continue to idle in the SUSPEND state, regardless of the

state of all input-control pins except RP#, which will immediately shut down the WSM and the

remainderofthechip,ifitisdriventoV

IL.SeeSection 3.2.4.1 and Section 3.2.4.1.

70 Read Status

This command places the device into read-status-register mode. Reading the device will output

the contents of the status register, regardless of the address presented to the device. The

device automatically enters this mode after a Program or Erase operation has been initiated.

See Section 3.2.3.

50 Clear Status

The WSM can set the block-lock status (SR.1), VPP status (SR.3), program status (SR.4), and

erase status (SR.5) bits in the status register to “1,” but it cannot clear them to “0.” Issuing this

command clears those bits to “0.”

90 Read Identifier

Puts the device into the intelligent-identifier-read mode, so that reading the device will output

the manufacturer and device codes (A0= 0 for manufacturer, A0= 1 for device, all other

address inputs must be 0). See Section Section 3.2.2.

28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3

3.2.2 Read Identifier

To read the manufacturer and device codes, the device must be in read-identifier mode, which can

be reached by writing the Read Identifier command (90H). Once in read-identifier mode, A0=0

outputs the manufacturer’s identification code, and A0= 1 outputs the device identifier (see

Table 5) Note: A1–A21 = 0. To return to read-array mode, write the Read-Array command (FFH).

3.2.3 Read Status Register

The device status register indicates when a Program or Erase operation is complete, and the success

or failure of that operation. To read the status register, issue the Read Status Register (70H)

command to the CUI. This causes all subsequent Read operations to output data from the status

Read Array (FFH) command.

The status-register bits are output on DQ0–DQ7. The upper byte, DQ8–DQ15, outputs 00H during a

Read Status Register command.

The contents of the status register are latched on the falling edge of OE# or CE#, which prevents

possible Bus errors that might occur if status-register contents change while being read. CE# or

OE# must be toggled with each subsequent status read, or the status register will not indicate

completion of a Program or Erase operation.

When the WSM is active, SR.7 will indicate the status of the WSM; the remaining bits in the status

Table 7 on page 17).

3.2.3.1 Clearing the Status Register

The WSM sets status bits 1 through 7 to “1,” and clears bits 2, 6, and 7 to “0,” but cannot clear

status bits 1 or 3 through 5 to “0.” Because bits 1, 3, 4, and 5 indicate various error conditions,

these bits can be cleared only through the Clear Status Register (50H) command. By allowing the

system software to control the resetting of these bits, several operations may be performed (such as

cumulatively programming several addresses or erasing multiple blocks in sequence) before

Table 5. Read Identifier Table

Size Mfr. ID

Device Identifier

-T

(Top Boot)

-B

(Bottom Boot)

28F004B3

0089H

D4H D5H

28F400B3 8894H 8895H

28F008B3

0089H

D2H D3H

28F800B3 8892H 8893H

28F016B3 D0H D1H

28F160B3

0089H

8890H 8891H

28F320B3 8896H 8897H

28F640B3 8898H 8899H

28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3

reading the status register to determine if an error occurred during that series. Clear the status

command must be issued before data can be read from the memory array.

3.2.4 Program Mode

Programming is executed using a two-write sequence. The Program Setup command (40H) is

written to the CUI followed by a second write that specifies the address and data to be

programmed. The WSM will execute a sequence of internally timed events to program preferred

bits of the addressed location, then verify the bits are sufficiently programmed. Programming the

memory results in specific bits within an address location being changed to a “0.” If users attempt

to program “1”s, the memory cell contents do not change and no error occurs.

The status register indicates programming status: while the program sequence executes, status bit 7

is “0.” The status register can be polled by toggling either CE# or OE#. While programming, the

only valid commands are Read Status Register, Program Suspend, and Program Resume.

When programming is complete, the program-status bits should be checked. If the programming

operation was unsuccessful, bit SR.4 of the status register is set to indicate a program failure. If

SR.3 is set, then VPP was not within acceptable limits, and the WSM did not execute the program

command. If SR.1 is set, a program operation was attempted on a locked block and the operation

was aborted.

The status register should be cleared before attempting the next operation. Any CUI instruction can

follow after programming is completed; however, to prevent inadvertent status-register reads, be

sure to reset the CUI to read-array mode.

3.2.4.1 Suspending and Resuming Program

The Program Suspend halts the in-progress program operation to read data from another location of

memory. Once the programming process starts, writing the Program Suspend command to the CUI

requests that the WSM suspend the program sequence (at predetermined points in the program

algorithm). The device continues to output status-register data after the Program Suspend

command is written. Polling status-register bits SR.7 and SR.2 will determine when the program

operation has been suspended (both will be set to “1”). tWHRH1/tEHRH1 specify the program-

suspend latency.

A Read Array command can now be written to the CUI to read data from blocks other than that

which is suspended. The only other valid commands while program is suspended are Read Status

the flash memory, the WSM will continue with the program process and status-register bits SR.2

and SR.7 will automatically be cleared. After the Program Resume command is written, the device

automatically outputs status-register data when read (see Appendix E for Program Suspend and

Resume Flowchart). VPP must remain at the same VPP level used for program while in program-

suspend mode. RP# must also remain at VIH.

3.2.5 Erase Mode

To erase a block, write the Erase Set-up and Erase Confirm commands to the CUI, along with an

address identifying the block to be erased. This address is latched internally when the Erase

Confirm command is issued. Block erasure results in all bits within the block being set to “1.” Only

one block can be erased at a time. The WSM will execute a sequence of internally timed events to

program all bits within the block to “0,” erase all bits within the block to “1,” then verify that all

bits within the block are sufficiently erased. While the erase executes, status bit 7 is a “0.”

28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3

When the status register indicates that erasure is complete, check the erase-status bit to verify that

the Erase operation was successful. If the Erase operation was unsuccessful, SR.5 of the status

the Erase Confirm command was issued, the WSM will not execute the erase sequence; instead,

SR.5 of the status register is set to indicate an Erase error, and SR.3 is set to a “1” to identify that

VPP supply voltage was not within acceptable limits.

After an Erase operation, clear the status register (50H) before attempting the next operation. Any

CUI instruction can follow after erasure is completed; however, to prevent inadvertent status-

3.2.5.1 Suspending and Resuming Erase

Since an Erase operation requires on the order of seconds to complete, an Erase Suspend command

is provided to allow erase-sequence interruption in order to read data from—or program data to—

another block in memory. Once the erase sequence is started, writing the Erase Suspend command

to the CUI requests that the WSM pause the erase sequence at a predetermined point in the erase

algorithm. The status register will indicate if/when the Erase operation has been suspended.

A Read Array/Program command can now be written to the CUI in order to read data from/

program data to blocks other than the one currently suspended. The Program command can

subsequently be suspended to read yet another array location. The only valid commands while

Erase is suspended are Erase Resume, Program, Read Array, Read Status Register, or Read

Identifier. During erase-suspend mode, the chip can be placed in a pseudo-standby mode by taking

CE# to VIH, which reduces active current consumption.

Erase Resume continues the erase sequence when CE# = VIL. As with the end of a standard Erase

operation, the status register must be read and cleared before the next instruction is issued.

NOTES:

PA: Program Address PD: Program Data BA: Block Address

IA: Identifier Address ID: Identifier Data SRD: Status Register Data

1. Bus operations are defined in Table 3.

2. Following the Intelligent Identifier command, two Read operations access manufacturer and device codes.

A0= 0 for manufacturer code, A0= 1 for device code. A1–A21 =0.

3. Either 40H or 10H command is valid although the standard is 40H.

4. When writing commands to the device, the upper data bus [DQ 8–DQ15] should be either VIL or VIH,to

minimize current draw.

Table 6. Command Bus Definitions (1,4)

First Bus Cycle Second Bus Cycle

Command Notes Oper Addr Data Oper Addr Data

Read Array Write X FFH

Read Identifier 2 Write X 90H Read IA ID

Read Status Register Write X 70H Read X SRD

Clear Status Register Write X 50H

Program 3 Write X 40H /

10H Write PA PD

Block Erase/Confirm Write X 20H Write BA D0H

Program/Erase Suspend Write X B0H

Program/Erase Resume Write X D0H

28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3

NOTE: A Command Sequence Error is indicated when SR.4, SR.5, and SR.7 are set.

3.3 Block Locking

The 3-Volt Advanced Boot Block flash memory architecture features two hardware-lockable

parameter blocks.

3.3.1 WP# = VIL for Block Locking

The lockable blocks are locked when WP# = VIL; any program or Erase operation to a locked

block will result in an error, which will be reflected in the status register. For top configuration, the

top two parameter blocks (blocks #133 and #134 for the 64 Mbit, #69 and #70 for the 32 Mbit,

blocks #37 and #38 for the 16 Mbit, blocks #21 and #22 for the 8 Mbit, blocks #13 and #14 for the

4 Mbit) are lockable. For the bottom configuration, the bottom two parameter blocks (blocks #0

and #1 for 4 /8 /16 /32/64 Mbit) are lockable. Unlocked blocks can be programmed or erased

normally (unless VPP is below VPPLK).

Table 7. Status Register Bit Definition

WSMS ESS ES PS VPPS PSS BLS R

76543210

NOTES:

SR.7 = WRITE STATE MACHINE STATUS (WSMS)

1=Ready

0=Busy

Check Write State Machine bit first to determine word program

or block-erase completion, before checking program or erase-

status bits.

SR.6 = ERASE-SUSPEND STATUS (ESS)

1 = Erase Suspended

0 = Erase In Progress/Completed

When erase suspend is issued, WSM halts execution and sets

both WSMS and ESS bits to “1.” ESS bit remains set at “1” until

an Erase Resume command is issued.

SR.5 = ERASE STATUS (ES)

1=ErrorInBlockErasure

0 = Successful Block Erase

When this bit is set to “1,” WSM has applied the max. number

of erase pulses to the block and is still unable to verify

successful block erasure.

SR.4 = PROGRAM STATUS (PS)

1=ErrorinWordProgram

0 = Successful Word Program

When this bit is set to “1,” WSM has attempted but failed to

program a word.

SR.3 = VPP STATUS (VPPS)

1=V

PP Low Detect, Operation Abort

0=V

PP OK

The VPP status bit does not provide continuous indication of

VPP level. The WSM interrogates VPP level only after the

Program or Erase command sequences have been entered,

and informs the system if VPP has not been switched on. The

VPP is also checked before the operation is verified by the

WSM. The VPP status bit is not guaranteed to report accurate

feedback between VPPLK max and VPP1 min or between VPP1

max and VPP4 min.

SR.2 = PROGRAM SUSPEND STATUS (PSS)

1 = Program Suspended

0 = Program in Progress/Completed

When program suspend is issued, WSM halts execution and

sets both WSMS and PSS bits to “1.” PSS bit remains set to “1”

until a Program Resume command is issued.

SR.1 = BLOCK LOCK STATUS

1 = Program/Erase attempted on locked block;

Operation aborted

0 = No operation to locked blocks

If a Program or Erase operation is attempted to one of the

locked blocks, this bit is set by the WSM. The operation

specifiedisabortedandthedeviceisreturnedtoreadstatus

mode.

SR.0 = RESERVED FOR FUTURE ENHANCEMENTS (R) This bit is reserved for future use and should be masked out

when polling the status register.

28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3

3.3.2 WP# = VIH for Block Unlocking

WP# = VIH unlocks all lockable blocks.

These blocks can now be programmed or erased.

Note that RP# does not override WP# locking as in previous Boot Block devices. WP# controls all

block locking and VPP provides protection against spurious writes. Table 8 defines the write-

protection methods.

3.4 VPP Program and Erase Voltages

Intel®3-Volt Advanced Boot Block products provide in-system programming and erase at 2.7 V.

For customers requiring fast programming in their manufacturing environment, 3-Volt Advanced

Boot Block includes an additional low-cost 12-V programming feature.

The 12-V VPP mode enhances programming performance during the short period of time typically

found in manufacturing processes; however, it is not intended for extended use. 12 V may be

applied to VPP during program and Erase operations for a maximum of 1000 cycles on the main

blocks, and 2500 cycles on the parameter blocks. VPP maybeconnectedto12Vforatotalof80

hours maximum.

Warning: Stressing the device beyond these limits may cause permanent damage.

During Read operations or idle times, VPP may be tied to a 5-V supply. For Program and Erase

operations, a 5-V supply is not permitted. The VPP must be supplied with either 2.7 V–3.6 V or

11.4 V–12.6 V during Program and Erase operations.

3.4.1 VPP =V

IL for Complete Protection

The VPP programming voltage can be held low for complete write protection of all blocks in the

flash device. When VPP is below VPPLK, any Program or Erase operation will result in a error,

prompting the corresponding status-register bit (SR.3) to be set.

3.5 Power Consumption

Intel flash devices have a tiered approach to power savings that can significantly reduce overall

system power consumption. The Automatic Power Savings (APS) feature reduces power

consumption when the device is selected but idle. If the CE# is deasserted, the flash enters its

standby mode, where current consumption is even lower. The combination of these features can

minimize memory power consumption, and therefore, overall system power consumption.

Table 8. Write-Protection Truth Table for the Advanced Boot Block Flash Memory Family

VPP WP# RP# Write Protection Provided

XXV

IL All Blocks Locked

VIL XV

IH All Blocks Locked

≥VPPLK VIL VIH Lockable Blocks Locked

≥VPPLK VIH VIH All Blocks Unlocked

28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3

3.5.1 Active Power

With CE# at a logic-low level and RP# at a logic-high level, the device is in the active mode. Refer

to the DC Characteristic tables for ICC current values. Active power is the largest contributor to

overall system power consumption. Minimizing the active current could have a profound effect on

system power consumption, especially for battery-operated devices.

3.5.2 Automatic Power Savings (APS)

Automatic Power Savings provides low-power operation during read mode. After data is read from

the memory array and the address lines are quiescent, APS circuitry places the device in a mode

where typical current is comparable to ICCS. The flash stays in this static state with outputs valid

until a new location is read.

3.5.3 Standby Power

With CE# at a logic-high level (VIH) and the device in read mode, the flash memory is in standby

mode, which disables much of the device circuitry, and substantially reduces power consumption.

Outputs are placed in a high-impedance state independent of the status of the OE# signal. If CE#

transitions to a logic-high level during Erase or Program operations, the device will continue to

perform the operation and consume corresponding active power until the operation is completed.

System engineers should analyze the breakdown of standby time versus active time, and quantify

the respective power consumption in each mode for their specific application. This approach will

provide a more accurate measure of application-specific power and energy requirements.

3.5.4 Deep Power-Down Mode

The deep power-down mode is activated when RP# = VIL (GND ±0.2 V). During read modes,

RP# going low de-selects the memory and places the outputs in a high-impedance state. Recovery

from deep power-down requires a minimum time of tPHQV (see AC Characteristics—Read

Operations, Section 4.5).

During program or erase modes, RP# transitioning low will abort the in-progress operation. The

memory contents of the address being programmed or the block being erased are no longer valid as

the data integrity has been compromised by the abort. During deep power-down, all internal

circuits are switched to a low-power savings mode (RP# transitioning to VIL or turning off power

to the device clears the status register).

3.6 Power and Reset Considerations

3.6.1 Power-Up/Down Characteristics

In order to prevent any condition that may result in a spurious write or erase operation, it is

recommended to power-up VCC and VCCQ together. Conversely, VCC and VCCQ must power-down

together. It is also recommended to power-up VPP with or slightly after VCC. Conversely, VPP must

powerdown with or slightly before VCC.

If VCCQ and/or VPP are not connected to the VCC supply, then VCC should attain VCCMin before

applying VCCQ and VPP. Device inputs should not be driven before supply voltage = VCCMin.

Power supply transitions should only occur when RP# is low.

28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3

3.6.2 RP# Connected to System Reset

The use of RP# during system reset is important with automated program/erase devices because the

system expects to read from the flash memory when it exits reset. If a CPU reset occurs without a

flash memory reset, proper CPU initialization will not occur because the flash memory may be

providing status information instead of array data. Intel recommends connecting RP# to the system

CPU RESET# signal to allow proper CPU/flash initialization following system reset.

System designers must guard against spurious writes when VCC voltages are above VLKO. Because

both WE# and CE# must be low for a command write, driving either signal to VIH will inhibit

writes to the device. The CUI architecture provides additional protection since alteration of

memory contents can occur only after successful completion of the two-step command sequences.

The device is also disabled until RP# is brought to VIH, regardless of the state of its control inputs.

By holding the device in reset (RP# connected to system POWERGOOD) during power-up/down,

invalid bus conditions during power-up can be masked, providing yet another level of memory

protection.

3.6.3 VCC,V

PP and RP# Transitions

The CUI latches commands as issued by system software and is not altered by VPP or CE#

transitions or WSM actions. Its default state upon power-up, after exit from reset mode or after

VCC transitions above VLKO (Lockout voltage), is read-array mode.

After any program or Block-Erase operation is complete (even after VPP transitions down to

VPPLK), the CUI must be reset to read-array mode via the Read Array command if access to the

flash-memory array is required.

3.7 Power Supply Decoupling

Flash memory power-switching characteristics require careful device decoupling. System

designers should consider the following three supply current issues:

1. Standby current levels (ICCS)

2. Read current levels (ICCR)

3. Transient peaks produced by falling and rising edges of CE#.

Transient current magnitudes depend on the device outputs’ capacitive and inductive loading. Two-

line control and proper decoupling capacitor selection will suppress these transient voltage peaks.

Each flash device should have a 0.1 µF ceramic capacitor connected between each VCC and GND,

and between its VPP and GND. These high-frequency, inherently low-inductance capacitors should

be placed as close as possible to the package leads.

28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3

4.0 Electrical Specifications

4.1 Absolute Maximum Ratings

NOTES:

1. Minimum DC voltage is -0.5 V on input/output pins, with allowable undershoot to -2.0 V for periods <20 ns.

Maximum DC voltage on input/output pins is VCC +0.5 V, with allowable overshoot to VCC +1.5 for periods of

<20 ns

2.MaximumDCvoltageonV

PP may overshoot to +14.0 V for periods <20 ns.

3. VPP Program voltage is normally 2.7 V–3.6 V. Connection to a 11.4 V–12.6 V supply can be done for a

maximum of 1000 cycles on the main blocks and 2500 cycles on the parameter blocks during program/erase.

VPP may be connected to 12 V for a total of 80 hours maximum. See Section 3.4 for details.

4. Minimum DC voltage is -0.5 V on VCC and VCCQ, with allowable undershoot to -2.0 V for periods <20 ns.

MaximumDCvoltageonV

CC and VCCQ pins is VCC +0.5 V, with allowable overshoot to VCC +1.5 for periods

of <20 ns.

5. Output shorted for no more than one second. No more than one output shorted at a time.

Warning: Stressing the device beyond the “Absolute Maximum Ratings” may cause permanent damage.

These are stress ratings only. Operation beyond the “Operating Conditions” is not recommended

and extended exposure beyond the “Operating Conditions” may affect device reliability.

Parameter Maximum Rating

Extended Operating Temperature

During Read –40 °C to +85 °C

During Block Erase and Program –40 °C to +85 °C

Temperature under Bias –40 °C to +85 °C

Storage Temperature –65 °C to +125 °C

VoltageOnAnyPin(exceptV

CC,V

CCQ and VPP)withRespecttoGND –0.5Vto+3.7V

(1)

VPP Voltage (for Block Erase and Program) with Respect to GND –0.5 V to +13.5 V(1,2,3)

VCC and VCCQ Supply Voltage with Respect to GND –0.2 V to +3.7 V(4)

Output Short Circuit Current 100 mA(5)

NOTICE: This datasheet contains preliminary information on new products in production. Specifications are

subject to change without notice. Verify with your local Intel Sales office that you have the latest datasheet before

finalizing a design.

28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3

4.2 Operating Conditions

NOTES:

1. VCC1,V

CCQ1,andV

PP3 must share the same supply when all three are between 2.7 V and 3.6 V.

2. VCCMax is 3.3 V on 0.25µm 32-Mbit devices.

3. During Read operations or idle time, 5 V may be applied to VPP indefinitely. VPP must be at valid levels for

Program and Erase operations

4. Applying VPP = 11.4 V–12.6 V during a program/erase can only be done for a maximum of 1000 cycles on

the main blocks and 2500 cycles on the parameter blocks. VPP maybeconnectedto12Vforatotalof

80 hours maximum. See Section 3.4 for details.

4.3 Capacitance

TA=25°C,f=1MHz

NOTE: Sampled, not 100% tested.

Symbol Parameter Notes Min Max Units

TAOperating Temperature –40 +85 °C

VCC1

VCC Supply Voltage

1, 2 2.7 3.6

VoltsVCC2 2.7 2.85

VCC3 2.7 3.3

VCCQ1

I/O Supply Voltage

12.73.6

VoltsVCCQ2 1.65 2.5

VCCQ3 1.8 2.5

VPP1

Program and Erase Voltage

12.73.6

Volts

VPP2 2.7 2.85

VPP3 2.7 3.3

VPP4 3, 4 11.4 12.6

Cycling Block Erase Cycling 4 100,000 Cycles

Sym Parameter Notes Typ Max Units Conditions

CIN Input Capacitance 1 6 8 pF VIN =0V

COUT Output Capacitance 1 10 12 pF VOUT =0V

28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3

4.4 DC Characteristics

Sym Parameter

VCC 2.7 V–3.6 V 2.7 V–2.85 V 2.7 V–3.3 V

Unit Test ConditionsVCCQ 2.7 V–3.6 V 1.65 V–2.5 V 1.8 V–2.5 V

Note Typ Ma x Typ Max Typ Max

ILI Input Load Current 1,2 ±1±1±1µA

VCC =V

CCMax

VCCQ =V

CCQMax

VIN =V

CCQ or GND

ILO Output Leakage Current 1,2 0.2 ±10 0.2 ±10 0.2 ±10 µA

VCC =V

CCMax

VCCQ =V

CCQMax

VIN =V

CCQ or GND

ICCS

VCC Standby Current for

0.13 and 0.18 Micron

Product

1 7 15 20 50 150 250 µA

VCC =V

CCMax

CE# = RP# = VCCQ

or during Program/

Erase Suspend

WP# = VCCQ or GND

VCC Standby Current for

0.25 Micron Product 1 18352050150250µA

ICCD

VCC Power-Down Current

for 0.13 and 0.18 Micron

Product

1,2 7 15 7 20 7 20 µA VCC =V

CCMax

VCCQ =V

CCQMax

VIN =V

CCQ or GND

RP#=GND±0.2V

VCC Power-Down Current

for 0.25 Product 1,2 7 25 7 25 7 25 µA

ICCR

VCC Read Current for

0.13 and 0.18 Micron

Product

1,2,3 9 18 8 15 9 15 mA VCC =V

CCMax

VCCQ =V

CCQMax

OE# = VIH ,CE#=V

f=5MHz,I

OUT=0 mA

Inputs = VIL or VIH

VCC Read Current for

0.25 Micron Product 1,2,3 10 18 8 15 9 15 mA

IPPD

VPP Deep Power-Down

Current 1 0.2 5 0.2 5 0.2 5 µA RP#=GND±0.2V

VPP ≤VCC

ICCW

VCC Program Current for

0.13 and 0.18 Micron

Product

1,4

18 55 18 55 18 55 mA VPP =V

PP1,2,3

Program in Progress

8 1510301030mA

VPP =V

PP4 (12v) ,

Program in Progress

VCC Program Current for

0.25 Micron Product 1,4

18 55 18 55 18 55 mA VPP =V

PP1,2,3

Program in Progress

10 30 10 30 10 30 mA VPP =V

PP4 (12v) ,

Program in Progress

ICCE VCC Erase Current 1,4

16 45 21 45 21 45 mA VPP =V

PP1,2,3

EraseinProgress

8 1516451645mA

VPP =V

PP4 (12v) ,

EraseinProgress

ICCES

VCC Erase Suspend

Current 1,4 7 15 50 200 150 250 µA CE# = VCC, Erase

Suspend in Progress

IPPR VPP Read Current 1,4

2±15 2 ±15 2 ±15 µA VPP ≤VCC

50 200 50 200 50 200 µA VPP >V

IPPW VPP Program Current 1,4

0.05 0.1 0.05 0.1 0.05 0.1 mA VPP =V

PP1,2,3

Program in Progress

822822822mA

VPP =V

PP4 (12v) ,

Program in Progress

28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3

IPPE VPP Erase Current 1,4

0.05 0.1 0.05 0.1 0.05 0.1 mA VPP =V

PP1, 2, 3

EraseinProgress

8 2216451645mA

VPP =V

PP4 (12v) ,

EraseinProgress

IPPES

VCC Erase Suspend

Current 1,4

0.2 5 0.2 5 0.2 5 µA

VPP =V

PP1, 2, 3

Program or Erase

SuspendinProgress

50 200 50 200 50 200 µA

VPP =V

PP4 (12v) ,

Program or Erase

SuspendinProgress

IPPWS

VPP Program Suspend

Current 1,4

0.2 5 0.2 5 0.2 5 µA

VPP =V

PP1, 2, 3

Program or Erase

SuspendinProgress

50 200 50 200 50 200 µA

VPP =V

PP4 (12v) ,

Program or Erase

SuspendinProgress

Sym Parameter

VCC 2.7 V–3.6 V 2.7 V–2.85 V 2.7 V–3.3 V

Unit Test ConditionsVCCQ 2.7 V–3.6 V 1.65 V–2.5 V 1.8 V–2.5 V

Note Typ Max Typ Max Typ Max

28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3

NOTES:

1. All currents are in RMS unless otherwise noted. Typical values at nominal VCC,T

A= +25 °C.

2. Since each column lists specifications for a different VCC and VCCQ voltage range combination, the test conditions VCCMax,

VCCQMax, VCCMin, and VCCQMin refer to the maximum or minimum VCC or VCCQ voltage listed at the top of each column.

VCCMaxis3.3Von0.25µm 32-Mbit devices.

3. Automatic Power Savings (APS) reduces ICCR to approximately standby levels in static operation.

4. Sampled, not 100% tested.

5. Erase and program are inhibited when VPP <V

PPLK and not guaranteed outside the valid VPP ranges of VPP1,V

PP2, VPP3

and VPP4. For Read operations or during idle time, a 5 V supply may be applied to VPP indefinitely. However, VPP must be at

valid levels for Program and Erase operations.

6. Applying VPP = 11.4 V–12.6 V during program/erase can only be done for a maximum of 1000 cycles on the main blocks and

2500 cycles on the parameter blocks. VPP may be connected to 12 V for a total of 80 hours maximum. See Section 3.4 for

details. For Read operations or during idle time, a 5-V supply may be applied to VPP indefinitely. However, VPP must be at

valid levels for Program and Erase operations.

7. ICCES and ICCWS are specified with device de-selected. If device is read while in erase suspend, current draw is sum of ICCES

and ICCR. If the device is read while in program suspend, current draw is the sum of ICCWS and ICCR.

0580_05

VIL Input Low Voltage –0.4

VCC

0.22

–0.4 0.4 –0.4 0.4 V

VIH Input High Voltage 2.0 VCCQ

+0.3

VCCQ

–

0.4V

VCCQ

+0.3

VCCQ

–

0.4V

VCCQ

+0.3

VOL Output Low Voltage –0.1 0.1 -0.1 0.1 -0.1 0.1 V

VCC =V

CCMin

VCCQ =V

CCQMin

IOL =100µA

VOH Output High Voltage

VCCQ

–

0.1V

VCCQ

–

0.1V

VCCQ

–

0.1V

VCC =V

CCMin

VCCQ =V

CCQMin

IOH =–100µA

VPPLK VPP Lock-Out Voltage 5 1.5 1.5 1.5 V Complete Write

Protection

VPP1

VPP during Program and

Erase Operations

52.73.6 V

VPP2 5 2.7 2.85 V

VPP3 52.73.3V

VPP4 5,6 11.4 12.6 11.4 12.6 11.4 12.6 V

VLKO

VCC Prog/Erase

Lock Voltage 1.5 1.5 1.5 V

VLKO2

VCCQ Prog/Erase

Lock Voltage 1.2 1.2 1.2 V

Sym Parameter

VCC 2.7 V–3.6 V 2.7 V–2.85 V 2.7 V–3.3 V

Unit Test ConditionsVCCQ 2.7 V–3.6 V 1.65 V–2.5 V 1.8 V–2.5 V

Note Typ Max Typ Ma x Typ Max

Figure 6. Input/Output Reference Waveform

TEST POINTSINPUT OUTPUT

VCCQ

0.0

VCCQ

28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3

NOTE: AC test inputs are driven at VCCQ for a logic “1” and 0.0V for a logic “0.” Input timing begins, and output

timing ends, at VCCQ/2. Input rise and fall times (10%–90%) <10 ns. Worst-case speed conditions are

when VCCQ =V

CCQMin.

0580_06

NOTE: See table for component values.

NOTE: CLincludes jig capacitance.

Figure 7. Test Configuration

Out

CCQ

Device

under

Test

Test Configuration Component Values for Worst

Case Speed Conditions

Test Configuration CL(pF) R1(Ω)R2(Ω)

VCCQ1 Standard Test 50 25 K 25 K

VCCQ2 Standard Test 50 14.5 K 14.5 K

VCCQ3 Standard Test 50 16 K 16 K

28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3

4.5 AC Characteristics —Read Operations

NOTES:

1. OE# may be delayed up to tELQV–tGLQV after the falling edge of CE# without impact on tELQV

2. Sampled, but not 100% tested.

See Figure 8, “AC Waveform: Read Operations” on page 31.

See Figure 6, “Input/Output Reference Waveform” on page 25 for timing measurements and maximum allowable

input slew rate.

#Sym Parameter

Density 8 Mbit

Unit

Product 90 ns 110 ns

VCC 3.0 V–3.6 V 2.7 V–3.6 V 3.0 V–3.6 V 2.7 V–3.6 V

Min Max Min Max Min Max Min Max

R1 tAVAV Read Cycle Time 80 90 100 110 ns

R2 tAVQV Address to Output Delay 80 90 100 110 ns

R3 tELQV CE# to Output Delay(1) 80 90 100 110 ns

R4 tGLQV OE# to Output Delay(1) 30 30 30 30 ns

R5 tPHQV RP# to Output Delay 600 600 600 600 ns

R6 tELQX CE# to Output in Low Z(2) 0000ns

R7 tGLQX OE#toOutputinLowZ

(2) 0000ns

R8 tEHQZ CE# to Output in High Z(2) 25 25 25 25 ns

R9 tGHQZ OE#toOutputinHighZ

(2) 25 25 25 25 ns

R10 tOH

Output Hold from Address,

CE#, or OE# Change,

Whichever Occurs First(2) 0000ns

28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3

AC Characteristics, Continued

NOTES:

1.OE#maybedelayeduptot

ELQV–tGLQV after the falling edge of CE# without impact on tELQV.

2. Sampled, but not 100% tested.

See Figure 8, “AC Waveform: Read Operations” on page 31.

See Figure 6, “Input/Output Reference Waveform” on page 25 for timing measurements and maximum

allowable input slew rate.

#Sym

Para-

meter

Density 16 Mbit

Unit

Product 70 ns 80 ns 90 ns 110 ns

VCC 2.7 V–3.6 V 2.7 V–3.6 V 3.0 V–3.6 V 2.7 V–3.6 V 3.0 V–3.6 V 2.7 V–3.6 V

Min Max Min Max Min Max Min Max Min Max Min Max

R1 tAVAV ReadCycleTime70808090100110ns

R2 tAVQV Address to Output

Delay 70 80 80 90 100 110 ns

R3 tELQV CE# to Output

Delay(1) 70 80 80 90 100 110 ns

R4 tGLQV OE# to Output

Delay(1) 20 20 30 30 30 30 ns

R5 tPHQV RP# to Output Delay 150 150 600 600 600 600 ns

R6 tELQX CE# to Output in

Low Z(2) 000000ns

R7 tGLQX OE# to Output in

Low Z(2) 000000ns

R8 tEHQZ CE# to Output in

High Z(2) 20 20 25 25 25 25 ns

R9 tGHQZ OE# to Output in

High Z(2) 20 20 25 25 25 25 ns

R10 tOH

Output Hold from

Address, CE#, or

OE# Change,

Whichever Occurs

First(2)

000000ns

28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3

AC Characteristics, Continued

NOTES:

1. OE# may be delayed up to tELQV–tGLQV after the falling edge of CE# without impact on tELQV

2. Sampled, but not 100% tested.

See Figure 8, “AC Waveform: Read Operations” on page 31.

See Figure 6, “Input/Output Reference Waveform” on page 25 for timing measurements and maximum

allowable input slew rate.

#Sym

Para-

meter

Density 32 Mbit

Unit

Product 70ns 90ns 100ns 110ns

VCC 2.7 V–3.6 V 2.7 V–3.6 V 3.0 V–3.3 V 2.7 V–3.3 V 3.0 V–3.3 V 2.7 V–3.3 V

Min Max Min Max Min Max Min Max Min Max Min Max

R1 tAVAV Read Cycle Time 70 90 90 100 100 110 ns

R2 tAVQV

Address to Output

Delay 70 90 90 100 100 110 ns

R3 tELQV

CE# to Output

Delay(1) 70 90 90 100 100 110 ns

R4 tGLQV

OE# to Output

Delay(1) 20 20 30 30 30 30 ns

R5 tPHQV

RP# to Output

Delay 150 150 600 600 600 600 ns

R6 tELQX CE# to Output in

Low Z(2) 000000ns

R7 tGLQX

OE# to Output in

Low Z(2) 000000ns

R8 tEHQZ

CE# to Output in

High Z(2) 20 20 25 25 25 25 ns

R9 tGHQZ

OE# to Output in

High Z(2) 20 20 25 25 25 25 ns

R10 tOH

Output Hold from

Address, CE#, or

OE# Change,

Whichever Occurs

First(2)

000000ns

28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3

AC Characteristics, Continued

NOTES:

1.OE#maybedelayeduptot

ELQV–tGLQV after the falling edge of CE# without impact on tELQV.

2. Sampled, but not 100% tested.

See Figure 8 for the AC waveform for Read operations.

See Figure 6, “Input/Output Reference Waveform” on page 25 for timing measurements and maximum

allowable input slew rate.

#Sym Parameter

Density 64 Mbit

Unit

Product 80 ns

VCC 2.7 V–3.6 V

Note Min Max

R1 tAVAV Read Cycle Time 80 ns

R2 tAVQV Address to Output Delay 80 ns

R3 tELQV CE# to Output Delay 1 80 ns

R4 tGLQV OE# to Output Delay 1 20 ns

R5 tPHQV RP# to Output Delay 150 ns

R6 tELQX CE#toOutputinLowZ 2 0 ns

R7 tGLQX OE# to Output in Low Z 2 0 ns

R8 tEHQZ CE#toOutputinHighZ 2 20 ns

R9 tGHQZ OE#toOutputinHighZ 2 20 ns

R10 tOH

Output Hold from Address, CE#, or

OE# Change, Whichever Occurs First 20 ns

28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3

Figure 8. AC Waveform: Read Operations

High Z

Valid Output

Address Stable

Data Valid

Device

Address Selection

Standby

ADDRESSES (A)

VIH

VIL

VIH

VIL

CE# (E)

VIH

VIL

VOH

VOL

VIH

VIL

OE# (G)

WE# (W)

DATA (D/Q)

RP# (P)

High Z

VIH

VIL

R10

28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3

4.6 AC Characteristics —Write Operations

NOTES:

1. Refer to command definition table (Ta bl e 6 )forvalidA

IN or DIN.

2. Write pulse width (tWP) is defined from CE# or WE# going low (whichever goes low last) to CE# or WE# going

high (whichever goes high first). Hence, tWP =t

WLWH =t

ELEH =t

WLEH =t

ELWH. Similarly, write pulse width

high (tWPH) is defined from CE# or WE# going high (whichever goes high first) to CE# or WE# going low

(whichever goes low first). Hence, tWPH =t

WHWL =t

EHEL =t

WHEL =t

EHWL.

3. Sampled, but not 100% tested.

Read timing characteristics during program suspend and erase suspend are the same as during read-only

operations.

See Figure 6 for timing measurements and maximum allowable input slew rate.

See Figure 9, “AC Waveform: Program and Erase Operations” on page 37.

#Sym Parameter

Density 8 Mbit

Unit

Product 90 ns 110 ns

VCC

3.0 V –

3.6 V

2.7 V –

3.6 V

3.0 V –

3.6 V

2.7 V –

3.6 V

Note Min Min Min Min

W1 tPHWL /

tPHEL

RP# High Recovery to WE# (CE#) Going Low 600 600 600 600 ns

W2 tELWL /

tWLEL

CE#(WE#)SetuptoWE#(CE#)GoingLow 0 0 0 0 ns

W3 tELEH /

tWLWH

WE#(CE#)PulseWidth 170707070ns

W4 tDVWH /

tDVEH

Data Setup to WE# (CE#) Going High 2 50 50 60 60 ns

W5 tAVWH /

tAVEH

Address Setup to WE# (CE#) Going High 2 70 70 70 70 ns

W6 tWHEH /

tEHWH

CE# (WE#) Hold Time from WE# (CE#) High 0 0 0 0 ns

W7 tWHDX /

tEHDX

Data Hold Time from WE# (CE#) High 2 0 0 0 0 ns

W8 tWHAX /

tEHAX

Address Hold Time from WE# (CE#) High 2 0 0 0 0 ns

W9 tWHWL /

tEHEL

WE# (CE#) Pulse Width High 1 30 30 30 30 ns

W10 tVPWH /

tVPEH

VPP Setup to WE# (CE#) Going High 3 200 200 200 200 ns

W11 tQVVL VPP Hold from Valid SRD 3 0 0 0 0 ns

28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3

AC Characteristics—Write Operations, continued

NOTES:

1. Refer to command definition table (Tab l e 6 )forvalidA

IN or DIN.

2. Write pulse width (tWP) is defined from CE# or WE# going low (whichever goes low last) to CE# or WE# going

high (whichever goes high first). Hence, tWP =t

WLWH =t

ELEH =t

WLEH =t

ELWH. Similarly, write pulse width

high (tWPH) is defined from CE# or WE# going high (whichever goes high first) to CE# or WE# going low

(whichever goes low first). Hence, tWPH =t

WHWL =t

EHEL =t

WHEL =t

EHWL.

3. Sampled, but not 100% tested.

Read timing characteristics during program suspend and erase suspend are the same as during Read-only

operations.

See Figure 6 for timing measurements and maximum allowable input slew rate.

See Figure 9, “AC Waveform: Program and Erase Operations” on page 37.

#Sym Parameter

Density 16 Mbit

Unit

Product 70 ns 80 ns 90 ns 110 ns

VCC 2.7 V –

3.6 V

2.7 V –

3.6 V

3.0 V –

3.6 V

2.7 V –

3.6 V

3.0 V –

3.6 V

2.7 V –

3.6 V

NoteMinMinMinMinMinMin

W1 tPHWL /

tPHEL

RP#HighRecoverytoWE#(CE#)

Going Low 150 150 600 600 600 600 ns

W2 tELWL /

tWLEL

CE#(WE#)SetuptoWE#(CE#)Going

Low 000000ns

W3 tELEH /

tWLWH WE#(CE#)PulseWidth 1455070707070ns

W4 tDVWH /

tDVEH Data Setup to WE# (CE#) Going High 2 40 40 50 50 60 60 ns

W5 tAVWH /

tAVEH

Address Setup to WE# (CE#) Going

High 2505070707070ns

W6 tWHEH /

tEHWH

CE# (WE#) Hold Time from WE#

(CE#) High 000000ns

W7 tWHDX /

tEHDX Data Hold Time from WE# (CE#) High 2 0 0 0 0 0 0 ns

W8 tWHAX /

tEHAX

Address Hold Time from WE# (CE#)

High 2000000ns

W9 tWHWL /

tEHEL WE# (CE#) Pulse Width High 1 25 30 30 30 30 30 ns

W10 tVPWH /

tVPEH VPP Setup to WE# (CE#) Going High 3 200 200 200 200 200 200 ns

W11 tQVVL VPP HoldfromValidSRD 3000000ns

28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3

AC Characteristics—Write Operations, continued

NOTES:

1. Refer to command definition table (Ta bl e 6 )forvalidA

IN or DIN.

2. Write pulse width (tWP) is defined from CE# or WE# going low (whichever goes low last) to CE# or WE# going

high (whichever goes high first). Hence, tWP =t

WLWH =t

ELEH =t

WLEH =t

ELWH. Similarly, write pulse width

high (tWPH) is defined from CE# or WE# going high (whichever goes high first) to CE# or WE# going low

(whichever goes low first). Hence, tWPH =t

WHWL =t

EHEL =t

WHEL =t

EHWL.

3. Sampled, but not 100% tested.

Read timing characteristics during program suspend and erase suspend are the same as during read-only

operations.

See Figure 6 for timing measurements and maximum allowable input slew rate.

See Figure 9, “AC Waveform: Program and Erase Operations” on page 37.

#Sym Parameter

Density 32 Mbit

Unit

Product 70 ns 90 ns 90 ns 110 ns

VCC 2.7 V –

3.6 V

2.7 V –

3.6 V

3.0 V –

3.3 V

2.7 V –

3.3 V

3.0 V –

3.3 V

2.7 V –

3.3 V

Note Min Min Min Min Min Min

W1 tPHWL /

tPHEL

RP#HighRecoverytoWE#(CE#)

Going Low 150 150 600 600 600 600 ns

W2 tELWL /

tWLEL

CE# (WE#) Setup to WE# (CE#) Going

Low 000000ns

W3 tELEH /

tWLWH WE#(CE#)PulseWidth 1456070707070ns

W4 tDVWH /

tDVEH Data Setup to WE# (CE#) Going High 2 40 40 50 50 60 60 ns

W5 tAVWH /

tAVEH

Address Setup to WE# (CE#) Going

High 2506070707070ns

W6 tWHEH /

tEHWH

CE# (WE#) Hold Time from WE#

(CE#) High 000000ns

W7 tWHDX /

tEHDX DataHoldTimefromWE#(CE#)High2000000ns

W8 tWHAX /

tEHAX

Address Hold Time from WE# (CE#)

High 2000000ns

W9 tWHWL /

tEHEL WE# (CE#) Pulse Width High 1 25 30 30 30 30 30 ns

W10 tVPWH /

tVPEH VPP Setup to WE# (CE#) Going High 3 200 200 200 200 200 200 ns

W11 tQVVL VPP HoldfromValidSRD 3000000ns

28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3

AC Characteristics—Write Operations, continued

NOTES:

1. Refer to command definition table (Tab l e 6 )forvalidA

IN or DIN.

2. Write pulse width (tWP) is defined from CE# or WE# going low (whichever goes low last) to CE# or WE# going

high (whichever goes high first). Hence, tWP =t

WLWH =t

ELEH =t

WLEH =t

ELWH. Similarly, write pulse width

high (tWPH) is defined from CE# or WE# going high (whichever goes high first) to CE# or WE# going low

(whichever goes low first). Hence, tWPH =t

WHWL =t

EHEL =t

WHEL =t

EHWL.

3. Sampled, but not 100% tested.

Read timing characteristics during program suspend and erase suspend are the same as during read-only

operations.

See Figure 6 for timing measurements and maximum allowable input slew rate.

See Figure 9, “AC Waveform: Program and Erase Operations” on page 37.

#Sym Parameter

Density 64 Mbit

Unit

Product 80 ns

VCC

2.7 V –

3.6 V

Note Min

W1 tPHWL /

tPHEL

RP# High Recovery to WE# (CE#) Going Low 150 ns

W2 tELWL /

tWLEL

CE# (WE#) Setup to WE# (CE#) Going Low 0 ns

W3 tELEH /

tWLWH

WE#(CE#)PulseWidth 1 60 ns

W4 tDVWH /

tDVEH

DataSetuptoWE#(CE#)GoingHigh 2 40 ns

W5 tAVWH /

tAVEH

Address Setup to WE# (CE#) Going High 2 60 ns

W6 tWHEH /

tEHWH

CE# (WE#) Hold Time from WE# (CE#) High 0 ns

W7 tWHDX /

tEHDX

Data Hold Time from WE# (CE#) High 2 0 ns

W8 tWHAX /

tEHAX

Address Hold Time from WE# (CE#) High 2 0 ns

W9 tWHWL /

tEHEL

WE#(CE#)PulseWidthHigh 1 30 ns

W10 tVPWH /

tVPEH

VPP Setup to WE# (CE#) Going High 3 200 ns

W11 tQVVL VPP Hold from Valid SRD 3 0 ns

28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3

4.7 Program and Erase Timings

NOTES:

1. Typical values measured at nominal voltages and TA=+25°C.

2. Excludes external system-level overhead.

3. Sampled, not 100% tested.

4. x8 not available on 0.13 and 0.18 µm offerings

Symbol Parameter

VPP 2.7 V–3.6 V 11.4 V–12.6 V

Units

Notes Typ(1) Max Typ(1) Max

tBWPB

8-KB Parameter Block

Program Time (Byte) 2, 3 0.16 0.48 0.08 0.24 s

4-KW Parameter Block

Program Time (Word) 2, 3 0.10 0.30 0.03 0.12 s

tBWMB

64-KB Main Block

Program Time (Byte) 2, 3, 4 1.2 3.7 0.6 1.7 s

32-KW Main Block

Program Time (Word) 2, 3 0.8 2.4 0.24 1 s

tWHQV1 /t

EHQV1

Byte Program Time 2, 3, 4 17 165 8 185 µs

Word Program Time for

0.13 and 0.18 Micron Product 2,3 12 200 8 185 µs

Word Program Time for 0.25

Micron Product 2, 3 22 200 8 185 µs

tWHQV2 /t

EHQV2

8-KB Parameter Block

EraseTime(Byte) 2, 3, 4 1 4 0.8 4 s

4-KW Parameter Block

EraseTime(Word) 2,30.540.44s

tWHQV3 /t

EHQV3

64-KB Main Block

EraseTime(Byte) 2,3,41515s

32-KW Main Block

EraseTime(Word) 2, 3 1 5 0.6 5 s

tWHRH1 /t

EHRH1 Program Suspend Latency 5 10 5 10 µs

tWHRH2 /t

EHRH2 Erase Suspend Latency 5 20 5 20 µs

28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3

0580_08

NOTES:

1. CE# must be toggled low when reading Status Register Data. WE# must be inactive (high) when reading

Status Register Data.

A. VCC Power-Up and Standby.

B. Write Program or Erase Setup Command.

C. Write Valid Address and Data (for Program) or Erase Confirm Command.

D. Automated Program or Erase Delay.

E. Read Status Register Data (SRD): reflects completed Program/Erase operation.

F. Write Read Array Command.

Figure 9. AC Waveform: Program and Erase Operations

ADDRESSES [A]

CE#(WE#) [E(W)]

OE# [G]

WE#(CE#) [W(E)]

DATA [D/Q]

RP# [P]

AIN

Valid

SRD

High Z

V[V]

PPH

PPLK

PPH

WP#

AB C D E F

W10 W11

(Note 1)

28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3

5.0 Reset Operations

0580_09

NOTES:

1. If tPLPH is <100 ns the device may still RESET but this is not guaranteed

2. .Sampled, but not 100% tested.

3. If RP# is asserted while a block erase or word program operation is not executing, the reset will complete

within 100 ns.

Figure 10. AC Waveform: Deep Power-Down/Reset Operation

RP# (P)

PLPH

RP# (P)

PLPH

(A) Reset during Read Mode

Abort

Complete PHQV

PHWL

PHEL

PHQV

PHWL

PHEL

(B) Reset during Program or Block Erase, <

PLPH

tPLR

PLRH

RP# (P)

PLPH

Abort

Complete PHQV

PHWL

PHEL

PLRH

Deep

Power-

Down

PLPH

tPLRH

Reset Specifications

Symbol Parameter Notes

VCC = 2.7 V–3.6 V

Unit

Min Max

tPLPH

RP# Low to Reset during Read

(If RP# is tied to VCC, this specification is not applicable) 1,2 100 ns

tPLRH RP# Low to Reset during Block Erase or Program 2,3 22 µs

28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3

6.0 Ordering Information

Figure 11. Ordering Information

Product line designator

for all Intel®Flash products

2 8 F 3 2 0 3 T C 7 0

Package

TE = 48-Lead TSOP

GT = 48-Ball µBGA* CSP

GE = VF BGA CSP

T E B

Device Density

640 = x16 (64 Mbit)

320 = x16 (32 Mbit)

160 = x16 (16 Mbit)

800 = x16 (8 Mbit)

016 = x8 (16 Mbit)

008 = x8 (8 Mbit)

Lithography

Not Present = 0.4 µm

A = 0.25 µm

C = 0.18 µm

D = 0.13 µm

Product Family

B3 = 3 Volt Advanced+ Boot Block

VCC =2.7V–3.6V

VPP =2.7V–3.6Vor

11.4 V–12.6 V

T=Top Blocking

B=Bottom Blocking

Access Speed (ns)

(70, 80, 90, 100, 110)

28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3

Table 9. Ordering Information Valid Combinations

1. The 48-ball µBGA package top side mark reads F160B3. This mark is identical for both x8 and x16 products.

All product shipping boxes or trays provide the correct information regarding bus architecture. However, once

the devices are removed from the shipping media, it may be difficult to differentiate based on the top side

mark. The device identifier (accessible through the Device ID command: see Section 3.2.2 for further details)

enables x8 and x16 µBGA package product differentiation.

2. The second line of the 48-ball µBGA package top side mark specifies assembly codes. For samples only, the

first character signifies either “E” for engineering samples or “S” for silicon daisy-chain samples. All other

assembly codes without an “E” or “S” as the first character are production units.

3. Intel recommends using .18 µm Advanced Boot Block Products.

40-Lead TSOP 48-Lead TSOP 48-Ball µBGA CSP(1,2) 48-Ball VF BGA

Ext. Temp. 64 Mbit TE28F640B3TC80

TE28F640B3BC80

GE28F640B3TC80

GE28F640B3BC80

Ext. Temp. 32 Mbit TE28F320B3TC70

TE28F320B3BC70

TE28F320B3TC90

TE28F320B3BC90

TE28F320B3TA100

TE28F320B3BA100

TE28F320B3TA110

TE28F320B3BA110

GE28F320B3TD70

GE28F320B3BD70

GE28F320B3TC70

GE28F320B3BC70

GE28F320B3TC90

GE28F320B3BC90

Ext. Temp. 16 Mbit

TE28F016B3TA90

TE28F016B3BA90

TE28F016B3TA110

TE28F016B3BA110

TE28F160B3TD70

TE28F160B3BD70

TE28F160B3TC70

TE28F160B3BC70

TE28F160B3TC80

TE28F160B3BC80

TE28F160B3TC90

TE28F160B3BC90

TE28F160B3TA90

TE28F160B3BA90

TE28F160B3TA110

TE28F160B3BA110

GT28F160B3TA90(3)

GT28F160B3BA90(3)

GT28F160B3TA110(3)

GT28F160B3BA110(3)

GE28F160B3TD70

GE28F160B3BD70

GE28F160B3TC70

GE28F160B3BC70

GE28F160B3TC80

GE28F160B3BC80

GE28F160B3TC90

GE28F160B3BC90

Ext. Temp. 8 Mbit

TE28F008B3TA90

TE28F008B3BA90

TE28F008B3TA110

TE28F008B3BA110

TE28F800B3TA90

TE28F800B3BA90

TE28F800B3TA110

TE28F800B3BA110

GE28F800B3TA70

GE28F800B3BA70

GE28F008B3TA70

GE28F008B3BA70

GE28F800B3TA90

GE28F800B3BA90

GE28F008B3TA90

GE28F008B3BA90

28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3

7.0 Additional Information

NOTES:

1. Please call the Intel Literature Center at (800) 548-4725 to request Intel documentation. International

customers should contact their local Intel or distribution sales office.

2. Visit Intel’s World Wide Web home page at http://www.Intel.com or http://developer.intel.com for technical

documentation and tools.

3. For the most current information on Intel Advanced and Advanced+ Boot Block Flash memory, visit our

microsite at http://developer.intel.com/design/flash/abblock.

Order Number Document/Tool

297948 3 Volt Advanced Boot Block Flash Memory Family Specification Update

292199 AP-641 Achieving Low Power with the 3 Volt Advanced Boot Block Flash Memory

292200 AP-642 Designing for Upgrade to the 3 Volt Advanced Boot Block Flash Memory

Note 2 3 Volt Advanced Boot Block Algorithms (‘C’ and assembly)

http://developer.intel.com/design/flash/swtools

Contact your Intel Representative Intel®Flash Data Integrator (IFDI) Software Developer’s Kit

297874 IFDI Interactive: Play with Intel®Flash Data Integrator on Your PC

28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3

Appendix A Write State Machine Current/Next States

Command Input (and Next State)

Current State SR.7

Data

When

Read

Array

(FFH)

Program

Setup (10/

40H)

Erase

Setup

(20H)

Erase

Confirm

(D0H)

Prog/Ers

Suspend

(B0H)

Prog/Ers

Resume

(D0H)

Read

Status

(70H)

Clear

Status

(50H)

Read

Identifier.

(90H)

Read Array “1” Array Read

Array

Program

Setup

Erase

Setup Read Array Read

Status

Read

Array

Read

Identifier

Read Status “1” Status Read

Array

Program

Setup

Erase

Setup Read Array Read

Status

Read

Array

Read

Identifier

Read

Identifier “1” Identifier Read

Array

Program

Setup

Erase

Setup Read Array Read

Status

Read

Array

Read

Identifier

Prog. Setup “1” Status Program (Command Input = Data to be Programmed)

Program

(continue) “0” Status Program (continue)

Prog.

Sysop. to

Rd. Status

Program (continue)

Program

Suspend to

Read Status

“1” Status

Prog.

Susp. to

Read

Array

Program Suspend

to Read Array

Program

(continue)

Program

Susp. to

Read Array

Program

(continue)

Prog.

Susp. to

Read

Status

Prog.

Susp. to

Read

Array

Prog.

Susp. to

Read

Identifier

Program

Suspend to

Read Array

“1” Array

Prog.

Susp. to

Read

Array

Program Suspend

to Read Array

Program

(continue)

Program

Susp. to

Read Array

Program

(continue)

Prog.

Susp. to

Read

Status

Prog.

Sus. to

Read

Array

Prog.

Susp. to

Read

Identifier

Prog. Susp. to

Read

Identifier

“1” Identifier

Prog.

Susp. to

Read

Array

Program Suspend

to Read Array

Program

(continue)

Program

Susp. to

Read Array

Program

(continue)

Prog.

Susp. to

Read

Status

Prog.

Sus. to

Read

Array

Prog.

Susp. to

Read

Identifier

Program

(complete) “1” Status Read

Array

Program

Setup

Erase

Setup Read Array Read

Status

Read

Array

Read

Identifier

Erase Setup “1” Status Erase Command Error Erase

(continue)

Erase

Cmd. Error

Erase

(continue) Erase Command Error

Erase Cmd.

Error “1” Status Read

Array

Program

Setup

Erase

Setup Read Array Read

Status

Read

Array

Read

Identifier

Erase

(continue) “0” Status Erase (continue)

Erase Sus.

to Read

Status

Erase (continue)

Erase

Suspend to

Status

“1” Status

Erase

Susp. to

Read

Array

Program

Setup

Erase

Susp. to

Read

Array

Erase

Susp. to

Read Array

Erase

Susp. to

Read

Status

Erase

Susp. to

Read

Array

Ers. Susp.

to Read

Identifier

Erase Susp.

to Read

Array

“1” Array

Erase

Susp. to

Read

Array

Program

Setup

Erase

Susp. to

Read

Array

Erase

Susp. to

Read Array

Erase

Susp. to

Read

Status

Erase

Susp. to

Read

Array

Ers. Susp.

to Read

Identifier

Erase Susp.

to Read

Identifier

“1” Identifier

Erase

Susp. to

Read

Array

Program

Setup

Erase

Susp. to

Read

Array

Erase

Susp. to

Read Array

Erase

Susp. to

Read

Status

Erase

Susp. to

Read

Array

Ers. Susp.

to Read

Identifier

Erase

(complete) “1” Status Read

Array

Program

Setup

Erase

Setup Read Array Read

Status

Read

Array

Read

Identifier

28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3

Appendix B Architecture Block Diagram

0580-C1

Output

Multiplexer

4-KWord

Parameter Block

32-KWord

Main Block

32-KWord

Main Block

4-KWord

Parameter Block

Y-Gating/Sensing Write State

Machine

Program/Erase

Voltage Switch

Data

Comparator

Status

Identifier

Data

I/O Logic

Address

Latch

Address

Counter

X-Decoder

Y-Decoder

Power

Reduction

Control

Input Buffer

Output Buffer

GND

CE#

WE#

OE#

RP#

Command

User

Interface

Input Buffer

-A

-DQ

CCQ

WP#

28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3

Appendix C Word-Wide Memory Map Diagrams

16-Mbit and 32-Mbit Word-Wide Memory Addressing

Top Boot Bottom Boot

Size

(KW) 16 Mbit 32 Mbit Size

(KW) 8Mbit 16Mbit 32Mbit

4FF000-FFFFF 1FF000-1FFFFF 32 1F8000-1FFFFF

4FE000-FEFFF 1FE000-1FEFFF 32 1F0000-1F7FFF

4FD000-FDFFF 1FD000-1FDFFF 32 1E8000-1EFFFF

4FC000-FCFFF 1FC000-1FCFFF 32 1E0000-1E7FFF

4FB000-FBFFF 1FB000-1FBFFF 32 1D8000-1DFFFF

4FA000-FAFFF 1FA000-1FAFFF 32 1D0000-1D7FFF

4F9000-F9FFF 1F9000-1F9FFF 32 1C8000-1CFFFF

4F8000-F8FFF 1F8000-1F8FFF 32 1C0000-1C7FFF

32 F0000-F7FFF 1F0000-1F7FFF 32 1B8000-1BFFFF

32 E8000-EFFFF 1E8000-1EFFFF 32 1B0000-1B7FFF

32 E0000-E7FFF 1E0000-1E7FFF 32 1A8000-1AFFFF

32 D8000-DFFFF 1D8000-1DFFFF 32 1A0000-1A7FFF

32 D0000-D7FFF 1D0000-1D7FFF 32 198000-19FFFF

32 C8000-CFFFF 1C8000-1CFFFF 32 190000-197FFF

32 C0000-C7FFF 1C0000-1C7FFF 32 188000-18FFFF

32 B8000-BFFFF 1B8000-1BFFFF 32 180000-187FFF

32 B0000-B7FFF 1B0000-1B7FFF 32 178000-17FFFF

32 A8000-AFFFF 1A8000-1AFFFF 32 170000-177FFF

32 A0000-A7FFF 1A0000-1A7FFF 32 168000-16FFFF

32 98000-9FFFF 198000-19FFFF 32 160000-167FFF

32 90000-97FFF 190000-197FFF 32 158000-15FFFF

32 88000-8FFFF 188000-18FFFF 32 150000-157FFF

32 80000-87FFF 180000-187FFF 32 148000-14FFFF

32 78000-7FFFF 178000-17FFFF 32 140000-147FFF

32 70000-77FFF 170000-177FFF 32 138000-13FFFF

32 68000-6FFFF 168000-16FFFF 32 130000-137FFF

32 60000-67FFF 160000-167FFF 32 128000-12FFFF

32 58000-5FFFF 158000-15FFFF 32 120000-127FFF

32 50000-57FFF 150000-157FFF 32 118000-11FFFF

32 48000-4FFFF 148000-14FFFF 32 110000-117FFF

32 40000-47FFF 140000-147FFF 32 108000-10FFFF

32 38000-3FFFF 138000-13FFFF 32 100000-107FFF

32 30000-37FFF 130000-137FFF 32 F8000-FFFFF 0F8000-0FFFFF

32 28000-2FFFF 128000-12FFFF 32 F0000-F7FFF 0F0000-0F7FFF

32 20000-27FFF 120000-127FFF 32 E8000-EFFFF 0E8000-0EFFFF

32 18000-1FFFF 118000-11FFFF 32 E0000-E7FFF 0E0000-0E7FFF

32 10000-17FFF 110000-117FFF 32 D8000-DFFFF 0D8000-0DFFFF

32 08000-0FFFF 108000-10FFFF 32 D0000-D7FFF 0D0000-0D7FFF

32 00000-07FFF 100000-107FFF 32 C8000-CFFFF 0C8000-0CFFFF

This column continues on next page This column continues on next page

28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3

16-Mbit and 32-Mbit Word-Wide Memory Addressing (Continued)

Top Boot Bottom Boot

Size

(KW) 16 Mbit 32 Mbit Size

(KW) 16 Mbit 32 Mbit

32 0F8000-0FFFFF 32 C0000-C7FFF 0C0000-0C7FFF

32 0F0000-0F7FFF 32 B8000-BFFFF 0B8000-0BFFFF

32 0E8000-0EFFFF 32 B0000-B7FFF 0B0000-0B7FFF

32 0E0000-0E7FFF 32 A8000-AFFFF 0A8000-0AFFFF

32 0D8000-0DFFFF 32 A0000-A7FFF 0A0000-0A7FFF

32 0D0000-0D7FFF 32 98000-9FFFF 098000-09FFFF

32 0C8000-0CFFFF 32 90000-97FFF 090000-097FFF

32 0C0000-0C7FFF 32 88000-8FFFF 088000-08FFFF

32 0B8000-0BFFFF 32 80000-87FFF 080000-087FFF

32 0B0000-0B7FFF 32 78000-7FFFF 78000-7FFFF

32 0A8000-0AFFFF 32 70000-77FFF 70000-77FFF

32 0A0000-0A7FFF 32 68000-6FFFF 68000-6FFFF

32 098000-09FFFF 32 60000-67FFF 60000-67FFF

32 090000-097FFF 32 58000-5FFFF 58000-5FFFF

32 088000-08FFFF 32 50000-57FFF 50000-57FFF

32 080000-087FFF 32 48000-4FFFF 48000-4FFFF

32 078000-07FFFF 32 40000-47FFF 40000-47FFF

32 070000-077FFF 32 38000-3FFFF 38000-3FFFF

32 068000-06FFFF 32 30000-37FFF 30000-37FFF

32 060000-067FFF 32 28000-2FFFF 28000-2FFFF

32 058000-05FFFF 32 20000-27FFF 20000-27FFF

32 050000-057FFF 32 18000-1FFFF 18000-1FFFF

32 048000-04FFFF 32 10000-17FFF 10000-17FFF

32 040000-047FFF 32 08000-0FFFF 08000-0FFFF

32 038000-03FFFF 4 07000-07FFF 07000-07FFF

32 030000-037FFF 4 06000-06FFF 06000-06FFF

32 028000-02FFFF 4 05000-05FFF 05000-05FFF

32 020000-027FFF 4 04000-04FFF 04000-04FFF

32 018000-01FFFF 4 03000-03FFF 03000-03FFF

32 010000-017FFF 4 02000-02FFF 02000-02FFF

32 008000-00FFFF 4 01000-01FFF 01000-01FFF

32 000000-007FFF 4 00000-00FFF 00000-00FFF

28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3

4-Mbit and 8-Mbit Word-Wide Memory Addressing

Top Boot Bottom Boot

Size

(KW) 4Mbit Size

(KW) 4Mbit 8Mbit

3F000-3FFFF 7F000-7FFFF 32 78000-7FFFF

3E000-3EFFF 7E000-7EFFF 32 70000-77FFF

3D000-3DFFF 7D000-7DFFF 32 68000-6FFFF

3C000-3CFFF 7C000-7CFFF 32 60000-67FFF

3B000-3BFFF 7B000-7BFFF 32 58000-5FFFF

3A000-3AFFF 7A000-7AFFF 32 50000-57FFF

39000-39FFF 79000-79FFF 32 48000-4FFFF

38000-38FFF 78000-78FFF 32 40000-47FFF

4 30000-37FFF 70000-77FFF 32 38000-3FFFF 38000-3FFFF

4 28000-2FFFF 68000-6FFFF 32 30000-37FFF 30000-37FFF

4 20000-27FFF 60000-67FFF 32 28000-2FFFF 28000-2FFFF

4 18000-1FFFF 58000-5FFFF 32 20000-27FFF 20000-27FFF

4 10000-17FFF 50000-57FFF 32 18000-1FFFF 18000-1FFFF

4 08000-0FFFF 48000-4FFFF 32 10000-17FFF 10000-17FFF

4 00000-07FFF 40000-47FFF 32 08000-0FFFF 08000-0FFFF

438000-3FFFF 4 07000-07FFF 07000-07FFF

32 30000-37FFF 4 06000-06FFF 06000-06FFF

32 28000-2FFFF 4 05000-05FFF 05000-05FFF

32 20000-27FFF 4 04000-04FFF 04000-04FFF

32 18000-1FFFF 4 03000-03FFF 03000-03FFF

32 10000-17FFF 4 02000-02FFF 02000-02FFF

32 08000-0FFFF 4 01000-01FFF 01000-01FFF

32 00000-07FFF 4 00000-00FFF 00000-00FFF

28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3

16-Mbit, 32-Mbit, and 64-Mbit Word-Wide Memory Addressing

Top Boot Bottom Boot

Size

(KW) 16 Mbit 32 Mbit 64 Mbit Size

(KW) 16 Mbit 32 Mbit 64 Mbit

4 FF000-FFFFF 1FF000-1FFFFF 3FF000-3FFFFF 32 3F8000-3FFFFF

4 FE000-FEFFF 1FE000-1FEFFF 3FE000-3FEFFF 32 3F0000-3F7FFF

4 FD000-FDFFF 1FD000-1FDFFF 3FD000-3FDFFF 32 3E8000-3EFFFF

4 FC000-FCFFF 1FC000-1FCFFF 3FC000-3FCFFF 32 3E0000-3E7FFF

4 FB000-FBFFF 1FB000-1FBFFF 3FB000-3FBFFF 32 3D8000-3DFFFF

4 FA000-FAFFF 1FA000-1FAFFF 3FA000-3FAFFF 32 3D0000-3D7FFF

4 F9000-F9FFF 1F9000-1F9FFF 3F9000-3F9FFF 32 3C8000-3CFFFF

4 F8000-F8FFF 1F8000-1F8FFF 3F8000-3F8FFF 32 3C0000-3C7FFF

32 F0000-F7FFF 1F0000-1F7FFF 3F0000-3F7FFF 32 3B8000-3BFFFF

32 E8000-EFFFF 1E8000-1EFFFF 3E8000-3EFFFF 32 3B0000-3B7FFF

32 E0000-E7FFF 1E0000-1E7FFF 3E0000-3E7FFF 32 3A8000-3AFFFF

32 D8000-DFFFF 1D8000-1DFFFF 3D8000-3DFFFF 32 3A0000-3A7FFF

32 D0000-D7FFF 1D0000-1D7FFF 3D0000-3D7FFF 32 398000-39FFFF

32 C8000-CFFFF 1C8000-1CFFFF 3C8000-3CFFFF 32 390000-397FFF

32 C0000-C7FFF 1C0000-1C7FFF 3C0000-3C7FFF 32 388000-38FFFF

32 B8000-BFFFF 1B8000-1BFFFF 3B8000-3BFFFF 32 380000-387FFF

32 B0000-B7FFF 1B0000-1B7FFF 3B0000-3B7FFF 32 378000-37FFFF

32 A8000-AFFFF 1A8000-1AFFFF 3A8000-3AFFFF 32 370000-377FFF

32 A0000-A7FFF 1A0000-1A7FFF 3A0000-3A7FFF 32 368000-36FFFF

32 98000-9FFFF 198000-19FFFF 398000-39FFFF 32 360000-367FFF

32 90000-97FFF 190000-197FFF 390000-397FFF 32 358000-35FFFF

32 88000-8FFFF 188000-18FFFF 388000-38FFFF 32 350000-357FFF

32 80000-87FFF 180000-187FFF 380000-387FFF 32 348000-34FFFF

32 78000-7FFFF 178000-17FFFF 378000-37FFFF 32 340000-347FFF

32 70000-77FFF 170000-177FFF 370000-377FFF 32 338000-33FFFF

32 68000-6FFFF 168000-16FFFF 368000-36FFFF 32 330000-337FFF

32 60000-67FFF 160000-167FFF 360000-367FFF 32 328000-32FFFF

32 58000-5FFFF 158000-15FFFF 358000-35FFFF 32 320000-327FFF

32 50000-57FFF 150000-157FFF 350000-357FFF 32 318000-31FFFF

32 48000-4FFFF 148000-14FFFF 348000-34FFFF 32 310000-317FFF

32 40000-47FFF 140000-147FFF 340000-347FFF 32 308000-30FFFF

32 38000-3FFFF 138000-13FFFF 338000-33FFFF 32 300000-307FFF

32 30000-37FFF 130000-137FFF 330000-337FFF 32 2F8000-2FFFFF

32 28000-2FFFF 128000-12FFFF 328000-32FFFF 32 2F0000-2F7FFF

32 20000-27FFF 120000-127FFF 320000-327FFF 32 2E8000-2EFFFF

32 18000-1FFFF 118000-11FFFF 318000-31FFFF 32 2E0000-2E7FFF

32 10000-17FFF 110000-117FFF 310000-317FFF 32 2D8000-2DFFFF

32 08000-0FFFF 108000-10FFFF 308000-30FFFF 32 2D0000-2D7FFF

32 00000-07FFF 100000-107FFF 300000-307FFF 32 2C8000-2CFFFF

32 0F8000-0FFFFF 2F8000-2FFFFF 32 2C0000-2C7FFF

32 0F0000-0F7FFF 2F0000-2F7FFF 32 2B8000-2BFFFF

32 0E8000-0EFFFF 2E8000-2EFFFF 32 2B0000-2B7FFF

32 0E0000-0E7FFF 2E0000-2E7FFF 32 2A8000-2AFFFF

32 0D8000-0DFFFF 2D8000-2DFFFF 32 2A0000-2A7FFF

32 0D0000-0D7FFF 2D0000-2D7FFF 32 298000-29FFFF

32 0C8000-0CFFFF 2C8000-2CFFFF 32 290000-297FFF

32 0C0000-0C7FFF 2C0000-2C7FFF 32 288000-28FFFF

32 0B8000-0BFFFF 2B8000-2BFFFF 32 280000-287FFF

32 0B0000-0B7FFF 2B0000-2B7FFF 32 278000-27FFFF

This column continues on next page This column continues on next page

28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3

16-Mbit, 32-Mbit, and 64-Mbit Word-Wide Memory Addressing (Continued)

Top Boot Bottom Boot

Size

(KW) 16 Mbit 32 Mbit 64 Mbit Size

(KW) 16 Mbit 32 Mbit 64 Mbit

32 0A8000-0AFFFF 2A8000-2AFFFF 32 270000-277FFF

32 0A0000-0A7FFF 2A0000-2A7FFF 32 268000-26FFFF

32 098000-09FFFF 298000-29FFFF 32 260000-267FFF

32 090000-097FFF 290000-297FFF 32 258000-25FFFF

32 088000-08FFFF 288000-28FFFF 32 250000-257FFF

32 080000-087FFF 280000-287FFF 32 248000-24FFFF

32 078000-07FFFF 278000-27FFFF 32 240000-247FFF

32 070000-077FFF 270000-277FFF 32 238000-23FFFF

32 068000-06FFFF 268000-26FFFF 32 230000-237FFF

32 060000-067FFF 260000-267FFF 32 228000-22FFFF

32 058000-05FFFF 258000-25FFFF 32 220000-227FFF

32 050000-057FFF 250000-257FFF 32 218000-21FFFF

32 048000-04FFFF 248000-24FFFF 32 210000-217FFF

32 040000-047FFF 240000-247FFF 32 208000-20FFFF

32 038000-03FFFF 238000-23FFFF 32 200000-207FFF

32 030000-037FFF 230000-237FFF 32 1F8000-1FFFFF 1F8000-1FFFFF

32 028000-02FFFF 228000-22FFFF 32 1F0000-1F7FFF 1F0000-1F7FFF

32 020000-027FFF 220000-227FFF 32 1E8000-1EFFFF 1E8000-1EFFFF

32 018000-01FFFF 218000-21FFFF 32 1E0000-1E7FFF 1E0000-1E7FFF

32 010000-017FFF 210000-217FFF 32 1D8000-1DFFFF 1D8000-1DFFFF

32 008000-00FFFF 208000-21FFFF 32 1D0000-1D7FFF 1D0000-1D7FFF

32 000000-007FFF 200000-207FFF 32 1C8000-1CFFFF 1C8000-1CFFFF

32 1F8000-1FFFFF 32 1C0000-1C7FFF 1C0000-1C7FFF

32 1F0000-1F7FFF 32 1B8000-1BFFFF 1B8000-1BFFFF

32 1E8000-1EFFFF 32 1B0000-1B7FFF 1B0000-1B7FFF

32 1E0000-1E7FFF 32 1A8000-1AFFFF 1A8000-1AFFFF

32 1D8000-1DFFFF 32 1A0000-1A7FFF 1A0000-1A7FFF

32 1D0000-1D7FFF 32 198000-19FFFF 198000-19FFFF

32 1C8000-1CFFFF 32 190000-197FFF 190000-197FFF

32 1C0000-1C7FFF 32 188000-18FFFF 188000-18FFFF

32 1B8000-1BFFFF 32 180000-187FFF 180000-187FFF

32 1B0000-1B7FFF 32 178000-17FFFF 178000-17FFFF

32 1A8000-1AFFFF 32 170000-177FFF 170000-177FFF

32 1A0000-1A7FFF 32 168000-16FFFF 168000-16FFFF

32 198000-19FFFF 32 160000-167FFF 160000-167FFF

32 190000-197FFF 32 158000-15FFFF 158000-15FFFF

32 188000-18FFFF 32 150000-157FFF 150000-157FFF

32 180000-187FFF 32 148000-14FFFF 148000-14FFFF

32 178000-17FFFF 32 140000-147FFF 140000-147FFF

32 170000-177FFF 32 138000-13FFFF 138000-13FFFF

32 168000-16FFFF 32 130000-137FFF 130000-137FFF

32 160000-167FFF 32 128000-12FFFF 128000-12FFFF

32 158000-15FFFF 32 120000-127FFF 120000-127FFF

32 150000-157FFF 32 118000-11FFFF 118000-11FFFF

32 148000-14FFFF 32 110000-117FFF 110000-117FFF

32 140000-147FFF 32 108000-10FFFF 108000-10FFFF

32 138000-13FFFF 32 100000-107FFF 100000-107FFF

32 130000-137FFF 32 F8000-FFFFF F8000-FFFFF F8000-FFFFF

32 128000-12FFFF 32 F0000-F7FFF F0000-F7FFF F0000-F7FFF

32 120000-127FFF 32 E8000-EFFFF E8000-EFFFF E8000-EFFFF

32 118000-11FFFF 32 E0000-E7FFF E0000-E7FFF E0000-E7FFF

32 110000-117FFF 32 D8000-DFFFF D8000-DFFFF D8000-DFFFF

32 108000-10FFFF 32 D0000-D7FFF D0000-D7FFF D0000-D7FFF

32 100000-107FFF 32 C8000-CFFFF C8000-CFFFF C8000-CFFFF

This column continues on next page This column continues on next page

28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3

16-Mbit, 32-Mbit, and 64-Mbit Word-Wide Memory Addressing (Continued)

Top Boot Bottom Boot

Size

(KW) 16 Mbit 32 Mbit 64 Mbit Size

(KW) 16 Mbit 32 Mbit 64 Mbit

32 0F8000-0FFFFF 32 C0000-C7FFF C0000-C7FFF C0000-C7FFF

32 0F0000-0F7FFF 32 B8000-BFFFF B8000-BFFFF B8000-BFFFF

32 0E8000-0EFFFF 32 B0000-B7FFF B0000-B7FFF B0000-B7FFF

32 0E0000-0E7FFF 32 A8000-AFFFF A8000-AFFFF A8000-AFFFF

32 0D8000-0DFFFF 32 A0000-A7FFF A0000-A7FFF A0000-A7FFF

32 0D0000-0D7FFF 32 98000-9FFFF 98000-9FFFF 98000-9FFFF

32 0C8000-0CFFFF 32 90000-97FFF 90000-97FFF 90000-97FFF

32 0C0000-0C7FFF 32 88000-8FFFF 88000-8FFFF 88000-8FFFF

32 0B8000-0BFFFF 32 80000-87FFF 80000-87FFF 80000-87FFF

32 0B0000-0B7FFF 32 78000-7FFFF 78000-7FFFF 78000-7FFFF

32 0A8000-0AFFFF 32 70000-77FFF 70000-77FFF 70000-77FFF

32 0A0000-0A7FFF 32 68000-6FFFF 68000-6FFFF 68000-6FFFF

32 098000-09FFFF 32 60000-67FFF 60000-67FFF 60000-67FFF

32 090000-097FFF 32 58000-5FFFF 58000-5FFFF 58000-5FFFF

32 088000-08FFFF 32 50000-57FFF 50000-57FFF 50000-57FFF

32 080000-087FFF 32 48000-4FFFF 48000-4FFFF 48000-4FFFF

32 078000-07FFFF 32 40000-47FFF 40000-47FFF 40000-47FFF

32 070000-077FFF 32 38000-3FFFF 38000-3FFFF 38000-3FFFF

32 068000-06FFFF 32 30000-37FFF 30000-37FFF 30000-37FFF

32 060000-067FFF 32 28000-2FFFF 28000-2FFFF 28000-2FFFF

32 058000-05FFFF 32 20000-27FFF 20000-27FFF 20000-27FFF

32 050000-057FFF 32 18000-1FFFF 18000-1FFFF 18000-1FFFF

32 048000-04FFFF 32 10000-17FFF 10000-17FFF 10000-17FFF

32 040000-047FFF 32 08000-0FFFF 08000-0FFFF 08000-0FFFF

32 038000-03FFFF 4 07000-07FFF 07000-07FFF 07000-07FFF

32 030000-037FFF 4 06000-06FFF 06000-06FFF 06000-06FFF

32 028000-02FFFF 4 05000-05FFF 05000-05FFF 05000-05FFF

32 020000-027FFF 4 04000-04FFF 04000-04FFF 04000-04FFF

32 018000-01FFFF 4 03000-03FFF 03000-03FFF 03000-03FFF

32 010000-017FFF 4 02000-02FFF 02000-02FFF 02000-02FFF

32 008000-00FFFF 4 01000-01FFF 01000-01FFF 01000-01FFF

32 000000-007FFF 4 00000-00FFF 00000-00FFF 00000-00FFF

28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3

Appendix D Byte-Wide Memory Map Diagrams

8-Mbit and 16-Mbit Byte-Wide Byte-Wide Memory Addressing

Top Boot Bottom Boot

Size(KB) 8Mbit 16Mbit Size(KB) 8Mbit 16Mbit

8 FE000-FFFFF 1FE000-1FFFFF 64

8 FC000-FDFFF 1FC000-1FDFFF 64

8 FA000-FBFFF 1FA000-1FBFFF 64

8 F8000-F9FFF 1F8000-1F9FFF 64

8 F6000-F7FFF 1F6000-1F7FFF 64

8 F4000-F5FFF 1F4000-1F5FFF 64

8 F2000-F3FFF 1F2000-1F3FFF 64

8 F0000-F1FFF 1F0000-1F1FFF 64

64 E0000-EFFFF 1E0000-1EFFFF 64

64 D0000-DFFFF 1D0000-1DFFFF 64

64 C0000-CFFFF 1C0000-1CFFFF 64

64 B0000-BFFFF 1B0000-1BFFFF 64

64 A0000-AFFFF 1A0000-1AFFFF 64

64 90000-9FFFF 190000-19FFFF 64

64 80000-8FFFF 180000-18FFFF 64

64 70000-7FFFF 170000-17FFFF 64

64 60000-6FFFF 160000-16FFFF 64

64 50000-5FFFF 150000-15FFFF 64

64 40000-4FFFF 140000-14FFFF 64

64 30000-3FFFF 130000-13FFFF 64

64 20000-2FFFF 120000-12FFFF 64

64 10000-1FFFF 110000-11FFFF 64

64 00000-0FFFF 100000-10FFFF 64

64 0F0000-0FFFFF 64

64 0E0000-0EFFFF 64

64 0D0000-0DFFFF 64

64 0C0000-0CFFFF 64

64 0B0000-0BFFFF 64

64 0A0000-0AFFFF 64

64 090000-09FFFF 64

64 080000-08FFFF 64

64 070000-07FFFF 64

64 060000-06FFFF 64 1F0000-1FFFFF

64 050000-05FFFF 64 1E0000-1EFFFF

64 040000-04FFFF 64 1D0000-1DFFFF

64 030000-03FFFF 64 1C0000-1CFFFF

64 020000-02FFFF 64 1B0000-1BFFFF

64 010000-01FFFF 64 1A0000-1AFFFF

64 000000-00FFFF 64 190000-19FFFF

This column continues on next page This column continues on next page

28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3

8-Mbit and 16-Mbit Byte-Wide Memory Addressing (Continued)

Top Boot Bottom Boot

Size(KB) 8Mbit 16Mbit Size(KB) 8Mbit 16Mbit

64 64 180000-18FFFF

64 64 170000-17FFFF

64 64 160000-16FFFF

64 64 150000-15FFFF

64 64 140000-14FFFF

64 64 130000-13FFFF

64 64 120000-12FFFF

64 64 110000-11FFFF

64 64 100000-10FFFF

64 64 F0000-FFFFF 0F0000-0FFFFF

64 64 E0000-EFFFF 0E0000-0EFFFF

64 64 D0000-DFFFF 0D0000-0DFFFF

64 64 C0000-CFFFF 0C0000-0CFFFF

64 64 B0000-BFFFF 0B0000-0BFFFF

64 64 A0000-AFFFF 0A0000-0AFFFF

64 64 90000-9FFFF 090000-09FFFF

64 64 80000-8FFFF 080000-08FFFF

64 64 70000-7FFFF 070000-07FFFF

64 64 60000-6FFFF 060000-06FFFF

64 64 50000-5FFFF 050000-05FFFF

64 64 40000-4FFFF 040000-04FFFF

64 64 30000-3FFFF 030000-03FFFF

64 64 20000-2FFFF 020000-02FFFF

64 64 10000-1FFFF 010000-01FFFF

64 8 0E000-0FFFF 00E000-00FFFF

64 8 0C000-0DFFF 00C000-00DFFF

64 8 0A000-0BFFF 00A000-00BFFF

64 8 08000-09FFF 008000-009FFF

64 8 06000-07FFF 006000-007FFF

64 8 04000-05FFF 004000-005FFF

64 8 02000-03FFF 002000-003FFF

64 8 00000-01FFF 000000-001FFF

4-Mbit Byte-Wide Memory Addressing

Top Boot Bottom Boot

Size

(KB) 4Mbit Size

(KB) 4Mbit

8 7E000-7FFFF 64 70000-7FFFF

8 7C000-7DFFF 64 60000-6FFFF

8 7A000-7BFFF 64 50000-5FFFF

8 78000-79FFF 64 40000-4FFFF

8 76000-77FFF 64 30000-3FFFF

8 74000-75FFF 64 20000-2FFFF

8 72000-73FFF 64 10000-1FFFF

8 70000-71FFF 8 0E000-0FFFF

64 60000-6FFFF 8 0C000-0DFFF

64 50000-5FFFF 8 0A000-0BFFF

64 40000-4FFFF 8 08000-09FFF

64 30000-3FFFF 8 06000-07FFF

64 20000-2FFFF 8 04000-05FFF

64 10000-1FFFF 8 02000-03FFF

64 00000-0FFFF 8 00000-01FFF

28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3

Appendix E Program and Erase Flowcharts

0580_E1

Figure 12. Program Flowchart

Start

Write 40H

Program Address/Data

Read Status Register

SR.7 = 1?

Full Status

Check if Desired

Program Complete

Read Status Register

Data (See Above)

Range Error

Programming Error

Attempted Program to

Locked Block - Aborted

Program Successful

SR.3 =

SR.4 =

SR.1 =

FULL STATUS CHECK PROCEDURE

Bus Operation

Write

Standby

Repeat for subsequent programming operations.

SR Full Status Check can be done after each program or after a sequence of

program operations.

Write FFH after the last program operation to reset device to read array mode.

Bus Operation

Standby

SR.3 MUST be cleared, if set during a program attempt, before further

attempts are allowed by the Write State Machine.

SR.1, SR.3 and SR.4 are only cleared by the Clear Staus Register Command,

in cases where multiple bytes are programmed before full status is checked.

If an error is detected, clear the status register before attempting retry or other

error recovery.

Yes

Command

Program Setup

Program

Comments

Data = 40H

Data=DatatoProgram

Addr = Location to Program

Check SR.7

1 = WSM Ready

0=WSMBusy

Command Comments

Check SR.3

1=V

Low Detect

Check SR.1

1=AttemptedProgramto

Locked Block - Program

Aborted

Read

Status Register Data Toggle

CE# or OE# to Update Status

Standby Check SR.4

1=V

Program Error

28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3

0580_E2

Figure 13. Program Suspend/Resume Flowchart

Start

Write B0H

Read Status Register

Comments

Data = 70H

Addr = X

Data = FFH

Addr = X

SR.7 =

SR.2 =

Write FFH

Read Array Data

Program Completed

Done

Reading

Yes

Write FFHWrite D0H

Program Resumed Read Array Data

Read array data from block

other than the one being

programmed.

Status Register Data Toggle

CE# or OE# to Update Status

Addr = X

Check SR.7

1 = WSM Ready

0=WSMBusy

Check SR.2

1 = Program Suspended

0 = Program Completed

Data = D0H

Addr = X

Bus

Operation

Write

Read

Standby

Write

Command

Read Status

Read Array

Program

Resume

Write 70H

Data = B0H

Addr = X

Write Program

Suspend

28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3

0580_E3

Figure 14. Block Erase Flowchart

Start

Write 20H

Write D0H and

Block Address

Read Status Register

SR.7 =

Full Status

Check if Desired

Block Erase Complete

FULL STATUS CHECK PROCEDURE

Bus Operation

Write

Standby

Repeat for subsequent block erasures.

Full Status Check can be done after each block erase or after a sequence of

block erasures.

Write FFH after the last write operation to reset device to read array mode.

Bus Operation

Standby

SR. 1 and 3 MUST be cleared, if set during an erase attempt, before further

attempts are allowed by the Write State Machine.

SR.1, 3, 4, 5 are only cleared by the Clear Staus Register Command, in cases

where multiple bytes are erased before full status is checked.

If an error is detected, clear the status register before attempting retry or other

error recovery.

No Yes

Suspend Erase

Suspend

Erase Loop

Standby

Command

Erase Setup

Erase Confirm

Comments

Data = 20H

Addr = Within Block to Be

Erased

Data = D0H

Addr = Within Block to Be

Erased

Check SR.7

1=WSMReady

0 = WSM Busy

Command Comments

Check SR.3

1=V

Low Detect

Check SR.4,5

Both1=CommandSequence

Error

Read Status Register

Data (See Above)

Range Error

Command Sequence

Error

Block Erase

Successful

SR.3 =

SR.4,5 =

Block Erase ErrorSR.5 =

Attempted Erase of

Locked Block - Aborted

SR.1 =

Read

Status Register Data Toggle

CE# or OE# to Update Status

Standby Check SR.5

1=BlockErase Error

Standby

Check SR.1

1 = Attempted Erase of

Locked Block - Erase Aborted

28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3

0580_E4

Figure 15. Erase Suspend/Resume Flowchart

Start

Write B0H

Read Status Register

Bus Operation

Write

Command

Erase Suspend

Read Array

Comments

Data = B0H

Addr = X

Data = FFH

Addr = X

SR.7 =

SR.6 =

Write FFH

Read Array Data

Erase Completed

Done

Reading

Yes

Write FFHWrite D0H

Erase Resumed Read Array Data

Read

Read array data from block

other than the one being

erased.

Read

Status Register Data Toggle

CE# or OE# to Update Status

Addr = X

Standby

Check SR.7

1 = WSM Ready

0=WSMBusy

Standby

Check SR.6

1 = Erase Suspended

0 = Erase Completed

Write Erase Resume Data = D0H

Addr = X

Write Read Status Data = 70H

Addr = X

Write 70H

28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3

Figure 16. Very Fine Pitch BGA (VF BGA) Package Drawing and Dimensions

M illimeters Inches

Symbol Min Nom Max Notes Min Nom Max

Pac kage Heig h t A 1.000 0.0394

Ball He igh t A 10.150 0.00 59

Package Body Thickne ss A20.665 0.0262

Ball (Lea d) W id th b 0.325 0.375 0.425 0.0128 0.0148 0.0167

Pac kag e Bo dy Width ( 16Mb / 32Mb) D 7.186 7.286 7.386 1 0.2829 0.2869 0.2 908

Pac kag e Bo dy Width (64Mb ) D 7.600 7.700 7.800 1 0.2994 0.3033 0.3073

Pac kag e Body Length (16Mb/ 32M b) E 6.864 6.964 7.064 1 0.2702 0.2742 0.2781

Pac kag e Body Len g th (64Mb) E 8.900 9.000 9.100 1 0.3506 0.3546 0.3585

Pitch [e ] 0.750 0.0295

Ball (Lead) Count (16Mg) N 46 2 46

Ball (Lead) Count (32Mg) N 47 2 47

Ball (Lead) Count (64Mg) N 48 2 48

Sea ting Plane Coplanarity Y 0.100 0.0039

Corner to Ball A1 Distance Along D ( 16Mb 32Mb) S10.918 1.018 1.118 1 0.0361 0.0401 0.0 440

Corner to Ball A1 Dis tance Along D (64M b) S11.125 1.225 1.325 1 0.0443 0.0482 0.0 522

Corner t o Ball A1 Dis tan ce Alon g E ( 16Mb/32M b ) S21.507 1.607 1.707 1 0.0593 0.0633 0.0672

Corner to Ball A1 Distance Along E (64Mb) S22.52 5 2.625 2.725 1 0.0994 0.1034 0.1073

ote: 1.) Package dimensions are for reference only. These dimensions are estimates based on die size, and are subject to change.

2.) For 16 Mb it devi ces A20 and A2 1 are not p opulated.

Dimensions

Bottom View -Bump side up

Ba ll A1

Corner

Top View - Bump Side down

Ball A1

Corner

Side View

Seating Y

Plan

123

5678

12345678

Note: Drawing not to scale

28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3

Figure 17. Easy BGA Package Drawing and Dimensions

Millimeters Inches

Symbol Min Nom Max Notes Min Nom Max

Package Height A 1.200 0.0472

Ball Heigh t A10.250 0.0098

Package Body Thickness A20.780 0.0307

Ball (Lead) Width b 0.330 0.430 0.530 0.0130 0.0169 0.0209

Package Body Width D 9.900 10.000 10.100 1 0.3898 0.3937 0.3976

Package Body Length E 12.900 13.000 13.100 1 0.5079 0.5118 0.5157

Pitch [e] 1.000 0.0394

Ball (Lead) Count N 64 64

Seating Plane Coplanarity Y 0.100 0.0039

Corn er t o Ba ll A1 Dis t ance Alo ng D S11.400 1.500 1.600 1 0.0551 0.0591 0.0630

Corn er t o Ba ll A1 Dis t ance Alo ng E S22.900 3.000 3.100 1 0.1142 0.1181 0.1220

Dimensions Table

Note: (1) Package dimensions are for reference only. These dimensions are estimates based

on die size, and are subject to change.

Seating

Plane

Top View - Ball side down Bottom Vi ew - Ball Side Up

Ball A1

Corner

Note: Drawing not to scal e

8765432187654321

Ball A1

Corner

Side View