MX28F160C3BTC-11G - Macronix International Co., Ltd.

P/N:PM0867 REV. 1.2, MAR. 17, 2004

MX28F160C3T/B

16M-BIT [1M x16] CMOS SINGLE VOLTAGE

3V ONLY FLASH MEMORY

- Word write suspend to read

- Sector erase suspend to word write

- Sector erase suspend to read register report

• Automatic sector erase, word write and sector lock/

unlock configuration

• Status Reply

- Detection of program and erase operation comple-

tion.

- Command User Interface (CUI)

- Status Register (SR)

• Data Protection Performance

- Include boot sectors and parameter and main sectors

to be locked/unlocked

• 100,000 minimum erase/program cycles

• Common Flash Interface (CFI)

• 128-bit Protection Register

- 64-bit Unique Device Identifier

- 64-bit User-Programmable

• Latch-up protected to 100mA from -1V to VCC+1V

• Package type:

- 48-pin TSOP (12mm x 20mm)

- 48-ball CSP (8mm x 6mm)

FEATURES

• Bit Organization: 1,048,576 x 16

• Single power supply operation

- VCC=VCCQ=2.7~3.6V for read, erase and program

operation

- VPP=12V for fast production programming

- Operating temperature:-40°C~85°C

• Fast access time : 70/90/110ns

• Low power consumption

- 9mA typical active read current, f=5MHz

- 18mA typical program current (VPP=1.65~3.6V)

- 21mA typical erase current (VPP=1.65~3.6V)

- 7uA typical standby current under power saving

mode

• Sector architecture

- Sector structure : 4Kword x 2 (boot sectors), 4Kword

x 6 (parameter sectors), 32Kword x 31 (main sectors)

- Top/Bottom Boot

• Auto Erase and Auto Program

- Automatically program and verify data at specified

address

- Auto sector erase at specified sector

• Automatic Suspend Enhance

GENERAL DESCRIPTION

The MX28F160C3T/B is a 16-mega bit Flash memory

organized as 1M w o rds o f 16 bits . The 1M word of data

is arranged in eight 4Kword boot and parameter sectors,

and thirty-one 32K word main sectors which are indi-

vidually erasable. MXIC's Flash memories offer the most

cost-effective and reliable read/write non-volatile random

access memory. The MX28F160C3T/B is pac kaged in

48-pin TSOP and 48-ball CSP. It is designed to be re-

programmed and erased in system or in standard

EPROM programmers.

The standard MX28F160C3T/B offers access time as

fast as 70ns, allowing operation of high-speed micropro-

cessors without wait states.

MXIC's Flash memories augment EPROM functionality

with in-circuit electrical erasure and pro gramming. The

MX28F160C3T/B uses a command register to manage

this functio nality . The command register allows fo r 100%

TTL level control inputs and fixed power supply levels

during erase and programming, while maintaining maxi-

mum EPROM compatibility.

MXIC Flash technology reliably stores memory contents

even after 100,000 erase and program cycles. The MXIC

cell is designed to optimize the erase and programming

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REV. 1.2, MAR. 17, 2004

mechanisms. In addition, the combination of advanced

tunnel oxide processing and low internal electric fields

for erase and program operations produces reliable cy-

cling. The MX28F160C3T/B uses a 2.7V~3.6V VCC sup-

ply to perform the High Reliability Erase and auto Pro-

gram/Erase algorithms.

The highest degree of latch-up protection is achieved

with MXIC's proprietary non-epi process. Latch-up pro-

tection is proved for stresses up to 100 milliamps on

address and data pin from -1V to VCC + 1V.

The dedicated VPP pin gives complete data protection

when VPP< VPPLK.

A Command User Interface (CUI) serves as the inter-

face between the system processor and internal opera-

tion of the device. A valid command sequence written to

the CUI initiates device automation. An internal Write

State Machine (WSM) automatically executes the algo-

rithms and timings necessary for erase, word write and

sector lock/unlock configuration operations.

A sector erase operation erases one of the device's 32K-

word sectors typically within 1.0s, 4K-word sectors typi-

cally within 0.5s independent of other sectors. Each sec-

tor can be independently erased minimum 100,000 times.

Sector erase suspend mode allows system software to

suspend sector erase to read or write data from any other

sector.

Writing memory data is performed in word increments of

the device's 32K-word sectors typically within 0.8s and

4K-wo rd sectors typically within 0.1s. Word pro gram sus-

pend mode enables the system to read data or execute

code from any other memory array location.

MX28F160C3T/B features with individual sectors lock-

ing by using a co mbination o f bits thirty-nine sector lock-

bits and WP, to lock and unlock sectors.

The status register indicates when the WSM's sector

erase, word program or lock configuration operation is

done.

The access time is 70/90/110ns (tELQV) over the oper-

ating temperature range (-40°C to +85°C) and VCC sup-

ply v oltage range o f 2.7V~3.6V.

MX28F160C3T/B's power saving mode feature substan-

tially reduces active current when the device is in static

mode (addresses not switching). In this mode, the typi-

cal ICCS current is 7uA (CMOS) at 3.0V VCC .

As CE and RP are at VCC, ICC CMOS standby mo de is

enabled. When RP is at GND , the reset mode is enabled

which minimize power consumption and provide data

write protection.

A reset time (tPHQV) is required from RP switching high

until outputs are valid. Similarly, the device has a w ake

time (tPHEL) from RP-high until writes to the CUI are

reco gniz ed. With RP at GND , the WSM is reset and the

status register is cleared.

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REV. 1.2, MAR. 17, 2004

BLOCK DIAGRAM

Output

Buffer

Output

Multiplexer

Data

DQ0-DQ15

Identifier

User

Interface

Input

Buffer

Status

Data

Comparator

Y-Gating

32K-Word

Main Sector

x31

.......

Boot Sector 0

Boot Sector 1

Parameter Sector 0

Parameter Sector 1

Parameter Sector 2

Parameter Sector 3

Parameter Sector 4

Parameter Sector 5

Main Sector 0

Main Sector 1

Main Sector 29

Main Sector 30

Write

State

Machine Program/Erase

Voltage Switch

Decoder

Input

Buffer

A0~A19

Address

Latch

Address

Counter

Decoder

I/O

Logic VCC

VPP

VCC

GND

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PIN CONFIGURATIONS

48 TSOP (Standard Type) (12mm x 20mm)

48 Ball CSP (8mm x 6mm) Top View, Ball Down for MX28F160C3T/BXA

(Ball Pitch=0.75mm, Ball Width=0.35mm)

A15

A14

A13

A12

A11

A10

VPP

A19

A18

A17

A16

VCCQ

GND

Q15

Q14

Q13

Q12

VCC

Q11

Q10

GND

MX28F160C3T/B

A13

A11

VPP

A19

A14

A10

A18

A17

A15

A12

A16

DQ14

DQ5

DQ11

DQ2

DQ8

VCCQ

DQ15

DQ6

DQ12

DQ3

DQ9

GND

DQ7

DQ13

DQ4

VCC

DQ10

DQ0

GND

DQ1

8.0 mm

6.0 mm

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Table 1. Pin Description

Symbol T ype Description and Function

A0-A19 input Address inputs for memory address. Data pin float to high-impedance when the chip is

deselected or outputs are disable. Addresses are internally latched during a write or

erase cycle.

DQ0-DQ15 input/output Data inputs/outputs: Inputs array data on the second CE and WE cycle during a pro-

gram command. Data is internally latched. Outputs array and configuration data. The

data pin float to tri-state when the chip is de-selected.

CE input Chip Enable : Activates the device's control logic, input buffers, and sense amplifiers.

CE high de-selects the memory device and reduce power consumption to standby

level. CE is active low.

RP input Reset/Deep Power Down: when RP=VIL, the device is in reset/deep power down mo de,

which drives the outputs to High Z, resets the WSM and minimizes current level.

When RP=VIH, the device is normal operation. When RP transitions from VIL to VIH,

the device defaults to the read array mode.

WE input Write Enable: to control write to CUI and array sector. WE=VIL becomes active. The

data and addresses are latched o n the rising edge o f the seco nd WE pulse .

VPP input/supply Program/Erase P ower Supply:(1.65V~3.6V or 11.4V~12.6V)

Lower VPP<VPPLK, to pro tect an y contents against Program and Erase Command.

Set VPP=VCC f o r in-system Read, Program and Erase Operation.

Raise VPP to 12V±5% f or f aster program and erase in a productio n en vironment.

OE input Output enable: gates the device's outputs during a real cycle.

WP input Write Protect: When WP is VIL, the sectors marked Lock Down can't be unlocked

through software. When WP is VIH, the lock down mechanism is disable and sectors

previously locked down are now locked and can be unlocked and locked through soft-

ware . After WP go es lo w , any sectors previo usly marked lo c k down re vert to that state.

VCC supply Device power supply: (2.7V~3.6V).

VCCQ input I/O P ow er Supply: supplies f or input/output b uff ers. (VCCQ must be tied to VCC)

G N D supply Ground voltage: all the GND pin shall not be connected.

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SECTOR STRUCTURE (TOP)

Sector Sector Size Address Range (h)

Boot Sector 0 4K W o rd FF000 ~ FFFFF

Boot Sector 1 4K W o rd FE000 ~ FEFFF

Parameter Secto r 0 4K Wo rd FD000 ~ FDFFF

Parameter Secto r 1 4K Wo rd FC000 ~ FCFFF

P arameter Secto r 2 4K Word FB000 ~ FBFFF

P arameter Secto r 3 4K Word FA000 ~ FAFFF

Parameter Sector 4 4K Word F9000 ~ F9FFF

Parameter Sector 5 4K Word F8000 ~ F8FFF

Main Sector 0 32K Wo rd F0000 ~ F7FFF

Main Sector 1 32K Wo rd E8000 ~ EFFFF

Main Sector 2 32K W o rd E0000 ~ E7FFF

Main Sector 3 32K Wo rd D8000 ~ DFFFF

Main Sector 4 32K Wo rd D0000 ~ D7FFF

Main Sector 5 32K Wo rd C8000 ~ CFFFF

Main Sector 6 32K Wo rd C0000 ~ C7FFF

Main Sector 7 32K Wo rd B8000 ~ BFFFF

Main Sector 8 32K W o rd B0000 ~ B7FFF

Main Sector 9 32K Wo rd A8000 ~ AFFFF

Main Sector 10 32K W o rd A0000 ~ A7FFF

Main Sector 11 32K Wo rd 98000 ~ 9FFFF

Main Sector 12 32K Wo rd 90000 ~ 97FFF

Main Sector 13 32K Wo rd 88000 ~ 8FFFF

Main Sector 14 32K Wo rd 80000 ~ 87FFF

Main Sector 15 32K Wo rd 78000 ~ 7FFFF

Main Sector 16 32K Wo rd 70000 ~ 77FFF

Main Sector 17 32K Wo rd 68000 ~ 6FFFF

Main Sector 18 32K Wo rd 60000 ~ 67FFF

Main Sector 19 32K Wo rd 58000 ~ 5FFFF

Main Sector 20 32K Wo rd 50000 ~ 57FFF

Main Sector 21 32K Wo rd 48000 ~ 4FFFF

Main Sector 22 32K Wo rd 40000 ~ 47FFF

Main Sector 23 32K Wo rd 38000 ~ 3FFFF

Main Sector 24 32K Wo rd 30000 ~ 37FFF

Main Sector 25 32K Wo rd 28000 ~ 2FFFF

Main Sector 26 32K Wo rd 20000 ~ 27FFF

Main Sector 27 32K Wo rd 18000 ~ 1FFFF

Main Sector 28 32K Wo rd 10000 ~ 17FFF

Main Sector 29 32K Wo rd 08000 ~ 0FFFF

Main Sector 30 32K Wo rd 00000 ~ 07FFF

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SECTOR STRUCTURE (BOTTOM)

Sector Sector Size Address Range (h)

Boot Sector 0 4K Word 00000 ~ 00FFF

Boot Sector 1 4K Word 01000 ~ 01FFF

Parameter Secto r 0 4K Wo rd 02000 ~ 02FFF

Parameter Secto r 1 4K Wo rd 03000 ~ 03FFF

Parameter Secto r 2 4K Wo rd 04000 ~ 04FFF

Parameter Secto r 3 4K Wo rd 05000 ~ 05FFF

Parameter Secto r 4 4K Wo rd 06000 ~ 06FFF

Parameter Secto r 5 4K Wo rd 07000 ~ 07FFF

Main Sector 0 32K Wo rd 08000 ~ 0FFFF

Main Sector 1 32K Wo rd 10000 ~ 17FFF

Main Sector 2 32K Wo rd 18000 ~ 1FFFF

Main Sector 3 32K Wo rd 20000 ~ 27FFF

Main Sector 4 32K Wo rd 28000 ~ 2FFFF

Main Sector 5 32K Wo rd 30000 ~ 37FFF

Main Sector 6 32K Wo rd 38000 ~ 3FFFF

Main Sector 7 32K Wo rd 40000 ~ 47FFF

Main Sector 8 32K Wo rd 48000 ~ 4FFFF

Main Sector 9 32K Wo rd 50000 ~ 57FFF

Main Sector 10 32K Wo rd 58000 ~ 5FFFF

Main Sector 11 32K Wo rd 60000 ~ 67FFF

Main Sector 12 32K Wo rd 68000 ~ 6FFFF

Main Sector 13 32K Wo rd 70000 ~ 77FFF

Main Sector 14 32K Wo rd 78000 ~ 7FFFF

Main Sector 15 32K Wo rd 80000 ~ 87FFF

Main Sector 16 32K Wo rd 88000 ~ 8FFFF

Main Sector 17 32K Wo rd 90000 ~ 97FFF

Main Sector 18 32K Wo rd 98000 ~ 9FFFF

Main Sector 19 32K W o rd A0000 ~ A7FFF

Main Sector 20 32K Wo rd A8000 ~ AFFFF

Main Sector 21 32K W o rd B0000 ~ B7FFF

Main Sector 22 32K Wo rd B8000 ~ BFFFF

Main Sector 23 32K Wo rd C0000 ~ C7FFF

Main Sector 24 32K Wo rd C8000 ~ CFFFF

Main Sector 25 32K Wo rd D0000 ~ D7FFF

Main Sector 26 32K Wo rd D8000 ~ DFFFF

Main Sector 27 32K W o rd E0000 ~ E7FFF

Main Sector 28 32K Wo rd E8000 ~ EFFFF

Main Sector 29 32K Wo rd F0000 ~ F7FFF

Main Sector 30 32K Wo rd F8000 ~ FFFFF

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2 PRINCIPLES OF OPERATION

The pro duct includes an o n-chip WSM to manage sec-

tor erase, word write and lock-bit configuration functions.

After initial device power-up or return from reset mode

(see section on Bus Operations), the device defaults to

read array mode. Manipulation of external memory con-

trol pins allow array read, standby and output disable

operations.

Status register and identifier codes can be accessed

through the CUI independent of the VPP voltage. All

functions associated with altering memory contents -

sector erase, word write, sector lock/unlock, status and

identifier codes - are accessed via the CUI and verified

thro ugh the status register .

Commands are written using standard microprocessor

write timings. The CUI contents serve as input to the

WSM, which controls the sector erase, word write and

secto r lock/unlo ck. The internal algorithms are regulated

by the WSM, including pulse repetition, internal verifica-

tion and margining of data. Addresses and data are in-

ternally latched during write cycles. Address is latched

at falling edge of CE and data latched at rising edge of

WE. Writing the appropriate command outputs array data,

accesses the identifier codes or outputs status register

data.

Interface software that initiates and polls progress of

sector erase, word write and sector lock/unlock can be

sto red in any secto r. This code is co pied to and executed

from system RAM during flash memory updates. After

successful completion, reads are again possible via the

Read Array command. Sector erase suspend allows

system software to suspend a sector erase to read/write

data from/to sectors other than that which is suspend.

Word write suspend allows system software to suspend

a word write to read data from any other flash memory

array location.

With the mechanism of sector lock, memory contents

cannot be altered due to noise or unwanted operation.

When RP=VIH and VCC<VLKO (lockout voltage), any

data write alteration can be failure. During read opera-

tion, if write VPP voltage is below VPPLK, then hard-

ware level data protection is achieved. With CUI's two-

step command sequence sector erase, word write or

sector lock/unlock, software level data protection is

achie ved also.

3 BUS OPERATION

The local CPU reads and writes flash memory in-sys-

tem. All bus cycles to or from the flash memory conform

to standard microprocessor bus cycles.

3.1 Read

Infor mation can be read from any sector, configuration

codes or status register independent of the VPP volt-

age. RP can be at VIH.

The first task is to write the appropriate read mode com-

mand (Read Arra y, Read Co nfiguratio n, Read Query o r

Read Status Register) to the CUI. Upon initial device

power-up or after exit from reset, the device automati-

cally resets to read array mode. In order to read data,

control pins set for CE, OE, WE, RP and WP must be

driven to active. CE and OE must be active to obtain

data at the outputs. CE is the device selection control.

OE is the data output (DQ0-DQ15) control and active

drives the selected memory data onto the I/O bus, WE

must be VIH, RP must be VIH, WP must be at VIL or

VIH.

3.2 Output Disable

With OE at a logic-high level (VIH), the device outputs

are disabled. Output pins (DQ0-DQ15) are placed in a

high-impedance state.

3.3 Standby

CE at a logic-high level (VIH) places the device in

standby mode which substantially reduces device power

consumption. DQ0~DQ15 outputs are placed in a high-

impedance state independent of OE. If deselected dur-

ing sector erase, word write or sector lock/unlock, the

device continues functioning, and consuming active

power until the operation completes.

3.4 Reset

As RP=VIL, it initiates the reset mode. The device en-

ters reset/deep power down mode. However, the data

stored in the memory has to be sustained at least 100ns

in the read mode before the device becomes deselected

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and output high impedance state.

In read modes, RP-low deselects the memor y, places

output drivers in a high-impedance state and turns off all

internal circuits. RP must be held low for a minimum of

100ns. Time tPHQV is required after retur n from reset

mode until initial memory access outputs are valid. Af-

ter this wake-up interval tPHEL or tPHWL, normal op-

eration is resto red. The CUI is reset to read arr ay mode

and status register is set to 80H. Sector lock bit is set at

lock status.

During sector erase, word write or sector lock/unlock

modes, RP-low will abort the operation. Memory con-

tents being altered are no longer valid; the data may be

partially erased o r written.

In addition, CUI will go into either array read mode or

erase/write interrupted mo de. When power is up and the

device reset subsequently, it is necessary to read sta-

tus register in order to assure the status of the device.

Recognizing status register (SR.7~0) will assure if the

device goes back to normal reset and enters array read

mode.

3.5 Read Configuration Codes

The read configuration codes operation outputs the manu-

facturer code, device code, sector lock configuration

codes, and the protection register. Using the manufac-

turer and device codes, the system CPU can automati-

cally match the device with its proper algorithms. The

sector lock codes identify locked and unlocked sectors.

3.6 Write

Writing commands to the CUI enable reading of device

data and identifier codes. They also control inspection

and clearing of the status register. When VCC=2.7V -3.6V

and VPP within VPP1 or VPP2 range, the CUI addition-

ally controls sector erase, word write and sector lock/

unlock.

The Sector Erase command requires appropriate com-

mand data and an address within the sector to be erased.

The Full Chip Erase command requires appropriate com-

mand data and an address within the de vice. The Word

Write command requires the command and address of

the location to be written. Set Sector lock/unlock com-

mands require the command and address within the de-

vice or sector within the device (Sector Lock) to be

locked. The Clear Sector Lock-Bits command requires

the command and address within the device.

The CUI does not occupy an addressable memory loca-

tio n. It is written when WE and CE are activ e (whichever

goes high first). The address and data needed to ex-

ecute a co mmand are latched o n the rising edge of WE

or CE. Standard microprocessor write timings are used.

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4 COMMAND DEFINITIONS

The flash memo ry has fo ur read modes: read array , read

configuration, read status, read query, and two write

modes: pro gram, erase. These read modes are acces-

sible independent of the VPP voltage. But write modes

are disable during VPP<VPPLK. Placing VPP o n VPP1/

2 enables successful sector erase, word write and sec-

tor lock/unlock.

Device operations are selected by writing specific com-

mands into the CUI. Table 3 defines these co mmands .

Table 2. Bus Operation

Mode Notes RP CE OE WE DQ0~DQ15

Read 1,2 VIH VIL VIL VIH DOUT

Output Disable 2 VIH VIL VIH VI H High Z

Standby 2 VIH VIH X X High Z

Reset 2 VIL X X X High Z

Write 2,3,4,5 VIH VIL VIH VIL DIN

Notes:

1. Refer to DC Characteristics for VPPLK, VPP1, VPP2 voltage.

2. X can be VIL o r VIH f or pin and addresses.

3. RP at GND±0.2 to ensure the lowest power consumption.

4. Ref er to Ta ble 3 for valid DIN during a write o peratio n.

5. To pro g r am or erase the lockable secto rs holds WP at VIH.

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Table 3. Command Definition (1)

Command Bus Notes First Bus Cycle Second Bus Cycle

Cycles Operation Address Data Operation Address Data

Required (1) (2) (3) (1) (2) (3)

Read Array 1 Write X FFH

Read Configuration > 2 2,4 Write X 90H Read IA ID

Read Query 2 2,7 Write X 98H Read QA QD

Read Status Register 2 3 Write X 7 0H Read X SRD

Clear Status Register 1 3 Write X 5 0 H

Sector Erase/Confirm 2 Write X 2 0H Write SA D 0H

Word Write 2 2,5 Write X 40H/10H Write WA WD

Program/Erase Suspend 1 Write X B0H

Program/Erase Resume 1 Write X D0H

Sector Lock 2 Wr i te X 6 0H Wr i t e SA 0 1H

Sector Unlock 2 6 Write X 6 0H Write SA D 0 H

Lock-Down Sector 2 Write X 60H Write SA 2FH

Protection Program 2 Write X C0H Write PA PD

Notes:

1. Bus o peratio n are defined in Table 2 and ref erred to AC Timing W av efo rm.

2. X=Any address within device.

IA=ID-Co de Address (refer to Table 4).

ID=Data read from identifier code.

SA=Sector Address within the sector being erased.

W A=Address of memory location to be written.

WD=Data to be written at location W A.

PA=Pro gram Address, PD=Program Data

QA=Query Address, QD=Query Data.

3. Data is latched from the rising edge o f WE o r CE (whiche v er goes high first)

SRD=Data read from status register , see Table 6 f or descriptio n of the status register bits .

4. Following the Read Configuration codes command, read operation access manufacturer, device codes, sector

lock/unlock codes, see chapter 4.2.

5. Either 40H o r 10H command is reco gnized b y the WSM as word write setup.

6. The sector unlock operation simultaneously clear all sector lock.

7. Read Query Command is read for CFI query information.

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4.1 Read Array Command

Upon initial device power-up and after exit from reset

mode, the device defaults to read array mode. This op-

eration is also initiated by writing the Read Array com-

mand. The device remains enabled for reads until an-

other command is written. Once the internal WSM has

started a sector erase, word write or sector lock con-

figuration the device will not recognize the Read Array

co mmand until the WSM co mpletes its operatio n unless

the WSM is suspended via a Sector Erase Suspend or

Word Write Suspend command. If RP=VIL device is in

read Read Array command mode, this read operation no

longer requires VPP. The Read Array command func-

tions independently of the VPP voltage and RP can be

VIH.

4.2 Read Configuration Codes Command

The configuration code operation is initiated by writing

the Read Configuration Codes command (90H). To re-

turn to read array mode, write the Read Array Command

(FFH). Following the command write, read cycles from

addresses shown in Table 4 retrie ve the manufacturer,

device, sector lock configuration codes and the protec-

tion register(see Tab le 4 f or configuration co de values).

To terminate the operation, write another valid command.

Like the Read Array command, the Read Configuration

Codes command functions independently of the VPP

voltage and RP can be VIH. Fo llowing the Read Co nfigu-

ration Codes command, the information is shown:

Code Address Data

(A19-A0) (DQ15-DQ0)

Manufacturer Code 00000H 00C2H

Device Co de(To p/Bo ttom) 00001H 88C2/88C3H

Sector Lock Configuration XX002H LocK

- Sector is unlocked DQ0=0

- Sector is locked DQ0=1

- Sector is locked-down DQ1=1

Protection Register Lock 8 0 PR-LK

Protection Register 81-88 PR

Table 4: ID Code

4.3 Read Status Register Command

CUI writes read status command (70H). The status reg-

ister may be read to determine when a sector erase,

word write or lock-bit configuration is complete and

whether the operation co mpleted successfully. (refer to

table 6) It may be read at any time by writing the Read

Status Register command. After writing this command,

all subsequent read operations output data from the sta-

tus register until another v alid command is written. The

status register contents are latched on the falling edge

of CE or OE, whichever occurs last. CE or OE must

toggle to VIH before further reads to update the status

tio ns independently o f the VPP v o ltage. RP can be VIH.

4.4 Clear Status Register Command

Status register bits SR.5, SR.4, SR.3 or SR.1 are set to

"1"s by the WSM and can only be reset by the Clear

Status Register command (50H). These bits indicate

various failure co nditions (see Table 6). By allowing sys-

tem software to reset these bits, several operations (such

as cumulatively erasing multiple sectors or writing sev-

eral words in sequence) may be perfo rmed. The status

during the sequence.

To clear the status register, the Clear Status Register

command (50H) is written on CUI. It functions indepen-

dently of the applied VPP Voltage. RP can be VIH. This

command is not functional during sector erase or word

write suspend modes.

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4.5 Sector Erase Command

Erase is executed one sector at a time and initiated by a

two-cycle command. A sector erase setup is first writ-

ten (20H), fo llowed by a sector erase confirm (D0H). This

command sequence requires appropriate sequencing and

an address within the sector to be erased. Sector pre-

conditioning, erase, and verify are handled internally by

the WSM. After the two-cycle secto r er ase sequence is

written, the device automatically outputs status register

data when read (see Figure 8). The CPU can detect sec-

tor erase completion by analyzing the output data of the

status register bit SR.7.

When the sector erase is complete, status register bit

SR.5 should be checked. If a sector erase error is de-

tected, the status register should be cleared before sys-

tem software attempts corrective actions. The CUI re-

mains in read status register mode until a new com-

mand is issued.

This two-step command sequence of set-up followed by

execution ensures that sector contents are not acciden-

tally erased. An invalid sector Erase command sequence

will result in both status register bits SR.4 and SR.5

being set to "1". Also, reliable sector erasure can only

occur when 2.7V~3.6V and VPP=VPP1/2. In the absence

of this high voltage, sector contents are protected against

erasure. If sector erase is attempted while VPP<VPPLK

SR.3 and SR.5 will be set to "1". To successfully erase

the boot sector, the corresponding sector lock-bit must

be clear first. In parameter and sectors case, it must be

cleared the corresponding sector lock-bit. If sector erase

is attempted when the excepting above sector being

locked conditions, SR.1 and SR.5 will be set to "1". Sec-

tor erase is not functional.

4.6 W ord Write Command

Word write is executed by a two-cycle command se-

quence. Word write setup (standard 40H or alternate 10H)

is written, followed by a second write that specifies the

address and data. The WSM then takes o ver , controlling

the word write and write verify algo rithms internally. Af-

ter the word write sequence is written, the device auto-

matically outputs status register data when read (see

Figure 6). The CPU can detect the completion of the

word write event by analyzing the status register bit SR.7.

When word write is complete, status register bit SR.4

should be checked. If word write error is detected, the

status register should be cleared. The internal WSM verify

only detects errors for "1"s that do not successfully write

to "0"s. The CUI remains in read status register mode

until it receives another command.

Reliable word writes can only occur when

VCC=2.7V~3.6V and VPP=VPP1/2. If VPP is no t within

acceptable limits , the WSM doesn't ex ecut the pro gram

co mmand. If wo rd write is attempted while VPP<VPPLK,

status register bits SR.3 and SR.4 will be set to "1".

Successful word write requires for boot sector that WP

is VIH the corresponding sector lock-bit be cleared. In

parameter and main sectors case, it must be cleared

the corresponding sector lock-bit. If word write is at-

tempted when the excepting above sector being clocked

conditions, SR.1 and SR.4 will be set to "1". W ord write

is not functional.

4.7 Sector Erase Suspend Command

The Sector Erase Suspend command (50H) allows sec-

tor-erase interruption to read or word write data in an-

other secto r of memo ry. Once the sector erase process

starts, writing the Sector Erase Suspend command re-

quests that the WSM suspend the sector erase sequence

at a predetermined point in the algorithm. The device

outputs status register data when read after the Sector

Erase Suspend co mmand is written. P o lling status reg-

ister bits SR.7 and SR.6 can determine when the sector

erase operation has been suspended (both will be set to

"1"). Specification tWHRH2/tEHRH2 defines the sector

erase suspend latency.

When Sector Erase Suspend command is written to the

CUI, if sector erase was finished, the device would be

placed read array mode. Therefore, after Sector Erase

Suspend command is written to the CUI, Read Status

status register bit SR.6 should be checked if/when the

device is in suspend mode.

At this point, a Read Array command can be written to

read data from sectors other than that which is sus-

pended. A Wo rd Write co mmands sequence can also be

issued during erase suspend to program data in other

secto rs . Using the W o rd Write Suspend co mmand (see

Section 4.9), a word write operation can also be sus-

pended. During a word write operation with sector erase

suspended, status register bit SR.7 will return to "0".

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REV. 1.2, MAR. 17, 2004

However, SR.6 will remain "1" to indicate sector erase

suspend status.

The only other valid commands while sector erase is

suspended are Read Status Register , Read Co nfigura-

tion, Read Query, Program Setup, Program Resume,

Sector Lock, Sector Unlock, Sector Lock-Down and sec-

tor erase Resume. After a Sector Erase Resume com-

mand is written to the flash memo ry, the WSM will co n-

tinue the sector erase process. Status register bits SR.6

and SR.7 will automatically be cleared. After the Erase

Resume command is written, the device automatically

outputs status register data when read (see Figure 9).

VPP must remain at VPP1/2 while sector erase is sus-

pended. RP must also remain at VIH (the same RP level

used for sector erase). Sector cannot resume until word

write operations initiated during sector erase suspend

has completed.

If the time between writing the Sector Erase Resume

command and writing the Sector Erase Suspend com-

mand is sho rter than 15ms and both co mmands are writ-

ten repeatedly, a longer time is required than standard

sector erase until the completion of the operation.

4.8 Word Write Suspend Command

The Word Write Suspend command allows word write

interruption to read data in other flash memory locations.

Once the word write process starts, writing the Word

Write Suspend command requests that the WSM sus-

pend the Wo rd write sequence at a predetermined point

in the algorithm. The device continues to output status

command is written. P olling status register bits SR.7 and

SR.2 can determine when the word write operation has

been suspended (both will be set to "1"). Specification

tWHRH1/tEHRH1 defines the wo rd write suspend latency .

When Wo rd Write Suspend command write to the CUI, if

word write was finished, the device places read array

mode. Therefore, after W ord Write Suspend co mmand

write to the CUI, Read Status Register command (70H)

has to be written to CUI, then status register bit SR.2

should be checked for if/when the device is in suspend

mode.

At this point, a Read Array command can be written to

read data from locations other than that which is sus-

pended. The only other valid co mmands while wo rd write

is suspended are Read Status Register Read Configura-

tion, Read Query and Word W rite Resume. After Word

Write Resume co mmand is written to the flash memory,

the WSM will continue the Word write process. Status

After the Word W r ite Resume command is written, the

device automatically outputs status register data when

read (see Figure 7). VPP must remain at VPP1/2 while

in word write suspend mode. RP must also remain at

VIH (the same RP level used for word write).

If the time between writing the W ord Write Resume com-

mand and writing the W o rd Write Suspend co mmand is

short and both commands are written repeatedly , a lo nger

time is required than standard word write until the comple-

tion of the operation.

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REV. 1.2, MAR. 17, 2004

4.9 Sector Lock/Unlock /Lockdown Command

4.9.1 Sector Locked State

The default status of all sectors upon power-up or reset

is locked. Any attempt on program or erase operations

will result in an error o n bit SR.1 of a lock ed sector. The

status of a locked sector can be changed to unlocked or

lock-down using software commands. An unlocked sec-

tor can be locked by writing the sector lock command

sequence, 60H followed by 01H.

4.9.2 Sector Unlocked State

An unlocked sector can be programmed or erased. All

unlocked sector return to the locked state when the de-

vice is either reset or powered down. The status of an

unlocked sector can be changed to locked or locked-

down using software commands. A locked sector can

be unlocked by writing unlock command sequence, 60H

followed by D0H.

4.9.3 Sector Locked-Down State

Sectors which are locked-down are protected from pro-

gram and erase operatio n; how e v er, the protection sta-

tus of these sectors cannot be changed using software

commands alone. Any sector locked or unlocked can be

locked-down by writing the lock-down command se-

quence, 60H f o llowed b y 2FH. When the device is reset

o r powered do wn, the locked-down secto rs will revert to

the locked state.

The status of WP will determine the function of sector

lock-down and is summarized is followed:

WP Sector Lock-down Description

WP=0 - sectors are protected from program, erase,

and lock status changes

WP=1 - the sector lock-down function is disabled

- an individual lock-down sector can be un-

locked and relocked via software command.

Once WP goes low, sectors that previously

locked-down returns to lock-down state

regardless o f any changes when WP was

high.

4.9.4 Read Sector Lock Status

The lock status of every sector can be read through

Read Co nfiguratio n mode. To enter this mode, first co m-

mand write 90H to the device. The subsequent reads at

sector address +00002 will output the lock status of this

sector . The lock status can be read from the lo west two

output pins DQ0 and DQ1. DQ0, DQ0 indicates the sec-

tor lock/unlock status and set by the lock command and

cleared by the unlock command. When entering lock-

down, the lock status is automatically set. DQ1 indi-

cates lock-down status and is set by the lock-down com-

mand. It cannot be further cleared by software, only by

device reset or power-down.

Secto r Lock Configuratio n Table

Lock Status Data

Sector is unlocked DQ0=0

Sector is locked DQ0=1

Sector is locked-down DQ1=1

In addition, sector lock-down is cleared only when the

device is reset or powered down.

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REV. 1.2, MAR. 17, 2004

4.9.5 Sector Locking while Erase Suspend

The sector lock status can be performed during an erase

suspend by using standard locking command sequences

to unlock, lock, or lock-down a sector.

In order to change sector locking during an erase opera-

tion, the write erase suspend command (B0H) is placed

first; then check the status register until it is shown that

the actual erase operation has been suspended. Subse-

quent writing the desired lock command sequence to a

sector and the lock status will be changed. When com-

pleting any desired lock, read or program operation, re-

sume the erase operation with the Erase Resume Com-

mand (D0H).

If a sector is locked or locked-down during the same

4.9.6 Status Register Error Checking

The operation of locking system for this device can be

used the term "state (X,Y,Z)" to specify locking status,

where X=v alue of WP, Y=bit DQ1 of the secto r lock sta-

tus register, and Z=bit DQ0 of the sector lock status

locked (0). DQ1 indicates if a sector has been locked-

down(1) or not (0).

Current State Erase/Prog. Lock Command Input Result (Next State)

(X, Y, Z)= Operation if (X, Y, Z)=

WP DQ1 DQ0 Name Enable ? Lock Unlock Lock-Down

0 0 0 Unlocked Yes (001) Unchanged (011)

0 0 1 Locked (default) N o Unchanged (000) (011)

0 1 1 Locked-Down No Unchanged Unchanged Unchanged

1 0 0 Unlocked Yes (101) Unchanged (111)

1 0 1 Locked No Unchanged (100) (111)

1 1 0 Lock-Down Disabled Yes (111) Unchanged (111)

1 1 1 Lock-Down Disabled N o Unchanged (110) Unchanged

Table 5. Sector Locking State Transitions

sector is being placed in erase suspend, the locking sta-

tus bits will be changed immediately, but when the erase

is resumed, the erase operation will complete.

Locking operation cannot be performed during a program

suspend.

Note:

At pow er-up or device reset, all sectors default to lock ed state (001) (if WP=0).

Ho lding WP=0 is the reco mmended default.

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Table 6. Status Register Definition

SR.7 = WRITE STATE MA CHINE STATUS (WSMS)

1 = Ready

0 = Busy

SR.6 = SECT OR ERASE SUSPEND STATUS (SESS)

1 = Sector ERASE Suspended

0 = Sector Erase in Progress/Completed

SR.5 = ERASE STATUS (ES)

1 = Error in Programming

0 = Successful Sector Erase or Clear Sector Lock-

Bits

SR.4 = PROGRAM STATUS (PS)

1 = Error in Programming

0 = Successful Programming

SR.3 = VPP STATUS (VPPS)

1 = VPP Low Detect, Operation Abort

0 = VPP OK

SR.2 = PROGRAM SUSPEND STATUS (PSS)

1 = Program Suspended

0 = Program in Progress/Completed

SR.1 = SECTOR LOCK STATUS (SLS)

1 =Program/Erase attempted an a locked sector;

o peratio n aborted

0 = No operation to locked sectors

SR.0 = RESERVED FOR FUTURE ENHANCEMENTS

(R)

NOTES:

Check WSM bit first to determine wo rd pro g ram o r sec-

tor Erase completion, before checking Program or Erase

Status bits.

When Sector Erase Suspend is issued, WSM halts e x-

ecutio n and sets both WSMS and SESS bits to "1". SESS

bit remains set to "1" until an Sector Erase Resume

command is issued.

When this bit (SR.5) is set to "1", it means WSM is

unable to verify successful sector erasure.

When this bit is set to "1", WSM has attempted but failed

to program a word.

The WSM interrogates VPP level o nly after the Program

or Erase command sequences have been entered and

infor ms the system if VPP has not been switched on.

SR.3 bit is not guaranteed to report accurate f eedback

between VPPLK and VPP1 min.

When program suspend is issued, WSM halts the ex-

ecutio n and sets both WSMS and PSS bits to "1". SR.2

remains set to "1" until a Program Resume command is

issued.

If a program or erase operation is attempted to one of

the locked sectors, this bit is set by the WSM. The op-

eratio n specified is aborted and the device is returned to

read status mode.

SR. 0 is reserved for future use and should be masked

o ut when polling the status register.

WSMS SESS ES PS VPPS PSS SLS R

76543 2 1 0

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REV. 1.2, MAR. 17, 2004

5. 128-Bit Protection Register

The 128 bits of protection register are divided into two

64-bit segments. One of the segments is programmed

at MXIC side with unique 64-bit number; where changes

are forbidden. The other segment is left empty for cus-

tomer to program. Once the customer segment is pro-

grammed, it can be locked to pre vent further repro gram-

ming.

5.1 Protection Register Read & Programming

The protection register is read in the configuration read

mode, which follows the stated Command Bus Defini-

tions.

The device is switched to this read mode by writing the

Read Configuration command (90H). Once in this mode,

read cycles from addresses shown in Table 7 will re-

trieve the specified information. To return to read array

mode, write the Read Array Command (FFH).

Two-cycle Pro tection Pro gram Command is used to pro-

gram protectio n register bits . The 64-bit number is pro-

grammed 16 bits at a time. First, write C0H Protection

Program Setup command. The next write to the device

will latch in address and data and program the specified

lo catio n. The allowable address are also shown in Table

7. Refer to Figure 11 for the Protection Register Pro-

gramming Flowchart.

Any attempt to address Protection Program command

onto undefined protection register address space will

result in a Status Register error (SR.4 set to "1"). In

addition, attempting to program to a previously locked

protection register segment will result in a status regis-

ter error (SR.4=1, SR.1=1).

Word User A7 A6 A5 A4 A3 A2 A1 A0

Lock Both 1 0 0 0 0 0 0 0

0 Factory 1 0 0 0 0 0 0 1

1 Factory 1 0 0 0 0 0 1 0

2 Factory 1 0 0 0 0 0 1 1

3 Factory 1 0 0 0 0 1 0 0

4 Customer 1 0 0 0 0 1 0 1

5 Customer 1 0 0 0 0 1 1 0

6 Customer 1 0 0 0 0 1 1 1

7 Customer 1 0 0 0 1 0 0 0

Table 7. Wo rd-Wide Protection Register Addressing

5.2 Protection Register Locking

The user-programmable segment of the protection reg-

ister is lockable by programming Bit 1 of the PR-Lock

location to 0. Bit 0 of this location is programmed to 0 at

MXIC to protect the unique device number. This bit is

set using the protection program command to program

"FFFD" to PR-LOCK location. After these bits have been

programmed, no fur ther changes can be made to the

value stored in the protection register. Protection Pro-

gram command to a locked section will result in a status

SR.1 will be set to 1). Protection register lockout state is

not reversible.

Protection Register Purpose

Bit Address

88H~85H 4 words User Program

84H~81H 4 wo rds F acto ry Pro gr am

80H(Bit0 & Bit1) Protection Register Lock

Table 8. Protection Register Memory Map

Notes: 1. Set address bit A19-A15=1 for TOP Boot de vice.

2. Set address bit A19-A15=0 for Bottom Boot device.

3. The address not specified in above are don't care.

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REV. 1.2, MAR. 17, 2004

6 ELECTRICAL SPECIFICATIONS

6.1 ABSOLUTE MAXIMUM RATINGS

Operating T emperature

During Read, Sector Erase, Wo rd

Write . . . . . . . . . . . . . . . . . . . . . . . . . -40oC to +85oC

Storage Temperature . . . . . . . . . . . . . .-65oC to +125oC

Voltage o n An y Pin (except VCC and

VPP) with respect to GND . . . . . . . . .-0.5 V to +3.7V(1)

VPP Supply Vo ltage (f or Secto r Erase and W ord Write)

with respect to GND . . . . . . . . . .-0.5V to +13.5V(1,2,4)

VCC and VCCQ Supply V o ltage

with respect to GND. . . . . . . . . . . . . . . . .-0.2V to +3.6V(1)

Output Shor t Circuit Voltage . . . . . . . . . . . . .100mA(3)

W ARNING: Stressing the de vice beyond the "Abso lute

Maximum Ratings" may cause permanent damage.

These are stress ratings only. Operation beyond the

"Operating Conditions" is not recommended and ex-

tended exposure beyond the "Operation Conditions" may

affect device reliability.

6.2.1 Capacitance (1) (TA=+25oC, f=1MHz)

Symbol Parameter Min. Max. Unit Notes

T A Operating Temperature -40 +85 oC

VCC1 VCC Supply V o ltage 2.7 3.6 V 1

VCCQ I/O Supply Voltage 2. 7 3. 6 V 1

VPP1 Supply Voltage 1.65 3.6 V 1

VPP2 Supply Voltage 11.4 12.6 V 1,2

Cycling Sector Erase Cycling 100,000 2

6.2 Operating Conditions (Temperature and VCC Operating Co nditions)

Symbol Parameter Typ. Max. Unit Test Condition

CIN Input Capacitance 6 8 pF VIN=0.0V

COUT Output Capacitance 10 12 pF VOUT=0.0V

NOTE:

1.Sampled, not 100% tested.

1. Minimum DC voltage is -0.5V on input/output pins.

During transitions, this level may undershoot to -2.0V

for periods <20ns. Maximum DC voltage on input/out-

put pins to VCC+0.5V which dur ing transition; may

overshoot to VCC+2.0V for periods <20ns.

2. Maximum DC voltage on VPP may overshoot to

+14.0V for periods <20ns.

3. Output shorted fo r no more than one second. No more

than one output shorted at a time.

4. VPP voltage is nor mally 1.65V~3.6V. Connection to

supply of 11.4V~12.6V can only be done for 1000

cycles on the main sectors and 2500 cycles on the

parameter sectors during program/erase. VPP may

be connected to 12V for a total of 80 hours maximum.

NOTE:

1.VCC and VCCQ must share the same supply when they are in the VCC1 range.

2.Applying VPP=11.4~12.6V during a program/erase can only be done for a maximum of 1000 cycles on the main

sectors and 2500 cycles o n the par ameter sectors. VPP ma y be connected to 12V f or a total of 80 ho urs maxim um.

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REV. 1.2, MAR. 17, 2004

6.2.2 AC Input/Output Test Conditions

Figure 1. T ransient Input/Output Reference W aveform

TEST POINTS VCCQ/2 Output

Note:AC test inputs are driven at VCCQ/2 for a Logic "1" and 0.0V for a Logic "0".

VCCQ

0.0

Input VCCQ/2

Figure 2. SWITCHING TEST CIRCUITS TEST SPECIFICA TIONS

Test Co nditio n 7 0 9 0 1 1 0 Unit

Output Load 1 TTL gate

Output Load Capacitance, CL 3 0 100 100 p F

(including jig capacitance)

Input Rise and F all Times 5 ns

Input Pulse Levels 0.0-3.0 V

Input timing measurement 1.5 V

reference levels

Output timing measurement 1.5 V

reference levels

DEVICE UNDER

TEST

DIODES=IN3064

OR EQUIVALENT

CL 6.2K ohm

2.7K ohm 3.3V

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6.2.3 AC Characteristic -- Read Only Operation (1)

-70 -90 -110

Sym. Parameter Notes Min. Max. Min. Max. Min. Max. Unit

tAV A V Read Cycle Time 7 0 9 0 11 0 ns

tA VQV Address to Output Delay 7 0 9 0 1 1 0 ns

tELQV CE to Output Delay 2 7 0 90 1 1 0 n s

tG LQV OE to Output Delay 2 20 3 0 30 ns

tPHQV RP to Output Delay 1 5 0 1 5 0 1 5 0 ns

tELQX CE to Output in Low Z 3 0 0 0 ns

tG LQ X OE to Output in Low Z 3 0 0 0 n s

tEHQZ CE to Output in High Z 3 20 20 2 0 n s

tGHQZ OE to Output in High Z 3 20 20 2 0 ns

tO H Output Hold from Address, 3 0 0 0 ns

CE, or OE Change,

Whichever Occurs First

Notes:

1. See A C Wavef o rm: Read Operatio ns at Figure 3.

2. OE ma y be delayed up to tELQV-tGLQV after the falling edge of CE without impact on tELQV.

3. Sampled, but not 100% tested.

4. See test Configuration.

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REV. 1.2, MAR. 17, 2004

Figure 3. READ-ONLY OPERATION AC WAVEFORM

tEHQZ

tAVAV

tGHQZ

tGLQV

tELQV

tELQX

tAVQV

tPHQV

tGLQX tOH

High Z

High Z Valid Output

Address Stable

Device and

Address Selection Data

Valid Standby

VIH

VIL

Addresses(A)

VIH

VIL

CE (E)

VIH

VIL

OE (G)

VIH

VIL

WE (W)

VIH

VIL

RP (P)

VOH

VOL

DATA

(D/Q)

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REV. 1.2, MAR. 17, 2004

6.2.5 AC Characteristic -- Write Operation

Notes:

1. Write timing characteristics during erase suspend are the same as during write-only operations.

2. Refer to Table 5 f or valid AIN or DIN.

3. Sampled, not 100% tested.

4. Write pulse width (tWP) is defined from CE or WE going low (whichever goes low last) to CE or WE going high

(whichever go es high first). Hence, tWP=tWLWH=tELEH=tWLEH=tEL WH. Similarly , Write pulse width high (tWPH)

is defined fro m CE o r WE go ing high (whichev er go es high first) to CE o r WE going low (whiche ver go es low first).

Hence, tWPH=tWHWL=tEHEL=tWHEL=tEHWL.

5. See T est Configuration.

-70 -90 -110

Sym. Parameter Note Min. Min. Min. Unit

tPHWL/tPHEL RP High Recovery to WE(CE) Go ing Low 1 5 0 1 5 0 1 50 ns

tELWL/tWLEL CE(WE) Setup to WE(CE) Go ing Low 0 0 0 ns

tWLWH/tELEH WE(CE) Pulse Width 4 4 5 60 70 ns

tDVWH/tDVEH Data Setup to WE(CE) Go ing High 2 4 0 5 0 6 0 ns

tA VWH/tA VEH Address Setup to WE(CE) Go ing High 2 5 0 6 0 7 0 ns

tWHEH/tEHWH CE(WE) Hold Time fro m WE(CE) High 0 0 0 ns

tWHDX/tEHDX Data Ho ld Time fro m WE(CE) High 2 0 0 0 ns

tWHAX/tEHAX Address Hold Time from WE(CE) High 2 0 0 0 ns

tWHWL/tEHEL WE(CE) Pulse Width High 4 2 5 30 30 ns

tVPWH/tVPEH VPP Setup to WE(CE) Go ing High 3 2 0 0 2 0 0 2 00 ns

tQVVL VPP Hold from Valid SRD 3 0 0 0 ns

tBHWH/tBHEH WP Setup to WE(CE)Going High 3 0 0 0 ns

tQVBL WP Hold from Valid SRD 3 0 0 0 ns

tWHGL WE High to OE Going Low 3 3 0 3 0 3 0 n s

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REV. 1.2, MAR. 17, 2004

Figure 4. WRITE AND ERASE OPERATION AC WAVEFORM

Notes:

1. CE must be toggled low when reading Status Register Data. WE must be inactive (high) when reading Status

A.VCC Power-Up and Standby.

B.Write Program or Erase Setup Command.

C.Write V alid Address and Data (fo r Pro gram) o r Erase Co nfirm Command.

D.A utomated Program or Erase Dela y.

E.Read Status Register Data (SRD): reflects completed program/erase operation.

F.Write Read Array Co mmand.

tVPWH

(tVPEH) tQVVL

tWHWL

(tEHEL) tWHGL

tPHWL

(tPHEL)

(Note 1)

tELEH

(tWLWH)

tWHDX

(tEHDX)

tWHEH

(tEHWH)

tELWL

(tWLEL)

tAVWH

(tAVEH) tWHAX

(tEHAX)

tDVWH

(tEVEH)

tBHWH

(tBHEH) tQVBL

High Z

DIN

Address (A)

AB CD E F

VIH

VIL

OE(G)

VIH

VIL

VIH

VIL

CE(WE)[E(W)]

VIH

Disable

Enable VIL

WE,(CE)[W(E)]

VIH

VIL

DATA[D/Q]

VOH

VOL

RP[P]

VIH

VIL

VPPH1

VPPH2

VPPLK

VIL

VPP[V]

DIN

AIN AIN

DIN

Valid

SRD

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REV. 1.2, MAR. 17, 2004

6.2.5 Erase and Program Timing (1)

Vpp 1.65V-3.6V 11.4V-12.6V

Symbol Parameter Note Typ(1) Max Typ(1) Max Unit

tBWPB 4-KW Parameter Secto r 2,3 0.10 0.30 0.03 0.12 s

Wo rd Program Time

tBWMB 32-KW Main Sector 2,3 0.8 2.4 0.24 1 s

Wo rd Program Time

tWHQV1/ Wo rd Program Time 2,3 12 200 8 185 us

tEHQV1

tWHQV2/ 4-KW Parameter Secto r 2,3 0.5 4 0.4 4.0 s

tEHQV2 Erase Time

tWHQV3/ 32-KW Main Sector 2,3 1 5 0.6 5 s

tEHQV3 Erase Time

tWHRH1/ Program Suspend Latency 3 1 5 20 1 5 2 0 us

tEHRH1

tWHRH2/ Erase Suspend Latency 3 15 2 0 1 5 2 0 us

tEHRH2

Notes:

1. Typical values measured at TA=+25°C and no minal vo ltage.

2. Excludes external system-level overhead.

3. Sampled, but not 100% tested.

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REV. 1.2, MAR. 17, 2004

AC Characteristic -- Under Reset Operation

Sym. Parameter VCC=2.7V~3.6V Unit Notes

Min. Max.

tPLPH RP Low to Reset during Read 100 ns 1,3

(If RP is tied to VCC, this specification is not applicable)

tPLRH1 RP Low to Reset during Sector Erase 2 2 u s 1, 4

tPLRH2 RP Low to Reset during Program 1 2 us 1,4

Notes:

1. See Section 3.4 for a full description of these conditions.

2. If tPLPH is < 100ns the device may still reset but this is not guaranteed.

3. If RP is asserted while a sector erase or word program operation is not executing, the reset will complete within

100ns.

4. Sampled, but not 100% tested.

Figure 5. RESET WAVEFORM

tPLPH

tPLRH Abort

Complete

tPHQV

tPHWL

tPHEL

tPHQV

tPHWL

tPHEL

VIH

VIL

RP (P)

(A) Reset during Read Mode

tPLPH

VIH

VIL

RP (P)

(B) Reset during Program or Sector Erase, tPLPH < tPLRH

tPLRH

Abort

Complete Deep

Power-

Down tPHQV

tPHWL

tPHEL

tPLPH

VIH

VIL

RP (P)

P/N:PM0867

MX28F160C3T/B

REV. 1.2, MAR. 17, 2004

6.2.6 DC Characteristics VCC 2.7V-3.6V

Sym. Parameter VCCQ 2.7V-3.6V Unit Test Conditions

Note Typ. Max.

ILI Input Load Current 1,2 ± 1 uA VCC=VCC Max. ; VCCQ=VCCQ Max.

VIN=VCCQ or GND

ILO Output Leakage 1,2 0.2 ± 10 uA VCC=VCC Max. ; VCCQ=VCCQ Max.

Current VIN=VCCQ or GND

ICCS VCC Standby Current 1 7 1 5 uA VCC=VCC Max. ; CE=RP=VCCQ

or during Program/Erase Suspend

WP=VCCQ or GND

ICCD VCC Power-Down 1,2 7 15 uA VCC=VCC Max; VCCQ=VCCQ Max

Current VIN=VCCQ or GND

RP=GND±0.2V

ICCR VCC Read Current 1,2,3 9 1 8 mA VCC=VCC Max; VCCQ=VCCQ Max

OE=VIH, CE=VIL, f=5MHz, IOUT=0mA

Inputs=VIL or VIH

IPPD VPP Deep Power- 1 0.2 5 uA RP=GND±0.2V

Down Current VPP < VCC

IPPR VPP Read Current 1,4 2 ±15 uA VPP < VCC

50 20 0 uA VPP > VCC

ICCW+ VCC+VPP Program 1,4 1 8 5 5 mA VPP=VPP1, Program in Progress

IPPW Current 10 30 mA VPP=VPP2(12V), Program in Progress

ICC E+ VCC+VPP Erase 1,4 21 4 5 mA VPP=VPP1, Erase in Progress

IPPE Current 16 45 mA VPP=VPP2(12V), Erase in Progress

ICCES VCC Program 1,4 7 15 uA CE=VCC,

o r or Erase Suspend Program or Erase Suspend in Progress

ICCWS Current

VIL Input Low V o ltage -0.4 VCC*0.22V V

VIH Input High V oltage 2.0 VCCQ+0.3V V

V OL Output Low V o ltage -0.1 0.1 V VCC=VCC Min, VCC=VCCQ Min

IOL=100uA

V O H Output High V oltage VCCQ V VCC=VCC Min, VCC=VCCQ Min

-0.1V IOH=-100uA

VPPLK VPP Lock-Out Voltage 6 1.0 V Complete Write Protection

VPP1 VPP during Program/ 6 1.65 3.6 V

VPP2 Erase Operations 6 11.4 12.6 V

VLK O VCC Prog/Erase 1.5 V

Lock Voltage

VLK O2 VCCQ Prog/Erase 1.2 V

Lock Voltage

P/N:PM0867

MX28F160C3T/B

REV. 1.2, MAR. 17, 2004

Notes:

1. All currents are in RMS unless o therwise noted. Typical values at no minal VCC , TA=+25°C.

2. The test co nditio ns VCC Max, VCCQ Max, VCC Min, and VCCQ Min refer to the maximum o r minimum VCC o r

VCCQ voltage listed at the top of each column.

3. Power Sa vings (Mode) reduces ICCR to appro ximately standby le v els in static o peratio n (CMOS inputs).

4. Sampled, but not 100% tested.

5. ICCES and ICCWS are specified with device de-selected. If device is read while in erase suspend, current draw is

sum of ICCES and ICCR. If the device is read while in program suspend, current draw is the sum of ICCWS and

ICCR.

6. Erase and Pro gram are inhibited when VPP<VPPLK.

P/N:PM0867

MX28F160C3T/B

REV. 1.2, MAR. 17, 2004

Figure 6. Automated Word Programming Flowchar t

Bus Command Comments

Operation

Write Program Data=40H

Setup

Write Program Data=Data to Program

Addr=Location to Program

Read Status Register Data To ggle

CE or OE to Update Status

Standby Check SR.7

1=WSM Ready

0=WSM Busy

Repeat for subsequent programming operations.

SR full status check can be done after each program

or after a sequence of program operations.

Write FFH after the last program operation to reset

device to read array mode.

Bus Command Comments

Operation

Standby Check SR.3

1=VPP Low Detect

Standby Check SR.4

1=VPP Program Error

Standby Check SR.1

1=Attempted Program to

Locked Sector-Program

Aborted

SR.3 MUST be cleared, if set during a program at-

tempt, befo re further attempts are allowed by the Write

State Machine.

SR.4, SR.3, and SR.1 are only cleared by the Clear

Status Register Command, in cases where multiple

bytes are programmed before full status is checked.

If an error is detected, clear the status register before

attempting retry o r o ther error reco v ery.

Start

Write 40H

Full Status

Check if Desired

Read Status Register

Program Address/Data

Yes

SR.7=1 ?

Program Ccomplete

Read Status Register

Data(See Above)

FULL STATUS CHECK PROCEDURE

Program Successful

SR.3=

VPP Range Error

Programming Error

Attempted Program to

Locked Sector- Aborted

SR.4=

SR.1=

P/N:PM0867

MX28F160C3T/B

REV. 1.2, MAR. 17, 2004

Figure 7. Program Suspend/Resume Flowchart

Bus Command Comments

Operation

Write Program Data=B0H

Suspend Addr=X

Write Read Status Data=70H

Addr=X

Read Status Register Data To ggle

CE or OE to Update Status

Addr=X

Standby Check SR.7

1=WSM Ready

0=WSM Busy

Stanby Check SR.2

1=Program Suspended

0=Program Completed

Write Read Array Data=FFH

Addr=X

Read Read array data from

sector other than the one

being programmed.

Write Program Data=D0H

Resume Addr=X

Start

Program Write Resumed

Program Completed

Write B0H

Write 70H

Read

Status Register

Write FFH

Read Array Data

Write D0H

SR.7=

SR.2=

Yes

Done Reading

Read Array Data

Write FFH

P/N:PM0867

MX28F160C3T/B

REV. 1.2, MAR. 17, 2004

Figure 8. Automated Sector Erase Flowchart

Bus Command Comments

Operation

Write Erase Setup Data=20H

Addr=Within Sector to Be

Erased

Write Erase Data=D0H

Confirm Addr=Within Sector to Be

Erased

Read Status Register Data To ggle

CE or OE to Update Status

Standby Check SR.7

1=WSM Ready

0=WSM Busy

Repeat for subsequent sector erasures.

Full status check can be done after each sector erase

or after a sequence of sector erasures.

Write FFH after the last write operation to reset device

to read array mode.

Bus Command Comments

Operation

Standby Check SR.3

1=VPP Low Detect

Standby Check SR.4, 5

Both 1=Command

Sequence Error

Standby Check SR.5

1=Sector Erase Error

Standby Check SR.1

1=Attempted Erase of

Locked Sector- Erase

Aborted

SR.1 and SR.3 MUST be cleared, if set during an erase

attempt, before further attempts are allowed by the

Write State Machine.

SR.1,3,4,5 are only cleared by the Clear Status Reg-

ister Command, in cases where multiple bytes are

erased before full status is checked.

If an error is detected, clear the status register before

attempting retry o r o ther error reco v ery.

Start

Write 20H

Write D0H and

Sector Address

Full Status Check if Desired

Sector Erase Complete

Read

Status Register Suspend

Erase Loop

Yes

SR.7= Suspend Erase

Read Status Register

Data(See Above)

FULL STATUS CHECK PROCEDURE

Sector Erase Successful

SR.3=

VPP Range Error

Command Sequence Error

Sector Erase Error

SR.4,5=

SR.5=

Attempted Erase of Locked

Sector - Aborted

SR.1=

P/N:PM0867

MX28F160C3T/B

REV. 1.2, MAR. 17, 2004

Figure 9. Erase Suspend/Resume Flowchart

Bus Command Comments

Operation

Write Erase Data=B0H

Suspend Addr=X

Write Read Status Data=70H

Addr=X

Read Status Register Data To ggle

CE or OE to Update Status

Addr=X

Standby Check SR.7

1=WSM Ready

0=WSM Busy

Stanby Check SR.6

1=Erase Suspended

0=Erase Completed

Write Read Array Data=FFH

Addr=X

Read Read array data from

sector other than the one

being erased.

Write Erase Data=D0H

Resume Addr=X

Start

Erase Write Resumed

Erase Completed

Write B0H

Write 70H

Read

Status Register

Write FFH

Read Array Data

Write D0H

SR.7=

SR.6=

Yes

Done Reading

Read Array Data

Write FFH

P/N:PM0867

MX28F160C3T/B

REV. 1.2, MAR. 17, 2004

Figure 10. Locking Operations Flowchart Bus Command Comments

Operation

Write Config. Setup Data=60H

Addr=X

Write Lock, unlock Data=01H (Sector Lock)

or Lockdown D0H(Sector Unlock)

2FH(Sector Lockdown)

Addr=Within sector to lock

Write Read Status Data=70H

(Optional) Register Addr=X

Read Status Register Register

(Optional) Addr=X

Stanby Check Status Register

(Optional) 80H=no error

30H=Lock Command

Sequence Error

Write Read Data=90H

(Optional) Configuration Addr=X

Read Sector Lock Sector Lock Status Data

(Optional) Status Addr=Second addr of

sector

Stanby Confirm Locking Change

on DQ1, DQ0 (See Sector

Locking State Table for

valid combinations.)

Start

Locking Change

Complete

Lock Command

Sequence Error

Write 60H

(Configuration Setup)

Write

01H, D0H, or 2FH

Write 70H

(Read Status Register)

Read Status Register

1,1

0,0

Write 90H

(Read Configuration)

Read Sector Lock Status

SR.4, SR.5=

Yes

Locking Change

Confirmed ?

P/N:PM0867

MX28F160C3T/B

REV. 1.2, MAR. 17, 2004

Figure 11. Protection Register Programming Flowchart

Start

Write C0H

(Protection Reg. Program Setup)

Full Status

Check if Desired

Read Status Register

Write Protect. Register

Address/Data

Yes

SR.7=1 ?

Program Ccomplete

Read Status Register

Data(See Above)

FULL STATUS CHECK PROCEDURE

Program Successful

SR.3, SR.4= VPP Range Error

1,1

Protection Register

programming Error

0,1

Attempted Program to

Locked Register Aborted

1,1

SR.1, SR.4=

Bus Command Comments

Operation

Write Protection Data=C0H

Program

Setup

Write Protection Data=Data to Program

Program Addr=Location to Program

Read Status Register Data To ggle

CE or OE to Update Status

Standby Check SR.7

1=WSM Ready

0=WSM Busy

Protection Program operations can only be addressed

within the protection register address space. Addresses

o utside the defined space will return an error .

Repeat for subsequent programming operations.

SR Full Status Check can be done after each program

or after a sequence of program operations.

Write FFH after the last operation to reset device to

read array mode.

Bus Command Comments

Operation

Standby SR.1, SR.3, SR.4

0 1 1 VPP Low

Standby 0 0 1 Prot. Reg.

Prog. Error

Stanby 1 0 1 Register

Locked:

Aborted

SR.3 MUST be cleared, if set during a program at-

tempt, befo re further attempts are allowed by the Write

State Machine.

SR.1,3,4 are only cleared by the Clear Status Regis-

ter Command, in cases of multiple protection register

program operations before full status is checked.

If an error is detected, clear the status register before

attempting retry o r o ther error reco v ery.

P/N:PM0867

MX28F160C3T/B

REV. 1.2, MAR. 17, 2004

7 VPP Program and Erase Voltage

MX28F160C3T/B product provides in-system program-

ming and erase in the 1.65V~3.6V o f VPP range . In ad-

ditio n, VPP pin o n 12V pro vides fast pro duction program-

ming.

7.1 VPP Fast manufacturing Programming

When VPP is between 1.65V and 3.6V, all pro gram and

erase current is drawn through the VCC pin. If VPP is

driven by a logic signal, VIH=1.65V. That is, VPP must

remain above 1.65V to perform in-system flash update/

modifications. When VPP is connected to a 12V power

supply, the de vice draws pro g ram and erase current di-

rectly from the VPP pin.

7.2 Protection Under VPP<VPPLK

VPP can off additional hardware write protection. The

VPP programming voltage can be kept low for the abso-

lute hardware protection of all sector in the flash device.

As VPP is below VPPLK, any program or erase opera-

tion will result in a error, prompting the corresponding

status register bit (SR.3) to be set.

P/N:PM0867

MX28F160C3T/B

REV. 1.2, MAR. 17, 2004

8. QUERY COMMAND AND COMMON FLASH

INTERFACE (CFI) MODE

MX28F160C3T/B is capable of operating in the CFI mode.

This mode allows the host system to determine the

manufacturer of the device such as operating param-

eters and co nfigur atio n. Two co mmands are required in

CFI mode. Query command of CFI mode is placed first,

then the Reset command exits CFI mode. These are

described in Table 3.

The single cycle Query command is valid only when the

device is in the Read mode, including Erase Suspend,

Program Suspend, Standby mode, and Read ID mode;

how ev er, it is igno red o therwise .

The Reset command exits from the CFI mode to the

Read mode, or Erase Suspend mode, Program Suspend

or read ID mode. The command is valid only when the

device is in the CFI mode.

Table 9-1. CFI mode: Identification Data Values

(All values in these tables are in hexadecimal)

Description Address h Data h

Query-unique ASCII string "QRY" 1 0 0051

11 0052

12 0059

Primary vendor command set and control interface ID code 1 3 0003

14 0000

Address for primary algorithm extended query table 1 5 0035

16 0000

Alternate vendor command set and control interface ID code (none) 1 7 0000

18 0000

Address for secondary algorithm extended query table (none) 19 0000

1A 0000

Table 9-2. CFI Mode: System Interface Data Values

Description Address h Data h

VCC supply, minimum (2.7V) 1B 0027

VCC supply, maximum (3.6V) 1 C 0036

VPP supply, minimum (11.4V) 1D 00B4

VPP supply, maximum (12.6V) 1E 00C6

Typical timeout for single word write (2N us) 1F 0005

Typical timeout for maximum size buffer write (2N us) 2 0 0000

Typical timeout for individual sector erase (2N ms) 2 1 000A

Typical timeout for full chip erase (2N ms) (not supported) 2 2 0000

Maximum timeout for single word write times (2N X Typ) 23 0004

Maximum timeout for maximum size buffer write times (2N X Typ) 24 0000

Maximum timeout for individual sector erase times (2N X Typ) 2 5 0003

Maximum timeout for full chip erase times (not supported) 2 6 0000

P/N:PM0867

MX28F160C3T/B

REV. 1.2, MAR. 17, 2004

Table 9-3. CFI Mode: Device Geometry Data Values

Description Address h Data h

Device size (2n bytes) 27 0015

Flash device interface code (asynchronous x16) 2 8 0001

29 0000

Maximum number of bytes in write buffer=2n (not supported) 2A 0000

2B 0000

Number of erase sector regions within device (one or more continuous 2 C 0002

same-size erase sectors at one sector region) TB

Erase Sector Region 1 information 2 D 1E 07

[2E,2D] = number of same-size sectors in region 1-1 2E 00 00

[30, 2F] = region erase sector size in multiples of 256-bytes 2 F 00 20

30 01 00

Erase Sector Region 2 information 3 1 0 7 1E

[32,31] = number of same-size sectors in region 2-1 3 2 00 0 0

[34,33] = region erase sector size in multiples of 256-bytes 33 20 00

34 00 01

P/N:PM0867

MX28F160C3T/B

REV. 1.2, MAR. 17, 2004

Table 9-4. CFI Mode: Primary Vendor-Specific Extended Query Data Values

Description Address h Data h

Query-unique ASCII string "PRI" 3 5 0050

36 0052

37 0049

Major version number, ASCII 3 8 0031

Minor version number, ASCII 3 9 0030

Optional Feature & Command Support 3A 66

bit 0 Chip Erase Supported (1=yes, 0=no) 3B 0 0

bit 1 Suspend Erase Supported (1=yes, 0=no) 3 C 0 0

bit 2 Suspend Program Supported (1=yes, 0=no) 3 D 0 0

bit 3 Lock/Unlock Supported (1=yes, 0=no)

bit 4 Queued Erase Supported (1=yes, 0=no)

bit 5 Instant individual sector locking supported (1=yes, 0=no)

bit 6 Protection bits supported (1=yes, 0=no)

bit 7 Page mode read supported (1=yes, 0=no)

bit 8 Synchronous read support (1=yes, 0=no)

bits 9-31 revered for future use; undefined bits are "0"

Supported functions after suspend 3E 01

bit 0 Program supported after erase suspend (1=yes, 0=no)

bit 1-7 Reserved for other supported options; undefined bits are "0"

Sector Lock Status 3F 03

Define which bits in the sector status Register section of the Query are 40 00

implemented.

bit 0 sector Lock Status Register Lock/Unlock bit (bit 0) active; (1=yes, 0=no)

bit 1 sector Lock Status Register Lock-Down bit (bit 1) active; (1=yes, 0=no)

Bits 2-15 reserved for future use. Undefined bits are "0".

VCC Logic Supply Optimum Program/Erase Voltage (highest performance) 41 33

bits 7-4 BCD value in volts

bits 3-0 BCD value in 100mV

VPP Supply Optimum Program/Erase Voltage 4 2 C 0

bits 7-4 HEX value in volts

bits 3-0 BCD value in 100mV

P/N:PM0867

MX28F160C3T/B

REV. 1.2, MAR. 17, 2004

ORDER INFORMATION

PART NO. ACCESS TIME OPERATING STANDBY PACKAGE

(ns) Read Current MAX.(mA) Current MAX.(uA)

MX28F160C3TTC-70 70 18 1 5 48 Pin TSOP

MX28F160C3BTC-70 7 0 1 8 15 48 Pin TSOP

MX28F160C3TTC-90 90 1 8 1 5 48 Pin TSOP

MX28F160C3BTC-90 9 0 1 8 15 48 Pin TSOP

MX28F160C3TTC-11 11 0 1 8 15 48 Pin TSOP

MX28F160C3BTC-11 110 1 8 15 48 Pin TSOP

MX28F160C3TTI-70 70 18 1 5 48 Pin TSOP

MX28F160C3BTI-70 7 0 18 15 48 Pin TSOP

MX28F160C3TTI-90 90 18 1 5 48 Pin TSOP

MX28F160C3BTI-90 9 0 18 15 48 Pin TSOP

MX28F160C3TTI-11 1 1 0 1 8 1 5 48 Pin TSOP

MX28F160C3BTI-11 11 0 1 8 1 5 48 Pin TSOP

MX28F160C3TXAC-70 70 1 8 1 5 48 Ball CSP

MX28F160C3BXAC-70 70 18 1 5 48 Ball CSP

MX28F160C3TXAC-90 90 1 8 1 5 48 Ball CSP

MX28F160C3BXAC-90 90 18 1 5 48 Ball CSP

MX28F160C3TXAC-11 11 0 1 8 1 5 48 Ball CSP

MX28F160C3BXAC-11 1 1 0 18 1 5 48 Ball CSP

MX28F160C3TXAI-70 7 0 1 8 1 5 48 Ball CSP

MX28F160C3BXAI-70 70 18 15 48 Ball CSP

MX28F160C3TXAI-90 9 0 1 8 1 5 48 Ball CSP

MX28F160C3BXAI-90 90 18 15 48 Ball CSP

MX28F160C3TXAI-11 11 0 1 8 15 48 Ball CSP

MX28F160C3BXAI-11 110 1 8 15 48 Ball CSP

M X2 8 F 1 6 0 C 3 T T C - 7 0G 7 0 18 15 48 Pin TSOP

MX28F160C3BTC-70G 7 0 18 1 5 48 Pin TSOP

M X2 8 F 1 6 0 C 3 T T C - 9 0G 9 0 18 15 48 Pin TSOP

MX28F160C3BTC-90G 9 0 18 1 5 48 Pin TSOP

M X2 8 F 1 6 0 C 3 T T C - 1 1G 1 1 0 18 15 48 Pin TSOP

MX28F160C3BTC-11G 11 0 18 1 5 48 Pin TSOP

MX 2 8 F1 6 0 C 3T T I -7 0 G 70 18 1 5 48 Pin TSOP

MX28F160C3BTI-70G 70 1 8 1 5 48 Pin TSOP

MX 2 8 F1 6 0 C 3T T I -9 0 G 90 18 1 5 48 Pin TSOP

MX28F160C3BTI-90G 90 1 8 1 5 48 Pin TSOP

P/N:PM0867

MX28F160C3T/B

REV. 1.2, MAR. 17, 2004

PART NO. ACCESS TIME OPERATING STANDBY PACKAGE

(ns) Read Current MAX.(mA) Current MAX.(uA)

MX 2 8 F1 6 0 C 3T T I -1 1 G 11 0 18 15 48 Pin TSOP

MX28F160C3BTI-11G 11 0 1 8 1 5 48 Pin TSOP

MX28F160C3TXAC-70G 70 1 8 1 5 48 Ball CSP

MX28F160C3BXAC-70G 7 0 18 15 48 Ball CSP

MX28F160C3TXAC-90G 90 1 8 1 5 48 Ball CSP

MX28F160C3BXAC-90G 9 0 18 15 48 Ball CSP

MX28F160C3TXAC-11G 11 0 1 8 15 48 Ball CSP

MX28F160C3BXAC-11G 1 1 0 18 1 5 48 Ball CSP

MX28F160C3TXAI-70G 70 1 8 1 5 48 Ball CSP

MX28F160C3BXAI-70G 70 18 15 48 Ball CSP

MX28F160C3TXAI-90G 90 1 8 1 5 48 Ball CSP

MX28F160C3BXAI-90G 90 18 15 48 Ball CSP

MX28F160C3TXAI-11G 11 0 1 8 1 5 48 Ball CSP

MX28F160C3BXAI-11G 11 0 1 8 15 48 Ball CSP

P/N:PM0867

MX28F160C3T/B

REV. 1.2, MAR. 17, 2004

PACKAGE INFORMATION

P/N:PM0867

MX28F160C3T/B

REV. 1.2, MAR. 17, 2004

P/N:PM0867

MX28F160C3T/B

REV. 1.2, MAR. 17, 2004

REVISION HISTORY

Revision No. Description Page Date

1.0 1. To modify "Advanced Info rmation" to "Preliminary" P1 NOV/27/2002

1. To modify Package Info rmatio n P41,42

1.1 1. To added address definition notes for Top/Bottom boot device of P 18 MAY/05/2003

Pro tection Register Section

1.2 1. Remo ved "Preliminary" wo rding P1 MAR/17/2004

MX28F160C3T/B

MACRONIX INTERNATIONAL CO., LTD .

HEADQUARTERS:

TEL:+886-3-578-6688

FAX:+886-3-563-2888

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TEL:+32-2-456-8020

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