HMPP-386x Series
MiniPak Surface Mount RF PIN Diodes
Data Sheet
Description/Applications
These ultra-miniature products represent the blending of
Avago Technologies’ proven semiconductor and the latest
in leadless packaging technology.
The HMPP-386x series of general purpose PIN diodes are
designed for two classes of applications. The rst is attenu-
ators where current consumption is the most important
design consideration. The second application for this
series of diodes is in switches where low capacitance with
no reverse bias is the driving issue for the designer.
The low dielectric relaxation frequency of the HMPP-386x
insures that low capacitance can be reached at zero volts
reverse bias at frequencies above 1 GHz, making this PIN
diode ideal for hand held applications.
Low junction capacitance of the PIN diode chip, combined
with ultra low package parasitics, mean that these products
may be used at frequencies which are higher than the upper
limit for conventional PIN diodes.
Note that Avago’s manufacturing techniques assure that
dice packaged in pairs are taken from adjacent sites on
the wafer, assuring the highest degree of match.
Minipak 1412 is a ceramic based package, while Minipak
QFN is a leadframe based package.
Package Lead Code Identication (Top View)
Features
• Surface mount MiniPak package
• Better thermal conductivity for higher power dissipa-
tion
• Single and dual versions
• Matched diodes for consistent performance
• Low capacitance at zero volts
• Low resistance
• Low FIT (Failure in Time) rate*
• Six-sigma quality level
* For more information, see the Surface Mount Schottky Reliability
Data Sheet.
Pin Connections and Package Marking
Notes:
1. Package marking provides orientation and identication.
2. See “Electrical Specications” for appropriate package marking.
Single
3
2
4
1
#0
Anti-parallel
3
2
4
1
#2
Parallel
3
2
4
1
#5
(Minipak 1412) (Minipak 1412) (Minipak 1412)
3
2
Product code Date code
4
AA
1
2
HMPP-386x Series Absolute Maximum Ratings[1], TC = 25°C
MiniPak 1412 /
Symbol Parameter Units MiniPak QFN
If Forward Current (1 µs pulse) Amp 1
PIV Peak Inverse Voltage V 100
Tj Junction Temperature °C 150
Tstg Storage Temperature °C -65 to +150
θjc Thermal Resistance[2] °C/W 150
Notes:
1. Operation in excess of any one of these
conditions may result in permanent dam-
age to the device.
2. TC = +25°C, where TC is dened to be the
temperature at the package pins where
contact is made to the circuit board.
MiniPak1412
Electrical Specications, TC = +25°C, each diode
Part Number Package Minimum Breakdown Typical Series
HMPP- Marking Code Lead Code Conguration Voltage (V) Resistance (Ω)
3860 H 0 Single 50 3.0/1.5*
3862 F 2 Anti-parallel
3865 E 5 Parallel
Test Conditions VR = VBR IF = 10 mA
Measure f = 100 MHz
IR ≤ 10 µA *IF = 100 mA
ESD WARNING:
Handling Precautions Should Be Taken
To Avoid Static Discharge.
MiniPak1412
Typical Parameters, TC = +25°C
Part Number Total Resistance Carrier Lifetime Reverse Recovery Time Total Capacitance
HMPP- RT (Ω) τ (ns) Trr (ns) CT (pF)
3860 22 500 80 0.20
3862
3865
Test Conditions IF = 1 mA IF = 50 mA VR = 10 V VR = 50V
f = 100 MHz TR = 250 mA IF = 20 mA f = 1 MHz
90% Recovery
3
MiniPak 1412 HMPP-386x Series Typical Performance
TC = +25 °C (unless otherwise noted), each diode
Figure 1. RF Capacitance vs. Reverse Bias.
0.15
0.30
0.25
0.20
0.35
0 2 64 10 128 1614 18 20
TOTAL CAPACITANCE (pF)
REVERSE VOLTAGE (V)
1 GHz
100 MHz
1 MHz
120
115
110
105
100
95
90
85
1 10 30
I
F
– FORWARD BIAS CURRENT (mA)
Figure 3. 2nd Harmonic Input Intercept Point
vs. Forward Bias Current for Switch Diodes.
INPUT INTERCEPT POINT (dBm)
Diode Mounted as a
Series Switch in a
50 Microstrip and
Tested at 123 MHz
FORWARD CURRENT (mA)
Figure 4. Reverse Recovery Time vs. Forward
Current for Various Reverse Voltages.
T
rr
– REVERSE RECOVERY TIME (ns)
10
100
1000
10 20 30
V
R
= 5V
V
R
= 10V
V
R
= 20V
Figure 2. Typical RF Resistance vs. Forward Bias
Current.
0.01 100
1000
1
10
RF RESISTANCE (OHMS)
BIAS CURRENT (mA)
10
100
10.1
T
A
= +85 C
T
A
= +25 C
T
A
= –55 C
100
10
1
0.1
0.01
0 0.2 0.4 0.6 0.8 1.0 1.2
I
F
– FORWARD CURRENT (mA)
V
F
– FORWARD VOLTAGE (mA)
Figure 5. Forward Current vs. Forward
Voltage.
125 C 25 C –50 C
Intercept point
will be higher
at higher
frequencies
4
Typical Applications
RF COMMON
RF 1
1
23
4
BIAS 1
RF 2
BIAS 2
RF COMMON
RF 2
BIAS
RF 1
2
3 4
12
34
1
Figure 6. Simple SPDT Switch Using Only Positive Bias. Figure 7. High Isolation SPDT Switch Using Dual Bias.
Figure 9. Four Diode π Attenuator. See AN1048 for details.
Figure 10. High Isolation SPST Switch (Repeat Cells as Required).
INPUT RF IN/OUT
1 2
4 3
3 4
2 1
Figure 9. Four Diode p Attenuator. See AN1048 for details.
FIXED
BIAS
VOLTAGE
VARIABLE BIAS
BIAS
3 4
2 1
3 4
2 1
RF COMMON
RF 2
RF 1
BIAS
2
34
12
34
1
3
41
2
Figure 8. Very High Isolation SPDT Switch, Dual Bias.
5
Dielectric Relaxation Frequency and Diode Capacitance
fDR (Dielectric Relaxation Frequency) for a PIN diode is
given by the equation
fDR = 1
2πρε
where…
ρ = bulk resistivity of the I-layer
ε = ε0 εR = 10-12 F/cm
= bulk susceptance of silicon
In the case of an epitaxial diode with a value for ρ of 10Ω-
cm, fDR will be in Ku-Band. For a bulk diode fabricated on
very pure material, ρ can be as high as 2000, resulting in
a value of fDR of 80 MHz.
The implications of a low fDR are very important in RF atten-
uator and switch circuits. At operating frequencies below
fDR, reverse bias (as much as 50V) is needed to minimize
junction capacitance. At operating frequencies well above
fDR, the curve of capacitance vs. reverse bias is at.
For the HMPP-386x family, fDR is around 500 MHz, resulting
in very low capacitance at zero bias for frequencies above
1 GHz. See Figure 1.
Diode Lifetime and Resistance
The resistance of a PIN diode is controlled by the con-
ductivity (or resistivity) of the I layer. This conductivity is
controlled by the density of the cloud of carriers (charges)
in the I layer (which is, in turn, controlled by the DC bias).
Minority carrier lifetime, indicated by the Greek symbol
τ, is a measure of the time it takes for the charge stored
in the I layer to decay, when forward bias is replaced with
reverse bias, to some predetermined value. This lifetime
can be short (35 to 200 nsec. for epitaxial diodes) or it
can be relatively long (400 to 3000 nsec. for bulk diodes).
Lifetime has a strong inuence over a number of PIN
diode parameters, among which are distortion and basic
diode behavior.
To study the eect of lifetime on diode behavior, we rst
dene a cuto frequency fC = 1/τ. For short lifetime diodes,
this cuto frequency can be as high as 30 MHz while for
our longer lifetime diodes fC ≅ 400 KHz. At frequencies
which are ten times fC (or more), a PIN diode does indeed
act like a current controlled variable resistor. At frequen-
cies which are one tenth (or less) of fC, a PIN diode acts
like an ordinary PN junction diode. Finally, at 0.1fC ≤ f ≤
10fC, the behavior of the diode is very complex. Suce it
to mention that in this frequency range, the diode can
exhibit very strong capacitive or inductive reactance — it
will not behave at all like a resistor.
The HMPP-386x family features a typical lifetime of 300 to
500 ns, so 10fC for this part is 5 MHz. At any frequency over
5 MHz, the resistance of this diode will follow the curve
given in Figure 2. From this curve, it can be seen that the
HMPP-386x family produces a lower resistance at a given
value of bias current than most attenuator PIN diodes,
making it ideal for applications where current consump-
tion is important.
6
Figure 11. Linear Equivalent Circuit of the MiniPak 1412 PIN Diode.
30 fF 30 fF
20 fF
20 fF
1.1 nH
Single diode package (HMPP-3860)
2
3
1
4
30 fF 30 fF
20 fF
20 fF
12 fF
12 fF
0.5 nH
Anti-parallel diode package (HMPP-3862)
2
3
1
4
0.5 nH0.05 nH
0.5 nH
0.05 nH
0.05 nH0.5 nH0.05 nH
30 fF 30 fF
20 fF
20 fF
0.5 nH 0.05 nH
Parallel diode package (HMPP-3865)
2
3
1
4
0.5 nH0.05 nH
0.5 nH 0.05 nH0.5 nH0.05 nH
Linear Equivalent Circuit
In order to predict the performance of the HMPP-386x
as a switch or an attenuator, it is necessary to construct a
model which can then be used in one of the several linear
analysis programs presently on the market. Such a model
is given in Figure 16, where RS + Rj is given in Figure 2 and
Cj is provided in Figure 1. Careful examination of Figure 16
will reveal the fact that the package parasitics (inductance
and capacitance) are much lower for the MiniPak than they
are for leaded plastic packages such as the SOT-23, SOT-
323 or others. This will permit the HMPP-386x family to be
used at higher frequencies than its conventional leaded
counterparts.
7
MiniPak 1412 Outline Drawing
1.44 (0.057)
1.40 (0.055)
Top view
Side view
Dimensions are in millimeters (inches)
Bottom view
1.20 (0.047)
1.16 (0.046)
0.70 (0.028)
0.58 (0.023)
1.12 (0.044)
1.08 (0.043)
0.82 (0.032)
0.78 (0.031)
0.32 (0.013)
0.28 (0.011)
-0.07 (-0.003)
-0.03 (-0.001)
0.00
-0.07 (-0.003)
-0.03 (-0.001)
0.42 (0.017)
0.38 (0.015)
0.92 (0.036)
0.88 (0.035)
1.32 (0.052)
1.28 (0.050)
0.00
8
SMT Assembly
Reliable assembly of surface mount components is a
complex process that involves many material, process, and
equipment factors, including: method of heating (e.g., IR
or vapor phase reow, wave soldering, etc.) circuit board
material, conductor thickness and pattern, type of solder
alloy, and the thermal conductivity and thermal mass of
components. Components with a low mass, such as the
MiniPak package, will reach solder reow temperatures
faster than those with a greater mass.
After ramping up from room temperature, the circuit board
with components attached to it (held in place with solder
paste) passes through one or more preheat zones. The
preheat zones increase the temperature of the board and
components to prevent thermal shock and begin evapo-
rating solvents from the solder paste. The reow zone
briey elevates the temperature suciently to produce a
reow of the solder.
The rates of change of temperature for the ramp-up and
cool-down zones are chosen to be low enough to not
cause deformation of the board or damage to components
due to thermal shock. The maximum temperature in the
reow zone (TMAX) should not exceed 260°C.
These parameters are typical for a surface mount assembly
process for Avago diodes. As a general guideline, the circuit
board and components should be exposed only to the
minimum temperatures and times necessary to achieve a
uniform reow of solder.
Assembly Information
The MiniPak diode is mounted to the PCB or microstrip
board using the pad pattern shown in Figure 17.
0.4 0.4
0.3
0.5
0.3
0.5
2.60
0.40
0.20
0.40 mm via hole
(4 places)
0.8 2.40
Figure 12. PCB Pad Layout, MiniPak (dimensions in mm).
This mounting pad pattern is satisfactory for most ap-
plications. However, there are applications where a high
degree of isolation is required between one diode and the
other is required. For such applications, the mounting pad
pattern of Figure 18 is recommended.
Figure 13. PCB Pad Layout, High Isolation MiniPak (dimensions in mm).
This pattern uses four via holes, connecting the crossed
ground strip pattern to the ground plane of the board.
9
Device Orientation
USER
FEED
DIRECTION
COVER TAPE
CARRIER
TAPE
REEL
END VIEW
8 mm
4 mm
TOP VIEW
AA
AA
AA
AA
Note: “AA” represents package marking code. Package marking is
right side up with carrier tape perforations at top. Conforms to
Electronic Industries RS-481, “Taping of Surface Mounted
Components for Automated Placement.” Standard quantity is 3,000
devices per reel.
Ordering Information
Part Number No. of Devices Container
HMPP-386x-TR2 10000 13˝ Reel
HMPP-386x-TR1 3000 7˝ Reel
HMPP-386x-BLK 100 antistatic bag
For product information and a complete list of distributors, please go to our web site: www.avagotech.com
Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies in the United States and other countries.
Data subject to change. Copyright © 2005-2008 Avago Technologies. All rights reserved. Obsoletes 5989-3629EN
AV02-0652EN
- November 24, 2008
Tape Dimensions and Product Orientation
For Outline 4T (MiniPak 1412)
P
P0
P2
F
W
C
D1
D
E
A0
5
°
MAX.
t1(CARRIER TAPE THICKNESS) Tt(COVER TAPE THICKNESS)
5
°
MAX.
B0
K0
DESCRIPTION
LENGTH
WIDTH
DEPTH
PITCH
BOTTOM HOLE DIAMETER
A0
B0
K0
P
D1
1.40
±
0.05
1.63
±
0.05
0.80
±
0.05
4.00
±
0.10
0.80
±
0.05
0.055
±
0.002
0.064
±
0.002
0.031
±
0.002
0.157
±
0.004
0.031
±
0.002
CAVITY
DIAMETER
PITCH
POSITION
D
P0
E
1.50
±
0.10
4.00
±
0.10
1.75
±
0.10
0.060
±
0.004
0.157
±
0.004
0.069
±
0.004
PERFORATION
WIDTH
THICKNESS
W
t1
8.00 + 0.30 - 0.10
0.254
±
0.02
0.315 + 0.012 - 0.004
0.010
±
0.001
CARRIER TAPE
CAVITY TO PERFORATION
(WIDTH DIRECTION)
CAVITY TO PERFORATION
(LENGTH DIRECTION)
F
P2
3.50
±
0.05
2.00
±
0.05
0.138
±
0.002
0.079
±
0.002
DISTANCE
WIDTH
TAPE THICKNESS
C
Tt
5.40
±
0.10
0.062
±
0.001
0.213
±
0.004
0.002
±
0.00004
COVER TAPE
SYMBOL SIZE (mm) SIZE (INCHES)
