© Semiconductor Components Industries, LLC, 2009
December, 2009 − Rev. 10
1Publication Order Number:
MC1455/D
MC1455, MC1455B,
NCV1455B
Timers
The MC1455 monolithic timing circuit is a highly stable controller
capable of producing accurate time delays or oscillation. Additional
terminals are provided for triggering or resetting if desired. In the time
delay mode, time is precisely controlled by one external resistor and
capacitor. For astable operation as an oscillator, the free−running
frequency and the duty cycle are both accurately controlled with two
external resistors and one capacitor. The circuit may be triggered and
reset on falling waveforms, and the output structure can source or sink
up to 200 mA or drive TTL circuits.
Features
•Direct Replacement for NE555 Timers
•Timing from Microseconds through Hours
•Operates in Both Astable and Monostable Modes
•Adjustable Duty Cycle
•High Current Output Can Source or Sink 200 mA
•Output Can Drive TTL
•Temperature Stability of 0.005% per °C
•Normally ON or Normally OFF Output
•Pb−Free Packages are Available
http://onsemi.com
See detailed ordering and shipping information in the package
dimensions section on page 9 of this data sheet.
ORDERING INFORMATION
x = B or V
yyy = BP1 or P1
A = Assembly Location
L = Wafer Lot
Y, YY = Year
W, WW = Work Week
G or G = Pb−Free Package
SOIC−8
D SUFFIX
CASE 751
1
8
MARKING
DIAGRAMS
PDIP−8
P1 SUFFIX
CASE 626
1
8
1
8
MC1455yyy
AWL
YYWWG
1455x
ALYW
G
1
8
Figure 1. 22 Second Solid State Time Delay Relay Circuit
Figure 2. Representative Block Diagram Figure 3. General Test Circuit
1.0 k Load
MT2
10 k
0.1 mF 0.01 mF1
5
2
4
38 6
7
1.0 mFC
20M GMT1
-10 V 1N4003
117 Vac/60 Hz
1N4740 3.5 k
250 V
-
+
t = 1.1; R and C = 22 sec
Time delay (t) is variable by
changing R and C (see Figure 16).
10 mF
VCC
Threshold
Control Voltage
Trigger
6
5
2
5 k
8
5 k
5 k
+
-
Comp
A
+
-
Comp
B
1
GND Reset
4
R
S
Flip
Flop
Q
Inhibit/
Reset
7
3
Discharge
Output
R
MC1455
VR
Reset 4 8
ICC
VCC
700
Discharge
6
Threshold
7
Ith 2.0 k VS
Trigger
2
GND
1
3
ISink
ISource
VO
0.01 mF
+5
Control
Voltage
Output
VCC
MC1455
Test circuit for measuring DC parameters (to set output and measure
parameters):
a) When VS w 2/3 VCC, VO is low.
b) When VS v1/3 VCC, VO is high.
c) When VO is low, Pin 7 sinks current. To test for Reset, set VO
c) high, apply Reset voltage, and test for current flowing into Pin 7.
c) When Reset is not in use, it should be tied to VCC.
MC1455, MC1455B, NCV1455B
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MAXIMUM RATINGS (TA = +25°C, unless otherwise noted.)
Rating Symbol Value Unit
Power Supply Voltage VCC +18 Vdc
Discharge Current (Pin 7) I7200 mA
Power Dissipation (Package Limitation)
P1 Suffix, Plastic Package
Derate above TA = +25°C
D Suffix, Plastic Package
Derate above TA = +25°C
PD
PD
625
5.0
625
160
mW
mW/°C
mW
°C/W
Operating Temperature Range (Ambient)
MC1455B
MC1455
NCV1455B
TA
−40 to +85
0 to +70
−40 to +125
°C
Maximum Operating Die Junction Temperature TJ+150 °C
Storage Temperature Range Tstg −65 to +150 °C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
ELECTRICAL CHARACTERISTICS (TA = +25°C, VCC = +5.0 V to +15 V, unless otherwise noted.)
Characteristics Symbol Min Typ Max Unit
Operating Supply Voltage Range VCC 4.5 −16 V
Supply Current
VCC = 5.0 V, RL = R
VCC = 15 V, RL = R, Low State (Note 1)
ICC
−
−
3.0
10
6.0
15
mA
Timing Error (R = 1.0 kW to 100 kW) (Note 2)
Initial Accuracy C = 0.1 mF
Drift with Temperature
Drift with Supply Voltage
−
−
−
1.0
50
0.1
−
−
−
%
PPM/°C
%/V
Threshold Voltage/Supply Voltage Vth/VCC −2/3 −
Trigger Voltage
VCC = 15 V
VCC = 5.0 V
VT
−
−
5.0
1.67
−
−
V
Trigger Current IT−0.5 −mA
Reset Voltage VR0.4 0.7 1.0 V
Reset Current IR−0.1 −mA
Threshold Current (Note 3) Ith −0.1 0.25 mA
Discharge Leakage Current (Pin 7) Idischg − − 100 nA
Control Voltage Level
VCC = 15 V
VCC = 5.0 V
VCL 9.0
2.6
10
3.33
11
4.0
V
Output Voltage Low
ISink = 10 mA (VCC = 15 V)
ISink = 50 mA (VCC = 15 V)
ISink = 100 mA (VCC = 15 V)
ISink = 200 mA (VCC = 15 V)
ISink = 8.0 mA (VCC = 5.0 V)
ISink = 5.0 mA (VCC = 5.0 V)
VOL
−
−
−
−
−
−
0.1
0.4
2.0
2.5
−
0.25
0.25
0.75
2.5
−
−
0.35
V
Output Voltage High
VCC = 15 V (ISource = 200 mA)
VCC = 15 V (ISource = 100 mA)
VCC = 5.0 V (ISource = 100 mA)
VOH
−
12.75
2.75
12.5
13.3
3.3
−
−
−
V
Rise Time Differential Output tr−100 −ns
Fall Time Differential Output tf−100 −ns
1. ‘Supply current when output is high is typically 1.0 mA less.
2. Tested at VCC = 5.0 V and VCC = 15 V Monostable mode.
3. This will determine the maximum value of RA + RB for 15 V operation. The maximum total R = 20 MW.
4. Tlow = 0°C for MC1455, Tlow = −40°C for MC1455B, NCV1455B
Thigh = +70°C for MC1455, Thigh = +85°C for MC1455B, Thigh = +125°C for NCV1455B
5. NCV prefix is for Automotive and other applications requiring site and change control.
MC1455, MC1455B, NCV1455B
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3
ISink (mA)
ISink (mA)
VCC, SUPPLY VOLTAGE (Vdc)
ISink (mA)
ISource (mA)
Figure 4. Trigger Pulse Width
VT(min), MINIMUM TRIGGER VOLTAGE (x VCC = Vdc)
Figure 5. Supply Current
Figure 6. High Output Voltage Figure 7. Low Output Voltage
@ VCC = 5.0 Vdc
Figure 8. Low Output Voltage
@ VCC = 10 Vdc
Figure 9. Low Output Voltage
@ VCC = 15 Vdc
0.4
150
125
100
75
50
25
0
PW, PULSE WIDTH (ns min)
ICC, SUPPLY CURRENT (mA)
1.0
1.0
VCC-V
OH (Vdc)
VOL, LOW OUTPUT VOLTAGE (Vdc)
0.30.20.10
25°C
0°C
70°C
VOL, LOW OUTPUT VOLTAGE (Vdc)
VOL, LOW OUTPUT VOLTAGE (Vdc)
25°C
10
8.0
6.0
4.0
2.0
0155.0 10
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
02.0 5.0 10 20 50 100
25°C
5.0 V ≤ VCC ≤ 15 V
10
1.0
0.1
0.01
1.0 2.0 5.0 10 20 50 100
25°C
2.0 5.0 10 20 50 100
10
1.0
0.1
0.01
25°C
1.0 2.0 5.0 10 20 50 100
10
1.0
0.1
0.01
25°C
MC1455, MC1455B, NCV1455B
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4
TA, AMBIENT TEMPERATURE (°C)
Figure 10. Delay Time versus Supply Voltage
VCC, SUPPLY VOLTAGE (Vdc)
Figure 11. Delay Time versus Temperature
Figure 12. Propagation Delay
versus Trigger Voltage
5.0
0
VT(min), MINIMUM TRIGGER VOLTAGE (x VCC = Vdc)
td, DELAY TIME NORMALIZED
td, DELAY TIME NORMALIZED
, PROPAGATION DELAY TIME (ns)tpd
1.015
1.010
1.005
1.000
0.995
0.990
0.985
0101510 20
1.015
1.010
1.005
1.000
0.995
0.990
0.985
- 75 - 50 - 25 0 25 50 75 100 125
300
250
200
150
100
50
0
0.1 0.2 0.3 0.4
0°C
25°C
70°C
MC1455, MC1455B, NCV1455B
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5
Figure 13. Representative Circuit Schematic
100
Threshold
Comparator
Trigger
Comparator Flip-Flop Output
VCC
Threshold
Trigger
Reset
Discharge
GND
Discharge
Reset
100 k 5.0 k
5.0 k e4.7 k
c b
7.0 k
6.8 k
3.9 k
b
220
4.7 k
Output
Control Voltage
5.0 k
1.0 k4.7 k 830 4.7k
10 k
c
GENERAL OPERATION
The MC1455 is a monolithic timing circuit which uses an
external resistor − capacitor network as its timing element. It
can be used in both the monostable (one−shot) and astable
modes with frequency and duty cycle controlled by the
capacitor and resistor values. While the timing is dependent
upon the external passive components, the monolithic circuit
provides the starting circuit, voltage comparison and other
functions needed for a complete timing circuit. Internal to the
integrated circuit are two comparators, one for the input
signal and the other for capacitor voltage; also a flip−flop and
digital output are included. The comparator reference
voltages are always a fixed ratio of the supply voltage thus
providing output timing independent of supply voltage.
Monostable Mode
In the monostable mode, a capacitor and a single resistor
are used for the timing network. Both the threshold terminal
and the discharge transistor terminal are connected together
in this mode (refer to circuit in Figure 14). When the input
voltage to the trigger comparator falls below 1/3 VCC, the
comparator output triggers the flip−flop so that its output sets
low. This turns the capacitor discharge transistor “off” and
drives the digital output to the high state. This condition
allows the capacitor to charge at an exponential rate which is
set by the RC time constant. When the capacitor voltage
reaches 2/3 VCC, the threshold comparator resets the
flip−flop. This action discharges the timing capacitor and
returns the digital output to the low state. Once the flip−flop
has been triggered by an input signal, it cannot be retriggered
until the present timing period has been completed. The time
that the output is high is given by the equation t = 1.1 RA C.
Various combinations of R and C and their associated times
are shown in Figure 16. The trigger pulse width must be less
than the timing period.
A reset pin is provided to discharge the capacitor, thus
interrupting the timing cycle. As long as the reset pin is low,
the capacitor discharge transistor is turned “on” and prevents
the capacitor from charging. While the reset voltage is applied
the digital output will remain the same. The reset pin should
be tied to the supply voltage when not in use.
Figure 14. Monostable Circuit
RL
+VCC (5.0 V to 15 V)
Reset VCC
8Discharge
7
6
5
Threshold
Control
Voltage 0.01 mF
1
2
Trigger
Output
3
4
RA
RL
MC1455
C
MC1455, MC1455B, NCV1455B
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6
C, CAPACITANCE ( F)
μ
Figure 15. Monostable Waveforms Figure 16. Time Delay
Figure 17. Astable Circuit Figure 18. Astable Waveforms
(RA = 10 kW, C = 0.01 mF, RL = 1.0 kW, VCC = 15 V)
(RA = 5.1 kW, C = 0.01 mF, RL = 1.0 kW; RB = 3.9 kW, VCC = 15 V)
t = 20 ms/cm
t = 50 ms/cm
100
10
1.0
0.1
0.01
0.001
10 ms 100 ms1.0 ms 10 ms 100 ms 1.0 10 100
td, TIME DELAY (s)
RL
+VCC (5.0 V to 15 V)
Reset VCC
8
7Discharge
6Threshold
5
Control
Voltage
1
2
Trigger
Output
3
4
RA
RL
MC1455
C
RB
Astable Mode
In the astable mode the timer is connected so that it will
retrigger itself and cause the capacitor voltage to oscillate
between 1/3 VCC and 2/3 VCC. See Figure 17.
The external capacitor changes to 2/3 VCC through RA and
RB and discharges to 1/3 VCC through RB. By varying the
ratio of these resistors the duty cycle can be varied. The
charge and discharge times are independent of the supply
voltage.
The charge time (output high) is given by:
t1+0.695(RA)RB)C
The discharge time (output low) is given by:
t2+0.695(RB)C
Thus the total period is given by:
T+t1)t2+0.695(RA)2RB)C
The frequency of oscillation is then:
f+1
1+1.44
(RA)2RB)C
and may be easily found as shown in Figure 19.
The duty cycle is given by: DC +RB
RA)2RB
To obtain the maximum duty cycle RA must be as small as
possible; but it must also be large enough to limit the
discharge current (Pin 7 current) within the maximum rating
of the discharge transistor (200 mA).
The minimum value of RA is given by:
RAwVCC(Vdc)
I7 (A) wVCC(Vdc)
0.2
Figure 19. Free Running Frequency
C, CAPACITANCE ( F)
μ
100
10
1.0
0.1
0.01
0.001
(RA + 2 RB)
0.1 1.0 10 100 1.0 k 10 k 100
f, FREE RUNNING FREQUENCY (Hz)
MC1455, MC1455B, NCV1455B
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7
APPLICATIONS INFORMATION
Linear Voltage Ramp
In the monostable mode, the resistor can be replaced by a
constant current source to provide a linear ramp voltage. The
capacitor still charges from 0 VCC to 2/3 VCC. The linear
ramp time is given by:
t = 2
3
VCC
1, where I = VCC − VB − VBE
RE
If VB is much larger than VBE, then t can be made
independent of VCC.
Missing Pulse Detector
The timer can be used to produce an output when an input
pulse fails to occur within the delay of the timer. To
accomplish this, set the time delay to be slightly longer than
the time between successive input pulses. The timing cycle
is then continuously reset by the input pulse train until a
change in frequency or a missing pulse allows completion of
the timing cycle, causing a change in the output level.
Figure 20. Linear Voltage Sweep Circuit Figure 21. Missing Pulse Detector
Figure 22. Linear Voltage Ramp Waveforms Figure 23. Missing Pulse Detector Waveforms
Discharge
Threshold
VCC
Reset 4
3
Digital
Output
2
Trigger
1
MC1455
8V
CC
RER1
2N4403
or Equiv
VB
R2
C
7
6
5Sweep
Output
0.01 mFControl
Voltage
+VCC (5.0 V to 15 V)
Reset
RL
VCC RA
7
6
5
Control
Voltage
0.01 mF
1
Trigger
Input
Output
48
C
2N4403
or Equiv
MC1455
t = 100 ms/cm
VE
3
2
t = 500 ms/cm
(RE = 10 kW, R2 = 100 kW, R1 = 39 kW, C = 0.01 mF, VCC = 15 V) (RA = 2.0 kW, RL = 1.0 kW, C = 0.01 mF, VCC = 15 V)
I
MC1455, MC1455B, NCV1455B
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8
Pulse Width Modulation
If the timer is triggered with a continuous pulse train in the
monostable mode of operation, the charge time of the
capacitor can be varied by changing the control voltage at
Pin 5. In this manner, the output pulse width can be
modulated by applying a modulating signal that controls the
threshold voltage.
Figure 24. Pulse Width Modulator
+VCC (5.0 V to 15 V)
RL
Output
Clock
Input
Modulation
Input
C
7
6
5
RA
48
3
2
1
MC1455
t = 0.5 ms/cm
(RA = 10 kW, C = 0.02 mF, VCC = 15 V)
Figure 25. Pulse Width Modulation Waveforms
Test Sequences
Several timers can be connected to drive each other for
sequential timing. An example is shown in Figure 26 where
the sequence is started by triggering the first timer which
runs for 10 ms. The output then switches low momentarily
and starts the second timer which runs for 50 ms and so forth.
Figure 26. Sequential Timer
Load
MC1455
6
7
2
84
5
3
27 k
15.0 mF
Load
MC1455
9.1 k
6
7
1.0 mF2
84
5
3
0.01 mF
27 k
1
0.001 mF
5.0 mF
MC1455
6
7
2
84
5
3
1
Load
0.001 mF
18.2 k
9.1 k
0.01 mF 0.01 mF
VCC (5.0 V to 15 V)
MC1455, MC1455B, NCV1455B
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9
ORDERING INFORMATION
Device Operating Temperature Range Package Shipping†
MC1455P1
TA = 0°C to +70°C
PDIP−850 Units / Rail
MC1455P1G PDIP−8
(Pb−Free)
50 Units / Rail
MC1455D SOIC−898 Units / Rail
MC1455DG SOIC−8
(Pb−Free)
98 Units / Rail
MC1455DR2 SOIC−82500 Units / Tape & Reel
MC1455DR2G SOIC−8
(Pb−Free)
2500 Units / Tape & Reel
MC1455BD
TA = −40°C to +85°C
SOIC−898 Units / Rail
MC1455BDG SOIC−8
(Pb−Free)
98 Units / Rail
MC1455BDR2 SOIC−82500 Units / Tape & Reel
MC1455BDR2G SOIC−8
(Pb−Free)
2500 Units / Tape & Reel
MC1455BP1 PDIP−850 Units / Rail
MC1455BP1G PDIP−8
(Pb−Free)
50 Units / Rail
NCV1455BDR2*
TA = −40°C to +125°C
SOIC−82500 Units / Tape & Reel
NCV1455BDR2G* SOIC−8
(Pb−Free)
2500 Units / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*NCV prefix is for automotive and other applications requiring site and control changes.
MC1455, MC1455B, NCV1455B
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10
PACKAGE DIMENSIONS
SOIC−8
D SUFFIX
CASE 751−07
ISSUE AJ
1.52
0.060
7.0
0.275
0.6
0.024
1.270
0.050
4.0
0.155
ǒmm
inchesǓ
SCALE 6:1
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
SOLDERING FOOTPRINT*
SEATING
PLANE
1
4
58
N
J
X 45 _
K
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. 751−01 THRU 751−06 ARE OBSOLETE. NEW
STANDARD IS 751−07.
A
BS
D
H
C
0.10 (0.004)
DIM
A
MIN MAX MIN MAX
INCHES
4.80 5.00 0.189 0.197
MILLIMETERS
B3.80 4.00 0.150 0.157
C1.35 1.75 0.053 0.069
D0.33 0.51 0.013 0.020
G1.27 BSC 0.050 BSC
H0.10 0.25 0.004 0.010
J0.19 0.25 0.007 0.010
K0.40 1.27 0.016 0.050
M0 8 0 8
N0.25 0.50 0.010 0.020
S5.80 6.20 0.228 0.244
−X−
−Y−
G
M
Y
M
0.25 (0.010)
−Z−
Y
M
0.25 (0.010) ZSXS
M
____
MC1455, MC1455B, NCV1455B
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11
PACKAGE DIMENSIONS
PDIP−8
P1 SUFFIX
CASE 626−05
ISSUE L
NOTES:
1. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
2. PACKAGE CONTOUR OPTIONAL (ROUND OR
SQUARE CORNERS).
3. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
14
58
F
NOTE 2 −A−
−B−
−T−
SEATING
PLANE
H
J
G
DK
N
C
L
M
M
A
M
0.13 (0.005) B M
T
DIM MIN MAX MIN MAX
INCHESMILLIMETERS
A9.40 10.16 0.370 0.400
B6.10 6.60 0.240 0.260
C3.94 4.45 0.155 0.175
D0.38 0.51 0.015 0.020
F1.02 1.78 0.040 0.070
G2.54 BSC 0.100 BSC
H0.76 1.27 0.030 0.050
J0.20 0.30 0.008 0.012
K2.92 3.43 0.115 0.135
L7.62 BSC 0.300 BSC
M--- 10 --- 10
N0.76 1.01 0.030 0.040
__
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to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
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associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
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MC1455/D
PUBLICATION ORDERING INFORMATION
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Phone: 81−3−5773−3850
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