High Speed Super Low Power SRAM 256k Word x 16 bit CS16LV40963 Revision History Rev. No. History Issue Date 2.0 Initial issue with new naming rule Jan.18,2005 2.1 Remove 48TSOP package Jan.11,2007 2.2 Revise AC/DC Char. Mar. 11, 2008 2.3 Add 48 BGA_6x7mm Jun. 25, 2008 1 Remark Rev. 2.3 Chiplus reserves the right to change product or specification without notice. High Speed Super Low Power SRAM CS16LV40963 256k Word x 16 bit GENERAL DESCRIPTION The CS16LV40963 is a high performance, high speed, super low power CMOS Static Random Access Memory organized as 262,144 words by 16 bits and operates from a wide range of 2.7 to 3.6V supply voltage. Advanced CMOS technology and circuit techniques provide both high speed and low power features with a typical CMOS standby current of 0.50uA and maximum access time of 55/70ns in 3.0V operation. Easy memory expansion is provided by an active LOW chip enable (/CE) and active LOW output enable (/OE) and three-state output drivers. The CS16LV40963 has an automatic power down feature, reducing the power consumption significantly when chip is deselected. The CS16LV40963 is available in JEDEC standard 44-pin TSOP 2 and 48-pin BGA package. FEATURES Low operation voltage : 2.7 ~ 3.6V Ultra low power consumption : Vcc = 3.0V 3mA1MHz (Typ.) operating current 0.5uA (Typ.) CMOS standby current High speed access time : 55/70ns (Max.) at Vcc = 3.0V. Automatic power down when chip is deselected. Three state outputs and TTL compatible, fully static operation Data retention supply voltage as low as 1.5V. Easy expansion with /CE and /OE options. Product Family Product Family Operating Temp Vcc. Range 0~70oC CS16LV40963 Speed (ns) 55/70 Standby (Typ.) 0.5 uA (Vcc = 3.0V) 2.7~3.6 -40~85oC 44 TSOP 2 48 BGA_6x7 55/70 2 Package Type 1.0 uA Dice (Vcc= 3.0V) Rev. 2.3 Chiplus reserves the right to change product or specification without notice. High Speed Super Low Power SRAM 256k Word x 16 bit CS16LV40963 PIN CONFIGURATIONS FUNCTIONAL BLOCK DIAGRAM 3 Rev. 2.3 Chiplus reserves the right to change product or specification without notice. High Speed Super Low Power SRAM CS16LV40963 256k Word x 16 bit PIN DESCRIPTIONS Name A0 - A17 Type Function Input Address inputs for selecting one of the 262,144 x 16 bit words in the RAM /CE is active LOW. Chip enable must be active when data read from or write to the /CE Input device. If chip enable is not active, the device is deselected and in a standby power mode. The DQ pins will be in high impedance state when the device is deselected. The Write enable input is active LOW. It controls read and write operations. With the /WE chip selected, when /WE is HIGH and /OE is LOW, output data will be present on the Input DQ pins, when /WE is LOW, the data present on the DQ pins will be written into the selected memory location. The output enable input is active LOW. If the output enable is active while the chip is /OE selected and the write enable is inactive, data will be present on the DQ pins and Input they will be enabled. The DQ pins will be in the high impedance state when /OE is inactive. /LB and /UB Lower byte and upper byte data input/output control pins. Input DQ0~DQ15 I/O These 16 bi-directional ports are used to read data from or write data into the RAM. Vcc Power Power Supply Gnd Power Ground TRUTH TABLE MODE Standby Output Disabled Read Write /CE /WE /OE /LB /UB X X X H H H X X X X L H H X L L H L L X 4 DQ0~7 DQ8~15 Vcc Current High Z High Z ICCSB, ICCSB1 X High Z High Z ICC L L DOUT DOUT ICC H L High Z DOUT ICC L H DOUT High Z ICC L L DIN DIN ICC H L X DIN ICC L H DIN X ICC Rev. 2.3 Chiplus reserves the right to change product or specification without notice. High Speed Super Low Power SRAM CS16LV40963 256k Word x 16 bit ABSOLUTE MAXIMUM RATINGS Symbol (1) Parameter VTERM Terminal Voltage with Respect to GND TBIAS Temperature Under Bias Rating Unit -0.5 to Vcc+0.5 V -40 to +125 O -60 to +150 O C TSTG Storage Temperature PT Power Dissipation 1.0 W IOUT DC Output Current 30 mA C 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. DC ELECTRICAL CHARACTERISTICS Parameter Parameter Name Test Conduction Guaranteed Input Low VIL o ( TA = 0 to 70 C , Vcc = 3.0V ) MIN TYP(1) MAX Unit -0.5 0.8 V 2.0 Vcc+0.2 V Voltage Guaranteed Input High VIH Voltage IIL Input Leakage Current VCC=MAX, VIN=0 to VCC -1 1 uA IOL Output Leakage VCC=MAX, /CE=VIN, or -1 1 uA Current /OE=VIN , VIO=0V to VCC Output Low Voltage VCC=MAX, IOL = 2mA 0.4 V Output High Voltage VCC=MIN, IOH = -1mA VOL VOH IOH = -100uA Operating Power ICC 2.4 V VCC -0.2 /CE=VIL, IDQ=0mA, F=FMAX(2) 30 mA 1 mA 5 uA Supply Current ICCSB Standby Supply - TTL /CE=VIH, IDQ=0mA, ICCSB1 Standby Current /CEVCC-0.2V, VIN -CMOS VCC-0.2V or VIN0.2V 0.5 o 1. Typical characteristics are at TA = 25 C. 2. Fmax = 1/tRC. 5 Rev. 2.3 Chiplus reserves the right to change product or specification without notice. High Speed Super Low Power SRAM CS16LV40963 256k Word x 16 bit OPERATING RANGE Range Ambient Temperature Vcc o Commercial 0~70 C 2.7V ~ 3.6V Industrial -40~85oC 2.7V ~ 3.6V 1. Overshoot : Vcc +2.0V in case of pulse width 20ns. 2. Undershoot : - 2.0V in case of pulse width 20ns. 3. Overshoot and undershoot are sampled, not 100% tested. DATA RETENTION CHARACTERISTICS ( TA = 0 to + 70oC ) Parameter Parameter Name Test Conduction /CEVCC-0.2V, VINVCC-0.2V VDR VCC for Data Retention ICCDR Data Retention Current Chip TCDR Deselect to or VIN0.2V tR Operation Recovery Time MAX Unit V 0.3 VCC-0.2V or VIN0.2V See Retention Waveform TYP(1) 1.5 /CEVCC-0.2V, VCC=1.5V VIN Data Retention Time MIN 2 uA 0 ns tRC (2) ns o 1. Vcc = 3.0V, TA = + 25 C. 2. tRC (2)= Read Cycle Time. CAPACITANCE (1) (TA = 25oC, f =1.0 MHz) Symbol Parameter Conditions MAX. Unit CIN Input Capacitance VIN=0V 6 pF CDQ Input/Output Capacitance VI/O=0V 8 pF 1. This parameter is guaranteed and not tested. 6 Rev. 2.3 Chiplus reserves the right to change product or specification without notice. High Speed Super Low Power SRAM CS16LV40963 256k Word x 16 bit LOW Vcc DATA RETENTION WAVEFORM ( /CE Controlled ) AC TEST CONDITIONS Input Pulse Levels Vcc/0V Input Rise and Fall Times Input and Output Timing Reference Level Output Load KEY TO SWITCHING WAVEFORMS WAVEFORMS INPUTS 5ns OUTPUTS MUST BE STEADY MUST BE STEADY 0.5Vcc See FIGURE 1A MAY CHANGE FROM H TO L WILL BE CHANGE FROM H TO L MAY CHANGE FROM L TO H WILL BE CHANGE FROM L TO H DON'T CARE ANY CHANGE PERMITTED CHANGE STATE UNKNOWN DOES NOT APPLY CENTER LINE IS HIGH IMPEDANCE OFF STATE and 1B AC TEST LOADS AND WAVEFORMS TERMINAL EQUIVALENT 667 OUTPUT 1.73V ALL INPUT PULSES VCC GND FIGURE 1A 90% FIGURE 2 FIGURE 1B 7 90% 10% 10% 5ns 5ns Rev. 2.3 Chiplus reserves the right to change product or specification without notice. High Speed Super Low Power SRAM CS16LV40963 256k Word x 16 bit AC ELECTRICAL CHARACTERISTICS ( TA = 0 to + 70oC , Vcc = 3V ) < READ CYCLE > JEDEC Parameter Name Name Description -55 -70 Unit MIN MAX MIN MAX tAVAX tRC Read Cycle Time 55 70 ns tAVQV tAA Address Access Time 55 70 ns tELQV tACS Chip Select Access Time (/CE) 55 70 ns tBA tBA Data Byte Control Access Time (/LB, /UB) 25 35 ns tGLQV tOE Output Enable to Output Valid 25 35 ns tELQX tCLZ Chip Select to Output Low Z (/CE) 10 10 ns tBE tBE Data Byte Control to Output Low Z (/LB, /UB) 5 5 ns tGLQX tOLZ Output Enable to Output in Low Z 5 5 ns tEHQZ tCHZ Chip Deselect to Output in High Z (/CE) 0 20 0 25 ns tBDO tBDO Data Byte Control to Output High Z (/LB, /UB) 0 20 0 25 ns tGHQZ tOHZ Output Disable to Output in High Z 0 20 0 25 ns tAXOX tOH Out Disable to Address Change 10 10 ns NOTES: 1. /WE is high in read Cycle. 2. Device is continuously selected when /CE = VIL. 3. Address valid prior to or coincident with CE transition low. 4. /OE = VIL. 5. Transition is measured 500mV from steady state with CL = 5pF as shown in Figure 1B. The parameter is guaranteed but not 100% tested. SWITCHING WAVEFORMS (READ CYCLE) 8 Rev. 2.3 Chiplus reserves the right to change product or specification without notice. High Speed Super Low Power SRAM 256k Word x 16 bit 9 CS16LV40963 Rev. 2.3 Chiplus reserves the right to change product or specification without notice. High Speed Super Low Power SRAM CS16LV40963 256k Word x 16 bit AC ELECTRICAL CHARACTERISTICS ( TA = 0 to + 70oC , Vcc = 3V ) < WRITE CYCLE > JEDEC Parameter Name Name tAVAX tWC Write Cycle Time 55 70 ns tE1LWH tCW Chip Select to End of Write 45 60 ns tAVWL tAS Address Setup Time 0 0 ns tAVWH tAW Address Valid to End of Write 45 60 ns tWLWH tWP Write Pulse Width 40 50 ns tWHAX tWR1 Write Recovery Time (/CE, /WE) 0 0 ns tBW tBW Data Byte Control to End of Write(/LB, /UB) 45 60 ns tWLQZ tWHZ Write to Output in High Z tDVWH tDW Data to Write Time Overlap 25 30 ns tWHDX tDH Data Hold from Write Time 0 0 ns tWHOX tOW End of Write to Output Active 5 5 ns Description -55 MIN -70 MAX MIN 25 MAX Unit 30 SWITCHING WAVEFORMS (WRITE CYCLE) 10 Rev. 2.3 Chiplus reserves the right to change product or specification without notice. ns High Speed Super Low Power SRAM 256k Word x 16 bit CS16LV40963 NOTES: 1. TAS is measured from the address valid to the beginning of write. 2. The internal write time of the memory is defined by the overlap of /CE and /WE low. All signals must be active to initiate a write and any one signal can terminate a write by going inactive. The data input setup and hold timing should be referenced to the second transition edge of the signal that terminates the write. 11 Rev. 2.3 Chiplus reserves the right to change product or specification without notice. High Speed Super Low Power SRAM 256k Word x 16 bit CS16LV40963 3. TWR is measured from the earliest of /CE or /WE or (/UB and ,or /LB) going high at the end of write cycle. 4. During this period, DQ pins are in the output state so that the input signals of opposite phase to the outputs must not be applied. 5. If the /CE low transition occurs simultaneously with the /WE low transitions or after the /WE transition, output remain in a high impedance state. 6. /OE is continuously low (/OE = VIL ). 7. DOUT is the same phase of write data of this write cycle. 8. DOUT is the read data of next address. 9. If /CE is low during this period, DQ pins are in the output state. Then the data input signals of opposite phase to the outputs must not be applied to them. 10. Transition is measured 500mV from steady state with CL = 5pF as shown in Figure 1B. The parameter is guaranteed but not 100% tested. 11. TCW is measured from the later of /CE going low to the end of write. ORDER INFORMATION Note: Package material code "P" & "R" meets ROHS. 12 Rev. 2.3 Chiplus reserves the right to change product or specification without notice.