1
Features
•Write Protect Pin f or Har dware Data Prot ection
– Utilizes Different Array Protection Compared to the AT24C02/04/08/16
•Low-voltag e and Standard-voltage Operation
– 2.7 (VCC = 2.7V to 5. 5V)
– 1.8 (VCC = 1.8V to 5. 5V)
•Internally Organized 256 x 8 (2K), 512 x 8 (4K), 1024 x 8 (8K) or 2048 x 8 (16K)
•2-w ire Serial Interface
•Schm itt Trigger, Fil tered Inputs f or Noise Suppressi on
•Bi-directional Data Transfer Protocol
•100 kHz (1.8V) and 400 kHz (2.5V, 2.7V, 5V) Clock Rate
•8-byte Page (2K), 16- byte Page (4K, 8K, 16K) Write Modes
•P artial Page Writes are Allowed
•Self-timed Wri te Cycle (5 ms Max)
•High Reliabilit y
– End urance: One Milli on Wr it e Cycles
– Data Retention: 100 Years
•A utomotive Grade, Extended Temperatur e and Lead-Free/Hal ogen-Free
Devices Av ailable
•8-lead PDIP, 8- lead JEDEC SOIC, 8-l ead MA P and 8-l ead TSSOP Packages
Description
The AT24C02A/04A/08A/16A provides 2048/4096/8192/16384 bits of serial electri-
cally erasable and programmable read only memory (EEPROM) organized as
256/512/1024/2048 words of 8 bits each. The device is optimized for use in many
industrial and commercial applications where low power and low voltage operation are
essenti al. The AT24C02A/04 A/08A/16A is available in space saving 8-lead PDIP,
8-lead JEDEC SOIC, 8-lead MAP and 8-lead TSSOP packages and is acce ssed via a
2-wire seri al interface. In ad dition, the entire family is avai lable in 2 .7 V (2.7V to 5.5V)
and 1.8V (1.8V to 5 .5V) ve rsions.
2-wire Se rial
EEPROM
2K (256 x 8)
4K (512 x 8)
8K (1024 x 8)
16K (2048 x 8)
AT24C02A
AT24C04A
AT24C08A
AT24C16A
Rev. 0976L–SEEPR–1/04
Pin Configurations
Pin Name Function
A0 - A2 Address Inputs
SD A Serial Data
SCL Serial Clock Input
WP Write Protect
NC No-connect
8-lead PDIP
1
2
3
4
8
7
6
5
A0
A1
A2
GND
VCC
WP
SCL
SDA
8-le ad SOIC
1
2
3
4
8
7
6
5
A0
A1
A2
GND
VCC
WP
SCL
SDA
8-l ead TSSO P
1
2
3
4
8
7
6
5
A0
A1
A2
GND
VCC
WP
SCL
SDA
8-l ead M AP
Bottom View
1
2
3
4
8
7
6
5
VCC
WP
SCL
SDA
A0
A1
A2
GND
2AT24C02A/04A/08A/16A 0976L–SEEPR–1/04
Block Diagram
Pin D escription SERIAL CLOCK (SCL) : The SCL input is used to positive edge clock data into eac h
EEPROM device a nd negative edge clock data out of each device.
SER IAL DA TA (SDA ): The SDA pin is bidirectional for serial data transfer. This pin is
open-drain driven a nd may be wire-ORed with any number of other open-drai n or open
collector devices.
DEVICE/PAGE ADDRESSES (A2, A1, A0): The A2, A1 and A0 pins are device
address inputs that must be hard wired for the AT24C02A. As many as eight 2K devices
may be addressed on a single bus system (device addressing is discussed in detail
under the Device Addres sing section).
The AT24 C04A us es the A2 and A 1 inpu ts for hard w ire addre ssing and a t otal of fo ur
4K devices may be addressed on a single bus system. The A0 pin is a no-connect.
Absolute Maximum Rat ings*
Operating Temperature.................................. -55°C to +125°C*NO TICE: Stresses beyond those listed under “Ab solute
Maximum Ratings” m ay cause per manent dam-
age to the de vice . Thi s is a stress r ating onl y and
functi onal operation of the device at these o r any
other conditi ons beyond those indicat ed in the
operational sections of t his specification is not
impli ed. Exposure to absolute maxi m um rating
condit ions f or e xtended p eriods ma y aff ect device
reliability.
Storage Temperature... ................. ................. -65°C to +150°C
Voltage on Any Pin
wit h R e spe ct to Gr o und ........... ......... .......... .......-1 . 0V to +7 .0 V
Maximum Operating Voltage .......................................... 6.25V
DC Output Current........................................................ 5.0 mA
3
AT24C02A/04A/08A/16A
0976L–SEEPR–1/04
The AT24C08A only uses the A2 input for hardwire addressing and a total of two 8K
devices may be addressed on a single bus system. The A0 and A1 pins are no-
connects.
Th e AT24C16A does not us e the device address pins , whic h limits the numb er of
devic es on a single bus to one. The A0, A1 and A2 pins are no-connects.
WRITE PROTEC T (WP): The AT24C02A/04A/08A/16A have a Write Protect pin that
provides hardware data protection. The Write Protect pin allows normal read/write oper-
ations when connected to ground (GND). When the Write Protect pin is connected to
VCC, the write protection feature is enab led and operates as shown in the following
table .
Memory Organization AT24C02A, 2K SERIAL EEPROM: Internally organi zed with 32 pages of 8 byt es eac h,
the 2K requires an 8-bit data word address for random word addressing.
AT24C04A, 4K SERIAL EEPROM: The 4K is internal ly organize d with 32 pag es of 16
bytes each. Rando m word addressing requires a 9-bit data word address.
AT24C08A, 8K SERIAL EEPROM: The 8K is internal ly organize d with 64 pag es of 16
bytes each. Rando m word addressing requires a 10-bit data word address.
AT24C16A, 16K SERIAL EEPROM: T he 16K is internally organized with 128 pages of
16 bytes each. Random word addres sing requires an 11-bit data word address.
Note: 1. This parameter is characteriz ed and is not 100% tested.
WP Pin Status
P art of the Array Protected
24C02A 24C04A 24C08A 24C16A
At VCC Upper Half
(1K) Array Upper Half
(2K) Array Full (8K )
Array Full (16K)
Array
At GND Normal Read/Write Operations
Pin C apacitance
Applicable over recomme nded operat ing range from TA = 25°C, f = 1.0 MHz, VCC = +1.8V .
Symbol Test Condition Max Units Conditions
CI/O Input/Output Capacitance (SDA) 8 pF VI/O = 0V
CIN Input Capacit ance (A0, A 1, A2, S CL) 6 pF VIN = 0V
4AT24C02A/04A/08A/16A 0976L–SEEPR–1/04
Note: 1. VIL min and VIH max are reference only and are not tested.
DC Characteristics
Applicable over recomme nded operat ing range from: TAI = - 40°C to +85°C, VCC = +1.8V to +5.5V, TAE = -40°C to +1 2 5 °C,
VCC = +1.8V to +5.5V (unless otherwise noted).
Symbol Parameter Test Condition Min Typ Max Units
VCC1 Supply Voltage 1.8 5.5 V
VCC2 Supply Voltage 2.5 5.5 V
VCC3 Supply Voltage 2.7 5.5 V
VCC4 Supply Voltage 4.5 5.5 V
ICC Supply Current VCC = 5.0V READ at 100 kHz 0.4 1.0 mA
ICC Supply Current VCC = 5.0V WRITE at 100 kHz 2.0 3.0 mA
ISB1 Standby Current V CC = 1.8V VIN = VCC or V SS 0.6 3.0 µA
ISB2 Standby Current V CC = 2.5V VIN = VCC or V SS 1.4 4.0 µA
ISB3 Standby Current V CC = 2.7V VIN = VCC or V SS 1.6 4.0 µA
ISB4 Standby Current V CC = 5.0V VIN = VCC or V SS 8.0 18.0 µA
ILI Input Leakage Current VIN = VCC or VSS 0.10 3.0 µA
ILO Outpu t Leakage Current V OUT = VCC or VSS 0.05 3.0 µA
VIL Input Low Level (1) -0.6 VCC x 0 .3 V
VIH Input High Level (1) VCC x 0.7 VCC + 0.5 V
VOL2 Output Low Level VCC = 3.0V IOL = 2.1 mA 0.4 V
VOL1 Output Low Level VCC = 1.8V IOL = 0. 1 5 m A 0. 2 V
5
AT24C02A/04A/08A/16A
0976L–SEEPR–1/04
Notes: 1. The AT24C02A/04A/08A bearing the process letter “D” on the package (the mark is located in the lower right corner on the
topsid e of the package), guarantees 400 kHz (2.5V, 2.7V).
2. This param eter is characterized and is not 100% tested (TA = 25°C).
3. This param eter is characterized and is not 100% tested.
AC Characteristics
Applic able over recommend ed operatin g range from TAI = -40°C to + 85°C, TAE = -40°C to +125°C, VCC = +1.8V to +5.5V,
CL = 1 TTL Gate and
100 pF (unless otherwise noted).
Symbol Parameter
AT24C02A/
04A/08A/16A
1.8V
AT2402A/04A/
08A
2.5V, 2.7V AT24C16A
2.5V, 2.7V
AT24C02A/
04A/08A/16A
5.0V
UnitsMin Max Min Max Min Max Min Max
fSCL Clock Frequency, SCL 100 400(1) 400 400 kHz
tLOW Clock Pul se Width Low 4.7 4.7 1.3 1.2 µs
tHIGH Clock Pulse Width High 4.0 4.0 0.6 0.6 µs
tINoise Suppression Time(2) 100 100 100 50 ns
tAA Clock L o w to Data Ou t Valid 0.1 4.5 0 .1 4.5 0 .2 0.9 0.1 0.9 µs
tBUF T ime th e bus mu st be free before
a new transmission can star t(3) 4.7 4.7 1.3 1.2 µs
tHD.STA Start Hold Tim e 4.0 4.0 0.6 0. 6 µs
tSU.STA Start Set-up Time 4.7 4.7 0.6 0.6 µs
tHD.DAT Data In Hol d Time 0 0 0 0 µs
tSU.DAT Data In Set- up Time 200 200 100 100 ns
tRInputs Rise Time(3) 1.0 1.0 0.3 0.3 µs
tFInputs Fall Time(3) 300 300 300 300 ns
tSU.STO Stop Set-up Time 4.7 4.7 0.6 0.6 µs
tDH Data Out Hold Time 100 100 100 50 ns
tWR Write Cycle Time 5 5 5 5 ms
Endurance(3) 5.0V, 25°C, Page Mode 1M 1M 1M 1M Write
Cycles
6AT24C02A/04A/08A/16A 0976L–SEEPR–1/04
De vice Operation CLOCK and DAT A T RANS ITIONS: The SDA pi n is norm ally p ulled hig h wi th an e xter-
nal device. Data on t he S DA pin m ay ch ange onl y during SCL low time periods (refer to
Data Validity timing diagram). Data changes during SCL high periods will indicate a start
or stop condition as defined below.
START CONDITION: A hig h-to-low transition of SDA with SCL high is a start condi tion
which must precede any other command (refer to Start and Stop Definition timing
diagram).
STO P CONDIT ION: A low-to -high transi tion o f SDA with S CL hi gh is a s top co nd ition.
After a read sequence, the stop co mmand will place the EEPROM in a standby power
mode (refer to Start and Stop Definition timing diagram).
ACKNOWLEDGE: All addresses and data words are serially transmitted to and from
the EEPROM in 8 bit words. The EEPROM sends a zero to acknowledge that it has
received each word. This happens during the ninth clock cycle.
STANDBY MODE: The AT24C02A /04A/08A/16A featur es a low power standby mode
w hich is en able d: (a) up on powe r-up an d (b) a fter the rec eipt of th e STO P b it an d th e
completion of any internal operations.
MEMORY RESET: After an interruption in protocol, power loss or system reset, any
2-wire part can be reset by following th ese steps: (a) Clo ck up to 9 cycles, (b) loo k for
SDA high in each cycle while SCL is high and then (c) create a start condition as SDA is
high.
7
AT24C02A/04A/08A/16A
0976L–SEEPR–1/04
Bus Timing (SCL: Serial Clock, SDA: Serial Data I/O)
Write Cycle Timing (SCL: Serial Clock, SDA: Serial Data I/O)
Note: 1. The write cycle time tWR is the time from a valid stop condition of a write sequence to the end of the i nterv al
clear/write cycle.
twr(1)
STOP
CONDITION START
CONDITION
WORDn
ACK
8th BIT
SCL
SDA
8AT24C02A/04A/08A/16A 0976L–SEEPR–1/04
Data Validity
Start and Stop Definition
Output Acknowledge
9
AT24C02A/04A/08A/16A
0976L–SEEPR–1/04
Device Addressing The 2K , 4K a nd 8K E EPROM d evices all require an 8 bit device address word fo llowing
a start condition to enable the chip for a read or write operation (refer to Figure 1).
The d evice a ddress wo rd consists of a m andat ory one, ze ro sequenc e for the first fo ur
most si g nificant bi ts a s shown . Th i s is common to all the EEPROM devi ce s .
The next 3 bits are the A2, A1 and A0 device address bits fo r the 2K EEPROM. These
3 bits must compare to their corresponding hard-wired input pins.
The 4K EEPR OM only uses the A2 an d A1 de vice address bits with the third bit being a
memory page address bit. The two device addres s bits must compare to their c orre-
spon ding hard-wired input pins. The A0 pin is no-conn ec t.
The 8K EEPROM only uses the A2 device address bit with the next 2 bits b eing for
memory page addressing. The A2 bit must compare to its corresponding hard-wired
input pin. The A1 and A0 pins are no-connect.
The 16K EEPROM does not use the device address pins , which limits the number of
devic es on a single bus to one. The A0, A1 and A2 pins are no-connects.
The ei ghth bit of th e device addres s is th e read/write operat ion select b it. A read opera-
tion is initiated if this bit is high and a write operation is initiated if this bit is lo w.
Up on a compare of the devic e addres s, the EE PR OM w ill out put a ze ro. If a com par e is
no t ma de, the chip will r eturn to a standby state.
Write Operations BYTE WRITE: A write ope ration requires a n 8 bit data word address following the
device address word and acknowledgement. Upon receipt of this address, the EEPROM
will again respond with a zero and the n clock in the first 8 bit data word. Following
receipt of the 8 bit data word, the EEPROM will output a zero and the addressing
devic e, such as a m icrocontro ller, mus t termina te the write sequenc e wi th a s top c on di-
tion. At this time the EEPROM enters an internally-timed write cycle, tWR, to the
nonvolatile memo ry. All inputs are disabled during this write cycle and the EEPROM will
not respond until the write is comple te (refer to F igure 2).
PAGE W RITE: The 2K EEPROM is capable of an 8-byte page write, and the 4K, 8K and
16K devices are cap able of 16-byte page writes.
A p age write is i nitiated t he sam e as a by te write, but th e m icroc ontroller does not send
a stop condition after the first data word is clocked in. Instead, after th e EEPROM
acknowledges receipt of the first data word, the microcontroller can transmit up to seven
(2K) or fifteen (4K, 8 K, 16K) more data words. T he EEPROM will respond with a zero
after each data word received. The microcontroller must terminate the page write
sequence with a stop condition (refer to Figure 3).
Th e dat a word addre ss l ower t hree (2K) or fo ur (4K, 8K, 1 6K) bi ts are intern ally incre-
men ted followin g the receipt of each d ata word. T he higher d ata word addre ss bits are
not incremented, retaining the memory page row location. When the word address,
internally generated, reaches the page boundary, the following byte is placed at t he
beginning of the same page. If more than eight (2K) or sixteen (4K, 8K, 16K) data words
are tr a n s mitt e d t o the EEPR O M, the dat a w ord address will “roll over” and previous data
will be overwritten.
ACKNOW LEDGE POLLING: Once the internally-timed write cycle h as started and the
EEPROM inputs are disabled, acknowledge polling can be initiated. This involves send-
ing a start condition followed by the device address word. The read/write bit is
representative of the operation desired. Only if the internal write cycle has completed
will the EEPROM respond with a ze ro allowing the read or write sequence to continue.
10 AT24C02A/04A/08A/16A 0976L–SEEPR–1/04
Rea d Oper ati on s Re ad operatio ns are initiated t he same way as write op erations with t he exception t hat
the read/write sele ct bit in the d evice address word i s set to on e. There a re thre e read
operations : current address read, random add ress read and sequential read.
CURRENT ADDRESS READ: The internal data word address counter maintains the
last a ddress acc essed during the last read or write operat ion , inc remen ted by one. This
address stays valid between operations as long as the chip power is maintained. The
addres s “roll over” du ring read is from the last byte of th e last memory page to the first
byte of the first page. The address “roll over” during write is from the last byte of the cur-
rent page to the first byte of the same page.
Once the device address with the rea d/write select bit set to one is cl ocked in and
acknowl edged by the EEPROM, the cur rent add ress data word is serially clocked out.
The microcon troller do es not res pond with an in put zero b ut does generate a followin g
stop condition (refer to F igure 4).
RANDOM READ: A random read requires a “dummy” byte write sequence to load in the
dat a word address . Onc e th e device add ress word an d data wo rd addres s are clocke d
in and ack nowledged by the E EPROM , the microcontroller must gen erate another start
con dition. The m icrocontroller now initiates a current address read by sending a device
address with the read/write select bit high. The EEPROM acknowledges the device
address and serially clocks out the data word. The microcontroller does not respond
with a zero but does generate a following stop condition (refer to Figure 5).
SEQUENTIAL READ: Sequential reads are initiated by either a current address read or
a random address re ad. After the m icroc ontroller receives a data word, it responds with
an ac know ledge. As long as the EEP ROM receives an ac know ledge, it will cont inue to
increment the data word address and serially clock out sequential data words. When the
mem ory addres s limi t is reac hed, t he dat a word addres s wil l “roll over” and t he sequen-
tial read will continue. The sequential read operation is terminated when the
micro controlle r does not respon d with a zero but do es generat e a fo llowing stop con di-
tion (refer to Figure 6).
Fi gure 1. Device Address
MSB
2K LSB
1A
2
A
0
A
1
R/W
4K 1A
2
P0
A
1
R/W
0
0
0
0
0
0
1
1
18K 1 A
2
P0
P
1
R/W
001
16K 1P2P0
R/W
P1
11
AT24C02A/04A/08A/16A
0976L–SEEPR–1/04
Figu re 2. Byte Write
Figu re 3. Page Write
Figu re 4. Current Address Read
S
T
A
R
T
M
S
B
M
S
B
L
S
B
S
T
O
P
W
R
I
T
E
SDA LINE
DEVICE
ADDRESS WORD ADDRESS DATA
L
S
B
A
C
K
A
C
K
A
C
K
R
/
W
S
T
A
R
T
M
S
B
S
T
O
P
W
R
I
T
E
SDA LINE
DEVICE
ADDRESS WORD ADDRESS (n) DATA (n) DATA (n + 1) DATA (n + x)
L
S
B
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
R
/
W
S
T
A
R
T
R
E
A
D
M
S
B
S
T
O
P
SDA LINE
DEVICE
ADDRESS
DATA
L
S
B
A
C
K
N
O
A
C
K
R
/
W
12 AT24C02A/04A/08A/16A 0976L–SEEPR–1/04
Figu re 5. Random Read
Figu re 6. Sequent ial Read
S
T
A
R
T
S
T
A
R
T
M
S
B
S
T
O
P
W
R
I
T
E
R
E
A
D
SDA LINE
DEVICE
ADDRESS
DUMMY WRITE
WORD
ADDRESS n
DEVICE
ADDRESS
DATA n
L
S
B
A
C
K
A
C
K
A
C
K
N
O
A
C
K
R
/
WM
S
B
L
S
BM
S
B
L
S
B
13
AT24C02A/04A/08A/16A
0976L–SEEPR–1/04
Note: Fo r 2. 7V devices used in the 4.5V to 5.5V range, please refer to performance values in t he AC and DC chara cteristics table.
AT24 C02A Ordering Information
Order ing Code Package Operation Range
AT24C02A-10PI-2.7
AT24C02AN-10SI-2.7
AT24C02A-10TI-2.7
AT24C02AY1-10YI-2.7
8P3
8S1
8A2
8Y1
Industrial
(-40°C to 85 °C)
AT24C02A-10PI-1.8
AT24C02AN-10SI-1.8
AT24C02A-10TI-1.8
AT24C02AY1-10YI-1.8
8P3
8S1
8A2
8Y1
Industrial
(-40°C to 85 °C)
AT24C02AN-10SU-2.7
AT24C02AN-10SU-1.8 8S1
8S1
Lead-Free/Halogen-Free/
Indust rial Temperature
(-40°C to 85 °C)
AT24C02AN-10SE-2.7 8S1 High Grade/Extended Temperature
(-40°C to 125 °C)
Package Type
8P3 8-pin, 0.300" Wide, Plastic Dual Inline Pack age (PDI P)
8S1 8-lead, 0.150" Wide, Plastic Gull Wi ng Small Outline (JEDEC SOIC)
8A2 8-lead, 0.170" Wide, Thin Shrink Small Outline Package (TSSOP)
8Y1 8-lead, 4.90 mm x 3.00 mm Body, Dual Footprint, Non-leaded, Miniature Array Package (MAP)
Options
-2.7 Low Voltage (2. 7V to 5.5V)
-1.8 Low Voltage (1. 8V to 5.5V)
14 AT24C02A/04A/08A/16A 0976L–SEEPR–1/04
Note: Fo r 2. 7V devices used in the 4.5V to 5.5V range, please refer to performance values in t he AC and DC chara cteristics table.
AT24 C04A Ordering Information
Order ing Code Package Operation Range
AT24C04A-10PI-2.7
AT24C04AN-10SI-2.7
AT24C04A-10TI-2.7
AT24C04AY1-10YI-2.7
8P3
8S1
8A2
8Y1
Industrial
(-40°C to 85 °C)
AT24C04A-10PI-1.8
AT24C04AN-10SI-1.8
AT24C04A-10TI-1.8
AT24C04AY1-10YI-1.8
8P3
8S1
8A2
8Y1
Industrial
(-40°C to 85 °C)
AT24C04AN-10SU-2.7
AT24C04AN-10SU-1.8 8S1
8S1
Lead-Free/Halogen-Free/
Indust rial Temperature
(-40°C to 85 °C)
AT24C04AN-10SE-2.7 8S1 High Grade/Extended Temperature
(-40°C to 125 °C)
Package Type
8P3 8-pin, 0.300" Wide, Plastic Dual Inline Pack age (PDI P)
8S1 8-lead, 0.150" Wide, Plastic Gull Wi ng Small Outline (JEDEC SOIC)
8A2 8-lead, 0.170" Wide, Thin Shrink Small Outline Package (TSSOP)
8Y1 8-lead, 4.90 mm x 3.00 mm Body, Dual Footprint, Non-leaded, Miniature Array Package (MAP)
Options
-2.7 Low Voltage (2. 7V to 5.5V)
-1.8 Low Voltage (1. 8V to 5.5V)
15
AT24C02A/04A/08A/16A
0976L–SEEPR–1/04
Note: Fo r 2. 7V devices used in the 4.5V to 5.5V range, please refer to performance values in t he AC and DC chara cteristics table.
AT24 C08A Ordering Information
Order ing Code Package Operation Range
AT24C08A-10PI-2.7
AT24C08AN-10SI-2.7
AT24C08A-10TI-2.7
AT24C08AY1-10YI-2.7
8P3
8S1
8A2
8Y1
Industrial
(-40°C to 85 °C)
AT24C08A-10PI-1.8
AT24C08AN-10SI-1.8
AT24C08A-10TI-1.8
AT24C08AY1-10YI-1.8
8P3
8S1
8A2
8Y1
Industrial
(-40°C to 85 °C)
AT24C08AN-10SU-2.7
AT24C08AN-10SU-1.8
AT24C08A-10TU-2.7
AT24C08A-10TU-1.8
8S1
8S1
8A2
8A2
Lead-Free/Halogen-Free/
Industrial Temperature
(-40°C to 85 °C)
AT24C08AN-10SE-2.7 8S1 High Grade/Extended Temperature
(-40°C to 125°C)
Package Type
8P3 8-pin, 0.300" Wide, Plastic Dual Inline Pack age (PDI P)
8S1 8-lead, 0.150" Wide, Plastic Gull Wi ng Small Outline (JEDEC SOIC)
8A2 8-lead, 0.170" Wide, Thin Shrink Small Outline Package (TSSOP)
8Y1 8-lead, 4.90 mm x 3.00 mm Body, Dual Footprint, Non-leaded, Miniature Array Package (MAP)
Options
-2.7 Low Voltage (2. 7V to 5.5V)
-1.8 Low Voltage (1. 8V to 5.5V)
16 AT24C02A/04A/08A/16A 0976L–SEEPR–1/04
Note: Fo r 2. 7V devices used in the 4.5V to 5.5V range, please refer to performance values in t he AC and DC chara cteristics table.
AT24 C16A Ordering Information
Order ing Code Package Operation Range
AT24C16A-10PI-2.7
AT24C16AN-10SI-2.7
AT24C16A-10TI-2.7
AT24C16AY1-10YI-2.7
8P3
8S1
8A2
8Y1
Industrial
(-40°C to 85 °C)
AT24C16A-10PI-1.8
AT24C16AN-10SI-1.8
AT24C16A-10TI-1.8
AT24C16AY1-10YI-1.8
8P3
8S1
8A2
8Y1
Industrial
(-40°C to 85 °C)
AT24C16AN-10SU-2.7
AT24C16AN-10SU-1.8
AT24C16A-10TU-2.7
AT24C16A-10TU-1.8
8S1
8S1
8A2
8A2
Lead-Free/Halogen-Free/
Industrial Temperature
(-40°C to 85 °C)
AT24C16AN-10SE-2.7 8S1 High Grade/Extended Temperature
(-40°C to 125°C)
Package Type
8P3 8-pin, 0.300" Wide, Plastic Dual Inline Pack age (PDI P)
8S1 8-lead, 0.150" Wide, Plastic Gull Wi ng Small Outline (JEDEC SOIC)
8A2 8-lead, 0.170" Wide, Thin Shrink Small Outline Package (TSSOP)
8Y1 8-lead, 4.90 mm x 3.00 mm Body, Dual Footprint, Non-leaded, Miniature Array Package (MAP)
Options
-2.7 Low Voltage (2. 7V to 5.5V)
-1.8 Low Voltage (1. 8V to 5.5V)
17
AT24C02A/04A/08A/16A
0976L–SEEPR–1/04
Packaging Information
8P3 – PDIP
2325 Orchard Parkway
San Jose, CA 95131
TITLE DRAWING NO.
R
REV.
8P3, 8-lead, 0.300" Wide Body, Plastic Dual
In-line Package (PDIP)
01/09/02
8P3 B
D
D1
E
E1
e
L
b2
b
A2 A
1
N
eA
c
b3
4 PLCS
Top View
Side View
End View
COMMON DIMENSIONS
(Unit of Measure = inches)
SYMBOL MIN NOM MAX NOTE
Notes: 1. This drawing is for general information only; refer to JEDEC Drawing MS-001, Variation BA for additional information.
2. Dimensions A and L are measured with the package seated in JEDEC seating plane Gauge GS-3.
3. D, D1 and E1 dimensions do not include mold Flash or protrusions. Mold Flash or protrusions shall not exceed 0.010 inch.
4. E and eA measured with the leads constrained to be perpendicular to datum.
5. Pointed or rounded lead tips are preferred to ease insertion.
6. b2 and b3 maximum dimensions do not include Dambar protrusions. Dambar protrusions shall not exceed 0.010 (0.25 mm).
A 0.210 2
A2 0.115 0.130 0.195
b 0.014 0.018 0.022 5
b2 0.045 0.060 0.070 6
b3 0.030 0.039 0.045 6
c 0.008 0.010 0.014
D 0.355 0.365 0.400 3
D1 0.005 3
E 0.300 0.310 0.325 4
E1 0.240 0.250 0.280 3
e 0.100 BSC
eA 0.300 BSC 4
L 0.115 0.130 0.150 2
18 AT24C02A/04A/08A/16A 0976L–SEEPR–1/04
8S1 – JEDEC SOIC
1150 E. Cheyenne Mtn. Blvd.
Colorado Springs, CO 80906
TITLE DRAWING NO.
R
REV.
Note:
10/7/03
8S1, 8-lead (0.150" Wide Body), Plastic Gull Wing
Small Outline (JEDEC SOIC) 8S1 B
COMMON DIMENSIONS
(Unit of Measure = mm)
SYMBOL MIN NOM MAX NOTE
A1 0.10 – 0.25
These drawings are for general information only. Refer to JEDEC Drawing MS-012, Variation AA for proper dimensions, tolerances, datums, etc.
A 1.35 – 1.75
b 0.31 – 0.51
C 0.17 – 0.25
D 4.80 – 5.00
E1 3.81 – 3.99
E 5.79 – 6.20
e 1.27 BSC
L 0.40 – 1.27
∅ 0˚ – 8˚
∅
Top View End View
Side View
eB
D
A
A1
N
E
1
C
E1
L
19
AT24C02A/04A/08A/16A
0976L–SEEPR–1/04
8A2 – TSSOP
2325 Orchard Parkway
San Jose, CA 95131
TITLE DRAWING NO.
R
REV.
5/30/02
COMMON DIMENSIONS
(Unit of Measure = mm)
SYMBOL MIN NOM MAX NOTE
D 2.90 3.00 3.10 2, 5
E 6.40 BSC
E1 4.30 4.40 4.50 3, 5
A – – 1.20
A2 0.80 1.00 1.05
b 0.19 – 0.30 4
e 0.65 BSC
L 0.45 0.60 0.75
L1 1.00 REF
8A2, 8-lead, 4.4 mm Body, Plastic
Thin Shrink Small Outline Package (TSSOP)
Notes: 1. This drawing is for general information only. Refer to JEDEC Drawing MO-153, Variation AA, for proper dimensions, tolerances,
datums, etc.
2. Dimension D does not include mold Flash, protrusions or gate burrs. Mold Flash, protrusions and gate burrs shall not exceed
0.15 mm (0.006 in) per side.
3. Dimension E1 does not include inter-lead Flash or protrusions. Inter-lead Flash and protrusions shall not exceed 0.25 mm
(0.010 in) per side.
4. Dimension b does not include Dambar protrusion. Allowable Dambar protrusion shall be 0.08 mm total in excess of the
b dimension at maximum material condition. Dambar cannot be located on the lower radius of the foot. Minimum space between
protrusion and adjacent lead is 0.07 mm.
5. Dimension D and E1 to be determined at Datum Plane H.
8A2 B
Side View
End View
Top View
A2
A
L
L1
D
123
E1
N
b
Pin 1 indicator
this corner
E
e
20 AT24C02A/04A/08A/16A 0976L–SEEPR–1/04
8Y1 – MAP
A – – 0.90
A1 0.00 – 0.05
D 4.70 4.90 5.10
E 2.80 3.00 3.20
D1 0.85 1.00 1.15
E1 0.85 1.00 1.15
b 0.25 0.30 0.35
e 0.65 TYP
L 0.50 0.60 0.70
PIN 1 INDEX AREA
D
E
A
A1 b
876
e
5
L
D1
E1
PIN 1 INDEX AREA
1234
A
Top View End View Bottom View
Side View
2325 Orchard Parkway
San Jose, CA 95131
TITLE DRAWING NO.
R
REV.
8Y1, 8-lead (4.90 x 3.00 mm Body) MSOP Array Package
(MAP) Y1 C
8Y1
2/28/03
COMMON DIMENSIONS
(Unit of Measure = mm)
SYMBOL
MIN NOM MAX
NOTE
Pr inted o n rec ycled pa per.
0976L–SEEPR–1/04 xM
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warranty which is detailed in Atmel’s Terms and Conditions located on the Company’s web site. The Company assumes no responsibility for a ny
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gran ted by th e Com pany in conn ecti on w ith th e sale of A tme l prod uc ts, exp ressl y or by im pli catio n. Atme l’s pro duct s ar e no t aut ho rized for us e
as critical components in life suppor t devices or systems.
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