1
¬
FN6707.0
ISL62871, ISL62872
PWM DC/DC Controller With VID Inputs
For Portable GPU Core-Voltage Regulator
The ISL62871 and ISL62872 IC’s are Single-Phase
Synchronous-Buck PWM voltage regulators featuring
Intersil’s Robust Ripple Regulator (R3) Technology™. The
wide 3.3V to 25V input voltage range is ideal for systems
that run on battery or AC-adapter power sources. The
ISL62871 and ISL62872 are low-cost solutions for
applications requiring dynamically selected slew-rate
controlled output voltages. The soft-start and dynamic
setpoint slew-rates are capacitor programmed. Voltage
identification logic-inputs select two (ISL62871) or four
(ISL62872) resistor-programmed setpoint reference voltages
that directly set the output voltage of the converter between
0.5V to 1.5V, and up to 3.3V using a feedback voltage
divider. Optionally, an external reference such as the DAC
output from a microcontroller, can be used by either IC to
program the setpoint reference voltage, and still maintain the
controlled slew-rate features. Robust integrated MOSFET
drivers and Schottky bootstrap diode reduce the
implementation area and lower component cost.
Intersil’s R3 Technology™ combines the best features of
both fixed-frequency and hysteretic PWM control. The PWM
frequency is 300kHz during static operation, becoming
variable during changes in load, setpoint voltage, and input
voltage when changing between battery and AC-adapter
power. The modulators ability to change the PWM switching
frequency during these events in conjunction with external
loop compensation produces superior transient response.
For maximum efficiency, the co nverter automatically enters
diode-emulation mode (DEM) during ligh t-lo ad conditions
such as system standby.
Features
• Input Voltage Range: 3.3V to 25V
• Output Voltage Range: 0.5V to 3.3V
• Output Load up to 30A
• Extremely Flexible Output Voltage Programmability
- 2-Bit VID (ISL62872) Selects Four Independent
Setpoint Voltages
- 1-Bit VID (ISL62871) Selects Two Independent Setpoint
Voltages
- Simple Resistor Programming of Setpoint Voltages
- Accepts External Setpoint Reference Such as DAC
• ±0.75% System Accuracy: -10°C to +100°C
• One Capacitor Programs Soft-start and Setpoint Slew-rate
• Fixed 300kHz PWM Frequency in Continuous Conduction
• External Compensation Af fords Optimum Con trol Loop
Tuning
• Automatic Diode Emulation Mode for Highest Efficiency
• Integrated High-current MOSFET Drivers and Schottky
Boot-Strap Diode for Optimal Efficiency
• Choice of Overcurrent Detection Schemes
- Lossless Inductor DC R Curr en t Sen s i n g
- Precision Resistive Current Sensing
• Power-Good Monitor for Soft-Start and Fault Detection
• Fault Protection
- Undervoltage
- Overvoltage
- Overcurrent (DCR-Sense or Resistive-Sense
Capability)
- Over-Temperature Protection
- Fault Identification by PGOOD Pull-Down Resistance
• Pb-Free (RoHS compliant)
Applications
• Mobile PC Graphical Processing Unit VCC rail
• Mobile PC I/O Controller Hub (ICH) VCC rail
• Mobile PC Memory Controller Hub (GMCH) VCC rail
• Built-in voltage margin for system-level test
Data Sheet August 14, 2008
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 |Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2008. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
2FN6707.0
August 14, 2008
ISL62871, ISL62872
Pinouts
ISL62872
(20 LD 3.2X1.8 µTQFN)
TOP VIEW
ISL62871
(16 LD 2.6X1.8 µTQFN)
TOP VIEW
19
18
17
16
15
14
13
1
20
10
11
2
3
4
5
6
7
8
PGND
GND
EN
VID1
VID0
SREF
SET0
VCC
BOOT
UGATE
PHASE
NC
OCSET
VO
LGATE
PVCC
SET2
PGOOD
9
SET1 12 FB
12
11
10
9
16
15
14
13
5
6
7
8
1
2
3
4
GND
EN
VID0
SREF
BOOT
UGATE
PHASE
OCSET
PGND
LGATE
PVCC
VCC
SET0
PGOOD
FB
VO
Ordering Information
PART NUMBER
(Note) PART
MARKING TEMP RANGE
(°C) PACKAGE
(Pb-Free) PKG.
DWG. #
ISL62872HRUZ GAN -10 to +100 20 Ld 3.2x1.8 µTQFN L20.3.2x1.8
ISL62872HRUZ -T* GAN -10 to +100 20 Ld 3.2x1.8 µTQFN L20.3.2x1.8
ISL62871HRUZ GAM -10 to +100 16 Ld 2.6x1.8 µTQFN L16.2.6x1.8A
ISL62871HRUZ -T* GAM -10 to +100 16 Ld 2.6x1.8 µTQFN L16.2.6x1.8A
*Please refer to TB347 for details on reel specifications.
NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and
NiPdAu plate - e4 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free
products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3FN6707.0
August 14, 2008
Block Diagram
PGND
PVCC
OVP
+
−
UVP
+
−
POR
*SET1
*SET2
*VID1
VID0
VID DECODER
SET0
SREF
BOOT
LGATE
DRIVER UGATE
DRIVER
PHASE
VO
OCSET
+
−
OCP
VSET
FB
PGOOD
SW1
SW2
SW3
SW0
100pF
SW4
VREF
FIGURE 1. SIMPLIFIED FUNCTIONAL BLOCK DIAGRAM OF ISL62872, ISL62871
100kΩ
VCC
INT
GND
IOCSET
10µF
+
−
+
−
+
−
Cr
H
L
IN
VCC
PWM
VW
EN
PWM
RUN
RUN
RUN
*ISL62872 ONLY FAULT
EXT
500mV
gmVO
gmVIN
VR
VCOMP
+
−
EA
FB
PROTECTION
SHOOT-THROUGH
OTP
FAULT
ISL62871, ISL62872
4FN6707.0
August 14, 2008
Application Schematics
FIGURE 2. ISL62872 APPLICATION SCHEMATIC WITH FOUR OUTPUT VOLTAGE SETPOINTS AND DCR CURRENT SENSE
FIGURE 3. ISL62872 APPLICATION SCHEMATIC WITH FOUR OUTPUT VOLTAGE SETPOINTS AND RESISTOR CURRENT SENSE
VCC
BOOT
UGATE
PHASE
NC
OCSET
VO
FB
PGND
GND
EN
VID1
VID0
SREF
SET0
SET1
SET2
PGOOD
LGATE
PVCC
LO
COC
CBOOT COCSET
ROCSET
QHS
QLS
CCOMP
RCOMP
RFB
3.3V TO 25V
0.5V TO 3.3V
RO
COB
CINCCINB
VIN
VOUT
CSOFT
RSET1 RSET2 RSET3
RSET4
CVCC
+5V
RVCC
CPVCC
GPIO
2
3
4
5
6
7
8
9
19
18
17
16
15
14
13
12
110
11 20
GPIO
RPGOOD
VCC
ROFS
VCC
BOOT
UGATE
PHASE
NC
OCSET
VO
FB
PGND
GND
EN
VID1
VID0
SREF
SET0
SET1
LO
COC
COCSET
ROCSET
QHS
QLS
CCOMP
RCOMP
RFB
GPIO
3.3V TO 25V
0.5V TO 3.3V
2
3
4
5
6
7
8
9
19
18
17
16
15
14
13
12
1LGATE
PVCC
10
11 20
SET2
PGOOD
RO
COB
CINCCINB
VIN
VOUT
CSOFT
RSET1 RSET2 RSET3
RSET4
CVCC
+5V
RVCC
CPVCC
RSNS
CBOOT
RPGOOD
VCC
GPIO
ROFS
ISL62871, ISL62872
5FN6707.0
August 14, 2008
FIGURE 4. ISL62871 APPLICATION SCHEMATIC WITH TWO OUTPUT VOLTAGE SETPOINTS AND DCR CURRENT SENSE
FIGURE 5. ISL62871 APPLICATION SCHEMATIC WITH TWO OUTPUT VOLTAGE SETPOINTS AND RESISTOR CURRENT SENSE
Application Schematics (Continued)
EN
GND
SREF
VID0
CBOOT
LO
COC
COCSET
ROCSET
QHS
QLS
CCOMP
RCOMP
RFB
3.3V TO 25V
0.5V TO 3.3V
RO
COB
CINCCINB
VIN
VOUT
CSOFT
RSET1
RSET2
CVCC
CPVCC
GPIO
GPIO
8
7
6
5
13
14
15
16
VO
FB
PGOOD
SET0
VCC
PVCC
LGATE
PGND
11 UGATE
BOOT
2
112
9OCSET
PHASE
4
310
+5V
RVCC
RPGOOD
VCC
ROFS
EN
GND
SREF
VID0
CBOOT
LO
COC
COCSET
ROCSET
QHS
QLS
CCOMP
RCOMP
RFB
3.3V TO 25V
0.5V TO 3.3V
RO
COB
CINCCINB
VIN
VOUT
CSOFT
RSET1
RSET2
CVCC
CPVCC
GPIO
8
7
6
5
13
14
15
16
VO
FB
PGOOD
SET0
VCC
PVCC
LGATE
PGND
11 UGATE
BOOT
2
112
9OCSET
PHASE
4
310
+5V
RVCC
GPIO
RPGOOD
VCC
ROFS
RSNS
ISL62871, ISL62872
6FN6707.0
August 14, 2008
FIGURE 6. ISL62872 APPLICATION SCHEMATIC WITH EXTERNAL REFERENCE INPUT AND DCR CURRENT SENSE
FIGURE 7. ISL62871 APPLICATION SCHEMATIC WITH EXTERNAL REFERENCE INPUT AND DCR CURRENT SENSE
Application Schematics (Continued)
VCC
BOOT
UGATE
PHASE
NC
OCSET
VO
FB
PGND
GND
EN
VID1
VID0
SREF
SET0
SET1
SET2
PGOOD
LGATE
PVCC
LO
COC
CBOOT COCSET
ROCSET
QHS
QLS
CCOMP
RCOMP
RFB
3.3V TO 25V
0.5V TO 3.3V
RO
COB
CINCCINB
VIN
VOUT
CSOFT
CVCC
+5V
RVCC
CPVCC
GPIO
2
3
4
5
6
7
8
9
19
18
17
16
15
14
13
12
110
11 20
GPIO
RPGOOD
VCC
ROFS
EXT_REF
EN
GND
SREF
VID0
CBOOT
LO
COC
COCSET
ROCSET
QHS
QLS
CCOMP
RCOMP
RFB
3.3V TO 25V
0.5V TO 3.3V
RO
COB
CINCCINB
VIN
VOUT
CVCC
CPVCC
GPIO
8
7
6
5
13
14
15
16
VO
FB
PGOOD
SET0
VCC
PVCC
LGATE
PGND
11 UGATE
BOOT
2
112
9OCSET
PHASE
4
310
+5V
RVCC
ROFS
CSOFT
EXT_REF
GPIO
RPGOOD
VCC
ISL62871, ISL62872
7FN6707.0
August 14, 2008
Absolute Maximum Ratings
VCC, PVCC, PGOOD to GND. . . . . . . . . . . . . . . . . . -0.3V to +7.0V
VCC, PVCC to PGND . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +7.0V
GND to PGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +0.3V
EN, SET0, SET1, SET2, VO,
VID0, VID1, FB, OCSET, SREF. . . . . . . -0.3V to GND, VCC + 0.3V
BOOT Voltage (VBOOT-GND). . . . . . . . . . . . . . . . . . . . .-0.3V to 33V
BOOT To PHASE Voltage (VBOOT-PHASE). . . . . . -0.3V to 7V (DC)
-0.3V to 9V (<10ns)
PHASE Voltage . . . . . . . . . . . . . . . . . . . . . . . . . .GND - 0.3V to 28V
GND -8V (<20ns Pulse Width, 10µJ)
UGATE Voltage . . . . . . . . . . . . . . . . VPHASE - 0.3V (DC) to VBOOT
VPHASE - 5V (<20ns Pulse Width, 10µJ) to VBOOT
LGATE Voltage . . . . . . . . . . . . . . . GND - 0.3V (DC) to VCC + 0.3V
GND - 2.5V (<20ns Pulse Width, 5µJ) to VCC + 0.3V
Thermal Information
Thermal Resistance (Typical, Note 1) θJA (°C/W)
20 Ld µTQFN Package . . . . . . . . . . . . . . . . . . . . . . 84
16 Ld µTQFN Package . . . . . . . . . . . . . . . . . . . . . . 84
Junction Temperature Range. . . . . . . . . . . . . . . . . .-55°C to +150°C
Operating Temperature Range . . . . . . . . . . . . . . . .-10°C to +100°C
Storage Temperature. . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Pb-free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Recommended Operating Conditions
Ambient Temperature Range. . . . . . . . . . . . . . . . . .-10°C to +100°C
Converter Input Voltage to GND . . . . . . . . . . . . . . . . . . 3.3V to 25V
VCC, PVCC to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5V ±5%
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
NOTES:
1. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See
Tech Brief TB379.
Electrical Specifications These specifications apply for TA = -10°C to +100°C, unless otherwise stated.
All typical specifications TA = +25°C, VCC = 5V. Parameters with MIN and/or MAX limits are 100% tested at
+25°C, unless otherwise specified. Temperature limits established by characterization and are not production
tested.
PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT
VCC and PVCC
VCC Input Bias Current IVCC EN = 5V, VCC = 5V, FB = 0.55V, SREF<FB - 1.1 1.5 mA
VCC Shutdown Current IVCCoff EN = GND, VCC = 5V - 0.1 1.0 µA
PVCC Shutdown Current IPVCCoff EN = GND, PVCC = 5V - 0.1 1.0 µA
VCC POR THRESHOLD
Rising VCC POR Threshold Voltage VVCC_THR 4.40 4.49 4.60 V
Falling VCC POR Threshold Voltage VVCC_THF 4.10 4.22 4.35 V
REGULATION
Reference Voltage VREF(int) -0.50- V
System Accuracy VID0 = VID1 = GND, PWM Mode = CCM -0.75 - +0.75 %
PWM
Switching Frequency FSW PWM Mode = CCM 270 300 330 kHz
VO
VO Input Voltage Range VVO 0-3.6V
VO Input Impedance RVO EN = 5V - 600 - kΩ
VO Reference Offset Current IVOSS VENTHR < EN, SREF = Soft-Start Mode - 10 - µA
VO Input Leakage Current IVOoff EN = GND, VO = 3.6V - .1 - µA
ERROR AMPLIFIER
FB Input Bias Current IFB EN = 5V, FB = 0.50V -20 - +50 nA
SREF
SREF Operating Voltage Range VSREF Nominal SREF Setting With 1% Resistors 0.5 - 1.5 V
Soft-Start Current ISS SREF = Soft-Start Mode 10 20 30 µA
Voltage Step Current IVS SREF = Setpoint-Stepping Mode ±60 ±100 ±140 µA
ISL62871, ISL62872
8FN6707.0
August 14, 2008
EXTERNAL REFERENCE
EXTREF Operating Voltage Range VEXT SET0 = VCC 0 - 1.5 V
EXTREF Accuracy VEXT_OFS SET0 = VCC, VID0 = 0V to 1.5V -0.5 - +0.5 %
POWER GOOD
PGOOD Pull-down Impedance RPG_SS PGOOD = 5mA Sink 75 95 150 Ω
RPG_UV PGOOD = 5mA Sink 75 95 150 Ω
RPG_OV PGOOD = 5mA Sink 50 65 90 Ω
RPG_OC PGOOD = 5mA Sink 25 35 50 Ω
PGOOD Leakage Current IPG PGOOD = 5V - 0.1 1.0 µA
PGOOD Maximum Sink Current (Note 2) IPG_max -5.0-mA
GATE DRIVER
UGATE Pull-Up Resistance (Note 2) RUGPU 200mA Source Current - 1.0 1.5 Ω
UGATE Source Current (Note 2) IUGSRC UGATE - PHASE = 2.5V - 2.0 - A
UGATE Sink Resistance (Note 2) RUGPD 250mA Sink Current - 1.0 1.5 Ω
UGATE Sink Current (Note 2) IUGSNK UGATE - PHASE = 2.5V - 2.0 - A
LGATE Pull-Up Resistance (Note 2) RLGPU 250mA Source Current - 1.0 1.5 Ω
LGATE Source Current (Note 2) ILGSRC LGATE - GND = 2.5V - 2.0 - A
LGATE Sink Resistance (Note 2) RLGPD 250mA Sink Current - 0.5 0.9 Ω
LGATE Sink Current (Note 2) ILGSNK LGATE - PGND = 2.5V - 4.0 - A
UGATE to LGATE Deadtime tUGFLGR UGATE falling to LGATE rising, no load - 21 - ns
LGATE to UGATE Deadtime tLGFUGR LGATE falling to UGATE rising, no load - 21 - ns
PHASE
PHASE Input Impedance RPHASE -33-kΩ
BOOTSTRAP DIODE
Forward Voltage VFPVCC = 5V, IF = 2 mA - 0.58 - V
Reverse Leakage IRVR = 25V - 0.2 - µA
CONTROL INPUTS
EN High Threshold Voltage VENTHR 2.0 - - V
EN Low Threshold Voltage VENTHF --1.0V
EN Input Bias Current IEN EN = 5V 1.5 2.0 2.5 µA
EN Leakage Current IENoff EN = GND - 0.1 1.0 µA
VID<0,1> High Threshold Voltage VVIDTHR 0.6 - - V
VID<0,1> Low Threshold Voltage VVIDTHF --0.5V
VID<0,1> Input Bias Current IVID EN = 5V, VVID = 1V - 0.5 - µA
VID<0,1> Leakage Current IVIDoff -0-µA
PROTECTION
OCP Threshold Voltage VOCPTH VOCSET - VO-1.75 - 1.75 mV
OCP Reference Current IOCP EN = 5.0V 9.0 10 11 µA
OCSET Input Resistance ROCSET EN = 5.0V - 600 - kΩ
OCSET Leakage Current IOCSET EN = GND - 0 - µA
UVP Threshold Voltage VUVTH VFB = %VSREF 81 84 87 %
Electrical Specifications These specifications apply for TA = -10°C to +100°C, unless otherwise stated.
All typical specifications TA = +25°C, VCC = 5V. Parameters with MIN and/or MAX limits are 100% tested at
+25°C, unless otherwise specified. Temperature limits established by characterization and are not production
tested. (Continued)
PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT
ISL62871, ISL62872
9FN6707.0
August 14, 2008
ISL62872 Functional Pin Descriptions
LGATE (Pin 1)
Low-side MOSFET gate driver output. Connect to the gate
terminal of the low-side MOSFET of the converter.
PGND (Pin 2)
Return current path for the LGATE MOSFET driver. Connect
to the source of the low-side MOSFET.
GND (Pin 3)
IC ground for bias supply and signal reference.
EN (Pin 4)
Enable input for the IC. Pulling EN above the VENTHR rising
threshold voltage initializes the soft-start sequence.
VID1 (Pin 5)
Logic input for setpoint voltage selector. Use in conjunction
with the VID0 pin to select among four setpoint reference
voltages.
VID0 (Pin 6)
Logic input for setpoint voltage selector. Use in conjunction
with the VID1 pin to select among four setpoint reference
voltages. External reference input when enabled by
connecting the SET0 pin to the VCC pin.
SREF (Pin 7)
Soft-start and voltage slew-ra te programming capacitor
input. Setpoint reference voltage programming resistor input.
Connects internally to the inverting input of the VSET voltage
setpoint amplifier. See Figure 8 page 12 for capacitor and
resistor connections.
SET0 (Pin 8)
Voltage set-point programming resistor input. See Figure 8
on page 12 for resistor connection.
SET1 (Pin 9)
Voltage set-point programming resistor input. See Figure 8
on page 12 for resistor connection.
SET2 (Pin 10)
Voltage set-point programming resistor input. See Figure 8
on page 12 for resistor connection.
PGOOD (Pin 11)
Power-good open-drain indicator output. This pin changes to
high impedance when the co nverter is able to supply
regulated voltage. The pull-down resistance between the
PGOOD pin and the GND pin identifies which protective fault
has shut down the regulator. See Table 3 on page 16.
FB (Pin 12)
Voltage feedback sense input. Connects internally to the
inverting input of th e control-loop error amplifier. The
converter is in regulation when the voltage at the FB pin
equals the voltage on the SREF pin. The control loop
compensation network connects between the FB pin and the
converter output. See Figure 13 on page 17.
VO (Pin 13)
Output voltage sense input for the R3 modulator . The VO pin
also serves as the reference input for the overcurrent
detection circuit. See Figure 10 on page 14.
OCSET (Pin 14)
Input for the overcurrent detection circuit. The overcurrent
setpoint programming resistor ROCSET conn ects from this
pin to the sense node. See Figure 10 on page 14.
NC (Pin 15)
No internal connection. Pin 15 should be connected to the
GND pin.
PHASE (Pin 16)
Return current path for the UGATE high-side MOSFET
driver . VIN sense input for the R3 modulator . Inductor current
polarity detector input. Connect to junction of output inductor ,
high-side MOSFET, and low-side MOSFET. See Figures 2
and 3 on page 4.
UGATE (Pin 17)
High-side MOSFET gate driver output. Connect to the gate
terminal of the high-side MOSFET of the converter.
OVP Rising Threshold Voltage VOVRTH VFB = %VSREF 113 116 120 %
OVP Falling Threshold Voltage VOVFTH VFB = %VSREF 100 102 106 %
OTP Rising Threshold Temperature
(Note 2) TOTRTH -150- °C
OTP Hysteresis (Note 2) TOTHYS -25-°C
NOTE:
2. Limits established by characterization and are not production tested.
Electrical Specifications These specifications apply for TA = -10°C to +100°C, unless otherwise stated.
All typical specifications TA = +25°C, VCC = 5V. Parameters with MIN and/or MAX limits are 100% tested at
+25°C, unless otherwise specified. Temperature limits established by characterization and are not production
tested. (Continued)
PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT
ISL62871, ISL62872
10 FN6707.0
August 14, 2008
BOOT (Pin 18)
Positive input supply for the UGA TE high-side MOSFET gate
driver. The BOOT pin is internally connected to the cathode
of the Schottky boot-strap diode. Connect an MLCC
between the BOOT pin and the PHASE pin.
VCC (Pin 19)
Input for the IC bias voltage. Connect +5V to the VCC pin
and decouple with at least a 1µF MLCC to the GND pin. See
“Application Schematics” (Figures 2 and 3) on page 4.
PVCC (Pin 20)
Input for the LGATE and UGATE MOSFET driver circuits.
The PVCC pin is internally conne cted to the anode of the
Schottky boot-strap diode. Connect +5V to the PVCC pin
and decouple with a 10µF MLCC to the PGND pin. See
“Application Schematics” (Figures 2 and 3) on page 4.
ISL62871 Functional Pin Descriptions
GND (Pin 1)
IC ground for bias supply and signal reference.
EN (Pin 2)
Enable input for the IC. Pulling EN above the VENTHR rising
threshold voltage initializes the soft-start sequence.
VID0 (Pin 3)
Logic input for setpoint voltage selector. Use to select
between the two setpoint reference voltages. Exte rnal
reference input when enabled by connecting the SET0 pin to
the VCC pin.
SREF (Pin 4)
Soft-start and voltage slew-ra te programming capacitor
input. Setpoint reference voltage programming resistor input.
Connects internally to the inverting input of the VSET voltage
setpoint amplifier . See Figure 9 on page 12 for capacitor and
resistor connections.
SET0 (Pin 5)
Voltage set-point programming resistor input. See Figure 9
on page 12 for resistor connection.
PGOOD (Pin 6)
Power-good open-drain indicator output. This pin changes to
high impedance when the converter is able to supply
regulated voltage. The pull-down resistance between the
PGOOD pin and the GND pin identifies which protective fault
has shut down the regulator. See Table 3 on page 16.
FB (Pin 7)
Voltage feedback sense input. Connects internally to the
inverting input of the control-loop error amplifier. The
converter is in regulation when the voltage at the FB pin
equals the voltage on the SREF pin. The control loop
compensation network connects between the FB pin and the
converter output. See Figure 13 on page 17.
VO (Pin 8)
Output voltage sense input for the R3 modulator . The VO pin
also serves as the reference input for the overcurrent
detection circuit. See Figure 10 on page 14.
OCSET (Pin 9)
Input for the overcurrent detection circuit. The overcurrent
setpoint programming resistor ROCSET conn ects from this
pin to the sense node. See Figure 10 on page 14.
PHASE (Pin 10)
Return current path for the UGATE high-side MOSFET
driver . VIN sense input for the R3 modulator . Inductor current
polarity detector input. Connect to junction of output inductor ,
high-side MOSFET, and low-side MOSFET. See “Application
Schematics” (Figures 4 and 5) on page 5.
UGATE (Pin 11)
High-side MOSFET gate driver output. Connect to the gate
terminal of the high-side MOSFET of the converter.
BOOT (Pin 12)
Positive input supply for the UGA TE high-side MOSFET gate
driver. The BOOT pin is internally connected to the cathode
of the Schottky boot-strap diode. Connect an MLCC
between the BOOT pin and the PHASE pin.
VCC (Pin 13)
Input for the IC bias voltage. Connect +5V to the VCC pin
and decouple with at least a 1µF MLCC to the GND pin. See
“Application Schematics” (Figures 4 and 5) on page 5.
PVCC (Pin 14)
Input for the LGATE and UGATE MOSFET driver circuits.
The PVCC pin is internally connected to the anode of the
Schottky boot-strap diode. Connect +5V to the PVCC pin
and decouple with a 10µF MLCC to the PGND pin. See
“Application Schematics” (Figures 4 and 5) on page 5.
LGATE (Pin 15)
Low-side MOSFET gate driver output. Connect to the gate
terminal of the low-side MOSFET of the converter.
PGND (Pin 16)
Return current path for the LGATE MOSFET driver. Connect
to the source of the low-side MOSFET.
Setpoint Reference Voltage Programming
Voltage identification (VID) pins select user-programmed
setpoint reference voltages that appear at the SREF pin. The
converter is in regulation when the FB pin voltage (VFB)
equals the SREF pin voltage (VSREF.) The IC measures VFB
and VSREF relative to the GND pin, not the PGND pin. The
setpoint reference voltages use the naming convention
ISL62871, ISL62872
11 FN6707.0
August 14, 2008
VSET(x) where (x) is the first, second, third, or fourth setpoint
reference voltage where:
-V
SET1 < VSET2 < VSET3 < VSET4
-V
OUT1 < VOUT2 < VOUT3 < VOUT4
The VSET1 setpoint is fixed at 500mV because it
corresponds to the closure of internal switch SW0 that
configures the VSET amplifier as a unity-gain voltage
follower for the 500mV voltage reference VREF.
A feedback voltage-divider network may be required to
achieve the desired reference voltages. Using the feedback
voltage-divider allows the maximum output voltage of the
converter to be higher than the 1.5V maximu m setpoint
reference voltage that can be programmed on the SREF pin.
Likewise, the feedback voltage-divider allows the minimum
output voltage of the converter to be higher than the fixed
500mV setpoint reference voltage of VSET1. Scale the
voltage-divider network such that the voltage VFB equals the
voltage VSREF when the converter output voltage is at the
desired level. The voltage-divider relation is given in
Equation 1:
Where:
-V
FB = VSREF
-R
FB is the loop-compensatio n feedback resistor that
connects from the FB pin to the converter output
-R
OFS is the voltage-scaling programming resistor that
connects from the FB pin to the GND pin
The attenuation of the feedback voltage divider is written as:
Where:
-K is the attenuation factor
-V
SREF(lim) is the VSREF voltage setpoint of either
500mV or 1.50V
-V
OUT(lim) is the output voltage of the converter when
VSREF = VSREF(lim)
Since the voltage-divider network is in the feedback path, all
output voltage setpoints will be attenuated by K, so it follows
that all of the setpoint reference voltages will be attenuated
by K. It will be necessary then to include the attenuation
factor K in all the calculations for selecting the RSET
programming resistors.
The value of offset resistor ROFS can be calculated only
after the value of loop-compensation resistor RFB has been
determined. The Calculation of ROFS is written as
Equation 3:
The setpoint reference voltages are programmed with
resistors that use the naming convention RSET(x) where (x)
is the first, second, third, or fourth programming resistor
connected in series starting at the SREF pin and ending at
the GND pin. When one of the internal switches closes, it
connects the inverting input of the VSET amplifier to a
specific node among the string of RSET programming
resistors. All the resistors between that node and the SREF
pin serve as the feedback impedance RF of the VSET
amplifier. Likewise, all the resistors between that node and
the GND pin serve as the input impedance RIN of the VSET
amplifier. Equation 4 gives the general form of the gain
equation for the VSET amplifier:
Where:
-V
REF is the 500mV internal reference of the IC
-V
SET(x) is the resulting setpoint refere nce voltage that
appears at the SREF pin
Calculating Setpoint Voltage Programming
Resistor Values for ISL62872
First, determine the attenuation facto r K. Next, assign an
initial value to RSET4 of approximately 100kΩ then calculate
RSET1, RSET2, and RSET3 using Equations 5, 6, and 7
respectively. The equation for the value of RSET1 is written
as Equation 5:
The equation for the value of RSET2 is written as Equation 6:
The equation for the value of RSET3 is written as Equation 7:
The sum of all the programming resistors should be
approximately 300kΩ as shown in Equati on 8 otherwise
adjust the value of RSET4 and repeat the calculations.
Equations 9, 10, 11 and 12 give the specific VSET gain
equations for the ISL62872 setpoint re ference voltages.
VFB VOUT ROFS
RFB ROFS
+
----------------------------------
⋅=(EQ. 1)
KVSREF lim()
VOUT lim()
------------------------------- ROFS
RFB ROFS
+
----------------------------------
== (EQ. 2)
ROFS VSET x() R⋅FB
VOUT VSET x()
–
--------------------------------------------
=(EQ. 3)
TABLE 1. ISL62872 VID TRUTH TABLE
VID STATE RESULT
VID1 VID0 CLOSE VSREF VOUT
11SW0V
SET1 VOUT1
10SW1V
SET2 VOUT2
01SW2V
SET3 VOUT3
00SW3V
SET4 VOUT4
VSET X)( VREF 1RF
RIN
----------
+
⎝⎠
⎜⎟
⎛⎞
⋅=(EQ. 4)
RSET1 RSET4 KVSET4 KVSET2 VREF
–()⋅⋅
VREF KVSET2
⋅
----------------------------------------------------------------------------------------------------
=(EQ. 5)
RSET2 RSET4 KVSET4 KVSET3 KVSET2
–()⋅⋅
KVSET2 KVSET3
⋅
-----------------------------------------------------------------------------------------------------------
=(EQ. 6)
RSET3 RSET4 KVSET4 KVSET3
–()⋅
KVSET3
--------------------------------------------------------------------------------
=(EQ. 7)
RSET1 RSET2 RSET3 RSET4
+++ 300kΩ≅ (EQ. 8)
ISL62871, ISL62872
12 FN6707.0
August 14, 2008
The ISL62872 VSET1 setpoint is written as Equation 9:
The ISL62872 VSET2 setpoint is written as Equation 10:
The ISL62872 VSET3 setpoint is written as Equation 11:
The ISL62872 VSET4 setpoint is written as Equation 12:
Component Selection for ISL62871 Setpoint
Voltage Prog rammin g Resi sto rs
First, determine the attenuation factor K. Next, assign an
initial value to RSET2 of approximately 150kΩ then calculate
RSET1 using Equat i o n 13.
The equation for the value of RSET1 is written as
Equation 13:
The sum of RSET1 and RSET2 programming resistors should
be approximately 300kΩ as shown in Equation 14 otherwise
adjust the value of RSET2 and repeat the calculations.
Equations 15 and 16 give the specific VSET gain equati ons
for the ISL62871 setpoint reference voltages.
The ISL62871 VSET1 setpoint is written as Equation 15:
The ISL62871 VSET2 setpoint is written as Equation 16:
TABLE 2. ISL62 871 VID TRUTH TABLE
STATE RESULT
VID0 CLOSE VSREF VOUT
1SW0V
SET1 VOUT1
0SW1V
SET2 VOUT2
VSET1 VREF
=(EQ. 9)
VSET2 VREF 1RSET1
RSET2 RSET3 RSET4
++
---------------------------------------------------------------------
+
⎝⎠
⎜⎟
⎛⎞
⋅=(EQ. 10)
VSET3 VREF 1RSET1 RSET2
+
RSET3 RSET4
+
--------------------------------------------
+
⎝⎠
⎜⎟
⎛⎞
⋅=(EQ. 11)
VSET4 VREF 1RSET1 RSET2 R+SET3
+
RSET4
---------------------------------------------------------------------
+
⎝⎠
⎜⎟
⎛⎞
⋅=(EQ. 12)
FIGURE 8. ISL62872 VOLTAGE PROGRAMMING CIRCUIT
SET2
SET0
SREF
VSET
+
−
SW0
VREF
SET1
SW1
SW2
SW3
CSOFT
RSET1
RSET2
RSET3
RSET4
EA
+
−
FB
ROFS
RFB
VOUT
VCOMP
500mV
RSET1 RSET2 KVSET2
VREF
-----------------------1–
⎝⎠
⎜⎟
⎛⎞
⋅=(EQ. 13)
RSET1 RSET2
+300kΩ≅ (EQ. 14)
VSET1 VREF
=(EQ. 15)
VSET2 VREF 1RSET1
RSET2
------------------
+
⎝⎠
⎜⎟
⎛⎞
⋅=(EQ. 16)
FIGURE 9. ISL62871 VOLTAGE PROGRAMMING CIRCUIT
SET0
SREF
VSET
+
−
SW0
VREF
SW1
CSOFT
RSET1
RSET2
EA
+
−
FB
ROFS
RFB
VOUT
VCOMP
ISL62871, ISL62872
13 FN6707.0
August 14, 2008
External Setpoint Reference
The IC can use an external setpoint reference voltage as an
alternative to VID-selected, resistor-programmed setpoints.
This is accomplished by removing all setpoint programming
resistors, connecting the SET0 pin to the VCC pin, and
feeding the external setpoint reference voltage to the VID0
pin. When SET0 and VCC are tied together, the followin g
internal reconfigurations take place:
- VID0 pin ope ns its 500nA pull-down current sink
- Reference source selector switch SW4 moves from INT
position (internal 500mV) to EXT positi on (VID0 pin)
- VID1 pin is disabled
The converter will now be in regulation when the voltage on
the FB pin equals the voltage on the VID0 pin. As with
resistor-programmed setpoints, the reference voltage range
on the VID0 pin is 500mV to 1.5V. Use Equations 1, 2, and 3
beginning on page 11 should it become necessary to
implement an output voltage-divider network to make the
external setpoint reference voltage compatible with the
500mV to 1.5V constraint.
Soft-Start and Voltage-Step Delay
Circuit Description
When the voltage on the VCC pin has ramped above the
rising power-on reset voltage VVCC_THR, and the voltage on
the EN pin has increased above the rising enable threshold
voltage VENTHR, the SREF pin releases its discharge clamp
and enables the reference amplifier VSET. The s oft-start
current ISS is limited to 20µA and is sourced out of the SREF
pin into the parallel RC network of capacitor CSOFT and
resistance RT. The resistance RT is the sum of all th e seri es
connected RSET programming resistors and is written as
Equation 17:
The voltage on the SREF pin rises as ISS charges CSOFT to
the voltage reference setpoint selected by the state of the
VID inputs at the time the EN pin is asserted. The regulator
controls the PWM such that the voltage on the FB pin tracks
the rising voltage on the SREF pin. Once CSOFT charges to
the selected setpoint voltage, the ISS current source comes
out of the 20µA current limit and decays to the static value
set by VSREF ÷ RT. The elapsed time from when the EN pin
is asserted to when VSREF has reached the voltage
reference setpoint is the soft-start delay tSS which is given
by Equation 18:
Where:
-I
SS is the soft-start current source at the 20µA limit
-V
START-UP is the setpoint reference voltage selected by
the state of the VID inputs at the time EN is asserted
-R
T is the sum of the RSET programming resistors
The end of soft-start is detected by ISS tapering off when
capacitor CSOFT charges to the designated VSET voltage
reference setpoint. The SSOK flag is set, the PGOOD pin
goes high, and the ISS current source changes over to the
voltage-step current source IVS which has a current limit of
±100µA. Whenever the VID inputs or the external setpoint
reference, programs a different setpoint reference voltage,
the IVS current source charges or discharges capacitor
CSOFT to that new level at ±100µA. Once CSOFT charges to
the selected setpoint voltage, the IVS current source comes
out of the 100µA current limit and decays to the static value
set by VSREF ÷ RT. The elapsed time to charge CSOFT to
the new voltage is called the voltage-step delay tVS and is
given by Equation 19:
Where:
-I
VS is the ±100µA setpoint voltage-step current
-V
NEW is the new setpoint voltage selected by the VID
inputs
-V
OLD is the setpoint voltage that VNEW is changing
from
-R
T is the sum of the RSET programming resistors
Component Selection For CSOFT Capacitor
Choosing the CSOFT capacitor to meet the requirements of a
particular soft-start delay tSS is calculated with Equation 20,
which is written as:
Where:
-t
SS is the soft-start delay
-I
SS is the soft-start current source at the 20µA limit
-V
START-UP is the setpoint reference voltage selected by
the state of the VID inputs at the time EN is asserted
-R
T is the sum of the RSET programming resistors
Choosing the CSOFT capacitor to meet the requirements of a
particular voltage-step delay tVS is calculated with
Equation 21, which is written as:
RTRSET1 RSET2 …RSET n()
++=(EQ. 17)
tSS ISS CSOFT
⋅()–LN 1 VSTART-UP
ISS RT
⋅
------------------------------
–()⋅=(EQ. 18)
tVS IVS CSOFT
⋅()LN 1 VNEW VOLD
–()
IVS RT
⋅
-------------------------------------------
–()⋅=(EQ. 19)
CSOFT tSS
–
RTLN 1 VSTART-UP
ISS RT
⋅
------------------------------
–()⋅
⎝⎠
⎜⎟
⎛⎞
---------------------------------------------------------------------
=(EQ. 20)
CSOFT tVS
–
RTLN 1 VNEW VOLD
–
I±VS RT
⋅
---------------------------------------
–()⋅
⎝⎠
⎜⎟
⎛⎞
------------------------------------------------------------------------------
=(EQ. 21)
ISL62871, ISL62872
14 FN6707.0
August 14, 2008
Where:
-t
VS is the voltage-step delay
-V
NEW is the new setpoint voltage
-V
OLD is the setpoint voltage that VNEW is changing
from
-I
VS is the ±100µA setpoint voltage-step current; positive
when VNEW > VOLD, negative when VNEW < VOLD
-R
T is the sum of the RSET programming resistors
Fault Protection
Overcurrent
The overcurrent protection (OCP) setpoint is programmed
with resistor ROCSET which is connected across the OCSET
and PHASE pins. Resistor RO is connected between the VO
pin and the actual output voltage of the converter. During
normal operation, the VO pin is a high impedance path,
therefore there is no voltage drop across RO. The value of
resistor RO should always match the value of resistor
ROCSET
Figure 10 shows the overcurrent set circuit. The inductor
consists of inductance L and the DC resistance DCR. The
inductor DC curre nt IL creates a voltage drop across DCR,
which is given by Equation 22:
The IOCSET current source sinks 10µA into the OCSET pin,
creating a DC voltage drop across the resistor ROCSET,
which is given by Equation 23:
The DC voltage difference between the OCSET pin and the
VO pin, which is given by Equation 24:
The IC monitors the voltage of the OCSET pin and the VO
pin. When the voltage of the OCSET pin is higher than the
voltage of the VO pin for more than 10µs, an OCP fault
latches the converter off.
Component Selection For ROCSET and CSEN
The value of ROCSET is calculated with Equation 25, which
is written as:
Where:
-R
OCSET (Ω) is the resistor used to program the
overcurrent setpoint
-I
OC is the output DC load current that will activate the
OCP fault detection circuit
- DCR is the inducto r DC resistance
For example, if IOC is 20A and DCR is 4.5mΩ, the choice of
ROCSET is = 20A x 4.5mΩ/10µA = 9kΩ.
Resistor ROCSET and capacitor CSEN form an R-C network
to sense the inductor current. To sense the inducto r curren t
correctly not only in DC operation, but also during dynamic
operation, the R-C network time constant ROCSET CSEN
needs to match the inductor time constant L/DCR. The value
of CSEN is then written as Equation 26:
For example, if L is 1.5µH, DCR is 4.5mΩ, and ROCSET is
9kΩ, the choice of CSEN = 1.5µH/(9kΩ x 4.5mΩ) = 0.037µF.
When an OCP fault is declared, the PGOOD pin will
pull-down to 35Ω and latch off the converter. The fault will
remain latched until the EN pin has been pulled below the
falling EN threshold voltage VENTHF or if VCC has decayed
below the falling POR threshold voltage VVCC_THF.
Overvoltage
The OVP fault detection circuit triggers after the FB pin
voltage is above the rising overvoltage threshold VOVRTH for
more than 2µs. For example, if the converter is programmed
to regulate 1.0V at the FB pin , that voltage would have to
rise above the typical VOVRTH thr esh old of 116% for more
than 2µs in order to trip the OVP fault latch. In numerical terms,
that would be 116% x 1.0V = 1.16V. W hen an OVP fault is
declared, the PGOOD pin will pull-down to 65Ω and latch-off
the converter. The OVP fault will remain latched until VCC
has decayed below the falling POR threshold voltage
VVCC_THF. An OVP fault cannot be reset by pul ling the EN
pin below the falling EN threshold voltage VENTHF.
Although the converter has latched-off in response to an
OVP fault, the LGATE gate-driver output will retain the ability
to toggle the low-side MOSFET on and off, in response to
the output voltage transversing the VOVRTH and VOVFTH
thresholds. The LGATE gate-driver will turn-on the low-side
MOSFET to discharg e th e ou t put voltage, protecting the
load. The LGATE gate-driver will turn-off the low-side
MOSFET once the FB pin voltage is lower than the falling
overvoltage threshold VOVRTH for more than 2µs. The
falling overvoltage threshold VOVFTH is typically 102%. That
FIGURE 10. OVERCURRENT PROGRAMMING CIRCUIT
PHASE
CO
L
VO
ROCSET CSEN
OCSET
VO
RO
DCR IL
10µ
+_
VDCR
+_
VROCSET
VDCR ILDCR⋅=(EQ. 22)
VROCSET 10μAR
OCSET
⋅=(EQ. 23)
VOCSET V–VO VDCR V–ROCSET ILDCR⋅IOCSET ROCSET
⋅–==
(EQ. 24)
(EQ. 25)
ROCSET IOC DCR⋅
IOCSET
----------------------------
=
(EQ. 26)
CSEN L
ROCSET DCR⋅
------------------------------------------
=
ISL62871, ISL62872
15 FN6707.0
August 14, 2008
means if the FB pin voltage fa lls below 102% x 1.0V = 1.02V
for more than 2µs, the LGATE gate-driver will turn off the
low-side MOSFET. If the output voltage rises again, the
LGATE driver will again turn on the low -side MOSFET when
the FB pin voltage is above the risi ng overvoltage threshold
VOVRTH for more than 2µs. By doing so, the IC protects the
load when there is a consistent overvol t age condi tion.
Undervoltage
The UVP fault detection circuit triggers after the FB pin
voltage is below the undervoltage threshold VUVTH for more
than 2µs. For example if the converter is programmed to
regulate 1.0V at the FB pin, that voltage would have to fall
below the typical VUVTH threshold of 84% for more than 2µs
in order to trip the UVP fault latch. In numerical terms, that
would be 84% x 1.0V = 0.84V. W hen a UVP fault is dec lared,
the PGOOD pin will pull-down to 95Ω and latch-off the
converter. The fault will remain latched until the EN pin has
been pulled below the falling EN threshold voltage VENTHF
or if VCC has decayed below the falling POR threshold
voltage VVCC_THF.
Over-Temperature
When the temperature of the IC increases above the rising
threshold temperature TOTRTH, it will enter the OTP state
that suspends the PWM, forcing the LGATE and UGATE
gate-driver outputs low. The status of the PGOOD pin does
not change nor does the converter latch-o ff. The PWM
remains suspended until the IC temperature falls below the
hysteresis temperature TOTHYS at which time normal PWM
operation resumes. The OTP state can be reset if the EN pin
is pulled below the falling EN threshold voltage VENTHF or if
VCC has decayed below the falling POR threshold voltage
VVCC_THF. All other protection circuits remain functional
while the IC is in the OTP state. It is likely that the IC will
detect an UVP fault because in the absence of PWM, the
output voltage decays below the undervoltage threshold
VUVTH.
Theory of Operation
The modulator features Intersil’s R3 Robust-Ripple-
Regulator technology, a hybrid of fixed frequency PWM
control and variable frequency hysteretic co ntrol. The PWM
frequency is maintained at 300KHz under static
continuous-conduction-mode opera tion within the entire
specified envelope of input voltage, output voltage, and
output load. If the application should experience a rising load
transient and/or a falling li ne transient such that the output
voltage starts to fall, the modulator will exten d the on-time
and/or reduce the off-time of the PWM pulse in progress.
Conversely, if the application should experience a falling
load transient and/or a rising line transient such that the
output voltage starts to rise, the modulator will truncate the
on-time and/or extend the off-time of the PWM pulse in
progress. The period and du ty cycle of the ensuing PWM
pulses are optimized by the R3 modulator for the remainder
of the transient and work in concert with the error amplifier
VERR to maintain output voltage regulation. Once the
transient has dissipated and the control loop has recovered,
the PWM frequency returns to the nominal static 300KHz.
Modulator
The R3 modulator synthesizes an AC signal VR, which is an
analog representation of the output inductor ripple current.
The duty-cycle of VR is the result of charge and discharge
current through a ripple capacitor CR. The current through
CR is provided by a transconductance amplifier gm that
measures the input voltage (VIN) at the PHASE pi n and
output voltage (VOUT) at the VO pin. The positive slope of
VR can be written as Equation 27:
The negative slope of V R can be written as Equatio n 28:
Where, gm is the gain of the transconductance amplifier.
A window voltage VW is referenced with respect to the error
amplifier output voltage VCOMP, creating an envelope into
which the ripp l e vo ltage VR is compared. The amplitude of
VW is controlled internally by the IC. The VR, VCOMP, and
VW signals feed into a window comparator in which VCOMP
is the lower threshold voltage and VW is the higher threshold
voltage. Figure 11 shows PWM pulses being generated as
VR traverses the VW and VCOMP thresholds. The PWM
switching frequency is proporti onal to the slew rates of the
positive and negative slopes of VR; it is inversely
proportional to the voltage between VW and VCOMP.
Synchronous Rectification
A standard DC/DC buck regulator uses a free-wheeling
diode to maintain uninterrupted current conduction through
the output inductor when the high-side MOSFET switches off
for the balance of the PWM switching cycle. Low conversion
efficiency as a result of the conduction loss of the diode
VRPOS gm
()VIN VOUT
–()CR
⁄⋅=(EQ. 27)
VRNEG gmVOUT CR
⁄⋅=(EQ. 28)
FIGURE 1 1. MODULA T OR W A VEFORMS DURING LOAD
TRANSIENT
PWM
RIPPLE CAPACITOR VOLTAGE CRWINDOW VOLTAGE V
W
ERROR AMPLIFIER VOLTAGE VCOMP
ISL62871, ISL62872
16 FN6707.0
August 14, 2008
makes this an unattractive option for all but the lowest
current applications. Efficiency is dramatically improved
when the free-wheeling diode is replaced with a MOSFET
that is turned on whenever the high-side MOSF ET is turned
off. This modification to the standard DC/DC buck regulator
is referred to as synchronous rectification, th e topology
implemented by the ISL62871 and ISL628 72 controllers.
Diode Emulation
The polarity of the output inductor current is define d as
positive when conducting away from the phase node, and
defined as negative when conducting towards the phase
node. The DC component of the inductor current is positive,
but the AC component known as the ripple current, can be
either positive or negative. Should the sum of th e AC and
DC components of the inductor current remain positive for
the entire switching period, the conver ter is in
continuous-conduction-mode (CCM.) However, if the
inductor current becomes negative or zero, the converter is
in discontinuous-conducti on-mode (DCM.)
Unlike the standard DC/DC buck regulator , the synchronous
rectifier can sink current from the output filter inductor during
DCM, reducing the light-load efficiency with unnecessary
conduction loss as the low-side MOSFET sinks the inductor
current. The ISL62871 and ISL62872 controllers avoid the
DCM conduction loss by making the low-sid e MOSFET
emulate the current-blocking behavior of a diode. This
smart-diode operation called diode-emulation-mode (DEM)
is triggered when the negative inducto r current prod uces a
positive voltage drop across the rDS(ON) of the low-side
MOSFET for eight consecutive PWM cycles while the
LGATE pin is high. The converter will exit DEM on the next
PWM pulse after detecting a negative voltage across the
rDS(ON) of the low-side MOSFET.
It is characteristic of the R3 architecture for the PWM
switching frequency to decrease while in DCM, increasing
efficiency by reducing unnecessary gate-driver switching
losses. The extent of the frequency reduction is proportional
to the reduction of load current. Upon entering DEM, the
PWM frequency is forced to fall approximatel y 30% by
forcing a similar increase of the window voltage VW. This
measure is taken to prevent oscillating between modes at
the boundary between CCM and DCM. The 30% increase of
VW is removed upon exit of DEM, forcing the PWM switching
frequency to jump back to the nominal CCM value.
Power-On Reset
The IC is disabled until th e voltage at the VCC pin has
increased above the rising power-on reset (POR) threshold
voltage VVCC_THR. The controller will become disabled
when the vo ltage at the VCC pin decreases below the falling
POR threshold voltage VVCC_THF. The POR detector has a
noise filter of approximately 1µs.
VIN and PVCC Voltage Sequence
Prior to pulling EN above the VENTHR rising threshold
voltage, the following criteria must be met:
-V
PVCC is at least equivalent to the VCC rising power-on
reset voltage VVCC_THR
-V
VIN must be 3.3V or the minimum required by the
application
Start-Up Timing
Once VCC has ramped above VVCC_THR, the controller can
be enabled by pulling the EN pin voltage above the
input-high threshold VENTHR. Approximately 20µs later, the
voltage at the SREF pin begins slewing to the designated
VID set-point. The converter output voltage at the FB
feedback pin follows the voltage at the SREF pin. During
soft-start, The regula to r always operates in CCM until the
soft-start sequence is complete.
PGOOD Monitor
The PGOOD pin indicates when the converter is ca pable of
supplying regulated voltage. The PGOOD pin is an
undefined impedance if the VCC pin has not reached the
rising POR threshold VVCC_THR, or if the VCC pin is below
the falling POR threshold VVCC_THF. The PGOOD
pull-down resistance corresponds to a specific protective
fault, thereby reducing troubleshootin g time and effort.
Table 3 maps the pull-down resistance of the PGOOD pin to
the corresponding fault status of the controller.
LGATE and UGATE MOSFET Gate-Drivers
The LGATE pin and UGATE pins are MOSFET driver
outputs. The LGATE pin drives the low-side MOSFET of the
converter while the UGATE pin drives the high-side
MOSFET of the converter.
The LGATE driver is optimized for low duty-cycle
applications where the low-si de MOSFET experiences long
conduction times. In this environment, the low-side
MOSFETs req uire exceptionally low rDS(ON) and tend to
have large parasitic charges that conduct transient currents
within the devices in response to high dv/dt switching
present at the phase node. The drain-gate charge in
particular can conduct sufficient current through the driver
pull-down resistance that the VGS(th) of the device can be
exceeded and turned on . For this reason the LGATE driver
has been designed with low pull-down resistance and high
sink current capability to ensure clamping the MOSFETs
gate voltage below VGS(th).
TABLE 3. PGOOD PULL-DOWN RESISTANCE
CONDITION PGOOD RESISTANCE
VCC Below POR Undefined
Soft-Start or Undervoltage 95Ω
Overvoltage 65Ω
Overcurrent 35Ω
ISL62871, ISL62872
17 FN6707.0
August 14, 2008
Adaptive Shoot-Through Protection
Adaptive shoot-through protection prevents a gate-driver
output from turning on until the opposite gate-driver output
has fallen below approximately 1V. The dead-time shown in
Figure 12 is extended by the additional period that the falling
gate voltage remains above the 1V threshold. The high-side
gate-driver output voltage is me asured across the UGATE
and PHASE pins while the low-side gate-driver output
voltage is measured across the LGA TE and PGND pins. The
power for the LGATE gate-driver is sourced directly from the
PVCC pin. The power for the UGATE gate-driver is supplied
by a boot-strap capacitor connected across the BOOT and
PHASE pins. The capacitor is charged each time the phase
node voltage falls a diode drop belo w PVCC such as when
the low-side MOSFET is turned on.
Compensation Design
Figure 13 shows the recommended T ype-II compensation
circuit. The FB pin is the inverting input of the error amplifier.
The COMP signal, the output of the error amplifier , is inside the
chip and unavailable to users. CINT is a 100pF capacitor
integrat ed inside th e IC, connec ting across the FB pi n and the
COMP signal. RFB, RCOMP, CCOMP and CINT form the T ype-II
compensator. The frequency domain transfer function is given
by Equation 29:
The LC output filter has a double pole at its resonant frequency
that causes rapid phase change. The R3 modulator used in the
IC makes the LC output filter resemble a first order system in
which the closed loop stability can be achieved with the
recommended T ype-II compensation network. Intersil provides
a PC-based tool that can be used to calculate compensation
network component value s and help simulate the loop
frequency response.
General Application Design Guide
This design guide is intended to provide a high-level
explanation of the steps necessary to desi gn a single-p hase
power converter. It is assumed that the reader is familiar with
many of the basic skills and techniques referen ced in the
following. In addition to this guide, Intersil provides complete
reference designs that include schematics, bills of materials,
and example board layou t s.
Selecting the LC Output Filter
The duty cycle of an ideal buck converter is a function of the
input and the output voltage. This relationship is expressed
in Equation 30:
The output inductor peak-to-peak ripple current is expressed
in Equation 31:
A typical step-down DC/DC converter will have an IPP of
20% to 40% of the maximum DC output load current. The
value of IP-P is selected based upon several criteria such as
MOSFET switching loss, inductor core loss, and the resistive
loss of the inductor winding . The DC copper loss of the
inductor can be estimated using Equation 32:
Where, ILOAD is the converter output DC current.
The copper loss can be significant so attention has to be
given to the DCR selection. Another factor to consider when
choosing the inductor is its saturation chara c teristics at
elevated temperature. A saturated inductor could cause
FIGURE 12. GATE DRIVER ADAPTIVE SHOOT-THROUGH
1V
1V
UGATE
LGATE
1V
1V
(EQ. 29)
GCOMP s() 1sR
FB RCOMP
+()C⋅COMP
⋅+
sR
FB CINT 1sR
COMP C⋅COMP
⋅+()⋅⋅ ⋅
---------------------------------------------------------------------------------------------------------------
=
ROFS
EA
+
FB
CINT = 100pF
-
SREF
VOUT
FIGURE 13. COMPENSATION REFERENCE CIRCUIT
RFB
RCOMP CCOMP
COMP
DVO
VIN
---------
=(EQ. 30)
(EQ. 31)
IP-P VO1D–()⋅
FSW L⋅
-------------------------------
=
(EQ. 32)
PCOPPER ILOAD2DCR⋅=
ISL62871, ISL62872
18 FN6707.0
August 14, 2008
destruction of circuit components, as well as nuisance OCP
faults.
A DC/DC buck regulator must have output capacitance CO
into which ripple current IP-P can flow . Current I P-P develops
a corresponding ripple voltage VP-P across CO, which is the
sum of the voltage drop across the capacitor ESR and of the
voltage change stemming from charge moved in and out of
the capacitor. These two voltages are expressed in
Equations 33 and 34:
If the output of the converter has to support a load with high
pulsating current, several ca pacitors will need to be p aralleled
to reduce the total ESR until th e req uired VP- P is ach ieved.
The inductance of the cap acitor can cau se a brief volt age dip
if the load transient has an extremely high slew rate. Low
inductance cap acitors shoul d be considered. A ca p acitor
dissipates he at as a function of RMS current and freq uency.
Be sure that IP-P is share d by a sufficient quantity of paralleled
capacitors so that they operate below the maximum rated
RMS current at FSW. Take into account that the rated value of
a capacitor can fade as much as 50 % as the DC volt age
across it increases.
Selection of the Input Capacitor
The important parameters for the bulk input capacitance are
the voltage rating and the RMS current rating. For reliable
operation, select bulk capacitors with voltage and current
ratings above the maximum input voltage and capable of
supplying the RMS current required by the switching circuit.
Their voltage rating should be at least 1.25x greater than the
maximum input voltage, while a voltage rating of 1.5x is a
preferred rating. Figure 14 is a graph of th e inpu t RMS ripple
current, normalized relative to output loa d cu rrent, as a
function of duty cycle that is adjusted for converter efficiency.
The ripple current calculation is written as Equation 35:
Where:
-I
MAX is the maximum continuous ILOAD of the converter
- x is a multiplier (0 to 1) correspondi ng to the inductor
peak-to-peak ripple amplitude expressed as a
percentage of IMAX (0% to 100%)
- D is the duty cycle that is adjusted to take into account
the efficiency of the converter
Duty cycle is written as Equation 36:
In addition to the bulk capacitance, some low ESL ceramic
capacitance is recommended to decouple between the drain
of the high-side MOSFET and the source of the low-side
MOSFET.
Selecting The Bootstrap Capacitor
Adding an external capacitor across the BOOT and PHASE
pins completes the bootstrap circu it. We selected the
bootstrap cap acitor breakdown volt age to be at lea st 10V.
Although the theoretical maximum voltage of the cap acitor is
PVCC-VDIODE (voltage drop across the boot diode), large
excursions below ground by the phase node requires we
select a capacitor with at least a bre akdown rating of 10V. The
bootstrap cap acitor can be ch osen from Equatio n 37:
Where:
-Q
GATE is the amount of gate charge required to fully
charge the gate of the upper MOSFET
-ΔVBOOT is the maximum decay across the BOOT
capacitor
As an example, suppose an upper MOSFET has a gate
charge, QGATE, of 25nC at 5V and also assume the droop in
the drive voltage over a PWM cycle is 200mV. One will find that
a bootstrap capacit ance of at least 0.125µF is required. The
next larger standard value capacitance is 0.15µF. A good
quality ceramic capacitor such as X7R or X5R is
recommended.
ΔVESR IP-P E⋅SR=(EQ. 33)
ΔΔVCIP-P
8C
OF⋅SW
⋅
---------------------------------
=(EQ. 34)
(EQ. 35)
IIN_RMS
IMAX2DD
2
–()⋅()xI
MAX2D
12
------
⋅⋅
⎝⎠
⎛⎞
+
IMAX
-----------------------------------------------------------------------------------------------------
=
(EQ. 36)
DVO
VIN EFF⋅
--------------------------
=
FIGURE 14. NORMALIZED RMS INPUT CURRENT FOR x = 0.8
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
0
0.05
0.10
0.15
0.20
0.25
0.30
0.35
0.40
0.45
0.50
0.55
0.60
NORMALIZED INPUT RMS RIPPLE CURRENT
DUTY CYCLE
x = 1
x = 0.75
x = 0.50
x = 0.25
x = 0
CBOOT QGATE
ΔVBOOT
------------------------
≥(EQ. 37)
ISL62871, ISL62872
19 FN6707.0
August 14, 2008
.
Driver Power Dissipation
Switching power dissipation in the driver is mainly a function
of the switching frequency and total gate charge of the
selected MOSFETs. Calculating the power dissipation in the
driver for a desired application is critical to ensuring safe
operation. Exceeding the maximum allowable power
dissipation level will push the IC beyond the maximum
recommended operating junction temperature of +125°C.
When designing the application, it is recommended that the
following calculation be performed to ensure safe operati on
at the desired frequency for the selected MOSFETs. The
power dissipated by the drivers is approximated as
Equation 38:
Where:
-F
sw is the switching frequency of the PWM signal
-V
U is the upper gate driver bias supply voltage
-V
L is the lower gate driver bias supply voltage
-Q
U is the charge to be delivered by the upper driver into
the gate of the MOSFET and discrete capacitors
-Q
L is the charge to be delivered by the lower driver into
the gate of the MOSFET and discrete capacitors
-P
L is the quiescent power consumption of the lower
driver
-P
U is the quiescent power consumption of the upper
driver
MOSFET Selection and Considera tions
Typically, a MOSFET cannot tolerate even brief excursions
beyond their maximum drain to source voltage rating. The
MOSFETs used in the power stage of the converter should
have a maximum VDS rating that exceeds the sum of the
upper voltage tolerance of the input power source and the
voltage spike that occurs when the MOSFET switches off.
There are several power MOSFETs readily available that are
optimized for DC/DC converter applications. The preferred
high-side MOSFET emphasizes low switch charge so that
the device spends the least amount of time dissipating
power in the linear region. Unlike the low-side MOSFET
which has the drain-source voltage clamped by its body
diode during turn-off, the high-side MOSFET turns off with
VIN-VOUT, plu s t he s pi ke , acro ss it . Th e preferred low-side
MOSFET emphasizes low rDS(ON) when fully saturated to
minimize conduction loss.
For the low-side MOSFET, (LS), the power loss can be
assumed to be conductive only and is written as
Equation 39:
For the high-side MOSFET, (HS), its conduction loss is
written as Equation 40:
For the high-side MOSFET, its switching loss is written as
Equation 41:
FIGURE 15. BOOT CAPACITANCE vs BOOT RIPPLE VOLTAGE
20nC
DVBOOT_CAP (V)
CBOOT_CAP (µF
2.0
1.6
1.4
1.0
0.8
0.6
0.4
0.2
0.0 0.30.0 0.1 0.2 0.4 0.5 0.6 0.90.7 0.8 1.0
QGATE = 100nC
1.2
1.8
50nC
PF
sw 1.5VUQUVLQL
+()PLPU
++=(EQ. 38)
FIGURE 16. POWER DISSIPATION vs FREQUENCY
FREQUENCY (Hz)
0
100
200
300
400
500
600
700
800
900
1000
0 200 400 600 800 1k 1.2k 1.4k 1.6k 1.8k 2k
POWER (mW)
QU=50nC
QL=50nC
QU=50nC
QL=100nC
QU=100nC
QL=200nC
QU=20nC
QL=50nC
(EQ. 39)
PCON_LS ILOAD2r⋅DS ON()_LS 1D–()⋅≈
(EQ. 40)
PCON_HS ILOAD2r⋅DS ON()_HS D⋅=
(EQ. 41)
PSW_HS VIN IVALLEY tON F⋅SW
⋅⋅
2
----------------------------------------------------------------------VIN IPEAK tOFF F⋅SW
⋅⋅
2
------------------------------------------------------------------
+=
ISL62871, ISL62872
20 FN6707.0
August 14, 2008
Where:
-I
VALLEY is the difference of the DC component of the
inductor current minus 1/2 of the inductor ripple current
-I
PEAK is the sum of the DC component of th e inductor
current plus 1/2 of the inductor ripple current
-t
ON is the time required to drive the device into
saturation
-t
OFF is the time required to drive the device into cut-off
Layout Considerations
The IC, analog signals, and logic signals should all be on the
same side of the PCB, located away from powerful emission
sources. The power conversion components should be
arranged in a manner similar to the example in Figure 17
where the area enclosed by the current circulating through
the input capacitors, high-side MOSFETs, and low-side
MOSFETs is as small as possible and all located on the
same side of the PCB. The power components can be
located on either side of the PCB relative to the IC.
Signal Ground
The GND pin is the signal-common also known as analog
ground of the IC. When laying out the PCB, it is very
important that the connection of the GND pin to the bottom
setpoint-reference programming-resistor, bottom feedback
voltage-divider resistor (if used), and the CSOFT capacitor
be made as close as possible to the GND pin on a conductor
not shared by any other components.
In addition to the critical single point connection discussed in
the previous paragraph, the ground plane layer of the PCB
should have a single-point-connected island located under
the area encompassing the IC, setpoint reference
programming components, feedback voltage divider
components, compensation components, CSOFT capacitor,
and the interconnecting traces among the components and
the IC. The island should be connected using several filled
vias to the rest of the ground plane layer at one point that is
not in the path of either large static curre nts or high di/dt
currents. The single connection point should also be where
the VCC decoupling capacitor and the GND pin of the IC are
connected.
Power Ground
Anywhere not within the analog-ground island is Power
Ground.
VCC and PVCC Pins
Place the decoupling capacitors as close as practical to the
IC. In particular , the PVCC decoupling capacitor should have
a very short and wide connection to the PGND pin. The VCC
decoupling capacitor should not share any vias with the
PVCC decoupling capacitor.
EN, PGOOD, VID0, and VID1 Pins
These are logic signals that are referenced to the GND pin.
Treat as a typical logic signal.
OCSET and VO Pins
The current-sensing network consisting of ROCSET, RO, and
CSEN needs to be connected to the inductor pads for
accurate measurement of the DCR voltage drop. These
components however, should be located physically close to
the OCSET and VO pins with traces leading back to the
inductor. It is critical that the traces are shielded by the
ground plane layer all th e way to the inductor pads. The
procedure is the same for resistive current sense.
FB, SREF, SET0, SET1, and SET2 Pins
The input impedance of these pins is high, making it critical
to place the loop compensation components, setpoint
reference programming resistors, feedback voltage divider
resistors, and CSOFT close to the IC, keeping the length of
the traces short.
LGATE, PGND, UGATE, BOOT, and PHASE Pins
The signals going through these traces are high dv/dt and
high di/dt, with high peak charging and discharging curre nt.
The PGND pin can only flow current from the gate-source
charge of the low-side MOSFETs when LGATE goes low.
Ideally, route the trace from the LGAT E pin in paralle l with
the trace from the PGND pin, route the trace from the
UGATE pin in parallel with the trace from the PHASE pin,
and route the trace from the BOOT pin in parallel with the
trace from the PHASE pin. These pairs of traces should be
short, wide, and away from other traces with high input
impedance; weak signal traces should not be in proximity
with these traces on any layer.
Copper Size for the Phase Node
The parasitic capacitance and parasitic inductance of the
phase node should be kept very low to minimize ringing. It is
best to limit the size of the PHASE node copper in strict
accordance with the current and thermal management of the
application. An MLCC should be connected directly across
the drain of the upper MOSFET and the source of the lower
MOSFET to suppress the turn-off voltage spike.
FIGURE 17. TYPICAL POWER COMPONENT PLACEMENT
VIN
VOUT
PHASE
NODE
GND
OUTPUT
CAPACITORS
LOW-SIDE
MOSFETS
INPUT
CAPACITORS
++
HIGH-SIDE
MOSFETS
ISL62871, ISL62872
21 FN6707.0
August 14, 2008
Typical Performance Curves
FIGURE 18. EFFICIENCY AT VOUT =1.1V FIGURE 19. LOAD REGULATION AT VOUT =1.1V
FIGURE 20. SWITCHING FREQUENCY AT VOUT =1.1V FIGURE 21. START-UP, VIN =12.6V, V
OUT = 1.05V, LOAD = 10A
FIGURE 22. ST ART -UP INT O 750mV PRE-BIASED OUTPUT,
VIN = 12.6V, VOUT = 1.05V, LOAD = 10A FIGURE 23. SHUT -DOWN, VIN = 12.6V , VOUT = 1.05V,
LOAD = 50mΩ
IOUT (A)
EFFICIENCY (%)
0 2 10 12 14 16
60
65
70
75
80
85
90
95
100
VIN = 19V
18 20
50
55
468
VIN = 8V
VIN = 12.6V
-0.6
-0.4
-0.2
0.0
0.2
0.4
0.6
0.8
1.0
-1.0
-0.8
0 2 10 12 14 16 18 204
REGULATION (%)
IOUT (A)
VIN = 8V
VIN = 12.6V
68
VIN = 19V
0 2 10 12 14 16 18 2046
-0.6
-0.4
-0.2
0.0
0.2
0.4
0.6
0.8
1.0
-1.0
-0.8
REGULATION (%)
8IOUT (A)
VIN = 8V
VIN = 12.6V
VIN = 19V
EN
SREF
PGOOD
VOUT
EN
SREF
PGOOD
VOUT
EN
SREF
PGOOD VOUT
20µs
ISL62871, ISL62872
22 FN6707.0
August 14, 2008
FIGURE 24. SHUT-DOWN, VIN =12.6V, V
OUT = 1.05V,
LOAD = OPEN-CIRCUIT FIGURE 25. CCM STEADY-STATE OPERATION,
VIN = 12.6V, VOUT = 1.0V, IOUT = 10A
FIGURE 26. DCM STEADY-STATE OPERATION,
VIN = 12.6V, VOUT = 1.0V, IOUT =3A FIGURE 27. CCM LOAD TRANSIENT RESPONSE
VIN = 12.6V, VOUT =1.0V
FIGURE 28. DCM LOAD TRANSIENT RESPONSE
VIN = 12.6V, VOUT =1.0V FIGURE 29. VID TO SREF RESPONSE
VIN = 12.6V, VOUT = 950mV AND 1.05V,
IOUT = 10A
Typical Performance Curves (Continued)
EN
SREF
PGOOD VOUT
10s
PHASE
UGATE
LGATE
VOUT
PHASE
UGATE
LGATE
VOUT
PHASE
IOUT
VOUT
5ADC
+10AµF
5ADC
15ADC
-10AµF
PHASE
IOUT
VOUT
1ADC
+10AµF
1ADC
11ADC
-10AµF
SREF
VOUT
VID0
VID1
ISL62871, ISL62872
23 FN6707.0
August 14, 2008
FIGURE 30. SREF FALLING RESPONSE
VIN = 12.6V, VOUT = 1.05V TO 950mV, IOUT = 10A FIGURE 31. SREF RISING RESPONSE
VIN = 12.6V, VOUT = 950mV TO 1.05V, IOUT = 10A
FIGURE 32. VID TO SREF RESPONSE IN DCM
VIN = 12.6V, VOUT = 950mV AND 1.05V, IOUT = 100mA
Typical Performance Curves (Continued)
SREF
VOUT
VID0
VID1
SREF VOUT
VID0
VID1
SREF
VOUT
VID0
VID1
ISL62871, ISL62872
24 FN6707.0
August 14, 2008
ISL62871, ISL62872
Package Outline Drawing
L20.3.2x1.8
20 LEAD ULTRA THIN QUAD FLAT NO-LEAD PLASTIC PACKAGE (UTQFN)
Rev 0, 5/08
located within the zone indicated . Th e pin #1 identifier may be
Unless otherwise specified, tol erance : Decim al ± 0.05
Tiebar shown (if present) is a non-functional feature.
The configuration of the pin #1 identifier is optio nal, but must be
between 0.15mm an d 0.3 0m m from the te rminal tip.
Dimension b applies to the metallized terminal and is measured
Dimensions in ( ) for Reference Only.
Dimensioning and tolerancing conform to AMSE Y14.5m-1994 .
6.
either a mold or mark feature.
3.
5.
4.
2.
Dimensions are in millimeters.1.
NOTES:
DETAIL "X"
SIDE VIEW
TYPICAL RECOMMENDED LAND PATTERN
TOP VIEW
(1 x 0.70)
( 19X 0 . 60 )
20
0.10
( 2. 30 )
(4X)
( 16 X 0 . 40 )
( 20X 0 . 20 ) C
MAX 0.55
3.20
12
PIN 1 ID#
6
1.80 B
A
19
16X 0.40
5
0 . 05 MAX.
0 . 00 MIN.
0 . 2 REF
BASE PLANE
SEE DETAIL "X"
C
C
0.10
SEATING PLANE
0.05 C
M
20X 0.20
M
4
19X 0.40 ± 0.10
11 10
0.10
0.05 ABC
C
9
6
PIN #1 ID
2
1
0.50±0.10
BOTTOM VIEW
VIEW “A-A”
( 1.0 )
25
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No lice nse is gran t ed by i mpli catio n or other wise u nder an y p a tent or patent rights of I nter sil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN6707.0
August 14, 2008
ISL62871, ISL62872
Ultra Thin Quad Flat No-Lead Plastic Package (UTQFN)
6
B
E
A
D
0.10 C
2X
C
0.05 CA
0.10 C
A1
SEATING PLANE
INDEX AREA
21
N
TOP VIEW
BOTTOM VIEW
SIDE VIEW
NX (b)
SECTION "C-C" e
CC
5
C
L
TERMINAL TIP
(A1)
L
0.10 C
2X
e
L1
NX L
21
0.10 M CAB
0.05 M C
5
NX b
(DATUM B)
(DATUM A)
PIN #1 ID
16X
3.00
1.40
2.20
0.40
0.50
0.20
0.40
0.20
0.90
1.40
1.80
LAND PATTERN
10
L16.2.6x1.8A
16 LEAD UL TRA THIN QUAD FLA T NO-LEAD PLASTIC P ACKAGE
SYMBOL
MILLIMETERS
NOTESMIN NOMINAL MAX
A 0.45 0.50 0.55 -
A1 - - 0.05 -
A3 0.127 REF -
b 0.15 0.20 0.25 5
D 2.55 2.60 2.65 -
E 1.75 1.80 1.85 -
e 0.40 BSC -
L 0.35 0.40 0.45 -
L1 0.45 0.50 0.55 -
N162
Nd 4 3
Ne 4 3
θ
0-12
4
Rev. 4 8/06
NOTES:
1. Dimensioning and tolerancing conform to ASME Y14.5-1994.
2. N is the number of terminals.
3. Nd and Ne refer to the number of terminals on D and E side,
respectively.
4. All dimensions are in millimeters. Angles are in degrees.
5. Dimension b applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
6. The configuration of the pin #1 identifier is optional, but must be
located wi thin the zone indicated. The pin #1 identif ier may be
either a mold or mark feature.
7. Maximum package warpage is 0.05mm.
8. Maximum allowable burrs is 0.076mm in all directions.
9. JEDEC Reference MO-255.
10. For additional information, to assist with the PCB Land Pattern
Design effort, see Intersil Technical Brief TB389.
