MB89P637PF-GE1 - CYPRESS SEMICONDUCTOR

The following document contains information on Cypress products.

FUJITSU MICROELECTRONICS

DATA SHEET

2009.5

For the information for microcontroller supports, see the following web site.

http://edevice.fujitsu.com/micom/en-support/

8-bit Proprietary Microcontroller

CMOS

F2MC-8L MB89630R Series

MB89635R/636R/637R/P637/PV630

■OUTLINE

The MB89630R series has been developed as a general-purpose version of the F2MC*-8L family consisting of

proprietary 8-bit, single-chip microcontrollers.

In addition to a compact instruction set, the microcontrollers contain a variety of peripheral functions such as

dual-clock control system, five operating speed control stages , a UART, timers, a PWM timer, a serial interface,

an A/D converter, an external interrupt, and a watch prescaler.

* : F2MC is the abbreviation for Fujitsu Flexible Microcontroller.

■FEATURES

• High-speed operating capability at low voltage

• Minimum execution time: 0.4 μs@3.5 V, 0.8 μs@2.7 V

•F

2MC-8L family CPU core

• Five types of timers

8-bit PWM timer: 2 channels (Also usable as a reload timer)

8-bit pulse-width count timer (Continuous measurement capable, applicable to remote control, etc.)

16-bit timer/counter

21-bit timebase timer (Continued)

Multiplication and division instructions

16-bit arithmetic operations

Test and branch instructions

Bit manipulation instructions, etc.

Instruction set optimized for controllers

DS07-12531-4E

MB89630R Series

2DS07-12531-4E

(Continued)

•UART

CLK-synchronous/CLK-asynchronous data transfer capable (6, 7, and 8 bits)

• Serial interface

Switchable transfer direction to allows communication with various equipment.

• 10-bit A/D converter

Start by an external input capable

• External interrupt: 4 channels

Four channels are independent and capable of wake-up from low-power consumption modes (with an edge

detection function).

• Low-power consumption modes

Stop mode (Oscillation stops to minimize the current consumption.)

Sleep mode (The CPU stops to reduce the current consumption to approx. 1/3 of normal.)

Subclock mode

Watch mode

• Bus interface function

With hold and ready function

MB89630R Series

DS07-12531-4E 3

■PRODUCT LINEUP

(Continued)

MB89636R MB89637R MB89P637 MB89PV630

Classification Mass-produced products

(mask ROM products) One-time

PROM

product

Piggyback/

e v aluation product

(f or e valuation and

development)

ROM size 16 K × 8 bits

(internal mask

ROM)

24 K × 8 bits

(internal mask

ROM)

32 K × 8 bits

(internal mask

ROM)

32 K × 8 bits

(Internal PROM,

to be programmed

with general-

purpose

EPROM

programmer)

32 K × 8 bits

(external ROM)

RAM size 512 × 8 bits 768 × 8 bits 1024 × 8 b i t s 1024 × 8 bits 1024 × 8 bits

CPU functions The number of instructionns: 136

Instruction bit length: 8 bits

Instruction length: 1 to 3 bytes

Data bit length: 1, 8, 16 bits

Minimum execution time: 0.4 μs/10 MHz, 61 μs@32.768 kHz

Interrupt processing time: 3.6 to 57.6 μs/10 MHz, 562.5 μs@32.768 kHz

Ports Input ports: 5 (All also serve as peripherals.)

Output ports (N-ch open-drain): 8 (All also serve as peripherals.)

I/O ports (N-ch open-drain): 4 (All also serve as peripherals.)

Output ports (CMOS): 8 (All also serve as bus control.)

I/O ports (CMOS): 28 (27 ports also serve as bus pins and peripherals.)

Total: 53

Watch timer 21 bits × 1 (in main clock)/15 bits × 1 (at 32.768 kHz)

8-bit PWM

timer 8-bit reload timer operation (toggled output capable, operating clock cycle: 0.4 μs to 3.3 ms) × 2

channels

7/8-bit resolution PWM operation (conversion cycle: 51.2 μs to 839 ms) × 2 channels

8-bit pulse

width count

timer

8-bit timer operation (overflow output capable, operating clock cycle: 0.4 to 12.8 μs)

8-bit reload timer operation (toggled output capable, operating clock cycle: 0.4 to 12.8 μs)

8-bit pulse width measurement operation (capable of continuous measurement, and

measurement of “H” pulse width/ “L” pulse width/ from ↑ to ↑/from ↓ to ↓)

16-bit timer/

counter 16-bit timer operation (operating clock cycle: 0.4 μs)

16-bit event counter operation (rising edge/falling edge/both edge selectable)

8-bit serial I/O 8 bits

LSB first/MSB first selectable

One clock selectable from four transfer clocks

(one external shift clock, three internal shift clocks: 0.8 μs, 3.2 μs, 12.8 μs)

UART Capable of switching two I/O systems by software

Transfer data length (6, 7, and 8 bits)

Transfer rate (300 to 62500 bps. at 10 MHz oscillation)

10-bit A/D

converter 10-bit resolution × 8 channels

A/D conversion mode (conversion time: 13.2 μs)

Sense mode (conversion time: 7.2 μs)

Capable of continuous activation by an external activation or an internal timer

MB89635R

Part number

Item

MB89630R Series

4DS07-12531-4E

(Continued)

* :Varies with conditions such as the operating frequency. (See section “■ Electrical Characteristics.”)

In the case of the MB89PV630, the voltage varies with the restrictions of the EPROM for use.

■PACKAGE AND CORRESPONDING PRODUCTS

: Available ×: Not available

Note: For more information about each package, see section “■ Package Dimensions.”

MB89636R MB89637R MB89P637 MB89PV630

External

interrupt input 4 independent channels (edge selection, interrupt vector, source flag).

Rising edge/falling edge selectable

Used also for wake-up from stop/sleep mode. (Edge detection is also permitted in stop mode.)

Standby mode Sleep mode, stop mode, watch mode, and subclock mode

Process CMOS

Operating

voltage* 2.2 V to 6.0 V 2.7 V to 6.0 V

EPROM f or use MBM27C256A-20CZ

MBM27C256A-20TV

Package MB89635R MB89636R

MB89637R MB89P637 MB89PV630

DIP-64P-M01 ×

FPT-64P-M06 ×

FPT-64P-M23 ××

MQP-64C-P01 ×××

MDP-64C-P02 ×××

MB89635R

Part number

Item

MB89630R Series

DS07-12531-4E 5

■DIFFERENCES AMONG PRODUCTS

1. Memory Size

Bef ore ev aluating using the pigg ybac k product, v erify its differences from the product that will actually be used.

Take particular care on the following points:

• On the MB89P637, the program area starts from address 8007H but on the MB89PV630 and MB89637R starts

from 8000H.

(On the MB89P637, addresses 8000H to 8006H comprise the option setting area, option settings can be read

by reading these addresses. On the MB89PV630/MB89637R, addresses 8000H to 8006H could also be used

as a program ROM. However , do not use these addresses in order to maintain compatibility of the MB89P637.)

• The stack area, etc., is set at the upper limit of the RAM.

• The external area is used.

2. Current Consumption

• In the case of the MB89PV630, add the current consumed by the EPROM which connected to the top socket.

• When operated at low speed, the product with an OTPROM (one-time PROM) or an EPROM will consume

more current than the product with a mask ROM. However, the current consumption in sleep/stop modes is

the same. (For more information, see sections “■ Electrical Characteristics” and “■ Example Characteristics”.)

3. Mask Options

Functions that can be selected as options and how to designate these options vary by the product.

Before using options check section “■ Mask Options”.

Take particular care on the following points:

• A pull-up resistor cannot be set for P50 to P53 on the MB89P637.

• Options are fixed on the MB89PV630.

4. Differences between the MB89630 and MB89630R Series

• Memory access area

There are no diff erence between the access area of MB89635/MB89635R, and that of MB89637/MB89637R.

The access area of MB89636 is different from that of the MB89636R when using in external bus mode.

Address Memory area

MB89636 MB89636R

0000H to 007FHI/O area I/O area

0080H to 037FHRAM area RAM area

0380H to 047FH

External area

Access prohibited

0480H to 7FFFHExternal area

8000H to 9FFFHAccess prohibited

A000H to FFFFHROM ar ea ROM area

MB89630R Series

6DS07-12531-4E

• Other specifications

Both MB89630 series and MB89635R/636R/637R is the same.

• Electrical specifications/electrical characteristics

Electrical specifications of the MB89635R/636R/637R series are the same as that of the MB89630 series.

Electrical characteristics of both the series are much the same.

■CORRESPONDENCE BETWEEN THE MB89630 AND MB89630R SERIES

• The MB89630R series is the reduction version of the MB89630 series.

• The the MB89630 and MB89630R series consist of the following products:

MB89630 series MB89635 MB89636 MB89637 MB89P637 MB89PV630

MB89630R series MB89635R MB89636R MB89637R

MB89630R Series

DS07-12531-4E 7

■PIN ASSIGNMENT

P51/BZ

P50/ADST

P60/AN0

P61/AN1

P62/AN2

P63/AN3

P64/AN4

P65/AN5

P66/AN6

P67/AN7

AVR

P74/EC

P73/INT3

P72/INT2

P00/AD0

P01/AD1

P02/AD2

P03/AD3

P04/AD4

P05/AD5

P06/AD6

P07/AD7

P10/A08

P11/A09

P12/A10

P13/A11

P14/A12

P15/A13

P16/A14

P17/A15

P52

P53/PTO2

P40/UCK2

P41/UO2

P42/UI2

P43/PTO1

P30/UCK1

P31/UO1

P32/UI1

P33/SCK1

P34/SO1

P35/SI1

P36/PWC

P37/WTO

P71/INT1/X0A*

P70/INT0/X1A*

RST

MOD0

MOD1

P27/ALE

P26/RD

P25/WR

P24/CLK

P23/RDY

P22/HRQ

P21/HAK

P20/BUFC

(Top view)

(FPT-64P-M23) *: When the dual-clock system is selected.

(DIP-64P-M01)

(MDP-64C-P02)

(Top view)

VPP 66

A12 67

A7 68

A6 69

A5 70

A4 71

A3 72

A2 73

A1 74

A0 75

O1 76

O2 77

O3 78

VSS

VCC

92 A14

91 A13

90 A8

89 A9

88 A11

87 OE

86 A10

85 CE

84 O8

83 O7

82 O6

81 O5

80 O4

P31/UO1 2

P30/UCK1 3

P43/PTO1 4

P42/UI2 5

P41/UO2 6

P40/UCK2 7

P53/PTO2 8

P52 9

P51/BZ 10

P50/ADST 11

P60/AN0 12

P61/AN1 13

P62/AN2 14

P63/AN3 15

P64/AN4 16

P65/AN5 17

P66/AN6 18

P67/AN7 19

AVCC 20

AVR 21

AVSS 22

P74/EC 23

P73/INT3 24

P72/INT2 25

P71/INT1/X0A* 26

P70/INT0/X1A* 27

RST 28

MOD0 29

MOD1 30

X0 31

X1 32

VSS

VCC

64 P32/UI1

63 P33/SCK1

62 P34/SO1

61 P35/SI1

60 P36/PWC

59 P37/WTO

58 VSS

57 P00/AD0

56 P01/AD1

55 P02/AD2

54 P03/AD3

53 P04/AD4

52 P05/AD5

51 P06/AD6

50 P07/AD7

49 P10/A08

48 P11/A09

47 P12/A10

46 P13/A11

45 P14/A12

44 P15/A13

43 P16/A14

42 P17/A15

41 P20/BUFC

40 P21/HAK

39 P22/HRQ

38 P23/RDY

37 P24/CLK

36 P25/WR

35 P26/RD

34 P27/ALE

Each pin inside

the dashed line is

for MB89PV630 only.

*: When the dual-clock system is selected.

MB89630R Series

8DS07-12531-4E

• Pin assignment on package top (MB89PV630 only)

N.C.: Internally connected. Do not use.

Pin no. Pin name Pin no. Pin name Pin no. Pin name Pin no. Pin name

65 N.C. 73 A2 81 N.C. 89 OE

66 VPP 74 A1 82 O4 90 N.C.

67A1275A083O591A11

68 A7 76 N.C. 84 O6 92 A9

69 A6 77 O1 85 O7 93 A8

70 A5 78 O2 86 O8 94 A13

71 A4 79 O3 87 CE 95 A14

72 A3 80 VSS 88 A10 96 VCC

P52

P51/BZ

P50/ADST

P60/AN0

P61/AN1

P62/AN2

P63/AN3

P64/AN4

P65/AN5

P66/AN6

P67/AN7

AVR

P74/EC

P73/INT3

P72/INT2

P71/INT1/X0A*

P70/INT0/X1A*

P37/WTO

P00/AD0

P01/AD1

P02/AD2

P03/AD3

P04/AD4

P05/AD5

P06/AD6

P07/AD7

P10/A08

P11/A09

P12/A10

P13/A11

P14/A12

P15/A13

P16/A14

P17/A15

P20/BUFC

P53/PTO2

P40/UCK2

P41/UO2

P42/UI2

P43/PTO1

P30/UCK1

P31/UO1

P32/UI1

P33/SCK1

P34/SO1

P35/SI1

P36/PWC

RST

MOD0

MOD1

P27/ALE

P26/RD

P25/WR

P24/CLK

P23/RDY

P22/HRQ

P21/HAK

(Top view)

(FPT-64P-M06)

(MQP-64C-P01)

Each pin inside the dashed line

is for MB89PV630 only.

*: When the dual-clock system is selected.

MB89630R Series

DS07-12531-4E 9

■PIN DESCRIPTION

(Continued)

*1: DIP-64P-M01 *4: FPT-64P-M06

*2: MDP-64C-P02 *5: MQP-M64C-P01

*3: FPT-64P-M23

Pin no. Pin name Circuit

type Function

SH-DIP*1

MDIP*2 QFP2*3 QFP1*4

MQFP*5

30 22 23 X0 A Main clock crystal oscillator pins

31 23 24 X1

28 20 21 MOD0 D Operating mode selection pins

Connect directly to VCC or VSS.

29 21 22 MOD1

27 19 20 RST C Reset I/O pin

This pin is an N-ch open-drain output type with a

pull-up resistor, and a hysteresis input type.

“L” is output from this pin by an internal reset

source. The internal circuit is initialized by the

input of “L”.

56 to 49 48 to 41 49 to 42 P00/AD0 to

P07/AD7 F General-purpose I/O ports

When an external bus is used, these ports

function as the multiplex pins of the low er address

output and the data I/O.

48 to 41 40 to 33 41 to 34 P10/A08 to

P17/A157 F General-purpose I/O ports

When an external bus is used, these ports

function as an upper address output.

40 32 33 P20/BUFC H General-purpose output port

When an external bus is used, this port can also

be used as a buffer control output by setting the

BCTR.

39 31 32 P21/HAK H General-purpose output port

When an external bus is used, this port can also

be used as a hold acknowledge by setting the

BCTR.

38 30 31 P22/HRQ F General-purpose output port

When an external bus is used, this port can also

be used as a hold request input by setting the

BCTR.

37 29 30 P23/RDY F General-purpose output port

When an external bus is used, this port functions

as a ready input.

36 28 29 P24/CLK H General-purpose output port

When an external bus is used, this port functions

as a clock output.

35 27 28 P25/WR H General-purpose output port

When an external bus is used, this port functions

as a write signal output.

34 26 27 P26/RD H General-purpose output port

When an external bus is used, this port functions

as a read signal output.

MB89630R Series

10 DS07-12531-4E

(Continued)

*1: DIP-64P-M01 *4: FPT-64P-M06

*2: MDP-64C-P02 *5: MQP-M64C-P01

*3: FPT-64P-M23

Pin no. Pin name Circuit

type Function

SH-DIP*1

MDIP*2 QFP2*3 QFP1*4

MQFP*5

33 25 26 P27/ALE H General-purpose output port

When an external bus is used, this port functions

as an address latch signal output.

2 58 59 P30/UCK1 G General-purpose I/O por t

Also serves as the clock I/O 1 for the UART.

This port is a hysteresis input type.

1 57 58 P31/UO1 F General-purpose I/O port

Also serves as the data output 1 for the UART.

63 55 56 P32/UI1 G General-purpose I/O port

Also serves as the data input 1 for the UART.

This port is a hysteresis input type.

62 54 55 P33/SCK1 G General-purpose I/O port

Also serves as the data input for the 8-bit serial

I/O.

This port is a hysteresis input type.

61 53 54 P34/SO1 F General-purpose I/O port

Also serves as the data output for the 8-bit serial

I/O.

60 52 53 P35/SI1 G General-purpose I/O port

Also serves as the data input for the 8-bit serial

I/O.

This port is a hysteresis input type.

59 51 52 P36/PWC G General-purpose I/O port

Also serves as the measured pulse input for the

8-bit pulse width counter.

This port is a hysteresis input type.

58 50 51 P37/WTO F General-purpose I/O port

Also serv es as the toggle output f or the 8-bit pulse

width counter.

6 62 63 P40/UCK2 G General-purpose I/O por t

Also serves as the clock I/O 2 for the UART.

This port is a hysteresis input type.

5 61 62 P41/UO2 F General-purpose I/O port

Also serves as the data output 2 for the UART.

4 60 61 P42/UI2 G General-purpose I/O port

Also serves as the data input 2 for the UART.

This port is a hysteresis input type.

3 59 60 P43/PTO1 F General-purpose I/O port

Also serv es as the toggle output f or the 8-bit PWM

timer.

10 2 3 P50/ADST K General-purpose I/O port

Also serves as an A/D converter external

activation.

This port is a hysteresis input type.

MB89630R Series

DS07-12531-4E 11

(Continued)

*1: DIP-64P-M01 *4: FPT-64P-M06

*2: MDP-64C-P02 *5: MQP-M64C-P01

*3: FPT-64P-M23

Pin no. Pin name Circuit

type Function

SH-DIP*1

MDIP*2 QFP2*3 QFP1*4

MQFP*5

9 1 2 P51/BZ J General-purpose I/O port

Also serves as a buzzer output.

8 64 1 P52 J General-purpose I/O port

7 63 64 P53/PT O2 J General-purpose I/O port

Also serves as the toggle output for the 8-bit PWM

timer.

11 to 18 3 to 10 4 to 11 P60/AN0 to

P67/AN7 I N-ch open-drain output ports

Also serve as an A/D converter analog input.

26,

25 18,

17 19,

18 P70/INT0/X1A,

P71/INT1/X0A B/E Input-only ports

These ports are a hysteresis input type.

Also serve as an external interrupt input (at single-

clock operation).

Subclock crystal oscillator pins (at dual-clock

operation)

24,

23 16,

15 17,

16 P72/INT2,

P73/INT3 E Input-only ports

Also serve as an external interrupt input.

These ports are a hysteresis input type.

22 14 15 P74/EC E General-purpose input port

Also serves as the external clock input for the

16-bit timer/counter.

This port is a hysteresis input type.

64 56 57 VCC — Power supply pin

32, 57 24,49 25, 50 VSS — Power supply (GND) pin

19 11 12 AVCC — A/D converter power supply pin

20 12 13 AVR — A/D converter reference voltage input pin

21 13 14 AVSS — A/D converter power supply pin

Use this pin at the same voltage as VSS.

MB89630R Series

12 DS07-12531-4E

•External EPROM pins (MB89PV630 only)

Pin no. Pin name I/O Function

MDIP MQFP

65 66 VPP O “H” level output pin

A12

O Address output pins

I Data input pins

78 80 VSS O Power supply (GND) pin

I Data input pins

84 87 CE O ROM chip enable pin

Outputs “H” during standby.

85 88 A10 O Address output pin

86 89 OE O ROM output enable pin

Outputs “L” at all times.

A11

O Address output pins

90 94 A13 O

91 95 A14 O

92 96 VCC O EPROM power supply pin

—65

N.C. — Internally connected pins

Be sure to leave them open.

MB89630R Series

DS07-12531-4E 13

■I/O CIRCUIT TYPE

(Continued)

Type Circuit Remarks

A • Crystal or ceramic oscillation type (main clock)

External clock input selection versions of MB89PV630,

MB89P637, MB89635R, MB89636R, and MB89637R

At an oscillation feedback resistor of approximately

1 MΩ@5.0 V

B • Crystal or ceramic oscillation type (subclock)

MB89PV630, MB89P637, MB89635R, MB89636R, and

MB89637R with dual-clock system

At an oscillation feedback resistor of approximately

4.5 MΩ@5.0 V

C • At an output pull-up resistor (P-ch) of approximately

50 kΩ@5.0 V

• Hysteresis input

E • Hysteresis input

• Pull-up resistor optional (except P70 and P71)

F • CMOS output

•CMOS input

• Pull-up resistor optional (except P22 and P23)

Standby control signal

X1A

X0A

Standby control signal

RP-ch

N-ch

P-ch

N-ch

P-ch

MB89630R Series

14 DS07-12531-4E

(Continued)

Type Circuit Remarks

G • CMOS output

• Hysteresis input

• Pull-up resistor optional

H CMOS output

I Analog input

J•CMOS input

• Pull-up resistor optional

K • Hysteresis input

• Pull-up resistor optional

P-ch

N-ch

P-ch

N-ch

Analog input

N-ch

RP-ch

N-ch

RP-ch

MB89630R Series

DS07-12531-4E 15

■HANDLING DEVICES

1. Preventing Latchup

Latchup ma y occur on CMOS ICs if voltage higher than VCC or lo wer than VSS is applied to input and output pins

other than medium- and high-v oltage pins or if higher than the v oltage which sho ws on “1. Absolute Maxim um

Ratings” in section “■ Electrical Characteristics” is applied between VCC and VSS.

When latchup occurs, power supply current increases rapidly and might thermally damage elements. When

using, take great care not to exceed the absolute maximum ratings.

Also , take care to pre v ent the analog power supply (AVCC and AVR) and analog input from exceeding the digital

power supply (VCC) when the analog system power supply is turned on and off.

2. Treatment of Unused Input Pins

Leaving un used input pins open could cause malfunctions. They should be connected to a pull-up or pull-do wn

resistor.

3. Treatment of Power Supply Pins on Microcontrollers with A/D and D/A Converters

Connect to be AVCC = DAVC = VCC and AVSS = AVR = VSS even if the A/D and D/A converters are not in use.

4. Treatment of N.C. Pins

Be sure to leave (internally connected) N.C. pins open.

5. Power Supply Voltage Fluctuations

Although VCC power supply voltage is assured to operate within the rated range, a rapid fluctuation of the voltage

could cause malfunctions, even if it occurs within the rated range. Stabilizing voltage supplied to the IC is

therefore important. As stabilization guidelines, it is recommended to control power so that VCC ripple fluctuations

(P-P v alue) will be less than 10% of the standard VCC value at the commercial frequency (50 Hz to 60 Hz) and

the transient fluctuation rate will be less than 0.1 V/ms at the time of a momentary fluctuation such as when

power is switched.

6. Precautions when Using an External Clock

When an external clock is used, oscillation stabilization time is required even for power-on reset (option selection)

and wake-up from stop mode.

MB89630R Series

16 DS07-12531-4E

■PROGRAMMING TO THE EPROM ON THE MB89P637

The MB89P637 is an OTPROM version of the MB89630 series.

1. Features

• 32-Kbytes PROM on chip

• Options can be set using the EPROM programmer.

• Equivalency to the MBM27C256A in EPROM mode (when programmed with the EPROM programmer)

2. Memory Space

Memory space in each mode is illustrated below.

3. Programming to the EPPROM

In EPROM mode, the MB89P637 functions equivalent to the MBM27C256A. This allows the PROM to be

programmed with a general-purpose EPROM programmer by using the dedicated socket adapter.

However, the electronic signature mode cannot be used.

When the operating ROM area for a single chip is 32 Kbytes (8007H to FFFFH) the EPROM can be programmed

as follows:

Program area

(EPROM)

32 KB

7FFFH

Option setting area

0000H

Option setting area 0007H

PROM

32 KB

External area

I/O

0000H

0080H

0100H

0200H

0480H

8000H

8007H

FFFFH

Normal operating mode EPROM mode

(Corresponding addresses

on the EPROM programmer)

MB89630R Series

DS07-12531-4E 17

•Programming procedure

(1) Set the EPROM programmer to the MBM27C256A.

(2) Load program data into the EPROM programmer at 0007H to 7FFFH. (Note that addresses 8000H to FFFFH

in the operating mode assign to 0000H to 7FFFH in EPROM mode).

(3) Load option data into addresses 0000H to 0006H of the EPROM programmer.

(For information about each corresponding option, see “8. OTPROM Option Bit Map”.)

(4) Program with the EPROM programmer.

4. Recommended Screening Conditions

High-temperature aging is recommended as the pre-assembly screening procedure for a product with a blanked

OTPROM microcomputer program.

5. Programming Yield

All bits cannot be programmed at Fujitsu shipping test to a b lanked O TPR OM microcomputer , due to its nature.

For this reason, a programming yield of 100% cannot be assured at all times.

Program, verify

Aging

+150°C, 48 Hrs.

Data verification

Assembly

MB89630R Series

18 DS07-12531-4E

6. OTPROM Option Bit Map

Note: Each bit is set to ‘1’ as the initialized value.

Address Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

0000H

Vacancy

Readable

and writable

Vacancy

Readable

and writable

Vacancy

Readable

and writable

Single/dual-

clock system

1: Dual clock

0: Single clock

Reset pin

output

1: Yes

0: No

Power-on

reset

1: Yes

0: No

Oscillation stabilization (/FCH)

11:218/FCH 01:217/FCH

10:214/FCH 00:24/FCH

0001H

P07

Pull-up

1: No

0: Yes

P06

Pull-up

1: No

0: Yes

P05

Pull-up

1: No

0: Yes

P04

Pull-up

1: No

0: Yes

P03

Pull-up

1: No

0: Yes

P02

Pull-up

1: No

0: Yes

P01

Pull-up

1: No

0: Yes

P00

Pull-up

1: No

0: Yes

0002H

P17

Pull-up

1: No

0: Yes

P16

Pull-up

1: No

0: Yes

P15

Pull-up

1: No

0: Yes

P14

Pull-up

1: No

0: Yes

P13

Pull-up

1: No

0: Yes

P12

Pull-up

1: No

0: Yes

P11

Pull-up

1: No

0: Yes

P10

Pull-up

1: No

0: Yes

0003H

P37

Pull-up

1: No

0: Yes

P36

Pull-up

1: No

0: Yes

P35

Pull-up

1: No

0: Yes

P34

Pull-up

1: No

0: Yes

P33

Pull-up

1: No

0: Yes

P32

Pull-up

1: No

0: Yes

P31

Pull-up

1: No

0: Yes

P30

Pull-up

1: No

0: Yes

0004H

Vacancy

Readable

and writable

Vacancy

Readable

and writable

Vacancy

Readable

and writable

Vacancy

Readable

and writable

P43

Pull-up

1: No

0: Yes

P42

Pull-up

1: No

0: Yes

P41

Pull-up

1: No

0: Yes

P40

Pull-up

1: No

0: Yes

0005H

Vacancy

Readable

and writable

Vacancy

Readable

and writable

Vacancy

Readable

and writable

P74

Pull-up

1: No

0: Yes

P73

Pull-up

1: No

0: Yes

P72

Pull-up

1: No

0: Yes

Vacancy

Readable

and writable

Vacancy

Readable

and writable

0006H

Vacancy

Readable

and writable

Vacancy

Readable

and writable

Vacancy

Readable

and writable

Vacancy

Readable

and writable

Vacancy

Readable

and writable

Vacancy

Readable

and writable

Vacancy

Readable

and writable

Reserved bit

Readable

and writable

MB89630R Series

DS07-12531-4E 19

■PROGRAMMING TO THE EPROM WITH PIGGYBACK/EVALUATION DEVICE

1. EPROM for Use

MBM27C256A-20CZ, MBM27C256A-20TV

2. Memory Space

Memory space in each mode, such as 32-Kbyte PROM, option area is diagrammed below.

3. Programming to the EPROM

(1) Set the EPROM programmer to the MBM27C256A.

(2) Load program data into the EPROM programmer at 0007H to 7FFFH.

(3) Program to 0000H to 7FFFH with the EPROM programmer.

PROM

32 KB

FFFFH

0000H

8000H

0080H

0480H

Not available

Single chip

Address

I/O

Corresponding addresses on the EPROM programmer

RAM

8007H

Not available

7FFFH

0000H

0007H

EPROM

32 KB

Not available

MB89630R Series

20 DS07-12531-4E

■BLOCK DIAGRAM

Subclock oscillator

(32.768 kHz)

RST

Clock controller

Reset circuit

(Watchdog timer)

P00/AD0

to P07/AD7

P10/A08

to P17/A15

CMOS I/O port

External bus

interface

MOD0

MOD1

P27/ALE

P26/RD

P25/WR

P24/CLK

P23/RDY

P22/HRQ

P21/HAK

P20/BUFC CMOS output port

RAM

F MC-8L

CPU

ROM

VCC × 2, VSS × 2

Other pins

21-bit timebase timer

8-bit PWC timer

UART

CMOS I/O port

8-bit PWM timer

Buzzer output

Input port

16-bit timer/counter

4P73/INT3

P74/EC

P50/ADST

P51/BZ

P52

P53/PTO2

P43/PTO1

P33/SCK1

P34/SO1

P36/PWC

X0A

X1A

Watch prescaler

CMOS I/O port

P37/WTO

P35/SI1

P30/UCK1

P31/UO1

P32/UI1

P42/UI2

P41/UO2

P40/UCK2

N-ch open-drain I/O port

10-bit A/D converter AVCC, AVSS,

AVR

P60/AN0

to P67/AN7

8 8

External interrupt P72/INT2

P71/INT1

P70/INT0

N-ch open-drain output port

Main clock oscillator

Port0 and port1Port 2

Internal data bus

8-bit serial I/O

Port 3Port 4

UART baud rate

generator

Port 5Port 6Port 7

MB89630R Series

DS07-12531-4E 21

■CPU CORE

1. Memory Space

The microcontrollers of the MB89630R series offer 64 Kbytes of memory for storing all of I/O, data, and program

areas. The I/O area is located at the lowest address. The data area is provided immediately above the I/O area.

The data area can be divided into register, stack, and direct areas according to the application. The program

area is located at exactly the opposite end of I/O area, that is, near the highest address. Provide the tables of

interrupt reset vectors and vector call instructions toward the highest address within the program area. The

memory space of the MB89630R series is structured as illustrated below.

• Memory space

*1: The ROM area is an external area depending on the mode.

*2: Addresses 8000H to 8006H for the MB89P637 comprise an option area, do not use

this area for the MB89PV630 and MB89637R.

0000H

0080H

0100H

0480H

8000H

8007H

MB89PV630

I/O

RAM

1024 B

External area

External ROM

32 KB

0000H

0080H

0100H

0200H

C000H

FFFFH

MB89635R

I/O

RAM

512 B

ROM*1

16 KB

0000H

0080H

0100H

0200H

A000H

MB89636R

I/O

RAM

768 B

ROM*1

24 KB

0000H

0080H

0100H

0200H

8000H

8007H

MB89637R

MB89P637

I/O

RAM

1024 B

ROM*1

32 KB

FFFFH

External area External area External area

0380H

0280H

0200H

0480H

FFFFHFFFFH

0480H

8000H

*3: The access is forbidden in the external bus mode.

MB89630R Series

22 DS07-12531-4E

2. Registers

The F2MC-8L family has two types of registers; dedicated registers in the CPU and general-purpose registers

in the memory. The following dedicated registers are provided:

Program counter (PC): A 16-bit register for indicating the instruction storage positions

Accumulator (A): A 16-bit temporary register for storing arithmetic operations, etc. When the

instruction is an 8-bit data processing instruction, the lower byte is used.

Temporary accumulator (T): A16-bit register which performs arithmetic operations with the accumulator

When the instruction is an 8-bit data processing instruction, the lower byte is used.

Index register (IX): A16-bit register for index modification

Extra pointer (EP): A16-bit pointer for indicating a memory address

Stack pointer (SP): A16-bit register for indicating a stack area

Program status (PS): A16-bit register for storing a register pointer, a condition code

The PS can further be divided into higher 8 bits f or use as a register bank pointer (RP) and the lo w er 8 bits for

use as a condition code register (CCR). (See the diagram below.)

16 bits

: Program counter

: Accumulator

: Temporary accumulator

: Index register

: Extra pointer

: Stack pointer

: Program status

FFFDH

I-flag = 0, IL1, IL0 = 11

The other bit values are indeterminate.

Initial value

Indeterminate

IndeterminateIndeterminate

Indeterminate

• Structure of the program status register

Vacancy Vacancy Vacancy

H I IL1, IL0 N Z VC

RPPS

109876 321015 14 13 12 11

RP CCR

MB89630R Series

DS07-12531-4E 23

The RP indicates the address of the register bank currently in use. The relationship between the pointer contents

and the actual address is based on the conversion rule illustrated below.

The CCR consists of bits indicating the results of arithmetic operations and the contents of transfer data and

bits for control of CPU operations at the time of an interrupt.

H-flag: Set to ‘1’ when a carry or a borrow from bit 3 to bit 4 occurs as a result of an arithmetic operation.

Cleared to ‘0’ otherwise. This flag is for decimal adjustment instructions.

I-flag: Interrupt is enabled when this flag is set to ‘1’. Interrupt is disabled when the flag is cleared to ‘0’. Cleared

to ‘0’ at the reset.

IL1, IL0: Indicates the level of the interrupt currently allowed. Processes an interrupt only if its request level is

higher than the value indicated by this bit.

N-flag: Set to ‘1’ if the MSB becomes to ‘1’ as the result of an arithmetic operation. Cleared to ‘0’ when the bit

is cleared to ‘0’.

Z-flag: Set to ‘1’ when an arithmetic operation results in 0. Cleared to ‘0’ otherwise.

V-flag: Set to ‘1’ if the complement on 2 overflows as a result of an arithmetic operation. Cleared to ‘0’ if the

overflow does not occur.

C-flag: Set to ‘1’ when a carry or a borrow from bit 7 occurs as a result of an arithmetic operation. Cleared to ‘0’

otherwise.

Set to the shift-out value in the case of a shift instruction.

IL1 IL0 Interrupt level High-low

00 1High

Low

10 2

11 3

• Rule for conversion of actual addresses of the general-purpose register area

“0”

↓

A15

“0”

↓

A14

“0”

↓

A13

“0”

↓

A12

“0”

↓

A11

“0”

↓

A10

“0”

↓

“1”

↓

Lower OP codes

Generated addresses

MB89630R Series

24 DS07-12531-4E

The following general-purpose registers are provided:

General-purpose registers: An 8-bit register for storing data

The general-purpose registers are 8 bits and located in the register banks of the memory. One bank contains

eight registers and up to a total of 32 banks can be used on the MB89630R ser ies. The bank currently in use

is indicated by the register bank pointer (RP).

• Register bank configuration

This address = 0100H + 8 × (RP)

Memory area

32 banks

R 0

R 1

R 2

R 3

R 4

R 5

R 6

R 7

MB89630R Series

DS07-12531-4E 25

■ I/O MAP

(Continued)

Address Read/write Register name Register description

00H(R/W) PDR0 Port 0 data register

01H(W) DDR0 Port 0 data direction register

02H(R/W) PDR1 Port 1 data register

03H(W) DDR1 Port 1 data direction register

04H(R/W) PDR2 Port 2 data register

05H(W) BCTR External bus pin control register

06HVacancy

07H(R/W) SYCC System clock control register

08H(R/W) STBC System clock control register

09H(R/W) WDTE Watchdog timer control register

0AH(R/W) TBCR Timebase timer control register

0BH(R/W) WPCR Watch prescaler control register

0CH(R/W) CHG3 Port 3 switching register

0DH(R/W) PDR3 Port 3 data register

0EH(W) DDR3 Port 3 data direction register

0FH(R/W) PDR4 Port 4 data register

10H(W) DDR4 Port 4 data direction register

11H(R/W) BUZR Buzzer register

12H(R/W) PDR5 Port 5 data register

13H(R/W) PDR6 Port 6 data register

14H(R) PDR7 Port 7 data register

15H(R/W) PCR1 PWC pulse width control register 1

16H(R/W) PCR2 PWC pulse width control register 2

17H(R/W) RLBR PWC reload buffer register

18H(R/W) TMCR 16-bit timer control register

19H(R/W) TCHR 16-bit timer count register (H)

1AH(R/W) TCLR 16-bit timer count register (L)

1BHVacancy

1CH(R/W) SMR1 Serial mode register

1DH(R/W) SDR1 Serial data register

1EHVacancy

1FHVacancy

MB89630R Series

26 DS07-12531-4E

(Continued)

Note: Do not use vacancies.

Address Read/write Register name Register description

20H(R/W) ADC1 A/D converter control register 1

21H(R/W) ADC2 A/D converter control register 2

22H(R/W) ADDH A/D converter data register (H)

23H(R/W) ADDL A/D converter data register (L)

24H(R/W) EIC1 External interrupt control register 1

25H(R/W) EIC2 External interrupt control register 2

26HVacancy

27HVacancy

28H(R/W) CNTR1 PWM timer control register 1

29H(R/W) CNTR2 PWM timer control register 2

2AH(R/W) CNTR3 PWM timer control register 3

2BH(W) COMR1 PWM timer compare register 1

2CH(W) COMR2 PWM timer compare register 2

2DH(R/W) SMC UART serial mode control register

2EH(R/W) SRC UART serial rate control register

2FH(R/W) SSD UART serial status/data register

30H(R)

(W) SIDR

SODR UART serial input data control register

UART serial output data control register

31H to 7BHVacancy

7CH(W) ILR1 Interrupt level setting register 1

7DH(W) ILR2 Interrupt level setting register 2

7EH(W) ILR3 Interrupt level setting register 3

7FHVacancy

MB89630R Series

DS07-12531-4E 27

■ELECTRICAL CHARACTERISTICS

1. Absolute Maximum Ratings

(AVSS = VSS = 0.0 V)

* :Use AVCC and VCC set at the same voltage.

Take care so that AVCC does not exceed VCC, such as when power is turned on.

WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,

temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.

Parameter Symbol Value Unit Remarks

Min. Max.

Power supply voltage VCC VSS – 0.3 VSS + 7.0 V *

AVCC VSS – 0.3 VSS + 7.0 V *

A/D converter reference input voltage AVR VSS – 0.3 VSS + 7.0 V AVR must not exceed

“AVCC + 0.3 V”.

Input voltage VIVSS – 0.3 VCC + 0.3 V Except P50 to P53

VI2 VSS – 0.3 VSS + 7.0 V P50 to P53

Output voltage VOVSS – 0.3 VCC + 0.3 V Except P50 to P53

VO2 VSS – 0.3 VSS + 7.0 V P50 to P53

“L” level maximum output current IOL ⎯20 mA

“L” level average output current IOLAV ⎯4mA

Average value (operating

current × operating rate)

“L” level total maximum output current ΣIOL ⎯100 mA

“L” level total average output current ΣIOLAV ⎯40 mA Average value (operating

current × operating rate)

“H” level maximum output current IOH ⎯–20 mA

“H” level average output current IOHAV ⎯–4 mA Average value (operating

current × operating rate)

“H” level total maximum output current ΣIOH ⎯–50 mA

“H” level total average output current ΣIOHAV ⎯–20 mA Average value (operating

current × operating rate)

Power consumption PD⎯500 mW

Operating temperature TA–40 +85 °C

Storage temperature Tstg –55 +150 °C

MB89630R Series

28 DS07-12531-4E

2. Recommended Operating Conditions

(AVSS = VSS = 0.0 V)

* :These values vary with the operating frequency, instruction cycle, and analog assurance range. See Figure 1

and “5. A/D Converter Electrical Characteristics”.

Figure 1 indicates the operating frequency of the external oscillator at an instruction cycle of 4/FCH.

Since the operating voltage range is dependent on the instruction cycle, see minimum execution time if the

operating speed is switched using a gear.

Parameter Symbol Value Unit Remarks

Min. Max

Power supply voltage VCC

2.2* 6.0* V Normal operation

assurance range*

MB89635R/636R/637R

2.7* 6.0* V Normal operation

assurance range*

MB89PV630/P637

AVCC 1.5 6.0 V Retains the RAM state in

stop mode

A/D converter reference input voltage AVR 3.0 AVCC V

Operating temperature TA–40 +85 °C

1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 10.0

4.0 2.0 0.8 0.4

Minimum execution time (instruction cycle) (μs)

Main clock operating frequency (at an instruction cycle of 4/F

) (MHz)

Operation assurance range

Analog accuracy assured in the

= 3.5 V to 6.0 V range

Operating voltage (V)

Note: The shaded area is assured only for the MB89635R/636R/637R.

Figure 1 Operating Voltage vs. Main Clock Operating Frequency

MB89630R Series

DS07-12531-4E 29

WARNING: The recommended operating conditions are required in order to ensure the normal operation of

the semiconductor device. All of the device's electrical characteristics are warranted when the

device is operated within these ranges.

Always use semiconductor devices within their recommended operating condition ranges.

Operation outside these ranges may adversely affect reliability and could result in device failure.

No warranty is made with respect to uses, operating conditions, or combinations not represented

on the data sheet. Users considering application outside the listed conditions are advised to contact

their representatives beforehand.

MB89630R Series

30 DS07-12531-4E

3. DC Characteristics

(AVCC = VCC = 5.0 V, AVSS = VSS = 0.0 V, TA = –40°C to +85°C)

(Continued)

Parameter Symbol Pin name Condition Value Unit Remarks

Min. Typ. Max.

“H” level input

voltage

VIH1

P00 to P07, P10 to P17,

P22, P23, P31, P34,

P37, P41, P43,

P51 to P53

⎯

0.7 VCC ⎯VCC + 0.3 VP51 to P53

with pull-up

resistor

VIH2 P51 to P53 0.7 VCC ⎯VSS + 6.0 VWithout pull-up

resistor

VIHS

RST, MOD0, MOD1,

P30, P32, P33, P35,

P36, P40, P42,P50,

P72 to P74 0.8 VCC ⎯VCC + 0.3 VP50 with

pull-up resistor

VIHS2 P50, P70, P71 0.8 VCC ⎯VSS + 6.0 VWithout pull-up

resistor

“L” level input

voltage

VIL P00 to P07, P10 to P17,

P22, P23, P31, P34,

P37, P41, P43 VSS − 0.3 ⎯0.3 VCC V

VILS

P30, P32, P33, P35,

P36, P40, P42,

P50 to P53,

P70 to P74,

RST,

MOD0, MOD1

VSS − 0.3 ⎯0.2 VCC V

Open-drain

output pin

application

voltage VDP50 to P53 VSS − 0.3 ⎯VSS + 6.0 V

“H” level output

voltage VOH P00 to P07, P10 to P17,

P20 to P27, P30 to P37,

P40 to P43 IOH = –2.0 mA 4.0 ⎯⎯V

“L” level output

voltage VOL

P00 to P07, P10 to P17,

P20 to P27, P30 to P37,

P40 to P43, P50 to P53,

P60 to P67, RST IOL = 4.0 mA ⎯⎯0.4 V

Input leakage

current

(Hi-z output

leakage current) ILI

P00 to P07, P10 to P17,

P20 to P23, P30 to P37,

P40 to P43, P50 to P53,

P70 to P74,

MOD0, MOD1

0.0 V < VI < VCC ⎯⎯±5μAWithout pull-up

resistor

MB89630R Series

DS07-12531-4E 31

(AVCC = VCC = 5.0 V, AVSS = VSS = 0.0 V, TA = –40°C to +85°C)

(Continued)

Parameter Symbol Pin name Condition Value Unit Remarks

Min. Typ. Max.

Pull-up

resistance RPULL P00 to P07, P10 to P17,

P30 to P37, P40 to P43,

P50 to P53, P72 to P74 VI = 0.0 V 25 50 100 kΩWith pull-up

resistor

Power supply

current*1

ICC1

VCC

FCH = 10 MHz

VCC = 5.0 V

tinst*2 = 0.4 μs—1220mA

ICC2 FCH = 10 MHz

VCC = 3.0 V

tinst*2 = 6.4 μs

—1.0 2mA

MB89635R/

636R/637R/

PV630

—1.52.5mA

MB89P637

ICCS1 FCH = 10 MHz

VCC = 5.0 V

tinst*2 = 0.4 μs—3 7mA

ICCS2 FCH = 10 MHz

VCC = 3.0 V

tinst*2 = 6.4 μs—0.51.5mA

ICCL FCL = 32.768 kHz,

VCC = 3.0 V

Subclock mode

—50100μAMB89635R/

636R/637R/

PV630

—500700μAMB89P637

ICCLS

FCL = 32.768 kHz,

VCC = 3.0 V

Subclock sleep

mode —2550μA

ICCT

FCL = 32.768 kHz,

VCC = 3.0 V

•Watch mode

• Main clock stop

mode at dual-

clock system

—315μA

ICCH

TA = +25°C

• Subclock stop

mode

• M a i n clock s t o p

mode at single-

clock system

—— 1μA

Sleep mode

MB89630R Series

32 DS07-12531-4E

(Continued) (AVCC = VCC = 5.0 V, AVSS = VSS = 0.0 V, TA = –40°C to +85°C)

*1: The power supply current is measured at the external clock.

In the case of the MB89PV630, the current consumed by the connected EPROM and ICE is not counted.

*2: For information on tinst, see “(4) Instruction Cycle” in “4. AC Characteristics”.

4. AC Characteristics

(1) Reset Timing

(VCC = 5.0 V±10%, AVSS = VSS = 0.0 V, TA = –40°C to +85°C)

Parameter Symbol Pin name Condition Value Unit Remarks

Min. Typ. Max.

Power supply

current*1

AVCC

FCH = 10 MHz,

when A/D

conversion

operates. —6—mA

IAH

FCH = 10 MHz,

TA = +25°C,

when A/D

conversion in

a stop.

—— 1μA

Input capacitance CIN Other than AVCC,

AVSS, VCC, and VSS f = 1 MHz — 10 — pF

Parameter Symbol Condition Value Unit Remarks

Min. Max.

RST “L” pulse width tZLZH — 48 tHCYL —ns

tZLZH

0.2 VCC 0.2 VCC

RST

MB89630R Series

DS07-12531-4E 33

(2) Specification for Power-on Reset

(AVSS = VSS = 0.0 V, TA = –40°C to +85°C)

Note: Make sure that power supply rises within the selected oscillation stabilization time.

If power supply voltage needs to be varied in the course of operation, a smooth voltage rise is recommended.

(3) Clock Timing

(AVSS = VSS = 0.0 V, TA = –40°C to +85°C)

Parameter Symbol Condition Value Unit Remarks

Min. Max.

Power supply rising time tR—— 50 ms Power-on reset function only

Power supply cut-off time tOFF 1—ms

Min. interval time for the next

power-on reset

Parameter Symbol Pin name Condition Value Unit Remarks

Min. Typ. Max.

Clock frequency FCH X0, X1

—

1—10MHz

FCL X0A, X1A — 32.768 — kHz

Clock cycle time tHCYL X0, X1 100 — 1000 ns

tLCYL X0A, X1A — 30.5 — μs

Input clock pulse width

PWH

PWL X0 20 — — ns External clock

PWLH

PWLL X0A — 15.2 — μs Exter nal clock

Input clock rising/

falling time tCR

tCF X0 — — 10 ns External clock

0.2

V 0.2

2.0

0.2

VCC

OFF

MB89630R Series

34 DS07-12531-4E

0.2

0.8

X0 0.2

0.8

0.2

X0 X1

FCH

X0 X1

When a crystal

ceramic reasonator is used When an external clock is used

Open

HCYL

• Main clock timing condition

• Main clock configurations

X0A

X0A X1A

Open

0.2

0.8

0.2

0.8

0.2

LCYL

WLH

WLL

When a crystal

ceramic reasonator is used When an external clock is used

• Subclock timing condition

• Subclock configurations

MB89630R Series

DS07-12531-4E 35

(4) Instruction Cycle

Note: Operating at 10 MHz, the cycle varies with the set execution time.

(5) Clock Output Timing (VCC = 5.0 V±10%, AVSS = VSS= 0.0 V, TA = –40°C to +85°C)

* :For information on tinst, see “(4) Instruction Cycle”.

Parameter Symbol Value (typical) Unit Remarks

Instruction cycle

(minimum execution time) tinst

4/FCH, 8/FCH, 16/FCH, 64/FCH μs(4/FCH) tinst = 0.4 μs, operating at

FCH = 10 MHz

2/FCL μstinst = 61.036 μs, operating at

FCL = 32.768 kHz

Parameter Symbol Pin

name Condition Value Unit Remarks

Min. Max.

Cycle time tCYC CLK —1/2 tinst*—μs

CLK ↑ → CLK ↓tCHCL CLK 1/4 tinst* – 70 ns 1/4 tinst*μs

CLK 2.4 V 2.4 V

0.8 V

tCYC

tCHCL

MB89630R Series

36 DS07-12531-4E

(6) Bus Read Timing

(VCC = 5.0 V±10%, 10 MHz, AVSS = VSS= 0.0 V, TA = –40°C to +85°C)

* :For information on tinst, see “(4) Instruction Cycle”.

Parameter Symbol Pin name Condition Value Unit Remarks

Min. Max.

Valid address → RD ↓ time tAVRL RD, A15 to A08,

AD7 to AD0

—

1/4 tinst*– 64 ns —μs

RD pulse width tRLRH RD 1/2 tinst*– 20 ns —μs

Valid address → data read

time tAVDV AD7 to AD0,

A15 to A08 1/2 tinst*200μsNo wait

RD ↓ → data read time tRLDV RD, AD7 to AD0 1/2 tinst*– 80 ns 120 μsNo wait

RD ↑ → data hold time tRHDX AD7 to AD0,

RD 0—μs

RD ↑ → ALE ↑ time tRHLH RD, ALE 1/4 tinst*– 40 ns —μs

RD ↑ → address loss time tRHAX RD, A15 to A08 1/4 tinst*– 40 ns —μs

RD ↓ → CLK ↑ time tRLCH RD, CLK 1/4 tinst*– 40 ns —μs

CLK ↓ → RD ↑ time tCLRH 0—ns

RD ↓ → BUFC ↓ time tRLBL RD, BUFC –5 — μs

BUFC ↑ → valid address

time tBHAV A15 to A08,

AD7 to AD0,

BUFC 5—μs

BUFC

A15 to A08

AD7 to AD0

ALE

CLK

0.8 V

2.4 V

0.8V

2.4V

0.8 V

2.4 V

0.8 V

2.4 V

0.8 V

2.4 V

0.8 V

2.4 V

0.3 V

0.7 V

0.3 V

0.7 V

RHDX

CLRH

RLBL

BHAV

RHLH

AVDV

RLCH

RHAX

RLDV

RLRH

AVRL

MB89630R Series

DS07-12531-4E 37

(7) Bus Write Timing

(VCC = 5.0 V±10%, FCH = 10 MHz, AVSS = VSS= 0.0 V, TA = –40°C to +85°C)

*1: For information on tinst, see “(4) Instruction Cycle”.

*2: This characteristics are also applicable to the bus read timing.

Parameter Symbol Pin name Condition Value Unit Remarks

Min. Max.

Valid address → ALE ↓ time tAVLL AD7 to AD0,

ALE

A15 to A08

—

1/4 tinst*1 – 64 ns*2—μs

ALE ↓ time → address loss

time tLLAX 5—ns

Valid address → WR ↓ time tAVWL WR, ALE 1/4 tinst*1 – 60 ns*2—μs

WR pulse width tWLWH WR 1/2 tinst*1 – 20 ns*2—μs

Write data → WR ↑ time tDVWH AD7 to AD0, WR 1/2 tinst*1 – 60 ns*2—μs

WR ↑ → address loss time tWHAX WR, A15 to A08 1/4 tinst*1 – 40 ns* 2—μs

WR ↑ → data hold time tWHDX AD7 to AD0, WR 1/4 tinst*1 – 40 ns*2—μs

WR ↑ → ALE ↑ time tWHLH WR, ALE 1/4 tinst*1 – 40 ns*2—μs

WR ↓ → CLK ↑ time tWLCH WR, CLK 1/4 tinst*1 – 40 ns*2—μs

CLK ↓ → WR ↑ time tCLWH 0—ns

ALE pulse width tLHLL ALE 1/4 tinst*1 – 35 ns*2—μs

ALE ↓ → CLK ↑ time tLLCH ALE,CLK 1/4 tinst*1 – 30 ns*2—μs

A15 to A08

AD7 to AD0

ALE

CLK

WR 0.8V

0.8 V

2.4 V

0.8 V

2.4 V

0.8 V

2.4 V

0.8 V

2.4 V

0.8 V

2.4 V

tCLWH

0.8 V

2.4 V

0.8 V

2.4 V

2.4 V 0.8 V

0.8 V

2.4 V

tLLAX

tLHLL tLLCH

tAVLL

tDVWH tWHDX

tWHAX

tWLCH

tAVWL

tWHLH

tWLWH

MB89630R Series

38 DS07-12531-4E

(8) Ready Input Timing

(VCC = 5.0 V±10%, FCH = 10 MHz, AVSS = VSS= 0.0 V, TA = –40°C to +85°C)

* :This characteristics are also applicable to the read cycle.

Parameter Symbol Pin name Condition Value Unit Remarks

Min. Max.

RDY valid → CLK ↑ time tYVCH RDY, CLK — 60 — ns *

CLK ↑ → RDY loss time tCHYX 0—ns*

A15 to A08

AD7 to AD0

ALE

CLK

RDY

2.4 V 2.4 V

tYVCH tCHYX

Address Data

Note: The bus cycle is also extended in the read cycle in the same manner.

MB89630R Series

DS07-12531-4E 39

(9) Serial I/O Timing (VCC = 5.0 V±10%, FCH = 10 MHz, AVSS = VSS= 0.0 V, TA = –40°C to +85°C)

* :For information on tinst, see “(4) Instruction Cycle”.

Parameter Symbol Pin name Condition Value Unit Remarks

Min. Max.

Serial clock cycle time tSCYC SCK1, UCK1,

UCK2

Internal

shift clock

mode

2 tinst*—μs

SCK1 ↓ → SO1 time

UCK1 ↓ → UO1 time

UCK2 ↓ → UO2 time tSLOV SCK1, SO1

UCK1, UO1

UCK2, UO2 –200 200 ns

Valid SI1 → SCK1 ↑

Valid UI1 → UCK1 ↑

Valid UI2 → UCK2 ↑ tIVSH SI1, SCK1

UI1, UCK1

UI2, UCK2 1/2 tinst*—μs

SCK1 ↑ → valid SI1 hold time

UCK1 ↑ → valid UI1 hold time

UCK2 ↑ → valid UI2 hold time tSHIX SCK1, SI1

UCK1, UI1

UCK2, UI2 1/2 tinst*—μs

Serial clock “H” pulse width tSHSL SCK1, UCK1,

UCK2

External

shift clock

mode

1 tinst*—μs

Serial clock “L” pulse width tSLSH SCK1, UCK1,

UCK2 1 tinst*—μs

SCK1 ↓ → SO1 time

UCK1 ↓ → UO1 time

UCK2 ↓ → UO2 time tSLOV SCK1, SO1

UCK1, UO1

UCK2, UO2 0 200 ns

Valid SI1 → SCK1 ↑

Valid UI1 → UCK1 ↑

Valid UI2 → UCK2 ↑ tIVSH SI1, SCK1

UI1, UCK1

UI2, UCK2 1/2 tinst*—μs

SCK1 ↓ → valid SI1 hold time

UCK1 ↓ → valid UI1 hold time

UCK2 ↓ → valid UI2 hold time tSHIX SCK1, SI1

UCK1, UI1

UCK2, UI2 1/2 tinst*—μs

MB89630R Series

40 DS07-12531-4E

2.4 V

0.8 V 0.8 V

tSLOV

0.8 V

2.4 V

0.2 VCC

0.8 VCC

0.2 VCC

0.8 VCC

SI1

UI1

UI2

SCK1

UCK1

UCK2

0.8 VCC

0.2 VCC

0.8 VCC

tSLOV

0.8 V

2.4 V

0.2 VCC

0.8 VCC

0.2 VCC

0.8 VCC

0.2 VCC

tSCYC

tIVSH tSHIX

tSLSH tSHSL

tIVSH tSHIX

SO1

UO1

UO2

SI1

UI1

UI2

SCK1

UCK1

UCK2

SO1

UO1

UO2

• Internal shift clock mode

• External shift clock mode

MB89630R Series

DS07-12531-4E 41

(10) Peripheral Input Timing

(VCC = 5.0 V±10%, AVSS = VSS = 0.0 V, TA = –40°C to +85°C)

* :For information on tinst, see “(4) Instruction Cycle”.

Parameter Symbol Pin name Value Unit Remarks

Min. Max.

Peripheral input “H” pulse width 1 tILIH1 PWC, INT0 to INT3,EC 2 tinst*— μs

Peripheral input “L” pulse width 1 tIHIL1 2 tinst*— μs

Peripheral input “H” pulse width 2 tILIH2 ADST 28 tinst*—μs A/D mode

Peripheral input “L” pulse width 2 tIHIL2 28 tinst*—μs A/D mode

Peripheral input “H” pulse width 3 tILIH3 ADST 28 tinst*—μsSense mode

Peripheral input “L” pulse width 3 tIHIL3 28 tinst*—μsSense mode

0.2 VCC

0.8 VCC

tIHIL1

PWC,

EC,

INT0 to INT3

0.2 VCC

tILIH1

ADST

0.8 VCC

0.2 VCC

0.8 VCC

tIHIL2

(tIHIL3)

0.2 VCC

tILIH2

(tILIH3)

0.8 VCC

MB89630R Series

42 DS07-12531-4E

5. A/D Converter Electrical Characteristics

(AVCC = VCC = 3.5 V to 6.0 V, FCH = 10 MHz, AVSS = VSS = 0.0 V, TA = –40°C to +85°C)

Parameter Symbol Pin

name Value Unit Remarks

Min. Typ. Max.

Resolution

——

——10bit

At AVCC = VCC

Linearity error — — ±2.0 LSB

Differential linearity error — — ±1.5 LSB

Total error — — ±3.0 LSB

Zero transition voltage VOT AN0 to

AN7

AVSS – 1.5 LSB AVSS + 0.5 LSB AVSS + 2.5 LSB V

Full-scale transition

voltage VFST AVR – 3.5 LSB AVR – 1.5 LSB AVR + 0.5 LSB V

Interchannel disparity —— —— 4LSB

A/D mode conversion time — 13.2 — μsAt 10 MHz

oscillation

Analog port input current IAIN AN0 to

AN7 ——10μA

Analog input voltage —0.0 — AVR V

Reference voltage —0.0 — AVCC V

Reference voltage

supply current IR—200⎯μAAVR = 5.0 V

MB89630R Series

DS07-12531-4E 43

6. A/D Converter Glossary

• Resolution

Analog changes that are identifiable with the A/D converter

• Linearity error

The de viation of the straight line connecting the z ero transition point (“00 0000 0000” ↔ “00 0000 0001”) with

the full-scale transition point (“11 1111 1110” ↔ “11 1111 1111”) from actual conversion characteristics

• Differential linearity error

The deviation of input voltage needed to change the output code by 1 LSB from the theoretical value

• Total error (unit: LSB)

The difference between theoretical and actual conversion values caused by the zero transition error, full-scale

transition error, linearity error, quantization error, and noise

(Continued)

0.5 LSB

1 LSB

Analog input

AVSS

1.5 LSB

Theoretical I/O characteristics

3FF

3FE

3FD

004

003

002

001

AVR

Theoretical value

Analog input

AVSS

VNT

Actual conversion

value

Total error

3FF

3FE

3FD

004

003

002

001

AVR

{1 LSB × N + 0.5 LSB}

VFST

VOT Actual conversion

value

Digital output N total error = VNT – {1 LSB ×N + 0.5 LSB}

1 LSB

1 LSB = VFST –VOT

1022

Digital output

(V)

MB89630R Series

44 DS07-12531-4E

(Continued)

Analog input

AVSS

Linearity error

3FF

3FE

3FD

004

003

002

001

AVR

Theoretical value

Analog input

AVSS

VNT

V(N + 1)T

Actual conversion

value

Differential linearity error

N + 1

N - 1

N - 2

AVR

VNT

VOT (Actual measurement)

Actual conversion value

Digital output N differential linearity error = 1 LSB

V(N + 1)T - VNT

Digital output

Digital output N linearity error = VNT - {1 LSB ×N + VOT }

1 LSB- 1

{1 LSB × N + VOT}

Actual conversion

value

VFST

(Actual

measurement)

Theoretical value

Analog input

AVSS AVSS

Zero transition error

004

003

002

001

Theoretical value

Analog input

Actual conversion

value

Full-scale transition error

AVR

Actual conversion value

Digital output

Actual conversion

value

Actual conversion

value

VOT (Actual measurement)

VFST

(Actual

measurement)

3FF

3FE

3FD

3FC

AVR

MB89630R Series

DS07-12531-4E 45

7. Notes on Using A/D Converter

• Input impedance of the analog input pins

The output impedance of the external circuit for the analog input must satisfy the following conditions.

If the output impedance of the exter nal circuit is too high, an analog voltage sampling time might be insufficient

(sampling time = 6 μs at 10 MHz oscillation.) Therefore, it is recommended to keep the output impedance of the

external circuit below 10 kΩ.

•Error

The smaller the | AVR–AVss |, the greater the error would become relatively.

• Analog input circuit model

Analog input

Note: The values mentioned here should be used as a guideline.

ON1

ON2

Converter

RON2RON1

Approx. 1.5 kΩ

Approx. 60 pF

Approx. 4 pF

MB89630R Series

46 DS07-12531-4E

■CHARACTERISTICS EXAMPLE

(1) “L” Level Output Voltage (2) “H” Level Output Voltage

(3) “H” Level Input Voltage/“L” Level Input (4) “H” Level Input Voltage/“L” Level Input

Voltage (CMOS Input) Voltage (Hysteresis Input)

VIHS: Threshold as the input voltage in hysteresis

VILS: Threshold as the input voltage in hysteresis

characteristics is set to “H” level

characteristics is set to “L” level

010123456789

0.1

0.2

0.3

0.4

0.5

VOL (V) VCC = 4.0 V

VCC = 3.0 V

VCC = 5.0 V

VCC = 6.0 V

IOL (mA)

OL vs.

TA = +25°C

0.0

1.0

VCC - VOH (V)

VCC = 2.5 V

VCC = 3.0 V

VCC = 4.0 V

VCC = 5.0 V

VCC = 6.0 V

IOH (mA)

- V

vs. I

0.9

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

0.0 –0.5 –1.0 –1.5 –2.0 –2.5 –3.0

TA = +25°C

0123456 7

VCC (V)

5.0

VIN (V) VIN vs. VCC

4.5

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

0.0

TA = +25°C

0123456 7

VCC (V)

5.0

VIN (V) VIN vs. VCC

4.5

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

0.0

VIHS

VILS

TA = +25°C

MB89630R Series

DS07-12531-4E 47

(Continued)

(5) Power Supply Current (External Clock)

ICC (mA)

VCC (V)

2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5

Divide by 8

Divide by 16

Divide by 64

(ICC2)

TA = +25°C

FCH = 10MHz

CC1

vs. V

, I

CC2

vs. V

CC ICCS (mA)

VCC (V)

2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5

Divide by 8

Divide by 16

Divide by 64

(ICCS2)

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

4.5

5.0

TA = +25°C

FCH = 10MHz

CCS1

vs. V

, I

CCS2

vs. V

ICCL (μA)

VCC (V)

2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5

100

120

140

160

180

200 TA = +25°C

CCL

vs. V

CC ICCLS (μA)

VCC (V)

2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5

50 TA = +25°C

CCLS

vs. V

Divide by 4

(ICC1)

Divide by 4

(ICCS1)

MB89630R Series

48 DS07-12531-4E

(Continued)

(6) Pull-up Resistance

I CCT (μA)

V CC (V)

2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5

20 TA = +25°C

CCT

vs. V

CC I CCH (μA)

V CC (V)

2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5

0.2

0.4

0.6

0.8

1.0

1.2

1.4

1.6

1.8

2.0 TA = +25°C

CCH

vs. V

R PULL vs. V CC

234 5 6

R PULL (kΩ)

10 1

100

1000 TA = +25°C

V CC (V)

MB89630R Series

DS07-12531-4E 49

■MASK OPTIONS

* :For P50 to P53, fixed to "Without pull-up resistor."

No.

Part number MB89635R

MB89636R

MB89637R MB89P637 MB89PV630

Specifying procedure Specify when

ordering

masking Set with EPROM

programmer Setting not possible

1Pull-up resistors

P00 to P07, P10 to P17,

P30 to P37, P40 to P43,

P50 to P53, P72 to P74

Selectable by

pin Can be set per pin* Fixed to “without pull-up

resistor”

2Power-on reset selection

With power-on reset

Without power-on reset Selectable Setting possible Fixed to “with power-on reset”

Selection of the main clock

oscillation stabilization time

(at 10 MHz)

218/FCH (Approx. 26.2 ms)

217/FCH (Approx. 13.1 ms)

214/FCH (Approx. 1.6 ms)

24/FCH (Approx. 1.6 μs)

FCH : Main clock frequency

Selectable Setting possible Fixed to 218/FCH

(Approx. 26.2 ms)

4Reset pin output

Reset output provided

No reset output Selectable Setting possible Fixed to “with reset output”

5Single/dual-clock system option

Single clock

Dual clock Selectable Setting possible MB89PV630-101 Single-clock system

MB89PV630-102 Dual-clock systems

MB89630R Series

50 DS07-12531-4E

■ORDERING INFORMATION

Part number Package Remarks

MB89635RP-SH

MB89636RP-SH

MB89637RP-SH

MB89P637P-SH

64-pin Plastic SH-DIP

(DIP-64P-M01)

MB89635RPF

MB89636RPF

MB89637RPF

MB89P637PF

64-pin Plastic QFP

(FPT-64P-M06)

MB89635RPMC

MB89636RPMC

MB89637RPMC 64-pin Plastic QFP

(FPT-64P-M23)

MB89PV630-101CF

MB89PV630-102CF 64-pin Ceramic MQFP

(MQP-64C-P01)

MB89PV630-101C

MB89PV630-102C 64-pin Ceramic MDIP

(MDP-64C-P02)

MB89630R Series

DS07-12531-4E 51

■PACKAGE DIMENSIONS

Please confirm the latest Package dimension by following URL.

http://edevice.fujitsu.com/package/en-search/

(Continued)

64-pin plastic SH-DIP Lead pitch 1.778mm(70mil)

Package width ×

package length 17 × 58 mm

Sealing method Plastic mold

Mounting height 5.65 mm MAX

64-pin plastic SH-DIP

(DIP-64P-M01)

2001-2008 FUJITSU MICROELECTRONICS LIMITED D64001S-c-4-6

58.00

+0.22

–0.55 +.009

–.022

2.283

17.00±0.25

(.669±.010)

3.30

+0.20

–0.30

.130

–.012

+.008

+.028

–.008

.195

–0.20

+0.70

4.95

+.016

–.008

.0543

–0.20

+0.40

1.3781.778(.0700) 0.47±0.10

(.019±.004) 1.00

+0.50

–0

.039

–.0

+.020

–.007

.028

–0.19

+0.50

0.70

19.05(.750)

(.011±.004)

0.27±0.10

0~15

INDEX-2

INDEX-1

0.25(.010)

Dimensions in mm (inches).

Note: The values in parentheses are reference values.

Note: Pins width and pins thickness include plating thickness.

MB89630R Series

52 DS07-12531-4E

Please confirm the latest Package dimension by following URL.

http://edevice.fujitsu.com/package/en-search/

(Continued)

64-pin plastic QFP Lead pitch 1.00 mm

Package width ×

package length 14 × 20 mm

Lead shape Gullwing

Sealing method Plastic mold

Mounting height 3.35 mm MAX

Code

(Reference) P-QFP64-14×20-1.00

64-pin plastic QFP

(FPT-64P-M06)

2003-2008 FUJITSU MICROELECTRONICS LIMITED F64013S-c-5-6

0.20(.008)

18.70±0.40

(.736±.016)

14.00±0.20

(.551±.008)

1.00(.039)

INDEX

0.10(.004)

119

3351

20.00±0.20(.787±.008)

24.70±0.40(.972±.016)

0.42±0.08

(.017±.003)

0.17±0.06

(.007±.002)

0~8

1.20±0.20

(.047±.008)

3.00

+0.35

–0.20

(Mounting height)

.118

+.014

–.008

0.25

+0.15

–0.20

.010

+.006

–.008

(Stand off)

Details of "A" part

"A" 0.10(.004)

Dimensions in mm (inches).

Note: The values in parentheses are reference values.

Note 1) * : These dimensions do not include resin protrusion.

Note 2) Pins width and pins thickness include plating thickness.

Note 3)Pins width do not include tie bar cutting remainder.

MB89630R Series

DS07-12531-4E 53

Please confirm the latest Package dimension by following URL.

http://edevice.fujitsu.com/package/en-search/

(Continued)

64-pin plastic LQFP Lead pitch 0.65 mm

Package width ×

package length 12.0 × 12.0 mm

Lead shape Gullwing

Sealing method Plastic mold

Mounting height

1.70 mm MAX

Code

(Reference) P-LFQFP64-12×12-0.65

64-pin plastic LQFP

(FPT-64P-M23)

2003 FUJITSU LIMITED F64034S-c-1-1

0.65(.026)

0.10(.004)

116

3249

3348

*12.00±0.10(.472±.004)SQ

14.00±0.20(.551±.008)SQ

INDEX

0.32±0.05

(.013±.002)

0.13(.005)

0.145±0.055

(.0057±.0022)

"A"

.059

–

.004

+.008

–

0.10

+0.20

1.50

0~8˚

0.25(.010)

(Mounting height)

0.50±0.20

(.020±.008)

0.60±0.15

(.024±.006)

0.10±0.10

(.004±.004)

Details of "A" part

(Stand off)

Dimensions in mm (inches).

Note: The values in parentheses are reference values

Note 1) * : These dimensions do not include resin protrusion.

Note 2) Pins width and pins thickness include plating thickness.

Note 3)Pins width do not include tie bar cutting remainder.

MB89630R Series

54 DS07-12531-4E

Please confirm the latest Package dimension by following URL.

http://edevice.fujitsu.com/package/en-search/

(Continued)

64-pin ceramic MQFP Lead pitch 1.00 mm

Lead shape Straight

Motherboard

materialCeramic

Mounted package

materialPlastic

64-pin ceramic MQFP

(MQP-64C-P01)

1994-2008 FUJITSU MICROELECTRONICS LIMITED M64004SC-1-4

15.58±0.20

(.613±.008)

16.30±0.33

(.642±.013)

18.70(.736)TYP

INDEX AREA

0.30(.012)

TYP

1.27±0.13

(.050±.005)

22.30±0.33

(.878±.013)

24.70(.972)

TYP

10.16(.400)

TYP

12.02(.473)

TYP14.22(.560)

TYP

18.12±0.20

(.713±.008)

1.27±0.13

(.050±.005) 0.30(.012)TYP

7.62(.300)TYP

9.48(.373)TYP

11.68(.460)TYP

0.50(.020)TYP 0.15±0.05

(.006±.002)

10.82(.426)

MAX

0.40±0.10

(.016±.004) .047

Ð.008

+.016

Ð0.20

+0.40

1.20

0.40±0.10

(.016±.004)

1.00±0.25

(.039±.010)

18.00(.709)

TYP

1.00±0.25

(.039±.010)

12.00(.472)TYP

.047

Ð.008

+.016

Ð0.20

+0.40

1.20

Dimensions in mm (inches).

Note: The values in parentheses are reference values.

MB89630R Series

DS07-12531-4E 55

(Continued)

Please confirm the latest Package dimension by following URL.

http://edevice.fujitsu.com/package/en-search/

64-pin ceramic MDIP Lead pitch 1.778mm (70mil)

Row spacing 19.05mm (750mil)

Motherboard

materialCeramic

Mounted

packing materialPlastic

64-pin ceramic MDIP

(MDP-64C-P02)

+0.13

–0.08

+.005

–.003

INDEX AREA

0°~9°

(.750±.012)

19.05±0.30

0.46

.018

(2.240±.025)

(.010±.002)

0.25±0.05

(.050±.010)

1.27±0.25

(.135±.015)

3.43±0.38

55.12(2.170)REF

(.035±.005)

0.90±0.13

(.070±.010)

1.778±0.25

10.16(.400)MAX

33.02(1.300)REF

(.100±.010)

2.54±0.25

(.738±.012)

18.75±0.30

TYP

15.24(.600)

56.90±0.64

1994-2008 FUJITSU MICROELECTRONICS LIMITED M64002SC-1-5

Dimensions in mm (inches).

Note: The values in parentheses are reference values.

MB89630R Series

56 DS07-12531-4E

■MAIN CHANGES IN THIS EDITION

The vertical lines marked in the left side of the page show the changes.

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49 ■ MASK OPTIONS Changed the explanation for "*" in "■ MASK OPTIONS".

MB89630R Series

DS07-12531-4E 57

MEMO

MB89630R Series

58 DS07-12531-4E

MEMO

MB89630R Series

DS07-12531-4E 59

MEMO

MB89630R Series

FUJITSU MICROELECTRONICS LIMITED

Shinjuku Dai-Ichi Seimei Bldg., 7-1, Nishishinjuku 2-chome,

Shinjuku-ku, Tokyo 163-0722, Japan

Tel: +81-3-5322-3329

http://jp.fujitsu.com/fml/en/

For further information please contact:

North and South America

FUJITSU MICROELECTRONICS AMERICA, INC.

1250 E. Arques Avenue, M/S 333

Sunnyvale, CA 94085-5401, U.S.A.

Tel: +1-408-737-5600 Fax: +1-408-737-5999

http://www.fma.fujitsu.com/

Europe

FUJITSU MICROELECTRONICS EUROPE GmbH

Pittlerstrasse 47, 63225 Langen, Germany

Tel: +49-6103-690-0 Fax: +49-6103-690-122

http://emea.fujitsu.com/microelectronics/

Korea

FUJITSU MICROELECTRONICS KOREA LTD.

206 Kosmo Tower Building, 1002 Daechi-Dong,

Gangnam-Gu, Seoul 135-280, Republic of Korea

Tel: +82-2-3484-7100 Fax: +82-2-3484-7111

http://kr.fujitsu.com/fmk/

Asia Pacific

FUJITSU MICROELECTRONICS ASIA PTE. LTD.

151 Lorong Chuan,

#05-08 New Tech Park 556741 Singapore

Tel : +65-6281-0770 Fax : +65-6281-0220

http://www.fmal.fujitsu.com/

FUJITSU MICROELECTRONICS SHANGHAI CO., LTD.

Rm. 3102, Bund Center, No.222 Yan An Road (E),

Shanghai 200002, China

Tel : +86-21-6146-3688 Fax : +86-21-6335-1605

http://cn.fujitsu.com/fmc/

FUJITSU MICROELECTRONICS PACIFIC ASIA LTD.

10/F., World Commerce Centre, 11 Canton Road,

Tsimshatsui, Kowloon, Hong Kong

Tel : +852-2377-0226 Fax : +852-2376-3269

http://cn.fujitsu.com/fmc/en/

Specifications are subject to change without notice. For further information please contact each office.

The contents of this document are subject to change without notice.

Customers are advised to consult with sales representatives before ordering.

The information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose

of reference to show examples of operations and uses of FUJITSU MICROELECTRONICS device; FUJITSU MICROELECTRONICS

does not warrant proper operation of the device with respect to use based on such information. When you develop equipment incorporating

the device based on such information, you must assume any responsibility arising out of such use of the information.

FUJITSU MICROELECTRONICS assumes no liability for any damages whatsoever arising out of the use of the information.

Any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license of the use

or exercise of any intellectual property right, such as patent right or copyright, or any other right of FUJITSU MICROELECTRONICS

or any third party or does FUJITSU MICROELECTRONICS warrant non-infringement of any third-party's intellectual property right or

other right by using such information. FUJITSU MICROELECTRONICS assumes no liability for any infringement of the intellectual

property rights or other rights of third parties which would result from the use of information contained herein.

The products described in this document are designed, developed and manufactured as contemplated for general use, including without

limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured

as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to

the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear

facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon

system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite).

Please note that FUJITSU MICROELECTRONICS will not be liable against you and/or any third party for any claims or damages arising

in connection with above-mentioned uses of the products.

Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by

incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current

levels and other abnormal operating conditions.

Exportation/release of any products described in this document may require necessary procedures in accordance with the regulations of

the Foreign Exchange and Foreign Trade Control Law of Japan and/or US export control laws.

The company names and brand names herein are the trademarks or registered trademarks of their respective owners.

Edited: Sales Promotion Department