INTEGRATED CIRCUITS DATA SEE TDA8703 8-bit high-speed analog-to-digital converter Product specification 1996 Aug 26 Supersedes data of April 1993 File under Integrated Circuits, |CO2 Philips Semiconductors PHILIPSPhilips Semiconductors errr rere errr reer 8-bit high-speed analog-to-digital converter Product specification TDA8703 FEATURES 8-bit resolution Sampling rate up to 40 MHz High signal-to-noise ratio over a large analog input APPLICATIONS * General purpose high-speed analog-to-digital conversion Digital TV, IDTV frequency range (7.1 effective bits at 4.43 MHz * Subscriber TV decoder full-scale input) required ORDERING INFORMATION Binary or two's complement 3-state TTL outpuis Overflow/underflow 3-state TTL output TTL compatible digital inputs Low-level AC clock input signal allowed Low analog input capacitance, no buffer amplifier Satellite TV decoders e Digital VCR. GENERAL DESCRIPTION The TDBA8703 is an 8-bit high-speed Analog-to-Digital Internal reference voltage generator Converter (ADC) for video and other applications. Power dissipation only 290 mW (typical) lt converts the analog input signal into 8-bit binary-coded digital words at a maximum sampling rate of 40 MHz. All digital inputs and outputs are TTL compatible, although a low-level AC clock inpui signal is allowed. No sample-and-hold circuit required. TYPE PACK AGE NUMBER NAME DESCRIPTION VERSION TDA8703 DIP24 plastic dual in-line package; 24 leads (600 mil} SOT101-1 TDA8703T S024 plastic small outline package; 24 leads; body width 7.6 mm SOT137-1 1996 Aug 26Philips Semiconductors Product specification 8-bit high-speed analog-to-digital converter TDA8703 QUICK REFERENCE DATA SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT Voca analog supply voltage 45 5.0 5.5 Vv Vecp digital supply voliage 45 5.0 5.5 Vv Voco output stages supply voltage 42 5.0 5.5 Vv leca analog supply current - 28 36 mA locp digital supply current - 19 25 mA loco output stages supply current - 11 14 mA ILE DC integral linearity error - - +1 LSB DLE DC differential linearity error - - +1/2 LSB AILE AC integral linearity error note 1 - - +2 LSB B 3 dB bandwidth note 23 fco_ = 40 MHz - 19.5 - MHz foikfeck = | maximum conversion rate note 3 40 - - MHz Prot total power dissipation - 290 415 mW Notes 1. Full-scale sinewave (fj = 4.4 MHz; foi; femk = 27 MHz}. 2. The -3 dB bandwidth is determined by the 3 dB reduction in the reconstructed output (full-scale signal at input). 3. The circuit has two clock inpuis GLK and CLK. There are four modes of operation: a) TTL (mode 1); CLK decoupled to DGND by a capacitor. CLK inputis TTL threshold voltage of 1.5 V and sampling on the LOW-to-HIGH transition of the input clock signal. b) TTL{mode 2); CLK decoupled to DGND by a capacitor. CLK inputis TTL threshold voltage of 1.5 V and sampling on the HIGH-to-LOW transition of the input clock signal. c) AC drive modes (modes 3 and 4); When driving the CLK input directly and with any AC signal of 0.5 V (peak-to-peak value) imposed on a DC level of 1.5 V, sampling takes place on the LOW-to-HIGH transition of the clock signal. When driving the CLK input with such a signal, sampling takes place on the HIGH-te-LOW transition. d) If one of the clock inputs is not driven, then it is recommended to decouple this input to DGND with a 100 nF capacitor. 1996 Aug 26Philips Semiconductors Product specification 8-bit high-speed analog-to-digital converter TDA8703 BLOCK DIAGRAM clock inputs . YOGA CLK CLK |Yocp | TG cE STABILIZER CLOCK DRIVER DEG ]5 TDA8703 TDA8703T VaTI9 MSB VIL8 analog ANALOG - TO - DIGITAL voltage input ! CONVERTER LATGHES TTL OUTPUTS data outputs LSB VRB |4 Yoco overflow / OER OW Ow TTL OUTPUT underflow output 3 20 AGND DGND MG AO? 5 analog ground digital ground Fig.1 Block diagram. 1996 Aug 26 4Philips Semiconductors Product specification 8-bit high-speed analog-to-digital converter TDA8703 PINNING SYMBOL |PIN DESCRIPTION D1 1 | data output; bit 1 BO 2 | data output; bit 0 (LSB) AGND 3 | analog ground Vap 4 | reference voltage bottom (decoupling) DEC 5 | decoupling input (internal stabilization loap decoupling) n.c. 6 | not connected Veca 7 | positive supply voltage for analog m C4 v 24] be circuits (+5 V) bo [2] [23] D3 VI 8 | analog voltage input AcNnD [3] [22] CE Vat 9 | reference voltage top (decoupling) Vas [4] fet] TC n.c. 10 | not connected vec [EI 20) DGND O/UF 11 | overflow/underflow data output y D7 12 | data output; bit 7 (MSB) " [El rpaszoa, [2] ooo D6 13 | data output; bit 6 voca [7] TPA878T Tig] Veco DS 14 | data outpui; bit 5 v (&] 17] GLK D4 15 | data output; bit 4 Var 5] 6] CLK CLK 16 | clock input ne. [10] 5] D4 CLK 17 | complementary clock input our Fa] Ha] Ds Vecp 18 Penis (a8 voltage for digital o7 [2 ra] bs Vcco 19 | positive supply voltage for output mieess stages (+5 V} DGND 20 | digital graund TC 21 | inputfor two's complement ouput (TTL level input, active LOW) CE 22 | chip enable input (TTL level input, active LOW) DS 23 | data output; bit 3 Fig.2 Pin configuration. D2 24 | data output; bit 2 1996 Aug 26 5Philips Semiconductors Product specification 8-bit high-speed analog-to-digital converter TDA8703 LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134). SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT Voca analog supply voltage -0.3 +7.0 Vv Vecp digital supply voltage -0.3 +7.0 Vv Voco output stages supply voliage -0.3 +7.0 Vv Veca Veep | supply voltage differences -1.0 +1.0 V Veco - Vecp | supply voltage differences -1.0 +1.0 V Veca- Vcco | supply voltage differences -1.0 +1.0 V Vu input voliage range referenced to AGND -0.3 +7.0 V Veik/VeLlk AC input voltage for switching note 1; referenced to DGND 2.0 V (peak-to-peak value) lo output current +10 mA Tstg storage temperature -55 +150 6 Tamb operating ambient temperature +70 C Tj junction ternperature +125 C Notes 1. The circuit has two clock inputs CLK and CLK. There are four modes of operation: a) TTL (mode 1); CLK decoupled to DGND by a capacitor. CLK inputis TTL threshold voltage of 1.5 V and sampling on the LOW-jo-HIGH transition of the input clock signal. b) TTL{mode 2}; CLK decoupled to DGND by a capacitor. CLK inputis TTL threshold voltage of 1.5 V and sampling on the HIGH-to-LOW transition of the input clock signal. c) AC drive modes (modes 3 and 4); When driving the CLK input directly and with any AC signal of 0.5 V (peak-to-peak value) imposed on a DC level of 1.5 V, sampling takes place on the LOW-to-HIGH transition of the clock signal. When driving the CLK input with such a signal, sampling takes place on the HIGH-te-LOW transition. d) If one of the clock inputs is not driven, then it is recommended to decouple this input ta DGND with a 100 nF capacitor. HANDLING Inpuis and outputs are protecied against electrostatic discharges in normal handling. However, to be totally safe, itis desirable to take normal precautions appropriate to hancling integrated circuits. THERMAL RESISTANCE SYMBOL PARAMETER VALUE UNIT Rihj-a fram junction to ambient in free air $0T101-1 55 K/W $OT137-1 75 K/AW 1996 Aug 26Philips Semiconductors Product specification 8-bit high-speed analog-to-digital converter TDA8703 CHARACTERISTICS Vecoa = V7 Va = 4.5 V to 5.5 Vi Vecp = Vig Vag = 4.5 V to 5.5 V; Veco = Vig - V29 = 4.5 V to 5.5 V; AGND and DGND shorted together; Veca - Vecp = -0.5 V to +0.5 V; Veco - Vecp = -0.5 V to 40.5 V; Veca Vecp = -0.5 V to 40.5 V; Tamb = 0 C to +70 C; unless otherwise specified (typical values measured at Voca = Vocp = Veco = V and Tamp = 25C). SYMBOL PARAMETER CONDITIONS MIN. | TYP. | MAX. | UNIT Supply Voca analog supply voltage 4.5 5.0 5.5 V Vecp digital supply voltage 4.5 5.0 5.5 V Veco oulpul stages supply voltage A2 5.0 5.5 V loca analog supply current - 28 36 mA lecp digital supply current - 19 25 mA loco output stage supply current all outputs LOW - 11 14 mA Inputs CLOCK INPUT CLK AND CLK (note 1; REFERENCED TO DGND) Vit LOW level input voltage 0 - 0.8 V Vin HIGH level input voltage 2.0 - Veco | V li LOW level input current VoukVer = 0.4 V -400 | - - HA lw HIGH level input current Vork/Verw = 0.4 V - - 100 HA VoikVork = Vccp - - 300 | pA Zj input impedance foikferk = 10 MHz - 4 - kQ C; input capacitance feikfene = 10 MHz - 4.5 - pF Voix Verk | AC input voliage for switching note 1;DC level=1.5V /|0.5 - 2.0 Vv (peak-to-peak value) TC AND CE (REFERENCED TO DGND) ViL LOW level input voltage 0 - 0.8 Vv Vin HIGH level input valtage 2.0 - Veep | V Iie LOW level input current Vii = 0.4 V 400 | - - HA hy HIGH level input current Vin=2.7V - - 20 HA VI (ANALOG INPUT VOLTAGE REFERENCED TO AGND) Vive) input voltage (bottom) 1.33 | 1.41 148 |V Vv) input voliage output code = 0 1.455 | 1.55 | 1.6385 | V Vosip} offset voltage (bottom) Vvioy Vane) 0.125 |- 0.155 | V Vviay input voltage (top) 3.2 3.36 /3.5 Vv Vviess) input voliage output code = 255 3.115 |3.26 | 3.385 | Vv Voscn offset voltage (top) Vyicn Vviess) 0.085 | - 0.115 | V Vvip-p) input voltage amplitude (peak-to-peak value) 1.66 (1.71 (1.75 |V liv LOW level input current Vywi=1.4V - 0 - HA lin HIGH level inpui current Vywi=3.6V 60 120 180 HA Z input impedance f, = 1 MHz - 10 - kQ C; input capacitance fi = 1 MHz - 14 - pF 1996 Aug 26Philips Semiconductors Product specification 8-bit high-speed analog-to-digital converter TDA8703 SYMBOL PARAMETER CONDITIONS MIN. | TYP. | MAX. | UNIT Reference resistance Rret | reference resistance | Ver to Vas |- | 220 | - | Q Outputs DIGITAL OUTPUTS (D7 - DO} (REFERENCED TO DGND) Vo. LOW level output voltage lo=1mA ) - 0.4 Vv Vou HIGH level output voliage lo =-0.4 mA 27 - Vecp | V loz output current in 3-state mode 0.4V<Vo< Vecp -20 - +20 HA Switching characteristics (note 2; see Fig.3) foikfenk maximum clock frequency | 40 | - | - | MHz Analog signal processing (fe_k = 40 MHz} B -3 dB bandwidth note 3 - 19.5 /- MHz Gq differential gain note 4 - 0.6 - % da differential phase nate 4 - 0.8 - deg i fundamental harmonics (full-scale) ff = 4.43 MHz - - a) dB fall harmonics (full-scale), all components f, = 4.43 MHz - 55 - dB SVRRI1 supply voltage ripple rejection note 5 - -28 |-25 dB SVRR2 supply voltage ripple rejection nate 5 - 1 2.5 %lV Transfer function ILE DC integral linearity error - - +1 LSB DLE DC differential linearity error - - +1/2 | LSB AILE AC integral linearity error note 6 - - +2 LSB EB effective bits f, = 4.43 MHz - 7.1 - bits Timing (note 7; see Figs 3 to 6 ferk = 40 MHz) las sampling delay - - 2 ns typ output hold time 6 - - ns tWLH output delay time LOW-to-HIGH transition | - 8 10 ns taHL output delay time HIGH-ta-LOW transition | - 16 20 ns ta7H 3-state output delay times enable-to-HIGH - 19 25 ns az 3-state output delay times enable-to-LOW - 16 20 ns tyuz 3-state output delay times disable-to-HIGH - 14 20 ns taLz 3-state output delay times disable-to-LOW - 9 12 ns 1996 Aug 26 8Philips Semiconductors Product specification 8-bit high-speed analog-to-digital converter TDA8703 Notes 1. The circuit has two clock inputs CLK and CLK. There are four modes of operation: a) TTL(mode 1); CLK decoupled to DGND by a capacitor. OLK inputis TTL threshold voliage of 1.5 V and sampling on the LOW-to-HIGH transition of the input clack signal. b) TTL{mode 2}; CLK decoupled to DGND by a capacitor. CLK inputis TTL threshold voltage of 1.5 V and sampling on the HIGH-to-LOW transition of the input clock signal. c) AC drive modes (modes 3 and 4); When driving the CLK input direcily and with any AC signal of 0.5 V (peak-to-peak value) imposed on a DC level of 1.5 V, sampling takes place on the LOW-to-HIGH transition of the clock signal. When driving the CLK input with such a signal, sampling takes place on the HIGH-to-LOW transition. d) If one of the clock inputs is not driven, then it is recommended to decouple this input to DGND with a 100 nF capacitor. 2. In addition to a good layout of the digital and analog ground, it is recommended that the rise and fall times of the clock must not be less than 2 ns. 3. The -3 dB bandwidth is determined by the 3 dB reduction in the reconstructed output (full-scale signal at the input). Low frequency ramp signal (Vyypp) = 1.8 V and f, = 15 KHz) combined with a sinewave inpul voliage (Vyipp) = 0.5 V, { = 4.43 MHz) at the input. 5. Supply voltage ripple rejection: a) SVRR1; variation of the input voltage producing output code 127 for supply voltage variation of 1 V: SVRR1 = 20 lag (AVyici27) / AVcca) b) SVRR; relative variation of the full-scale range of analog input for a supply voltage variation of 1 V: SVR2 = {A(Vviay Vvicessy) / (Vv) Vvie5sy)} + AVcca. Full-scale sinewave (fj = 4.4 MHz; foi; feng = 27 MHz}. Output data acquisition: a) Output data is available after the maximum delay of tgy, and tgp. 1996 Aug 26 9Philips Semiconductors Product specification 8-bit high-speed analog-to-digital converter TDA8703 Table 1 Output coding and input voltage (referenced to AGND; typical values) BINARY OUTPUT BITS TWO'S COMPLEMENT OUTPUT BITS STEP Vvupp | OfUF | D7 |D6 | D5 )D4 | D3 | D2 |D1 | DO | D7 | D6 | D5 | D4 | D3 | D2 | D1 | DO Underflow | <1.55 1 1 0 0 1.55 0 1 0 1 - 0 oO |O |G |0 0 0 0 1 1 0 254 . 0 1 1 1 1 1 1 1 0 |0 1 1 1 1 1 1 0 255 3.26 0 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 Overflow | >3.26 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 Table 2. Made selection Tc CE D7-D0 O/UF xt) 1 high impedance high impedance 0 0 active; twos complement active 1 aciive; binary active Note 1. X=don'tcare. DO-D? dataN-1 vi 1.3V CLK /\ t I sample N sample N + 1 sample N + 2 1.3V dataN dataN +1 IN 24V ~ *| tgp H + et THE Fig.3 Timing diagram. O4V MEAT OS 1996 Aug 26 10Philips Semiconductors Product specification 8-bit high-speed analog-to-digital converter TDA8703 CE level input aq4vVv ata Uj outputs yy ZZ. _l TdHz yl gt dZH ld Z tae MLBOS5- 1 Fig.4 3-state delay timing diagram. Vcco 2 ko Voco [ St 2 ko DO to D7 I Ge) @ DO to D7 a c J 19 PF I IN916 or ) ne IN3064 G 3 MG D651 Fig.6 Load circuit for timing measurement; data outputs (CE = LOW). 3-414 44H o = Oo MBBI55 see Table 3. 1 MHz; Vu = Qo Fig.6 Load circuit for timing measurement; 3-state outputs (CE: fj = 3 V); 1996 Aug 26 11Philips Semiconductors Product specification 8-bit high-speed analog-to-digital converter TDA8703 Table 3. Mode selection TIMING MEASUREMENT SWITCH $1 SWITCH S2 CAPACITOR ta7H open closed 15 pF tazL closed open 15 pF tgHz closed closed 5 pF taLz closed closed 5 pF INTERNAL PIN CONFIGURATIONS Yoco VOCA a a a D7 to Do . Vv v * 80) OU a a DGND AGND ~oee MGD92 Fig.? TTL data and overflow/underflow outputs. MiLB037 Fig.8 Analog inputs. Veco Ds | re ba I re DGND MG D93 Fig.9 CE (3-state) input. Vcb J a Tc ft +b >I a DGND MLB039 Fig.10 TC (two's complement) input. 1996 Aug 26 12Philips Semiconductors Product specification 8-bit high-speed analog-to-digital converter TDA8703 VGcA j x <& a Vat DEG ! x << AGND ! ! Mc Di 6e Fig.11 Veep; Vat and DEC. Vocpb ba * Vv ret CLK * 30 kid ~ 30 kad bd re DGND * + MCD1 89-17 Fig.12 CLK and CLK inputs. 1996 Aug 26 13Philips Semiconductors Product specification 8-bit high-speed analog-to-digital converter TDA8703 APPLICATION INFORMATION Additional application information will be supplied upon request (please quote number FTV/8901). 1 D1 og | 2 Do] 2 93 | 03 AGND | 3 a9 | CE V _ RB | 4 > LIC DEG] 5 q nc. 6 we ti PF , TDA8703 Voca TDA8703T A7 pF mS ear vi} 3 ; Vat] 9 ol 470 [pone nc. 710 $e O/UF] 11 44 [28 AGND D7 | 12 13 [28 MG A074 -7 CLK should be decoupled to the DGND with a 100 nF capacitor, if a TTL signal is used on CLK (see Chapter Characteristics, note 1). CLK and GLK can be used in a differential mode (see Chapter Characteristics, note 1). Vap and Vp7 are decoupling pins for the internal reference ladder; do not draw current from these pins in order to achieve good linearity. If itis required to use the TDA8703 in a parallel system configuration, the references (Vpp and V_z) of each TDA8703 can be connected together. Code 0 will be identical and code 255 will remain in the 1 LSB variation for each TDA8703. Analog and digital supplies should be separated and decoupled. Pins 6 and 10 should be connected to AGND in order to prevent noise influence. (1) tis recommended to decouple Veco through a 22 resistor especially when the output data of the TDA8703 interfaces with a capacitive GMOS load device. Fig.13 Application diagram. 1996 Aug 26 14Philips Semiconductors Product specification 8-bit high-speed analog-to-digital converter TDA8703 PACKAGE OUTLINES DIP 24: plastic dual in-line package; 24 leads (600 mil) $07T101-1 |~ seating plane 24 13 <M, Soo 7 ope pin 1 index LILILILILILILICILICICIci 1 12 0 5 10mm | anal! scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) 2 (1) A Ay As (3 a UNIT max. min. max. b by D E 4 L Me Mn w max. 17 | 053 | 032 | 320 | 144 3.9 | 15.80 | 17.15 mm 5.1 0.51 4.0 13 | 038 | 023 | 314 | 137 | 294 | 1524) 34 | asa4 | isgo | 075 | 22 0.066 | 0.021 0.013 1.26 0.56 0.10 060 0.15 0.62 0.68 0.01 0.087 inches | 0.20 | 0.020 | 016 | oo51 | o.015 | 0.009 | 124 | 054 | % 0.13 | 0.60 | 0.63 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE REFERENCES EUROPEAN VERSION IEC IEDEG FIAJ PROJECTION SOTIO1-1 051G02 MO-015AD } ae 33 ISSUE DATE 1996 Aug 26 15Philips Semiconductors 8-bit high-speed analog-to-digital converter Product specification TDA8703 $024: plastic small outline package; 24 leads; body width 7.56 mm $0T137-1 1996 Aug 26 Eb [a] < | x =) f x ee 2 2 2-2-2 + + ' \ - or" = = SoS cm 7 if A H-_==2 sala] oly | =[v@A ie 24 13 | \ oe hoe _ _ _ _ _ _ Ag > [" \ ' ms pin 1 index i Sh - aa aal Lp =a f HHHHH RYH HHA 1 | 12 detail X = , P 0 5 10mm I rn | scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) A UNIT | wax, At | Az | As | bp e | D]) EM] 6 | He L Lp | @ w y | 2%] 6 0.30 | 2.45 O49 | 0.32 | 15.6 7.6 10.65 14 1.1 0.9 mm 2.65 0.10 | 2.25 0.25 0.36 | 0.23 | 15.2 74 Ver 10.00 14 o4 1.0 0.25 | 0.25 o.1 04 ge o . 0.012 | 0.096 0.019 | 0.013 | 0.61 0.30 0.42 0.043 | 0.043 0.035 0 inches | 0.19 | 9'o04| 0.089 | 9-91 | g.014| 0.009] 0.60 | 0.29 | 9-89} o.39 | 9-959 | o.916 | 0.039) 2-01 | 9-01 | 0.004 | g'g1 Note 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. REFERENCES VERSION PROJECTION | ISSUE DATE IEC JEDEC EIAd Sette SOT137-1 075E05 MS-013AD oe on o4 16Philips Semiconductors Product specification 8-bit high-speed analog-to-digital converter TDA8703 SOLDERING Introduction There is no soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. However, wave soldering is not always suitable for surface mounied ICs, or for printed-circuits with high population densities. In these situations reflow soldering is often used. This text gives avery brief insight to a complex technology. Amore in-depth account cf soldering ICs can be found in our"IC Package Databook" (order code 9398 652 90011). DIP SOLDERING BY DIPPING OR BY WAVE The maximum permissible temperature of the solder is 260 C; solder at this temperature must not be in contact with the joint for more than 5 seconds. The total contact time of successive solder waves must not exceed 5 seconds. The device may be mounted up to the seating plane, but the temperature of the plastic body musi not exceed the specified maximum storage temperature (Tsig max). li the printed-circuit board has been pre-heated, forced cooling may be necessary immediately after soldering to keep the temperature within the permissible limit. REPAIRING SOLDERED JOINTS Apply a low voltage soldering iran (less than 24 V) to the lead(s) of the package, below the seating plane or not more than 2 mm above it. If the temperature of the soldering iron bit is less than 300 C it may remain in contact for up to 10 seconds. If the bit temperature is between 300 and 400 C, contact may be up to 5 seconds. so REFLOW SOLDERING Reflow saldering techniques are suitable for all SO packages. Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. 1996 Aug 26 Several techniques exist for reflowing; for example, thermal conduction by heated belt. Dwell times vary between 50 and 300 seconds depending on heating method. Typical reflow temperatures range from 215 to 250 C. Preheating is necessary to dry the paste and evaporate the binding agent. Preheating duration: 45 minutes at AB C. WAVE SOLDERING Wave soldering techniques can be used for all SO packages if the following conditions are observed: A double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used. The longitudinal axis of the package footprint must be parallel to the solder flow. The package footprint must incorporate solder thieves at the downstream end. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Maximum permissible solder ternperaiure is 260 C, and maximum duration of package immersion in solder is 10 seconds, if cooled to less than 150 C within 6 seconds. Typical dwell time is 4 seconds at 250 C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. REPAIRING SOLDERED JOINTS Fix the component by first soldering two diagonally- opposite end leads. Use only a low voltage saldering iron (less than 24 V) applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 C.Philips Semiconductors Product specification 8-bit high-speed analog-to-digital converter TDA8703 DEFINITIONS Data sheet status Objective specification This data sheet contains target or goal specifications for praduct development. Preliminary specification This data sheet contains preliminary data; supplementary data may be published later. Product specification This data sheet contains final product specifications. Limiting values Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134}. Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, itis advisory and does not form part of the specification. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. 1996 Aug 26 18