MB89680 - Fujitsu - Product.Network

DS07-12525-2E

FUJITSU SEMICONDUCTOR

DATA SHEET

8-bit Proprietary Microcontroller

CMOS

F2MC-8L MB89680 Series

MB89689/P689/W689/PV680

■OUTLINE

The MB89680 series is a line of single-chip microcontrollers. In addition to a compact instruction set, the

microcontrollers contain a variety of peripheral functions such as dual-clock control system, four operating speed

control stages, timers, PWM timer, a serial interface, a UART, an A/D conv erter, and an external interrupt.

■FEATURES

•F

2MC-8L family CPU core

• Dual-clock control system

• Maximum memory space: 64 Kbytes

• Minimum execution time: 0.5 µs/8 MHz

• Interrupt processing time: 4.5 µs/8 MHz

• I/O ports: max. 85 channels

• 21-bit timebase counter

• 8-bit PWM timer

• 8/16-bit timer

•UART

• Serial I/O with 1-byte buffer

• 8-bit A/D converter

• Pulse width counter

• Modem signal output

• External interrupts: 16 channels

• Power-on reset function

• Low-power consumption modes (subclock mode, watch mode, sleep mode, and stop mode)

• CMOS technology

■PACKAGE

100-pin Plastic QFP

(FPT-100P-M06)

100-pin Ceramic QFP

(FPT-100C-A02)

100-pin Ceramic MQFP

(MQP-100C-P01)

MB89680 Series

■PRODUCT LINEUP

* :Varies with conditions such as the operating frequency. (See section “■ ELECTRICAL CHARACTERISTICS.”)

MB89P689 MB89W689 MB89PV680

Classification Mass-produced

product

(mask ROM product) One-time PROM

product EPROM product Piggyback/

evaluation product

(for development)

ROM size 60 K × 8 bits

(internal mask ROM) 60 K × 8 bits

(int er nal PR OM) 60 K × 8 bits

(internal EPROM) 60 K × 8 bits

(external ROM)

RAM size 2.0 K × 8 bits

Instruction bit length 8 bits

Instruction length 1 byte to 3 bytes

Data bit length 1, 8, 16 bits

Number of instructions 136

Clock generator Built-in

Minimum execution time 0.5 µs/8 MHz to 8 µs/8 MHz, 61 µs/32.768 kHz

Interrupt processing time 4.5 µs/8 MHz to 72 µs/8 MHz, 562.5 µs/32.768 kHz

Ports

( ) indicate dual function

ports

Output ports (N-ch open-drain): 21 (8)

Output ports (CMOS): 8 (0)

I/O ports (N-ch open-drain): 8 (6)

I/O ports (CMOS): 48 (29)

Total: 85 (43)

8-bit PWM timer 8 bits × 1 channel

8/16-bit timer/counter 8 bits × 2 channels, or 16 bits × 1 channel

8-bit serial I/O With 1-byte buffer × 1 channel

8-bit A/D converter 8 bits × 8 channel s

UART Full-duplex double buffer

Transfer data length: 6 bits to 8 bits

8 baud rates selectability, external clock available

Pulse width counter 5-bit noise reduction circuit

Pulse edge detectable and selectable (rising, falling, and both edges)

Software modem

transmission circuit 1200-bps/2400-bps modem output

External interrupt 16 channels

Timebase timer 21 bits

Watch prescaler 15 bits

Standby mode Watch mode, subclock mode, sleep mode, and stop mode

Process CMOS

Power supply voltage* 2.2 V to 6.0 V 2.7 V to 6.0 V

EPROM for use MBM27C512-20TV

MB89689

Part number

Item

MB89680 Series

■PACKAGE AND CORRESPONDING PRO DUCTS

: Available × : Not available

Note: For more information about each package, see section “■ Package Dimensions.”

■DIFFERENCES AMONG PRO DUCTS

1. Memory Size

Before e valuating using the piggyback product, v erify its differences from the product that will actually be used.

2. Current Consumption

In the case of the MB89PV680, add the current consumed by the EPROM which is connected to the top socket.

When op erated at l ow speed, the pr oduct wi th an OTPROM or an E PROM will con sume more current t han

the product with a mask ROM.

However, the current consumption in sleep/stop modes is the same.

3. Mask Options

Functions that can be selected as options and how to designate these options vary by the product. Before using

options check section “■ Mask Options.” Take particular care on the following points:

• Options are fixed on the MB89PV680.

Package MB89689

MB89P689 MB89W689 MB89PV680

FPT-100P-M06 ××

FPT-100C-A02 ××

MQP-100C-P01 ××

MB89680 Series

■PIN ASSIGNMENT

(FPT-100P-M06)

(FPT-100C-A02)

(Top view)

1VCC 80

2X1A 79

3X0A 78

4MOD0 77

5MOD1 76

6X0 75

7X1 74

8VSS 73

9RST 72

10P00 71

11P01 70

12P02 69

13P03 68

14P04 67

15P05 66

16P06 65

17P07 64

18P10 63

19P11 62

20P12 61

21P13 60

22P14 59

23P15 58

24P16 57

25P17 56

26P20 55

27P21 54

28P22 53

29P23 52

30P24 51

P97/INL7

P96/INL6

P95/INL5

P94/INL4

P93/INL3

P92/INL2

P91/INL1

P90/INL0

P87

P86

P85

P84

P83

P82

P81

P80

P77

P76

P75/BSO2

P74/BSI2

P73/BSK2

VSS

P72/UO2

P71/UI2

P70/UCK2

P67/BSO1

P66/BSI1

P65/BSK1

P64

P63/MSKO

100

PA7/INT3

PA6/INT2

PA5/INT1

PA4/INT0

PA3/INLB

N.C.

AVR

(AVCC) VCC

P57/AN07

P56/AN06

P55/AN05

P54/AN04

P53/AN03

P52/AN02

P51/AN01

P50/AN00

(AVSS) VSS

PA2/INLA

PA1/INL9

PA0/INL8

P25

P26

P27

P40

P41

P42

P43

P44

P30/PWM

P31/BUZR

P32/MSKI

P33

P34

P35/UCK1

P36/UI1

P37/UO1

P60/TMO1

P61/TMO2

P62/TCLK

VCC

MB89680 Series

• Pin assignment on package top (MB89PV680 only)

N.C.: Internally connected. Do not use.

Pin no. Pin name Pin no. Pin name Pin no. Pin name Pin no. Pin name

101 N.C. 109 A2 117 N.C. 125 OE

102 A15 110 A1 118 O4 126 N.C.

103 A12 111 A0 119 O5 127 A11

104 A7 112 N.C. 120 O6 128 A9

105 A6 113 O1 121 O7 129 A8

106 A5 114 O2 122 O8 130 A13

107 A4 115 O3 123 CE 131 A14

108 A3 116 VSS 124 A10 132 VCC

(Top view)

(

MQP-100C-P01

)

N.C.

A10

N.C.

A11

A12

A15

N.C.

V CC

A14

A13

VCC

X1A

X0A

MOD0

MOD1

VSS

RST

P00

P01

P02

P03

P04

P05

P06

P07

P10

P11

P12

P13

P14

P15

P16

P17

P20

P21

P22

P23

P24

P97/INL7

P96/INL6

P95/INL5

P94/INL4

P93/INL3

P92/INL2

P91/INL1

P90/INL0

P87

P86

P85

P84

P83

P82

P81

P80

P77

P76

P75/BSO2

P74/BSI2

P73/BSK2

VSS

P72/UO2

P71/UI2

P70/UCK2

P67/BSO1

P66/BSI1

P65/BSK1

P64

P63/MSKO

101

132

VSS

N.C.

100

PA7/INT3

PA6/INT2

PA5/INT1

PA4/INT0

PA3/INLB

N.C.

AVR

(AVCC) VCC

P57/AN07

P56/AN06

P55/AN05

P54/AN04

P53/AN03

P52/AN02

P51/AN01

P50/AN00

(AVSS) VSS

PA2/INLA

PA1/INL9

PA0/INL8

P25

P26

P27

P40

P41

P42

P43

P44

P30/PWM

P31/BUZR

P32/MSKI

P33

P34

P35/UCK1

P36/UI1

P37/UO1

P60/TMO1

P61/TMO2

P62/TCLK

VCC

MB89680 Series

■PIN DESCRIPTION

(Continued)

*1: FPT-100P-M06, FPT-100C-A02

*2: MQP-100C-P01

Pin no. Pin name Circuit type Function

QFP*1, MQFP*2

CC — Power supply pin

2 X1A A Subclock crystal oscillator pins (32.768 kHz)

3X0A

4 MOD0 B Operating mode selection pins

Connect to VSS (GND) when using.

5MOD1

6 X0 A Main clock crystal oscillator pins (8 MHz)

7X1

SS — Power supply (GND) pin

9RST C Reset input pin

10 to 17 P00 to P07 D General-purpose I/O ports

18 to 25 P10 to P17 D General-purpose I/O ports

26 to 33 P20 to P27 F General-purpose output ports

34 to 38 P40 to P44 I General-purpose output ports

39 P30/PWM E General-purpose I/O port

Also serve as an 8-bit PWM.

40 P31/BUZR E General-purpose I/O port

Also serve as a buzzer output.

41 P32/MSKI E General-purpose I/O port

Also serve as a pulse width counter.

42,

43 P33,

P34 E General-purpose I/O ports

44,

45,

P35/UCK1,

P36/UI1,

P37/UO1

E General-purpose I/O ports

Also serve as a UART I/O 1.

47,

48,

P60/TMO1,

P61/TMO2,

P62/TCLK

E General-purpose I/O ports

Also serve as an 8/16-bit timer.

50 VCC — Power supply pin

51 P63/MSKO E General-purpose I/O port

Also serve as a modem output.

52 P64 E General-purpose I/O port

53,

54,

P65/BSK1,

P66/BSI1,

P67/BSO1

E General-purpose I/O ports

Also serve as a serial I/O 1 with 1-byte buffer.

MB89680 Series

(Continued)

*1: FPT-100P-M06, FPT-100C-A02

*2: MQP-100C-P01

Pin no. Pin name Circuit type Function

QFP*1, MQFP*2

56,

57,

P70/UCK2,

P71/UI2,

P72/UO2

H General-purpose I/O ports

Also serve as a UART I/O 2.

59 VSS — Power supply (GND) pin

60,

61,

P73/BSK2,

P74/BSI2,

P75/BSO2

H General-purpose I/O ports

Also serve as a serial I/O 2 with 1-byte buffer.

63,

64 P76,

P77 H General-purpose I/O ports

65 to 72 P80 to P87 I General-purpose output ports

73 to 80 P90/INL0 to

P97/INL7 E General-purpose I/O ports

External interrupt input is hysteresis input.

81 to 83 PA0/INL8 to

PA2/INLA E General-purpose I/O ports

External interrupt input is hysteresis input.

84 VSS (AVSS) — (A/D converter) power supply (GND) pin

85 to 92 P50/AN00 to

P57/AN07 G General-purpose I/O ports

Also serve as an analog input.

93 VCC (AVCC) — (A/D converter) power supply pin

94 AVR — A/D c onverter refer ence voltage input pin

95 N.C. — Internally connected pins

Be sure to leave them open.

96 to 100 PA3/INLB,

PA4/INT0 to

PA7/INT3

E General-purpose I/O ports

External interrupt input is hysteresis input.

MB89680 Series

■I/O CIRCUIT TYPE

(Continued)

Type Circuit Remarks

A • Main cl oc k (A 2)

(At an oscillation feedback resistor of approximately

1 MΩ/5.0 V)

• Subclock (A1)

(At an oscillation feedback resistor of approximately

4.5 MΩ/5.0 V

* The subclock circuit in the MB89PV680

contains no oscillation feedback resistor.

C • At an output pull-up resistor (P-ch) of appro ximately

50 kΩ/5.0 V

• Hysteresis input

D • CMOS output

• CMOS input

• Pul l-up resistor optional

E • CMOS output

• Hysteresis input

• Pul l-up resistor optional

X1, X1A

X0, X0A

Standby control signal

P-ch

N-ch

P-ch

N-ch

P-ch

N-ch

P-ch

MB89680 Series

(Continued)

Type Circuit Remarks

F • CMOS output

G • N-ch open-drain output

• Analog input

H • N-ch open-drain output

• Hysteresis input

• Pul l-up resistor optional

I • N-ch open-drain output

• Pul l-up resistor optional

P-ch

N-ch

P-ch

N-ch

Analo

input

N-ch

P-ch

N-ch

P-ch

MB89680 Series

■HANDLING DEVICES

1. Pre venting Latchup

Latchup ma y occur on CMOS ICs if voltage higher than VCC or lower than VSS is applied to input and output pins

other than medium- and high-voltage pins or if higher than the voltage which shows on “1. Absolute Maximum

Ratings” in section “■ Electrical Characteristics” is applied between VCC and VSS.

When latchup occurs, power supply current increases rapidly and might thermally damage elements. When

using, take great care not to exceed the absolute maximum ratings.

Also, tak e care to prev ent the analog power supply (AVCC and AVR) and analog input from exceeding the digital

power supply (VCC) when the analog system power supply is turned on and off.

2. Treatment of Unused Input Pins

Leaving unused input pins open could cause malfunctions . They should be connected to a pull-up or pull-do wn

resistor.

3. Treatment of Power Supply Pins on Microcontrollers with A/D and D/A Conver ters

Connect to be AVCC = DAVC = VCC and AVSS = AVR = VSS even if the A/D and D/A converters are not in use.

4. Treatment of N.C. Pins

Be sure to leave (internally connected) N.C. pins open.

5. Power Supply Voltage Fluctuations

Although VCC power supply voltage is assured to operate within the rated range, a rapid fluctuation of the voltage

could cause malfunctions, even if it occurs within the rated range. Stabilizing voltage supplied to the IC is therefore

important. As stabilization guidelines, it is recommended to control power so that VCC ripple fluctuations (P-P

value) will be less than 10% of the standard VCC v alue at the commercial frequency (50 Hz to 60 Hz) and the

transient fluctuation r ate will be less than 0.1 V/ms at the time of a momentary fluctuation such as when power

is switched.

6. Precautions when Using an External Clock

When an ex ternal clock is used, oscillation stabilization time is required e v en for pow er-on reset (optional) and

wake-up from stop mode.

MB89680 Series

■PROGRAMMING TO THE EPROM ON THE MB89P689/W689

The MB89P689/W689 is an OTPROM version of the MP89680 series.

1. Features

• 60-Kbyte PROM on chip

• Options can be set using the EPROM programmer.

• Equivalent to the MBM27C1001 in EPR OM mode (when progr ammed with the EPROM programmer) and

supporting the 4-byte programming mode

2. Memory Space

Memory space in each mode such as 60-Kbyte PROM, option area is diagrammed below.

3. Programming to the EPROM

In EPROM mode, the MB89P689 functions equivalent to the MBM27C1001. This allows the PROM to be

programmed with a gener al-purpose EPR OM programmer (the electronic signature mode cannot be used) b y

using the dedi cated socket adapter.

When the operating R OM area f or a single chip is 60 Kbytes (1000H to FFFFH) the PROM can be programmed

as follows:

• Programming procedure

(1) Set the EPROM programmer to MBM27C1001.

(2) Load program data into the EPROM programmer at 1000H to FFFFH.

Load option data into addresses 0FE4H to 0FFCH of the EPR OM programmer. (F or information about each

corresponding option, see “8. Setting PROM Options.”)

(3) Program to 0FE4H to 0FFCH and 1000H to FFFFH with the EPROM programmer.

PROM

60 KB

0FFFFH

00000H

00FE4H

00080H

00880H

Option area

Single chip EPROM mode

(Corresponding addresses on the EPROM programmer)

I/O

RAM

2 KB

Not available

1FFFFH

00000H

PROM

60 KB

01000H01000H

0FFFFH

00FE4H

00FFCH

Not available

Option area

Address

MB89680 Series

4. Recommended Screening Conditions

High-temperature aging is recommended as the pre-assembly screening procedure for a product with a blanked

OTPROM microcomputer prog ram.

5. Programming Yield

All bits cannot be programmed at Fujitsu shipping test to a b lanked O TPROM microcomputer, due to its nature.

For this reason, a programming yield of 100% cannot be assured at all times.

6. MB89W689 Erasure

In order to clear all locations of their programmed contents, it is necessary to e xpose the internal EPROM to an

ultraviolet light source. A dosage of 10 W-seconds/cm2 is required to completely erase an internal EPROM. This

dosage can be obtained by exposure to an ultraviolent lamp (wa v elength of 2537 Angstroms (Å)) with intensity

of 12000µW/cm2 for 15 to 21 minutes. The internal EPROM should be about one inch from the source and all

filters should be removed from the UV light source prior to erasure.

It is important to note that the internal EPROM and similar de vices, will erase with light sources having wave-

lengths shorter than 4000 Å. Although erasure time will be much longer than with UV source at 2537 Å,

nevertheless the exposure to fluorescent light and sunlight will eventually erase the internal EPROM, and

exposure to them should be prevented to realize maximum system reliability. If used in such an environment,

the package windows should be covered by an opaque label or substance.

Program, verify

Data verification

Assembly

Aging

+150°C, 48 Hrs.

MB89680 Series

7. EPR OM Programmer Socket Adapter

Inquiry: Sun Hayato Co., Ltd.: TEL: (81)-3-3986-0403

FAX: (81)-3-5396-9106

8. Setting PROM Options

The programming procedure is the same as that for the program data. Options can be set by programming

values at the addresses shown on the memory map . The relationship between bits and options is shown on the

following bit map:

• PROM option bit map

Notes: •Note that the option setting area addresses are at intervals of four addresses to support the 4-byte

programming mode.

•In three bytes between adjacent setup addresses, the value written to the preceding setup address is

mirrored. Be sure to set the same data in the programmer.

•Each bit is set to ‘1’ as the initialized value.

Part no. MB89P689PF

Package QFP-100

Compatible

socket adapter

Sun Hayato Co.,

Ltd.

ROM-100QF-32DP-8LA

Address Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

00FE4H

Vacancy

Readable

and writab le

Vacancy

Readable

and writable

Vacancy

Readable

and writab le

Single/dual-

clock system

1: Dual clock

2: Single cloc k

Reset

output

1: Yes

0: No

Power-on

reset

1: Yes

0: No

Oscillation stabilization time

11 218/FCH 10 216/FCH

01 212/FCH 00 2 3/FCH

00FE8H

P07

Pull-up

1: No

0: Yes

P06

Pull-up

1: No

0: Yes

P05

Pull-up

1: No

0: Yes

P04

Pull-up

1: No

0: Yes

P03

Pull-up

1: No

0: Yes

P02

Pull-up

1: No

0: Yes

P01

Pull-up

1: No

0: Yes

P00

Pull-up

1: No

0: Yes

00FECH

P17

Pull-up

1: No

0: Yes

P16

Pull-up

1: No

0: Yes

P15

Pull-up

1: No

0: Yes

P14

Pull-up

1: No

0: Yes

P13

Pull-up

1: No

0: Yes

P12

Pull-up

1: No

0: Yes

P11

Pull-up

1: No

0: Yes

P10

Pull-up

1: No

0: Yes

00FF0H

P37

Pull-up

1: No

0: Yes

P36

Pull-up

1: No

0: Yes

P35

Pull-up

1: No

0: Yes

P34

Pull-up

1: No

0: Yes

P33

Pull-up

1: No

0: Yes

P32

Pull-up

1: No

0: Yes

P31

Pull-up

1: No

0: Yes

P30

Pull-up

1: No

0: Yes

00FF4H

P67

Pull-up

Readable

and writab le

P66

Pull-up

Readable

and writable

P65

Pull-up

Readable

and writab le

P64

Pull-up

1: No

0: Yes

P63

Pull-up

1: No

0: Yes

P62

Pull-up

1: No

0: Yes

P61

Pull-up

1: No

0: Yes

P60

Pull-up

1: No

0: Yes

00FF8H

P97

Pull-up

1: No

0: Yes

P96

Pull-up

1: No

0: Yes

P95

Pull-up

1: No

0: Yes

P94

Pull-up

1: No

0: Yes

P93

Pull-up

1: No

0: Yes

P92

Pull-up

1: No

0: Yes

P91

Pull-up

1: No

0: Yes

P90

Pull-up

1: No

0: Yes

00FFCH

PA7

Pull-up

1: No

0: Yes

PA6

Pull-up

1: No

0: Yes

PA5

Pull-up

1: No

0: Yes

PA4

Pull-up

1: No

0: Yes

PA3

Pull-up

1: No

0: Yes

PA2

Pull-up

1: No

0: Yes

PA1

Pull-up

1: No

0: Yes

PA0

Pull-up

1: No

0: Yes

MB89680 Series

■PROGRAMMING TO THE EPROM WITH PIGGYBACK/EVALUATION DEVICE

1. EPROM for Use

MBM27C512-20TV

2. Programming Socket Adapter

Inquiry: Sun Hayato Co., Ltd.: TEL: (81)-3-3986-0403

FAX: (81)-3-5396-9106

3. Memory Space

4. Programming to the EPROM

(1) Set the EPROM programmer to the MBM27C512.

(2) Load program data into the EPROM programmer at 1000H to FFFFH.

(3) Program to 1000H to FFFFH with the EPROM programmer.

Package Adapter socket part numb er

LCC-32 (Recta ngle) ROM-32LC-28DP -YG

External ROM

60 KB

FFFFH

0000H

0880H

0080H

0200H

MB89PV680Address

I/O

RAM

2 KB

1000H

0100H

MBM27C512

1000H

EPROM

60 KB

FFFFH

MB89680 Series

■BLOCK DIAGRAM

Timebase timer

CMOS I/O port 0

Main clock oscillator

(max 8 MHz)

RST

X0A

X1A

P00 to P07

P10 to P17

CMOS I/O port 2

P20 to P27

RAM

F2MC-8L

CPU

ROM

VCC ×2, VSS ×2

MOD0, MOD1, N.C.

AVCC, AVR, AVSS

Other pins

8-bit PWM timer

Buzzer output

Modem timer

UART

8-bit A/D

converter

CMOS I/O

8/16-bit timer

Modem output

N-ch open-drain I/O

N-ch open-drain output port 8

CMOS I/O

External interrupt 2

P30/PWM

P31/BUZR

P32/MSKI

P33

P34

P35/UCK1

P36/UI1

P37/UO1

P50/AN00

t o P57/AN07

P40 t o P44

P60/TMO1

P61/TMO2

P62/TCLK

P63/MSKO

P64

P65/BSK1

P66/BSI1

P67/BSO1

P70/UCK2

P71/UI2

P72/UO2

P73/BSK2

P74/BSI2

P75/BSO2

P76

P77

P80 t o P87

P90/INL0

t o P97/INL7

PA0/INL8

t o PA3/INLB

PA4/INT0

t o PA7/INT3

Reset circuit

(Watchdog)

Clock controller

Subclock o scillator

(32.768 kHz)

CMOS I/O port 1

Internal data bus

CMOS I/O

N-ch open-drain output

Port 5

N-ch open-drain output port 4

Port 6

8-bit serial I/O

with 1-byte buffer

Port 7Port 9 and port A

External interrupt 1

Port 3

MB89680 Series

■CPU CORE

1. Memory Space

The microcontrollers of the MB89680 series off er 64 Kbytes of memory f or storing all of I/O , data, and program

areas. The I/O area is located at the lowest address. The data area is provided immediately abo ve the I/O area.

The data area can be divided into register, stack, and direct areas according to the application. The program

area is located at exactly the opposite end of I/O area, that is, near the highest address. Provide the tab les of

interrupt reset vectors and vector call instructions toward the highest address within the program area. The

memory space of the MB89680 series is structured as illustrated below.

• Memory space

I/O

RAM

2.0 KB

ROM

60 KB

MB89689

I/O

RAM

2.0 KB

ROM

60 KB

MB89P689

MB89W689

I/O

RAM

2.0 KB

External ROM

60 KB

MB89PV680

0000H

FFFFH

0FFFH

1000H

087FH

0880H

01FFH

0200H

00FFH

0100H

007FH

0080H

0000H

FFFFH

0FFFH

1000H

087FH

0880H

01FFH

0200H

00FFH

0100H

007FH

0080H

0000H

FFFFH

0FFFH

1000H

087FH

0880H

01FFH

0200H

00FFH

0100H

007FH

0080H

Vacancy Vacancy Vacancy

MB89680 Series

2. Registers

The F2MC-8L family has two types of registers; dedicated registers in the CPU and general-purpose registers

in the memory. The follo wing dedicated registers are provided:

Program counter (PC): A 16-bit register for indicating the instruction stor age positions

Accumulator (A): A 16-bit temporary register for storing arithmetic operations, etc. When the

instruction is an 8-bit data processing instruction, the lower byte is used.

Temporary accumulator (T): A 16-bit register which performs arithmetic operations with the accumulator

When the instruction is an 8-bit data processing instruction, the lower byte is used.

Index register (IX): A 16-bit register for index modification

Extra pointer (EP): A 16-bit pointer for indicating a memory address

Stack pointer (SP): A 16-bit register for indicating a stack area

Program status (PS): A 16-bit register for storing a register pointer, a condition code

The PS can further be divided into higher 8 bits for use as a register bank pointer (RP) and the lower 8 bits f or

use as a condition code register (CCR). (See the diagram below.)

16 bits

: Program counter

: Accumulator

: Temporary accumulator

: Index register

: Extra pointer

: Stack pointer

: Program status

FFFDH

Indeterminate

I-flag = 0, IL1, 0 = 11

The other bit values are indeterminate.

Initial value

• Structure of the program status register

Vacancy

H I IL1, 0 N Z VC

RPPS

109876 321015 14 13 12 11

RP CCR

Vacancy Vacancy

MB89680 Series

The RP indicates the address of the register bank currently in use. The relationship between the pointer contents

and the actual address is based on the conversion rule illustrated below.

The CCR consists of bits indicating the results of arithmetic operations and the contents of transf er data and

bits for control of CPU operations at the time of an interrupt.

H-flag: Set to ‘1’ when a carry or a borrow from bit 3 to bit 4 occurs as a result of an arithmetic operation.

Cleared to ‘0’ otherwise. This flag is for decimal adjustment instructions.

I-flag: Interrupt is enabled when this flag is set to ‘1’. Interrupt is disab led when the flag is cleared to ‘0’.

Cleared to ‘0’ at the reset.

IL1, 0: Indicates the level of the interrupt currently allowed. Processes an interrupt only if its request level is

higher than the value indicated by this bit.

N-flag: Set to ‘1’ if the MSB becomes ‘1’ as the result of an arithmetic operation. Cleared to ‘0’ when the bit is

cleared to ‘0’.

Z-flag: Set to ‘1’ when an arithmetic operation results in 0. Cleared to ‘0’ otherwise.

V-flag: Set to ‘1’ if the complement on 2 overflows as a result of an arithmetic operation. Cleared to ‘0’ if the

overflow does not occur.

C-flag: Set to ‘1’ when a carry or a borro w from bit 7 occurs as a result of an arithmetic operation. Cleared to

‘0’ otherwise. Set to the shift-out value in the case of a shift instruction.

IL1 IL0 Interrupt level High-low

0 0 0 High

Low

01 1

10 2

11 3

• Rule for conversion of actual addresses of the general-purpose register area

“0”

↓

A15

“0”

↓

A14

“0”

↓

A13

“0”

↓

A12

“0”

↓

A11

“0”

↓

A10

“0”

↓

“1”

↓

Generated addresses

Lower OP codes

MB89680 Series

The follo wing general-purpose registers are provided:

General-purpose registers: An 8-bit register f or storing data

The general-purpose registers are 8 bits and located in the register banks of the memory. One bank contains

eight registers and up to a total of 32 banks can be used. The bank currently in use is indicated b y the register

bank pointer (RP).

• Register bank configuration

R 0

R 1

R 2

R 3

R 4

R 5

R 6

R 7

This address = 0100H + 2 × (RP)

Memory area

32 banks

MB89680 Series

■I/O MAP

(Continued)

Address Read/write Register name Register description

00H(R/W) PDR0 Port 0 data register

01H(W) DDR0 Port 0 data direction register

02H(R/W) PDR1 Port 1 data register

03H(W) DDR1 Port 1 data direction register

04H(R/W) PDR2 Port 2 data register

05H(Vacancy)

06H

07H(R/W) SYCC System clock control register

08H(R/W) SMC Standby control register

09H(R/W) WDTC Watchdog timer control register

0AH(R/W) TBTC Timebase timer control register

0BH(R/W) WPCR Watch prescaler control register

0CH(R/W) PDR3 Port 3 data register

0DH(R/W) DDR3 Port 3 data direction register

0EH(R/W) PDR4 Port 4 data register

0FH(R/W) BZCR Buzzer register

10H(R/W) PDR5 Port 5 data register

11H(Vacancy)

12H(R/W) PDR6 Port 6 data register

13H(R/W) DDR6 Port 6 data direction register

14H(R/W) PDR7 Port 7 data register

15H(Vacancy)

16H(R/W) PDR8 Port 8 data register

17H(Vacancy)

18H(R/W) PDR9 Port 9 data register

19H(R/W) DDR9 Port 9 data direction register

1AH(R/W) PDRA Port A data register

1BH(R/W) DDRA Port A data direction register

1CH(Vacancy)

1DH

1EH(R/W) CNTR PWM control register

1FH(W) COMR PW M co mpa re registe r

20H(Vacancy)

21H

22H(R/W) SBMR Serial mode register with 1 byte buffer

MB89680 Series

(Continued)

Note: Do not use (vacancies).

Address Read/write Register name Register description

23H(R/W) SBFR Serial flag register with 1 byte buffer

24H(W) SBUFW Serial buffer write register

(R) SBUFR Serial buffer read register

25H(R) SBDR Serial data register with 1 byte buffer

26H(R/W) T2CR Timer 2 control register

27H(R/W) T1CR Timer 1 control register

28H(R/W) T2DR Timer 2 data register

29H(R/W) T1DR Timer 1 data register

2AH(R/W) MODC Modem output control register

2BH(R/W) MODA Modem output data register

2CH(Vacancy)

2DH(R/W) ADC1 A/D converter control 1 register

2EH(R/W) ADC2 A/D converter control 2 register

2FH(R/W) ADCD A/D converter data register

30H(R/W) EIE1 External interrupt 1 enable register

31H(R/W) EIF1 External interr upt 1 flag r egister

32H(R/W) EIE2 External interrupt 2 enable register

33H(R/W) EIF2 External interr upt 2 flag r egister

34H(R/W) MDC1 Modem timer control 1 register

35H(R/W) MDC2 Modem timer control 2 register

36H(R) MLDH Modem timer “H” level data register

37H(R) MLDL Modem timer “L” level data register

38H(R/W) SMC UART serial mode control register

39H(R/W) SRC UART serial rate control register

3AH(R/W) SSD UART serial status and data register

3BH(R) SIDR UART serial input data register

3CH(W) SODR UART serial output data register

3DH(R/W) SSEL Serial I/O port switching register

3EH to 7BH(Vacancy)

7CH(W) ILR1 Interrupt level 1 setting register

7DH(W) ILR2 Interrupt level 2 setting register

7EH(W) ILR3 Interrupt level 3 setting register

7FH(Vacancy)

MB89680 Series

■ELECTRICAL CHARACTERISTICS

1. Absolute Maximum Ratings

(AVSS = VSS = 0.0 V)

* :Use AVCC and VCC set to the same voltage.

Take care so that AVCC does not exceed VCC, such as when power is turned on.

WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,

temperature, etc.) in excess of absolute maximum ratings. Do not ex ceed these ratings.

Parameter Symbol Value Unit Remarks

Min. Max.

Power supply voltage

VCC VSS – 0.3 VSS + 7.0 V

AVCC VSS – 0.3 VSS + 7.0 V Set VCC = AVCC*

AVR VSS – 0.3 VSS + 7.0 V AVR must not ex ce ed “AVCC +

0.3 V”.

Input voltage VIVSS – 0.3 V CC + 0.3 V Except P4, P7, P8

VIVSS – 0.3 VSS + 7.0 V P4, P7, P8

Output voltage V OVSS – 0.3 VCC + 0.3 V

“L” level maximum output

current IOL 20 mA Peak value

“L” level average output current IOLAV 10 mA Average value (operating current

× operating rate)

“L” level total maximum output

current ∑IOL 120 mA Peak value

“L” level total average output

current ∑IOLAV 40 mA Average value (operating current

× operating rate)

“H” level maximum output

current IOH –20 mA Peak value

“H” level average output current IOHAV –10 mA Av erage value (operating current

× operating rate)

“H” level total maximum output

current ∑IOH –60 mA Peak value

“H” level total average output

current ∑IOHAV –20 mA Av erage value (operating current

× operating rate)

Power consumption PD200 mW

Operating temperature TA–40 +85 °C

Storage temperature Tstg –55 +150 °C

MB89680 Series

2. Recommended Operating Conditions

(AVSS = VSS = 0.0 V)

* :This values vary with the operating frequency. See Figure 1.

Figure 1 indicates the operating frequency of the external oscillator at an instruction cycle of 4/FCH.

Since the operating voltage range is dependent of the instruction cycle, see minimum execution time if the

operating speed is switched using a gear.

Parameter Symbol Value Unit Remarks

Min. Max.

Power supply voltage

VCC,

AVCC 2.2* 6.0* V Normal operation assurance range*

(MB89689)

VCC,

AVCC 2.7* 6.0* V Normal operation assurance range*

(MB89P689/W689/PV680)

VCC,

AVCC 1.5 6.0 V Retains the RAM state in stop mode

A/D converter reference input

voltage AVR 0.0 AVCC V

Operating temperature TA–40 +85 °C

1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 10.0

Operating voltage (V)

Operation assurance range

Main clock operating frequency (MHz) (at an instruction cycle of 4/FCH)

Figure 1 Operating Voltage vs. Main Clock Operating Frequency

Analog accuracy assured in the

AVCC = 3.5 V to 6.0 V range

MB89680 Series

WARNING: Recommended operating conditions are normal operating ranges for the semiconductor device. All the

device’s electrical characteristics are warranted when operated within these ranges.

Alwa ys use semiconductor devices within the recommended operating conditions . Operation outside

these ranges may adversely affect reliability and could result in device failure.

No warranty is made with respect to uses, operating conditions, or combinations not represented on

the data sheet. Users considering application outside the listed conditions are advised to contact their

FUJITSU representative beforehand.

MB89680 Series

3. DC Characteristics

(AVCC = VCC = 5.0 V ±10%, AVSS = VSS = 0.0 V, TA = –40°C to +85°C)

(Continued)

Parameter Symbol Pin name Condition Value Unit Remarks

Min. Typ. Max.

“H” level input

voltage

VIH P0, P1

—

0.7 VCC —VCC + 0.3 V

VIHS P3, P6, P9, PA,

RST, MOD0,

MOD1, X0, X0A 0.8 VCC —VCC + 0.3 V

VIHS2 P7 0.8 VCC VSS + 7.0 V

“L” level input

voltage

VIL P0, P1 VSS − 0.3 —0.3 V

CC V

VILS P3, P6, P7, P9, PA,

RST, MOD0,

MOD1, X0, X0A VSS − 0.3 —0.2 V

CC V

Open-drain

output pin applied

voltage VDP4, P7, P8 VSS − 0.3 —VSS + 7.0 V

P5 VSS − 0.3 —VCC + 0.3 V

“H” level output

voltage VOH P0 to P3, P6, P9,

PA IOH = –2.0 mA 2.4 — — V

“L” level output

voltage VOL1 P0 to P4, P6 to P9,

PA IOL = 4.0 mA — — 0.4 V

VOL2 RST IOL = 4.0 mA — — 0.4 V

Input leaka ge

current (Hi - z

output leakage

current) ILI P0 to P9, PA,

MOD0, MOD1 0.45 V < VI <

VCC ——±5µA

Power supply

current

ICC VCC

FCH = 8 MHz

VCC = 5.0 V

Main clock

opration

Highest gear

speed

—1326mA

ICCS1 VCC

FCH = 8 MHz

VCC = 5.0 V

Main sleep

mode

Highest gear

speed

—4 8mA

ICCS2 VCC

FCH = 32.768 kHz

VCC = 3.0 V

Subclock

sleep mode —2550µA

ICCH1 VCC TA = +25°C

Subclock stop

mode —— 1µA

MB89680 Series

(Continued)

(AVCC = VCC = 5.0 V ±10%, AVSS = VSS = 0.0 V, TA = –40°C to +85°C)

Parameter Symbol Pin name Condition Value Unit Remarks

Min. Typ. Max.

Power supply

current

ICCH2 VCC TA = +85°C

Subclock stop

mode —110µA

ICSB VCC

FCL = 32.768 kHz

VCC = 3.0 V

Subclock

operation — 50 100 µA

ICCT VCC VCC = 3.0 V

Watch mode ——15µA

IAAVCC

FCH = 8 MHz

—1.53.5mA

When A/D

con versio n

is activated

IAH AVCC —1 5µAWhen A/D

con versio n

is stopped

Input ca pacitance CIN Other than AVCC,

AVSS, VCC, and VSS f = 1 MHz — 10 — pF

MB89680 Series

4. AC Characteristics

(1) Reset Timing

(VCC = 5.0 V ±10%, AVSS = VSS = 0.0 V, TA = –40°C to +85°C)

* : tXCYL is the oscillation cycle input to the X0.

(2) Specifications for Power-on Reset

(AVSS = VSS = 0.0 V, TA = –40°C to +85°C)

Note: Make sure that power supply rises within the selected oscillation stabilization time selected.

For example, when the main cloc k is operating at FCH = 8 MHz and the oscillation stabilization time is 212/FCH,

the oscillation stabilization time is 0.5 ms. Therefore, the maximum value of power supply rising time is about

0.5 ms.

When increasing the supply voltage during operation, voltage variation should be within twice the intended

increment so that the voltage rises as smoothly as possible.

Parameter Symbol Condition Value Unit Remarks

Min. Max.

RST “L” pulse width tZLZH —48 tXCYL*—ns

RST “H” pulse width tZHZL 24 tXCYL*—ns

Parameter Symbol Condition Value Unit Remarks

Min. Max.

Power supply rising time tR—— 50 ms Power-on reset function only

Power supply cut-off time tOFF 1 — ms Due to repeated operations

0.2 VCC 0.2 VCC 0.2 VCC

0.8 VCC

RST

tZLZH tZHZL

0.2 V 0.2 V

4.5 V

0.2 V

VCC

tOFF

MB89680 Series

(3) Clock Timing

(AVSS = VSS = 0.0 V, TA = –40°C to +85°C)

*1: du ty = PWH/tHCYL

*2: duty1= PWHL/tHCYL

Parameter Symbol Pin

name Condition Value Unit Remarks

Min. Typ. Max.

Input clock frequency FCH X0, X1

—

1 — 8 MHz Main clock

FCL X0A,

X1A —32.768 —kHzSubclock

Clock cycle time tHCYL X0, X1 125 — 1000 ns Main clock

tLCYL X0A,

X1A —30.5— µs Subclock

Input clock duty rate duty*1X0 30 — 70 %

External cl ock

duty1*2X1 30 — 70 %

Input clock rising/falling

time

tCR1 X0 — — 24 ns

tCF1 X0 — — 24 ns

tCR2 X0A — — 200 ns

tCF2 X0A — — 200 ns

FCH

When a crystal

ceramic resonator is used

X0 X1

When an external clock is used

Open

0.8 VCC

0.2 VCC

tCR

tCF

0.8 VCC

0.2 VCC

PWH PWL

tHCYL

• Main clock timing conditions

• Main clock configurations

MB89680 Series

(4) Instruction Cycle

(AVSS = VSS = 0.0 V, TA = –40°C to +85°C)

Parameter Symbol Value (typical) Unit Remarks

Minimum execution time

(instruction cycle)

tinst 4/FCH, 8/FCH, 16/FCH, 64/FCH µs(4/FCH) tinst = 0.5 µs when operating at

FCH = 8 MHz

tinst 2/FCL µstinst = 61.036 µs when operating at

FCL = 32.768 kHz

X0A X1A

When a crystal

ceramic resonator is used

X0A X1A

When an external clock is used

Open

C0C1

FCL

0.8 VCC

X0A

0.8 VCC

0.2 VCC

tCR

tCF

0.8 VCC

0.2 VCC

PWHL PWLL

tLCYL

• Subclock timing conditions

• Subclock configurations

MB89680 Series

(5)Serial I/O Timing

(AVCC = VCC = 5.0 V ±10%, VSS = 0.0 V, TA = –40°C to +85°C)

* :For information on tinst, see “(4) Instruction Cycle.”

ParameterSymbolPin nameCondition ValueUnitRemarks

Min.Max.

Serial clock cycle timetSCYCBSK/UCK

Internal shift

clock mode

2 tinst*—µs

BSK/UCK ↓ → BSO/UO

timetSLOVBSK/UCK,

BSO/UO–200200ns

Valid BSI/UI → BSK/UCK ↑tIVSHBSI/UI,

BSK/UCK1/2 tinst*—µs

BSK/UCK ↑ → valid BSI/UI

hold timetSHIXBSK/UCK,

BSI/UI1/2 tinst*—µs

Serial clock “H” pulse widthtSHSLBSK/UCK

External shift

clock mode

1 tinst*—µs

Serial clock “L” pulse widthtSLSHBSK/UCK1 tinst*—µs

BSK/UCK ↓ → BSO/UO

timetSLOVBSK/UCK,

BSO/UO0200ns

Valid BSI/UI → BSK/UCK ↑tIVSHBSI/UI,

BSK/UCK1/2 tinst*—µs

BSK/UCK ↑ → valid BSI/UI

hold timetSHIXBSK/UCK,

BSI/UI1/2 tinst*—µs

tSCYC

tSLOV

tSHIXtIVSH

BSK/UCK 2.4 V

0.8 V 0.8 V

2.4 V

0.8 V

0.8 VCC

0.2 VCC

0.8 VCC

0.2 VCC

BSO/UO

BSI/UI

tSLSH

tSLOV

tSHIXtIVSH

BSK/UCK 0.8 VCC

0.2 VCC

2.4 V

0.8 V

0.8 VCC

0.2 VCC

0.8 VCC

0.2 VCC

BSO/UO

BSI/UI

0.2 VCC

tSHSL

0.8 VCC

• Internal shift clock mode

• External shift clock mode

MB89680 Series

(6) Peripheral Input Timing

(AVCC = VCC = 5.0 V ±10%, VSS = 0.0 V, TA = –40°C to +85°C)

* :For information on tinst, see “(4) Instruction Cycle.”

Parameter Symbol Pin Value Unit Remarks

Min. Max.

Peripheral input “H” level pulse

width tILIH INL0 to INLB,

INT0 to INT3 2 tinst*—µs

Peripheral input “L” level pulse

width tIHIL INL20 to INLB,

INT0 to INT3 2 tinst*—µs

0.2 VCC

0.8 VCC

tIHIL

INL0 to INLB

INT0 to INT3

0.2 VCC

0.8 VCC

tILIH

MB89680 Series

5. A/D Converter Electrical Characteristics

(AVCC = VCC = 3.5 V to 6.0 V, AVSS = VSS = 0.0 V, TA = –40°C to +85°C)

* :For information on tinst, see “(4) Instruct ion Cycle.”

6. A/D Converter Glossary

• Resolution

Analog changes that are identifiable by the A/D converter

When the number of bits is 8, analog voltage can be divided into 28 = 256.

• L inear i t y er ror (unit: LSB)

The deviation of the straight line connecting the z ero transition point (“0000 0000” ↔ “0000 0001”) with the

full-scale transition point (“1111 1111” ↔ “1111 1110”) from actual conversion characteristics

• Differential linearity error (unit: LSB)

The deviation of input voltage needed to change the output code by 1 LSB from the theoretical v alue

• Total error (unit: LSB)

The difference between theoretical and actual con version values

Paramet er Symbol Pin

name Condition Value Unit Remarks

Min. Typ. Max.

Resolution — — AVR = AVCC

= 5.0 V —— 8bit

Total error — —

AVR = AVCC

——±1.5 LSB

Linearity error — — — — ±1.0 LSB

Differential linearity

error —— — — ±0.9 LSB

Zero transition

voltage V0T —AVss

–1.0 LSB AVss

+0.5 LSB AVss

+2.0 LSB mV 1 LSB =

AVR/256

Full-scale transition

voltage VFST —AVR

–3.0 LSB AVR

–1.5 LSB AVR mV

Interchannel

disparity —— — — 0.5LSB

A/D mode

conversion time ——

—

—44—t

inst*

Sense mode

conversion time —— — 12 — t

inst*

Analog port input

current IAIN AN00 to

AN07 ——10µA

Analog input voltage — AN00 to

AN07 0.0 — AVR V

Reference voltage — AVR 0.0 — AVCC V

Reference voltage

supply current IRAVR AVR = AVCC

= 5.0 V — 100 300 µA

IRH AVR — — 1 µA

MB89680 Series

7. Notes on Using A/D Converter

• Input impedance of the analog input pins

The A/D converter used for the MB89890 series contains a sample hold circuit as illustrated below to fetch

analog input voltage into the sample hold capacitor for eight instruction cycles after starting A/D conversion.

For this reason, if the output impedance of the e xternal circuit for the analog input is high, analog input voltage

might not stabilize within the analog input sampling period. Therefore, it is recommended to keep the output

impedance of the external circuit low (below 10 kΩ).

Note that if the impedance cannot be k ept low, it is recommended to connect an e xternal capacitor of approx.

0.1 µF for the analog input pin.

•Error

The smaller the | AVR – AVSS |, the greater the error would become relatively.

VOT VNT V(N + 1)T VFST

Digital output

(1 LSB × N + VOT)

0000

0000 0000

0001

0010

1111

1111 1110

1111

1 LSB = AVR

256

Linearity error =

Differential linearity error =

Analog input

Actual conversion value

Theoretical conversion value

Total error =

VNT – (1 LSB × N + VOT)

1 LSB

V( N + 1 ) T – VNT

1 LSB – 1

1 LSB

VNT – (1 LSB × N + 1 LSB)

Linearity error

•

Sample hold circuit

Analog channel selector

Close for 8 instruction cycles after starting

A/D conversion.

If the analog input

impedance is higher

than 10 kΩ, it is

recommended to

connect an external

capacitor of approx.

0.1 µF.

Analog input pin Comparator

C ≅ 33 pF

R ≅ 6 kΩ

• Analog Input Equivalent Circuit

MB89680 Series

■INSTRUCTIONS (136 INSTRUCTIONS)

Execution instructions can be divided into the following four groups:

•Transfer

• Arithmetic operation

• Branch

•Others

Table 1 lists symbols used for notation of instructions.

Table 1 Instruction Symbols

(Continued)

Symbol Meaning

dir Direct address (8 bits)

off Offset (8 bits)

ext Extended address (16 bits)

#vct Vector table number (3 bits)

#d8 Immediate data (8 bits)

#d16 Immediate data (16 bits)

dir: b Bit direct address (8:3 bits)

rel Branch relative address (8 bits)

@ Register indirect (Example: @A, @IX, @EP)

A Accumulator A (Whether its length is 8 or 16 bits is determined by the instruction in use .)

AH Upper 8 bits of accumulator A (8 bits)

AL Lower 8 bits of accumulator A (8 bits)

TTemporary accumulator T (Whether its length is 8 or 16 bits is determined by the

instruction in use.)

TH Upper 8 bits of temporary accumulator T (8 bits)

TL Lower 8 bits of temporary accumulator T (8 bits)

IX Index register IX (16 bits)

MB89680 Series

(Continued)

Columns indicate the following:

Mnemonic: Assembler notation of an instruction

~: The number of instructions

#: The number of bytes

Operation: Operation of an instruction

TL, TH, AH: A content change when each of the TL, TH, and AH instructions is ex ecuted. Symbols in

the column indicate the following:

•“–” indicates no chang e.

• dH is the 8 upper bits of operation description data.

• AL and AH must become the contents of AL and AH prior to the instruction executed.

• 00 become s 00.

N, Z, V, C: An instruction of which the corresponding flag will change. If + is written in this column,

the relevant instruction will change its corresponding flag.

OP code: Code of an instruction. If an instruction is more than one code, it is written according to

the following rule:

Example: 48 to 4F ← This indicates 48, 49, ... 4F.

Symbol Meaning

EP Extra pointer EP (16 bits)

PC Program counter PC (16 bits)

SP Stack pointer SP (16 bits)

PS Program status PS (16 bits)

dr Accumulator A or index register IX (16 bits)

CCR Condition code register CCR (8 bits)

RP Register bank pointer RP (5 bits)

Ri General-purpose register Ri (8 bits, i = 0 to 7)

×Indicates that the very × is the immediate data.

(Whether its length is 8 or 16 bits is determined by the instruction in use.)

( × )Indicates that the contents of × is the target of accessing.

(Whether its length is 8 or 16 bits is determined by the instruction in use.)

(( × )) The address indicated by the contents of × is the target of accessing.

(Whether its length is 8 or 16 bits is determined by the instruction in use.)

MB89680 Series

Table 2 Transfer Instructions (48 instructions)

Notes: •During byte transfer to A, T ← A is restricted to low bytes.

•Operands in more than one operand instruction must be stored in the order in which their mnemonics

are written. (Reverse arrangement of F2MC-8 family)

Mnemonic ~ # Operation TL TH AH N Z V C

MOV dir,A

MOV @IX +off,A

MOV ext,A

MOV @EP,A

MOV Ri,A

MOV A,#d8

MOV A,dir

MOV A,@IX +off

MOV A,ext

MOV A,@A

MOV A,@EP

MOV A,Ri

MOV dir,#d8

MOV @IX +off,#d8

MOV @EP,#d8

MOV Ri,#d8

MOVW dir,A

MOVW @IX +off,A

MOVW ext,A

MOVW @EP,A

MOVW EP,A

MOVW A,#d16

MOVW A,dir

MOVW A,@IX +off

MOVW A,ext

MOVW A,@A

MOVW A,@EP

MOVW A,EP

MOVW EP,#d16

MOVW IX,A

MOVW A,IX

MOVW SP,A

MOVW A,SP

MOV @A,T

MOVW @A,T

MOVW IX,#d16

MOVW A,PS

MOVW PS,A

MOVW SP,#d16

SWAP

SETB dir: b

CLRB dir: b

XCH A,T

XCHW A,T

XCH W A,EP

XCHW A,IX

XCH W A,SP

MOVW A,PC

(dir) ← (A)

( (IX) +off ) ← (A)

(ext) ← (A)

( (EP) ) ← (A)

(Ri) ← (A)

(A) ← d8

(A) ← (dir)

(A) ← ( (IX) +off)

(A) ← (ext)

(A) ← ( (A) )

(A) ← ( (EP) )

(A) ← (Ri)

(dir) ← d8

( (IX) +off ) ← d8

( (EP) ) ← d8

(Ri) ← d8

(dir) ← (AH),(dir + 1) ← (AL)

( (IX) +off) ← (AH),

( (IX) +off + 1) ← (AL)

(ext) ← (AH), (ext + 1) ← (AL)

( (EP) ) ← (AH),( (EP) + 1) ← (A L)

(EP) ← (A)

(A) ← d16

(AH) ← (dir), (AL) ← (dir + 1)

(AH) ← ( (IX) +off),

(AL) ← ( (IX) +off + 1)

(AH) ← (ext), (AL) ← (ext + 1)

(AH) ← ( (A) ), (AL) ← ( (A) ) + 1)

(AH) ← ( (EP) ), (A L) ← ( (EP) + 1)

(A) ← (EP)

(EP) ← d16

(IX) ← (A)

(A) ← (IX)

(SP) ← (A)

(A) ← (SP)

( (A) ) ← (T)

( (A) ) ← (TH),( (A) + 1) ← (TL)

(IX) ← d16

(A) ← (PS)

(PS) ← (A)

(SP) ← d1 6

(AH) ↔ (AL )

(dir): b ← 1

(dir): b ← 0

(AL) ↔ (TL)

(A) ↔ (T)

(A) ↔ (EP)

(A) ↔ (IX)

(A) ↔ (SP)

(A) ← (PC)

–

– – – –

+ + – –

– – – –

+ + – –

– – – –

+ + + +

– – – –

MB89680 Series

Table 3 Arithmetic Operation Instructions (62 instructions)

(Continued)

Mnemonic ~ # Operation TL TH AH N Z V C OP code

ADDC A,Ri

ADDC A,#d8

ADDC A,dir

ADDC A,@IX +off

ADDC A,@EP

ADDCW A

ADDC A

SUBC A,Ri

SUBC A,#d8

SUBC A,dir

SUBC A,@ IX +of f

SUBC A,@EP

SUBCW A

SUBC A

INC Ri

INCW EP

INCW IX

INCW A

DEC Ri

DECW EP

DECW IX

DECW A

MULU A

DIVU A

ANDW A

ORW A

XORW A

CMP A

CMPW A

RORC A

ROLC A

CMP A, #d8

CMP A, dir

CMP A, @EP

CMP A, @IX +off

CMP A, Ri

DAA

DAS

XOR A

XOR A,#d8

XOR A,dir

XOR A,@EP

XOR A,@IX +o ff

XOR A,Ri

AND A

AND A,#d8

AND A,dir

(A) ← (A) + (Ri) + C

(A) ← (A) + d8 + C

(A) ← (A) + (dir) + C

(A) ← (A) + ( (IX) +off) + C

(A) ← (A) + ( (EP) ) + C

(A) ← (A) + (T) + C

(AL) ← (AL) + (TL) + C

(A) ← (A) − (Ri) − C

(A) ← (A) − d8 − C

(A) ← (A) − (dir) − C

(A) ← (A) − ( (IX) +off) − C

(A) ← (A) − ( (EP) ) − C

(A) ← (T) − (A) − C

(AL) ← (TL) − (AL) − C

(Ri) ← (Ri) + 1

(EP) ← (EP) + 1

(IX) ← (IX) + 1

(A) ← (A) + 1

(Ri) ← (Ri) − 1

(EP) ← (EP) − 1

(IX) ← (IX) − 1

(A) ← (A) − 1

(A) ← (AL) × (TL)

(A) ← (T) / (AL),MOD → (T)

(A) ← (A) ∧ (T)

(A) ← (A) ∨ (T)

(A) ← (A) ∀ (T)

(TL) − (AL)

(T) − (A)

(A) − d8

(A) − (dir)

(A) − ( (EP) )

(A) − ( (IX) +off)

(A) − (Ri)

Decimal adjust for add i tion

Decimal ad just for subtraction

(A) ← (AL) ∀ (TL)

(A) ← (AL) ∀ d8

(A) ← (AL) ∀ (dir)

(A) ← (AL) ∀ ( (EP) )

(A) ← (AL) ∀ ( (IX) +off)

(A) ← (AL) ∀ (Ri)

(A) ← (AL) ∧ (TL )

(A) ← (AL) ∧ d8

(A) ← (AL) ∧ (dir)

–

+ + + +

+ + + –

– – – –

+ + – –

+ + + –

– – – –

+ + – –

– – – –

+ + R –

+ + + +

+ + – +

+ + + +

+ + R –

28 to 2F

38 to 3F

C8 to CF

D8 to DF

18 to 1F

58 to 5F

←

→→

MB89680 Series

(Continued)

Table 4 Branch Instructions (17 instructions)

Table 5 Other Instructions (9 instructions)

Mnemonic ~ # Operation TL TH AH N Z V C OP code

AND A,@EP

AND A,@IX +off

AND A,Ri

OR A

OR A,#d8

OR A,di r

OR A,@EP

OR A,@IX +off

OR A,Ri

CMP dir,#d8

CMP @EP,#d8

CMP @IX +off,#d8

CMP Ri,#d8

INCW SP

DECW SP

(A) ← (AL) ∧ ( (EP) )

(A) ← (AL) ∧ ( (IX) +off)

(A) ← (AL) ∧ (Ri)

(A) ← (AL) ∨ (TL)

(A) ← (AL) ∨ d8

(A) ← (AL) ∨ (dir)

(A) ← (AL) ∨ ( (EP) )

(A) ← (AL) ∨ ( (IX) +off)

(A) ← (AL) ∨ (Ri)

(dir) – d8

( (EP) ) – d8

( (IX) + off) – d8

(Ri) – d8

(SP) ← (SP) + 1

(SP) ← (SP) – 1

–

+ + R –

+ + + +

– – – –

68 to 6F

78 to 7F

98 to 9F

Mnemonic ~ # Operation TL TH AH N Z V C OP code

BZ/BEQ rel

BNZ/BNE rel

BC/BL O re l

BNC/BHS rel

BN rel

BP rel

BLT rel

BGE rel

BBC dir: b,rel

BBS dir: b,rel

JMP @A

JMP ext

CALLV #vct

CALL ext

XCHW A,PC

RET

RETI

If Z = 1 then PC ← PC + rel

If Z = 0 then PC ← PC + rel

If C = 1 then PC ← PC + rel

If C = 0 then PC ← PC + rel

If N = 1 then PC ← PC + rel

If N = 0 then PC ← PC + rel

If V ∀ N = 1 then PC ← PC + rel

If V ∀ N = 0 then PC ← PC + reI

If (dir: b) = 0 then PC ← PC + rel

If (dir: b) = 1 then PC ← PC + rel

(PC) ← (A)

(PC) ← ext

Vector call

Subroutine call

(PC) ← (A),(A) ← (PC) + 1

Return from subrountine

Return form interrupt

–

– – – –

– + – –

– – – –

Restore

B0 to B7

B8 to BF

E8 to EF

Mnemonic ~ # Operation TL TH AH N Z V C OP code

PUSHW A

POPW A

PUSHW IX

POPW IX

NOP

CLRC

SETC

CLRI

SETI

–

– – – –

– – – R

– – – S

– – – –

MB89680 Series

■INSTRUCTION MAP

0123456789ABCDEF

0NOP SWAP RET RETI PUSHW

APOPWAMOV

A,ext MOVW

A,PS CLRI SETI CLRB

dir: 0 BBC

dir: 0,rel INCW ADECWAJMP@A MOVW

A,PC

1MULUADIVU AJMP

addr16 CALL

addr16 PUSHW

IX POPW

IX MOV

ext,A MOVW

PS,A CLRC SETC CLRB

dir: 1 BBC

dir: 1,rel INCW

SP DECW

SP MOVW

SP,A MOVW

A,SP

2ROLCACMP AADDCASUBCAXCH

A, T XOR AAND AOR AMOV

@A,T MOV

A,@A CLRB

dir: 2 BBC

dir: 2,rel INCWIX DECW

IX MOVW

IX,A MOVW

A,IX

3RORCACMPW

AADDCW

ASUBCW

AXCHW

A, T XORWAANDWAORW AMOVW

@A,T MOVW

A,@A CLRB

dir: 3 BBC

dir: 3,rel INCW

EP DECW

EP MOVW

EP,A MOVW

A,EP

4MOV

A,#d8 CMP

A,#d8 ADDC

A,#d8 SUBC

A,#d8 XOR

A,#d8 AND

A,#d8 OR

A,#d8 DAA DAS CLRB

dir: 4 BBC

dir: 4,rel MOVW

A,ext MOVW

ext,A MOVW

A,#d16 XCHW

A,PC

5MOV

A,dir CMP

A,dir ADDC

A,dir SUBC

A,dir MOV

dir,A XOR

A,dir AND

A,dir ORA,dir MOV

dir,#d8 CMP

dir,#d8 CLRB

dir: 5 BBC

dir: 5,rel MOVW

A,dir MOVW

dir,A MOVW

SP,#d16 XCHW

A,SP

6MOV

A,@IX +d CMP

A,@IX +d ADDC

A,@ IX +d SUBC

A,@IX +d MOV

@IX +d,A XOR

A,@IX +d AND

A,@IX +d OR

A,@IX +d MOV

@IX +d,#d8 CMP

@IX + d,#d8 CLRB

dir: 6 BBC

dir: 6,rel MOVW

A,@IX +d MOVW

@IX +d,A MOVW

IX,#d16 XCHW

A,IX

7MOV

A,@EP CMP

A,@EP ADDC

A,@EP SUBC

A,@EP MOV

@EP,A XOR

A,@EP AND

A,@EP OR

A,@EP MOV

@EP,#d8 CMP

@EP,#d8 CLRB

dir: 7 BBC

dir: 7,rel MOVW

A,@EP MOVW

@EP,A MOVW

EP,#d16 XCHW

A,EP

8MOV

A,R0 CMP

A,R0 ADDC

A,R0 SUBC

A,R0 MOV

R0,A XOR

A,R0 AND

A,R0 ORA,R0 MOV

R0,#d8 CMP

R0,#d8 SETB

dir: 0 BBS

dir: 0,rel INC R0 DECR0 CALLV

#0 BNC rel

9MOV

A,R1 CMP

A,R1 ADDC

A,R1 SUBC

A,R1 MOV

R1,A XOR

A,R1 AND

A,R1 ORA,R1 MOV

R1,#d8 CMP

R1,#d8 SETB

dir: 1 BBS

dir: 1,rel INC R1 DECR1 CALLV

#1 BC rel

AMOV

A,R2 CMP

A,R2 ADDC

A,R2 SUBC

A,R2 MOV

R2,A XOR

A,R2 AND

A,R2 ORA,R2 MOV

R2,#d8 CMP

R2,#d8 SETB

dir: 2 BBS

dir: 2,rel INC R2 DECR2 CALLV

#2 BP rel

BMOV

A,R3 CMP

A,R3 ADDC

A,R3 SUBC

A,R3 MOV

R3,A XOR

A,R3 AND

A,R3 ORA,R3 MOV

R3,#d8 CMP

R3,#d8 SETB

dir: 3 BBS

dir: 3,rel INC R3 DECR3 CALLV

#3 BN rel

CMOV

A,R4 CMP

A,R4 ADDC

A,R4 SUBC

A,R4 MOV

R4,A XOR

A,R4 AND

A,R4 ORA,R4 MOV

R4,#d8 CMP

R4,#d8 SETB

dir: 4 BBS

dir: 4,rel INC R4 DECR4 CALLV

#4 BNZ rel

DMOV

A,R5 CMP

A,R5 ADDC

A,R5 SUBC

A,R5 MOV

R5,A XOR

A,R5 AND

A,R5 ORA,R5 MOV

R5,#d8 CMP

R5,#d8 SETB

dir: 5 BBS

dir: 5,rel INC R5 DECR5 CALLV

#5 BZ rel

EMOV

A,R6 CMP

A,R6 ADDC

A,R6 SUBC

A,R6 MOV

R6,A XOR

A,R6 AND

A,R6 ORA,R6 MOV

R6,#d8 CMP

R6,#d8 SETB

dir: 6 BBS

dir: 6,rel INC R6 DEC R6 CALLV

#6 BGE rel

FMOV

A,R7 CMP

A,R7 ADDC

A,R7 SUBC

A,R7 MOV

R7,A XOR

A,R7 AND

A,R7 ORA,R7 MOV

R7,#d8 CMP

R7,#d8 SETB

dir: 7 BBS

dir: 7,rel INC R7 DEC R7 CALLV

#7 BLT rel

MB89680 Series

■MASK OPTIONS

■ORDERING INFORMATION

No. Part number MB89689 MB89P689

MB89W689 MB89PV680

Specifying procedure Spcify when ordering

masking Set with EPROM

programmer Setting not

possible

Pull-up resistors

P00 to P07,

P10 to P17,

P30 to P37,

P60 to P67,

P90 to P97,

PA0 to PA7

Selectable by pin Selectable by pin Fixed to without a

pull-up resistor

2Power-on reset (POR)

With power-on reset

Without power-on reset Selectable Selectable Fixed to with pow er-on

reset

Oscillation stabilization time

selection (OSC)

The initial value of the main

clock oscillation stabilization

time can be set with WTM1

and WTM0 bit.

Selectable

WTM1 WTM0

00:2

3/FCH

01:2

12/FCH

10:2

16/FCH

11:2

18/FCH

Selectable

WTM1 WTM0

00:2

3/FCH

01:2

12/FCH

10:2

16/FCH

11:2

18/FCH

Fixed to oscillation

stabilization time of

218/FCH

4Reset pin output (RST)

With reset output

Without reset output Selectable Selectable Fixed to with reset

output

5Clock mode selection (CLK)

Dual-clock mode

Single-clock mode Selectable Selectable Fixed to dual clock

Part number Package Remarks

MB89689PF

MB89P689PF 100-pin Plastic QFP

(FPT-100P-M06)

MB89W689CF 100-pin Ceramic QFP

(FPT-100C-A02)

MB89PV680CF 100-pin Ceramic MQFP

(MQP-100C-P01)

MB89680 Series

■PACKAGE DIMENSIONS

(.0256±.0060)

0.65±0.15

TYP

0.30±0.05

8.89(.350)DIA

0.80(.0315) TYP22.30(.878) TYP

22.00(.866) TYP

1.60(.063) TYP

(.012±.002)

0.65±0.15

(.0256±.0060)

18.85(.742)REF

(.787±.010)

20.00±0.25

23.90(.941) TYP

(.006±.002)

0.15±0.05

4.45(.175)MAX

0.51(.020) TYP

REF

12.34(.486)

TYP

16.31(.642)

TYP

16.00(.630)

(.551±.010)

TYP

17.91(.705)

14.00±0.25

INDEX AREA

1994 FUJITSU LIMITED F100013SC-1-2

CDimensions in mm (inches)

100-pin Ceramic QFP

(FPT-100C-A02)

(.031±.008)

0.80±0.20

LEAD No.

(.012±.004)

0.30±0.10

0.65(.0256)TYP

0.30(.012)

0.25(.010)

100

80 51

22.30±0.40(.878±.016)

18.85(.742)REF

0.13(.005)

(.705±.016)(.551±.008)

14.00±0.20 17.90±0.40

20.00±0.20(.787±.008)

23.90±0.40(.941±.016)

INDEX

0.15±0.05(.006±.002)

(STAND OFF)

0.05(.002)MIN

3.35(.132)MAX

(.642±.016)

16.30±0.40

REF

12.35(.486)

Details of "B" part

0 10°

Details of "A" part

0.18(.007)MAX

0.53(.021)MAX

0.10(.004)

"B"

"A"

1994 FUJITSU LIMITED F100008-3C-2

(Mounting height)

Dimens ion s in mm (inc hes )

100-pin Plastic QFP

(FPT-100P-M06)

MB89680 Series

+0.40

–0.20

+.016

–.008

+0.40

–0.20

+.016

–.008

1.20

.047

12.35(.486)TYP

(.0256±.0060)

0.65±0.15

TYP

18.85(.742)

(.0256±.0060)

0.65±0.15

(.012±.003)

0.30±0.08 1.20

.047

(.012±.003)

0.30±0.08

MAX

10.82(.426)

(.006±.002)

0.15±0.05

11.68(.460)TYP

9.48(.373)TYP

7.62(.300)TYP

0.30(.012)TYP

(.050±.005)

1.27±0.13

(.713±.008)

18.12±0.20

TYP

14.22(.560)

TYP

12.02(.473)

TYP

10.16(.400)

TYP

24.70(.972)

(.878±.013)

22.30±0.33

(.050±.005)

1.27±0.13

TYP

0.30(.012)

INDEX AREA

18.70(.736)TYP

(.642±.013)

16.30±0.33

(.613±.008)

15.58±0.20

1994 FUJITSU LIMITED M100001SC-1-2

CDimensions in mm (inches)

100-pin Ceramic MQFP

(MQP-100C-P01)

MB89680 Series

FUJITSU LIMITED

The contents of this document are subject to change without notice.

Customers are advised to consult with FUJITSU sales

representatives before ordering.

The information and circuit diagrams in this document are

presented as examples of semiconductor device applications, and

are not intended to be incorporated in devices for actual use. Also,

FUJITSU is unable to assume responsibility for infringement of

any patent rights or other rights of third parties arising from the use

of this information or circuit diagrams.

The products described in this document are designed, developed

and manufactured as contemplated for general use, including

without limitation, ordinary industrial use, general office use,

personal use, and household use, but are not designed, developed

and manufactured as contemplated (1) for use accompanying fatal

risks or dangers that, unless extremely high safety is secured, could

have a serious effect to the public, and could lead directly to death,

personal injury, severe physical damage or other loss (i.e., nuclear

reaction control in nuclear facility, aircraft flight control, air traffic

control, mass transport control, medical life support system, missile

launch control in weapon system), or (2) for use requiring

extremely high reliability (i.e., submersible repeater and artificial

satellite).

Please note that Fujitsu will not be liable against you and/or any

third party for any claims or damages arising in connection with

above-mentioned uses of the products.

Any semiconductor devices have an inherent chance of failure. You

must protect against injury, damage or loss from such failures by

incorporating safety design measures into your facility and

equipment such as redundancy, fire protection, and prevention of

over-current levels and other abnormal operating conditions.

If any products described in this document represent goods or

technologies subject to certain restrictions on export under the

Foreign Exchange and Foreign Trade Law of Japan, the prior

authorization by Japanese government will be required for export

of those products from Japan.

F9802

 FUJITSU LIMITED Printed in Japan