ACS71020 Single Phase, Isolated, AC Power Monitoring IC with Voltage Zero Crossing and Overcurrent Detection DESCRIPTION FEATURES AND BENEFITS * Accurate power monitoring for AC applications * UL certification for reinforced isolation up to 517 VRMS in a single package * Accurate measurements of active, reactive, and apparent power, as well as power factor * Separate RMS and instantaneous measurements for both voltage and current channels * 0.85 m primary conductor resistance for low power loss and high inrush current withstand capability * Dedicated voltage zero crossing pin * Overcurrent fault output pin * Hall-effect-based current measurement with commonmode stray field rejection * User-programmable undervoltage and overvoltage thresholds for input voltage as well as overcurrent fault thresholds * 1 kHz bandwidth * Current-sensing range from 0 to 90A * Options for I2C or SPI digital interface protocols * User-programmable EEPROM and integrated charge pump * 16-bit voltage and current ADCs PACKAGE 16-pin SOICW (suffix MA) 1 M 1 M 1 M 1 M 1 2 3 4 5 6 7 CB Certificate Number: US-32210-M1-UL The ACS71020 power monitoring IC offers key power measurement parameters that can easily be accessed through its SPI or I2C digital protocol interfaces. Dedicated and configurable I/O pins for voltage zero crossing, undervoltage and overvoltage reporting, and overcurrent fault detection are also available (in I2C mode). The thresholds for overvoltage, undervoltage, and overcurrent are all user-programmable via EEPROM. REINFORCED ISOLATION N (L) IP Allegro's Hall-effect-based galvanically isolated current sensing technology achieves reinforced isolation ratings in a small PCB footprint. These features enable isolated current sensing without expensive Rogowski coils, oversized current transformers, isolated operational amplifiers, or the power loss of shunt resistors. The ACS71020 is provided in a small low-profile surface mount SOIC16 wide-body package, is lead (Pb) free, and is fully calibrated prior to shipment from the Allegro factory. Customer calibration can further increase accuracy in application. Not to scale L (N) The Allegro ACS71020 power monitoring IC greatly simplifies the addition of power monitoring to many AC powered systems. The sensor may be powered from the same supply as the system's MCU, eliminating the need for multiple power supplies and expensive digital isolation ICs. The device's construction includes a copper conduction path that generates a magnetic field proportional to applied current. The magnetic field is sensed differentially to reject errors introduced by common mode fields. 8 MCU RSENSE GND IP+ ACS71020 VINP IP+ VINN IP+ GND IP+ VCC IP- SDA / MISO IP- SCL / SCLK IP- DIO_0 / MOSI IP- DIO_1 / CS Single Output Isolated Power Supply (Flyback, etc.) 16 VCC I2C Only 15 14 RPULLUP To User 13 12 RPULLUP 11 10 9 Linear Regulator Figure 1: Typical Application ACS71020-DS, Rev. 9 MCO-0000459 November 21, 2019 Single Phase, Isolated, AC Power Monitoring IC with Voltage Zero Crossing and Overcurrent Detection ACS71020 SELECTION GUIDE Part Number VCC(NOM) (V) IPR (A) ACS71020KMABTR-015B5-SPI 5 15 ACS71020KMABTR-030B3-SPI 3.3 30 ACS71020KMABTR-030B3-I2C 3.3 30 ACS71020KMABTR-090B3-I2C 3.3 90 [1] Contact Allegro Communication Protocol TA (C) Packing [1] -40 to 125 Tape and reel, 1000 pieces per reel, 3000 pieces per box SPI I2C for additional packing options. ACS 71020 K MAB TR - 015 B 5 - SPI Communication Protocol Supply Voltage: 5 - VCC = 5 V 3 - VCC = 3.3 V Output Directionality: B - Bidirectional (positive and negative current) Current Sensing Range (A) Packing Designator Package Designator Operating Temperature Range 5 Digit Part Number Allegro Current Sensor Allegro MicroSystems 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com 2 Single Phase, Isolated, AC Power Monitoring IC with Voltage Zero Crossing and Overcurrent Detection ACS71020 ABSOLUTE MAXIMUM RATINGS Characteristic Symbol Notes Rating Units Supply Voltage VCC 6.5 V Reverse Supply Voltage VRCC -0.5 V Input Voltage VINP, VINN VCC + 0.5 V Reverse Input Voltage VRNP, VRNN -0.5 V 6 V -0.5 V Digital I/O Voltage VDIO Reverse Digital I/O Voltage VRDIO Maximum Continuous Current ICMAX TA = 25C 60 A TA Range K -40 to 125 C Operating Ambient Temperature SPI, I2C, and general purpose I/O Junction Temperature TJ(max) 165 C Storage Temperature Tstg -65 to 170 C ISOLATION CHARACTERISTICS Characteristic Dielectric Strength Test Voltage Symbol VISO Notes Agency type-tested for 60 seconds per UL 60950-1 (edition 2). Production tested at 3000 VRMS for 1 second, in accordance with UL 60950-1 (edition 2). Rating Unit 4800 VRMS 1480 VPK or VDC 1047 VRMS 730 VPK or VDC 517 VRMS Working Voltage for Basic Isolation VWVBI Maximum approved working voltage for basic (single) isolation according to UL 60950-1 (edition 2). Working Voltage for Reinforced Isolation VWVRI Maximum approved working voltage for reinforced isolation according to UL 60950-1 (edition 2). Dcl Minimum distance through air from IP leads to signal leads. 7.5 mm Creepage Dcr Minimum distance along package body from IP leads to signal leads 7.9 mm Distance Through Insulation DTI Minimum internal distance through insulation 90 m Comparative Tracking Index CTI Material Group II 400 to 599 V Clearance ESD RATINGS Value Unit Human Body Model Characteristic Symbol VHBM Per AEC-Q100 Test Conditions 4.5 kV Charged Device Model VCDM Per AEC-Q100 1 kV THERMAL CHARACTERISTICS Characteristic Symbol Test Conditions* Package Thermal Resistance (Junction to Ambient) RJA Mounted on the Allegro 85-0738 evaluation board with 700 of 4 oz. copper on each side, connected to pins 1 and 2, and to pins 3 and 4, with thermal vias connecting the layers. Performance values include the power consumed by the PCB. Package Thermal Resistance (Junction to Lead) RJL Mounted on the Allegro ACS71020 evaluation board. Value Units 23 C/W 5 C/W mm2 *Additional thermal information available on the Allegro website. See https://www.allegromicro.com/en/Design-Center/Technical-Documents/Hall-Effect-Sensor-IC-Publications/DC-and-Transient-Current-Capability-Fuse-Characteristics.aspx. Allegro MicroSystems 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com 3 Single Phase, Isolated, AC Power Monitoring IC with Voltage Zero Crossing and Overcurrent Detection ACS71020 FUNCTIONAL BLOCK DIAGRAM VCC DIGITAL SYSTEM R Bandgap Reference To All Subcircuits VINP ADC VINN 2R IP+ Temperature Compensation Logic Temperature Sensor ADC EEPROM + Charge Pump V I I2C/SPI Communication Metrology Engine SDA / MISO SCL / SCLK DIO_0 / MOSI DIO_1 / CS Fault Logic Hall Sensor Array GND IP- Table of Contents Features and Benefits............................................................ 1 Description........................................................................... 1 Package.............................................................................. 1 Typical Application................................................................. 1 Selection Guide.................................................................... 2 Absolute Maximum Ratings.................................................... 3 Isolation Characteristics......................................................... 3 Thermal Characteristics......................................................... 3 Functional Block Diagram...................................................... 4 Pinout Diagram and Terminal List............................................ 5 Digital I/O............................................................................. 5 Electrical Characteristics........................................................ 6 Data Acquisition.................................................................. 13 ADCs............................................................................. 13 Raw Signal Sensitivity and Offset Trim................................ 13 Phase Compensation....................................................... 13 Zero Crossing.................................................................. 13 Power Calculations.............................................................. 14 Digital Communication......................................................... 17 Registers and EEPROM................................................... 17 EEPROM Error Checking and Correction (ECC).................. 19 Memory Map................................................................... 20 Volatile Memory Map........................................................ 28 Voltage Input Application Connections................................... 36 Recommended PCB Layout................................................. 37 Package Outline Drawing..................................................... 38 Allegro MicroSystems 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com 4 Single Phase, Isolated, AC Power Monitoring IC with Voltage Zero Crossing and Overcurrent Detection ACS71020 PINOUT DIAGRAM AND TERMINAL LIST Terminal List Table IP+ 1 16 VINP IP+ 2 15 VINN IP+ 3 14 GND IP+ 4 13 VCC IP- 5 12 SDA / MISO IP- 6 11 SCL / SCLK IP- 7 10 DIO_0 / MOSI IP- 8 9 Pinout Diagram DIO_1 / CS Description Number Name 1, 2, 3, 4 IP+ Terminals for current being sensed; fused internally 5, 6, 7, 8 IP- Terminals for current being sensed; fused internally 9 DIO_1/CS Digital I/O 1 10 DIO_0/MOSI Digital I/O 0 MOSI 11 SCL/SCLK SCL SCLK 12 SDA/MISO SDA MISO 13 VCC Device power supply terminal 14 GND Device Power and Signal ground terminal 15 VINN Negative Input Voltage 16 VINP Positive Input Voltage I2C SPI Chip Select (CS) DIGITAL I/O The Digital I/O can be programmed to represent the following functions (Digital Output pins are low true): DIO_0: DIO_1: 0. 1. 2. 3. 0. 1. 2. 3. VZC: Voltage zero crossing OVRMS: The VRMS overvoltage flag UVRMS: The VRMS undervoltage flag The OR of OVRMS and UVRMS (if either flag is triggered, the DIO_0 pin will be asserted) VZC OCF: Overcurrent fault UVRMS: The VRMS undervoltage flag OVRMS: The VRMS overvoltage flag The OR of OVRMS, UVRMS, and OCF_LAT [Latched Overcurrent fault] (if any of the three flags are triggered, the DIO_1 pin will be asserted) DIO_0 OVRMS DIO_0 / MOSI MOSI UVRMS DIO_0_Sel[0..1] OCF Comm_Sel DIO_1 UVRMS OVRMS OCF_LAT DIO_1 / CS CS DIO_1_Sel[0..1] Comm_Sel Allegro MicroSystems 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com 5 ACS71020 Single Phase, Isolated, AC Power Monitoring IC with Voltage Zero Crossing and Overcurrent Detection COMMON ELECTRICAL CHARACTERISTICS [1]: Valid through the full range of TA and VCC = VCC(nom), unless otherwise specified Characteristic Symbol Test Conditions Min. Typ. Max. Unit VCC(nom) x 0.9 VCC(nom) VCC(nom) x 1.1 V - 12 14 mA - 90 - s -275 - 275 mV x VCC + 0.275 V ELECTRICAL CHARACTERISTICS Supply Voltage VCC Supply Current ICC Power-On Time tPO VCC(min) VCC VCC(max), no load on output pins VOLTAGE INPUT BUFFER Differential Input Range VIN VINP - VINN x VCC - 0.275 - fS - 32 - kHz NADC(V) - 16 - bits 60 70 - dB VN - 10 - LSB Internal Bandwidth BW - 1 - kHz Linearity Error ELIN - 0.2 - % fS - 32 - kHz - 16 - bits 60 70 - dB - 1 - kHz Common Mode Input Voltage 2/ 3 VIN(CM) 2/ 3 VOLTAGE CHANNEL ADC Sample Frequency Number of Bits Voltage ADC Power Supply Rejection V_PSRR Ratio of change on VCC to change in ADC internal reference at DC VOLTAGE CHANNEL Noise CURRENT CHANNEL ADC Sample Frequency Number of Bits Current Channel ADC Power Supply Rejection NADC(I) I_PSRR Ratio of change on VCC to change in ADC internal reference at DC CURRENT CHANNEL Internal Bandwidth BW Primary Conductor Resistance RIP - 0.85 - m Noise VN - 100 - LSB ELIN - 1.5 - % - 5 - s Linearity Error TA = 25C OVERCURRENT FAULT CHARACTERISTICS Fault Response Time tRF Time from IP rising above IFAULT until VFAULT < VFAULT(max) for a current step from 0 to 1.2 x IFAULT; 10 k and 100pF from DIO_1 to ground; fltdly = 0 Internal Bandwidth BW - 200 - kHz Fault Hysteresis [2] IHYST - 0.05 x IPR - A Fault Range IFAULT 0.5 x IPR - 1.75 x IPR A - 350 - s Set using FAULT field in EEPROM VOLTAGE ZERO CROSSING Voltage Zero Crossing Delay td Continued on next page... Allegro MicroSystems 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com 6 ACS71020 Single Phase, Isolated, AC Power Monitoring IC with Voltage Zero Crossing and Overcurrent Detection COMMON ELECTRICAL CHARACTERISTICS [1] (continued): Valid through the full range of TA and VCC = VCC(nom), unless otherwise specified Characteristic Symbol Test Conditions Min. Typ. Max. Unit DIO PINS DIO Output High Level VCC = 3.3 V 3 - - V DIO Output Low Level VCC = 3.3 V - - 0.3 V DIO Input Voltage for Address Selection 0 VCC = 3.3 V - 0 - V DIO Input Voltage for Address Selection 1 VCC = 3.3 V - 1.1 - V DIO Input Voltage for Address Selection 2 VCC = 3.3 V - 2.2 - V DIO Input Voltage for Address Selection 3 VCC = 3.3 V - 3.3 - V Device may be operated at higher primary current levels, IP, ambient, TA, and internal leadframe temperatures, TA, provided that the Maximum Junction Temperature, TJ(max), is not exceeded. [2] After I goes above I P FAULT, tripping the internal fault comparator, IP must go below IFAULT - IHYST, before the internal fault comparator will reset. [1] Allegro MicroSystems 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com 7 Single Phase, Isolated, AC Power Monitoring IC with Voltage Zero Crossing and Overcurrent Detection ACS71020 xKMATR-I2C OPERATING CHARACTERISTICS: Valid through the full range of TA, VCC = VCC(nom), REXT = 10k, unless otherwise specified Characteristic Symbol Test Conditions Min. Typ. Max. Unit I2C INTERFACE CHARACTERISTICS [1] Bus Free Time Between Stop and Start tBUF 1.3 - - s Hold Time Start Condition thdSTA 0.6 - - s Setup Time for Repeated Start Condition tsuSTA 0.6 - - s SCL Low Time tLOW 1.3 - - s SCL High Time tHIGH 0.6 - - s Data Setup Time tsuDAT 100 - - s Data Hold Time thdDAT 0 - 900 s Setup Time for Stop Condition tsuSTO 0.6 - - s Logic Input Low Level (SDA, SCL pins) VIL - - 30 %VCC Logic Input High Level (SDA, SCL pins) VIH 70 Logic Input Current IIN Output Low Voltage (SDA) VOL Clock Frequency (SCL pin) fCLK Output Fall Time (SDA pin) tf I2C Pull-Up Resistance Total Capacitive Load for Each of SDA and SCL Buses [1] - - %VCC Input voltage on SDA or SCL = 0 V to VCC -1 - 1 A SDA sinking = 1.5 mA - - 0.36 V kHz - - 400 - - 250 ns REXT 2.4 10 - k CB - - 20 pF REXT = 2.4 k, CB = 100 pF These values are ratiometric to the supply voltage, I2C Interface Characteristics are ensured by design and not factory tested. tsuSTA tsuDAT thdSTA thdDAT tsuSTO tBUF SDA SCL tLOW tHIGH Figure 2: I2C Interface Timing Allegro MicroSystems 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com 8 ACS71020 Single Phase, Isolated, AC Power Monitoring IC with Voltage Zero Crossing and Overcurrent Detection xKMATR-SPI OPERATING CHARACTERISTICS [1]: Valid through the full range of TA, VCC = VCC(nom), unless otherwise specified Characteristic Symbol Test Conditions Min. Typ. Max. Unit MOSI, SCLK, CS pins, VCC (nom) = 3.3 V 2.8 - 3.63 V MOSI, SCLK, CS pins, VCC (nom) = 5 V 4 - 5.5 V MOSI, SCLK, CS pins - - 0.5 V MISO pin, CL = 20 pF, TA = 25C, VCC (nom) = 3.3 V 2.8 3.3 3.8 V MISO pin, CL = 20 pF, TA = 25C, VCC (nom) = 5 V 4 5 5.5 V - 0.3 0.5 V 0.1 - 10 MHz 5.8 - 588 kHz SPI INTERFACE CHARACTERISTICS Digital Input High Voltage VIH Digital Input Low Voltage VIL SPI Output High Voltage VOH SPI Output Low Voltage VOL MISO pin, CL = 20 pF, TA = 25C SPI Clock Frequency fSCLK MISO pin, CL = 20 pF SPI Frame Rate tSPI Chip Select to First SCLK Edge tCS Time from CS going low to SCLK falling edge 50 - - ns Data Output Valid Time tDAV Data output valid after SCLK falling edge - 40 - ns MOSI Setup Time tSU Input setup time before SCLK rising edge 25 - - ns MOSI Hold Time tHD Input hold time after SCLK rising edge 50 - - ns SCLK to CS Hold Time tCHD Hold SCLK high time before CS rising edge 5 - - ns Loading on digital output (MISO) pin - - 20 pF Load Capacitance [1] CL The ACS71020 MISO pin continues to drive the MISO line when CS goes high. This may prevent other devices from communicating properly. It is recommended that the ACS71020 be the only device on the SPI bus if using SPI communication. Figure 3: SPI Timing Allegro MicroSystems 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com 9 Single Phase, Isolated, AC Power Monitoring IC with Voltage Zero Crossing and Overcurrent Detection ACS71020 ACS71020KMA-015B5 PERFORMANCE CHARACTERISTICS: Valid through the full operating temperature range, TA = -40C to 125C, CBYPASS = 0.1 F, and VCC = 5 V, unless otherwise specified Characteristic Symbol Test Conditions Min. Typ. [1] Max. Unit - 5 - V -15 - 15 A - 2184 - LSB/A Measured at IP = IPR (max), TA = 25C to 125C - 2 - % Measured at IP = IPR (max), TA = -40C to 25C - 3 - % Measured at IP = IPR (max), TA = 25C to 125C - 1 - % Measured at IP = IPR (max), TA = -40C to 25C - 1.5 - % IP = 0 A, TA = 25C to 125C - 300 - LSB IP = 0 A, TA = -40C to 25C - 500 - LSB - 238 - LSB/mV Measured at VP = VPR (max), TA = 25C to 125C - 1.2 - % Measured at VP = VPR (max), TA = -40C to 25C - 1.3 - % Measured at VP = VPR (max), TA = 25C to 125C - 1 - % Measured at VP = VPR (max), TA = -40C to 25C - 1 - % VP = 0 mV, TA = 25C to 125C - 100 - LSB VP = 0 mV, TA = -40C to 25C - 150 - LSB Measured at VP = VPR (max), TA = 25C to 125C - 2.3 - % Measured at VP = VPR (max), TA = -40C to 25C - 3.3 - % GENERAL CHARACTERISTICS Nominal Supply Voltage VCC (nom) NOMINAL PERFORMANCE - CURRENT CHANNEL Current Sensing Range Sensitivity IPR Sens(I) IPR (min) < IP < IPR (max) ACCURACY PERFORMANCE - CURRENT CHANNEL Total Output Error ETOT(I) TOTAL OUTPUT ERROR COMPONENTS - CURRENT CHANNEL Sensitivity Error Offset Error ESENS(I) EO(I) NOMINAL PERFORMANCE - VOLTAGE CHANNEL Sensitivity Sens(V) VPR (min) < VP < VPR (max) ACCURACY PERFORMANCE - VOLTAGE CHANNEL Total Output Error ETOT(V) TOTAL OUTPUT ERROR COMPONENTS - VOLTAGE CHANNEL Sensitivity Error Offset Error ESENS(V) EO(V) ACCURACY PERFORMANCE - ACTIVE POWER Total Output Error [1] ETOT(P) Typical values are based on mean 3 sigma. Allegro MicroSystems 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com 10 Single Phase, Isolated, AC Power Monitoring IC with Voltage Zero Crossing and Overcurrent Detection ACS71020 ACS71020KMA-030B3 PERFORMANCE CHARACTERISTICS: Valid through the full operating temperature range, TA = -40C to 125C, CBYPASS = 0.1 F, and VCC = 3.3 V, unless otherwise specified Characteristic Symbol Test Conditions Min. Typ. [1] Max. Unit - 3.3 - V -30 - 30 A - 1092 - LSB/A Measured at IP = IPR (max), TA = 25C to 125C - 2 - % Measured at IP = IPR (max), TA = -40C to 25C - 3 - % Measured at IP = IPR (max), TA = 25C to 125C - 1 - % Measured at IP = IPR (max), TA = -40C to 25C - 1.5 - % IP = 0 A, TA = 25C to 125C - 500 - LSB IP = 0 A, TA = -40C to 25C - 700 - LSB - 238 - LSB/mV Measured at VP = VPR (max), TA = 25C to 125C - 1.2 - % Measured at VP = VPR (max), TA = -40C to 25C - 1.3 - % Measured at VP = VPR (max), TA = 25C to 125C - 1 - % Measured at VP = VPR (max), TA = -40C to 25C - 1 - % VP = 0 mV, TA = 25C to 125C - 60 - LSB VP = 0 mV, TA = -40C to 25C - 80 - LSB Measured at VP = VPR (max), TA = 25C to 125C - 2.3 - % Measured at VP = VPR (max), TA = -40C to 25C - 3.3 - % GENERAL CHARACTERISTICS Nominal Supply Voltage VCC (nom) NOMINAL PERFORMANCE - CURRENT CHANNEL Current Sensing Range Sensitivity IPR Sens(I) IPR (min) < IP < IPR (max) ACCURACY PERFORMANCE - CURRENT CHANNEL Total Output Error ETOT(I) TOTAL OUTPUT ERROR COMPONENTS - CURRENT CHANNEL Sensitivity Error Offset Error ESENS(I) EO(I) NOMINAL PERFORMANCE - VOLTAGE CHANNEL Sensitivity Sens(V) VPR (min) < VP < VPR (max) ACCURACY PERFORMANCE - VOLTAGE CHANNEL Total Output Error ETOT(V) TOTAL OUTPUT ERROR COMPONENTS - VOLTAGE CHANNEL Sensitivity Error Offset Error ESENS(V) EO(V) ACCURACY PERFORMANCE - ACTIVE POWER Total Output Error [1] ETOT(P) Typical values are based on mean 3 sigma. Allegro MicroSystems 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com 11 Single Phase, Isolated, AC Power Monitoring IC with Voltage Zero Crossing and Overcurrent Detection ACS71020 ACS71020KMA-090B3 PERFORMANCE CHARACTERISTICS: Valid through the full operating temperature range, TA = -40C to 125C, CBYPASS = 0.1 F, and VCC = 3.3 V, unless otherwise specified Characteristic Symbol Test Conditions Min. Typ. [1] Max. Unit - 3.3 - V -90 - 90 A - 364 - LSB/A Measured at IP = IPR (max), TA = 25C to 125C - 2 - % Measured at IP = IPR (max), TA = -40C to 25C - 3 - % Measured at IP = IPR (max), TA = 25C to 125C - 1 - % Measured at IP = IPR (max), TA = -40C to 25C - 1.5 - % IP = 0 A, TA = 25C to 125C - 300 - LSB IP = 0 A, TA = -40C to 25C - 500 - LSB - 238 - LSB/mV Measured at VP = VPR (max), TA = 25C to 125C - 1.2 - % Measured at VP = VPR (max), TA = -40C to 25C - 1.3 - % Measured at VP = VPR (max), TA = 25C to 125C - 1 - % Measured at VP = VPR (max), TA = -40C to 25C - 1 - % VP = 0 mV, TA = 25C to 125C - 100 - LSB VP = 0 mV, TA = -40C to 25C - 150 - LSB Measured at VP = VPR (max), TA = 25C to 125C - 2.3 - % Measured at VP = VPR (max), TA = -40C to 25C - 3.3 - % GENERAL CHARACTERISTICS Nominal Supply Voltage VCC (nom) NOMINAL PERFORMANCE - CURRENT CHANNEL Current Sensing Range Sensitivity IPR Sens(I) IPR (min) < IP < IPR (max) ACCURACY PERFORMANCE - CURRENT CHANNEL Total Output Error ETOT(I) TOTAL OUTPUT ERROR COMPONENTS - CURRENT CHANNEL Sensitivity Error Offset Error ESENS(I) EO(I) NOMINAL PERFORMANCE - VOLTAGE CHANNEL Sensitivity Sens(V) VPR (min) < VP < VPR (max) ACCURACY PERFORMANCE - VOLTAGE CHANNEL Total Output Error ETOT(V) TOTAL OUTPUT ERROR COMPONENTS - VOLTAGE CHANNEL Sensitivity Error Offset Error ESENS(V) EO(V) ACCURACY PERFORMANCE - ACTIVE POWER Total Output Error [1] ETOT(P) Typical values are based on mean 3 sigma. Allegro MicroSystems 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com 12 Single Phase, Isolated, AC Power Monitoring IC with Voltage Zero Crossing and Overcurrent Detection ACS71020 DATA ACQUISITION ADCs Phase Compensation Both the Current and Voltage channels are sampled at a high frequency and then digitally filtered and decimated to avoid large anti-aliasing filters. The final sample rate will be near 32 kHz for an 8 MHz clock. The digital low-pass filters have a cutoff of 1kHz. The digital word from the ADC is 16 bits for both the current and the voltage. Phase delay may be introduced on either the voltage or current channels. The range is EEPROM selectable, either 5 of delay (step size of 0.67) or 40 of delay (step size of 5.36). Raw Signal Sensitivity and Offset Trim The gain and offset for both current and voltage channels use a shared temperature compensation engine which is trimmed in production. The fine sensitivity and offset are also trimmed in production at the factory; however, the user has access to the fine sensitivity field for the current channel should they want to trim the gain in application. Voltage Input Zero Crossing The zero crossings are only detected on the voltage signal. Both the high-to-low and low-to-high transitions will be detected with time-based hysteresis that removes the possibility of noise causing multiple zero crossings to be reported at each true zero crossing. The zero crossing output can be a square wave that transitions at each zero crossing or a pulse with a fixed width at each zero crossing. When in pulse mode, the width of the pulse is tP (see delaycnt_sel; nominal setting is 32s). There will be a fixed delay, tD, from the time that a true zero crossing has occurred to the time that it is reported. This delay helps to keep the zero crossing detection more precise. VZC Pulse Mode tP tD Square Wave Mode Figure 4: Zero Crossing Allegro MicroSystems 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com 13 Single Phase, Isolated, AC Power Monitoring IC with Voltage Zero Crossing and Overcurrent Detection ACS71020 POWER CALCULATIONS IRMS / VRMS Reactive Power Half cycle-by-cycle calculation of the root mean square of both the current and voltage channels: Imaginary component of power being measured; calculated at the end of each cycle: IRMS = nn == N0 - 1 In2 N VRMS = nn == N0 - 1 Vn2 N where In (Icodes) and Vn (Vcodes) are the instantaneous measurements of current and voltage, respectively. The figure below represents how the calculation is performed. Each voltage zero crossing determines end of the rms calculation window and also starts the next rms calculation window. S2 - PACTIVE2 Q= Power Factor The magnitude of the ratio of real power to apparent power; calculated at the end of each cycle: |PF| = PACTIVE |S| Lead/Lag The voltage leading or lagging the current will be communicated as a single bit. This bit also represents the sign of the Reactive Power. This is stored in the register field "posangle". Leading or lagging is determined by comparing the zero crossings of the voltage and current channels. POSPF = 0 POSANG = 0 Imaginary POSPF = 1 POSANG = 1 Figure 5 Apparent Power Lagging The magnitude of the complex power being measured; calculated at the end of each cycle: |S| = IRMS x VRMS Real POSPF = 0 POSANG = 1 Leading POSPF = 1 POSANG = 0 Active Power The real component of power being measured; calculated cycle by cycle: nn == N0 - 1 Pn PACTIVE = N Figure 6 Pn = In x Vn Allegro MicroSystems 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com 14 Single Phase, Isolated, AC Power Monitoring IC with Voltage Zero Crossing and Overcurrent Detection I r, tP n re a p Ap e ow V S= S= P2+Q2 Reactive Power, Q = VI sin ACS71020 Active Power, P = VI cos Figure 7: Power Triangle Allegro MicroSystems 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com 15 Single Phase, Isolated, AC Power Monitoring IC with Voltage Zero Crossing and Overcurrent Detection ACS71020 Overcurrent Fault The overcurrent fault threshold may be set from 50% to 175% of IP. The user sets the trip point with an 8-bit word. The user also has the ability to set the trip level digital delay. This allows for up to a 32 s delay on the Fault. Averaging Over Time IRMS or VRMS and PACTIVE may be averaged over a programmable number of updates. Note that either VMRS and IRMS can be averaged, not both. The number of averages is controlled by two different registers. There is an accumulator that averages the above values. A 7-bit number, rms_avg_1, is used to determine the number of averages. There is an additional accumulator that will be used to average the output of the first accumulator. There is a 10-bit number, rms_avg_2, that will be used to determine the number of averages for this accumulator. For optimal performance, setting an even number of averages for both accumulators is recommended. The combination of the two accumulator allows the user to select how long to average for as well as how often the values are updated. The exact time this averages over depends on n (the number of samples per cycle). Averages could be read in Reg 0x26 to 0x29. Over/Undervoltage Detection There are two flags that can be used to detect undervoltage and overvoltage. These flags have a programmable voltage trip level. Refer to the Digital I/O section for all possible configurations. Acve Power Averaging pinstant RMS Calculaon pacve Averaging Block 1 Averaging Block 2 RMS Calculaons rms_avg_1 vcodes RMS Calculaon n icodes rms_avg_2 Averaging Block 1 Averaging Block 2 RMS Calculaon iavgselen VRMS/IRMS Averaging Figure 8: ACS71020 Trim Diagram Allegro MicroSystems 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com 16 Single Phase, Isolated, AC Power Monitoring IC with Voltage Zero Crossing and Overcurrent Detection ACS71020 DIGITAL COMMUNICATION Communication Interfaces Registers and EEPROM The ACS71020 supports communication over 1MHz I2C and 10MHz SPI. However, the communication protocol is fixed during factory programming. Refer to the Selection Guide for more information. The ACS71020 MISO pin continues to drive the MISO line when CS goes high. This may prevent other devices from communicating properly. It is recommended that the ACS71020 be the only device on the SPI bus if using SPI communication. WRITE ACCESS The ACS71020 supports factory and customer EEPROM space as well as volatile registers. The customer access code must be sent prior to writing these customer EEPROM spaces. In addition, the device includes a set of free space EEPROM registers that are accessible with or without writing the access code. SPI READ ACCESS All EEPROM and volatile registers may be read at any time regardless of the access code. The SPI frame consists of: * The Master writes on the MOSI line the 7-bit address of the register to be read from or written to. EEPROM * The next bit on the MOSI line is the read/write (RW) indicator. A high state indicates a Read and a low state indicates a Write. At power up all shadow registers are loaded from EEPROM including all configuration parameters. The shadow registers can be written to in order to change the device behavior without having to perform an EEPROM write. Any changes made it shadow memory are volatile and do not persist through a reset event. * The device sends a 32-bit response on the MISO line. The contents correspond to the previous command. * On the MOSI line, if the current command is a write, the 32 bits correspond to the Write data, and in the case of a read, the data is ignored. WRITING The Timing Diagram for an EEPROM write is shown in Figure 9 and Figure 10. CSN SCLK 0 MOSI 1 5 6 REGISTER ADDRESS MISO 0 RW 1 30 31 WRITE DATA OR DC PREVIOUS CMD DATA Figure 9: EEPROM Write - SPI Mode SDA SA[6:0] ST A[6:0] D[7:0] D[7:0] D[7:0] D[7:0] Slave W A 0 Register A Register A Register A Register A Register A address C address C Data C Data C Data C Data C K K [7:0] K [15:8] K [23:16] K [31:24] K SP Figure 10: EEPROM Write - I2C Mode Blue represents data sent by the master and orange is the data sent by the slave. Allegro MicroSystems 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com 17 Single Phase, Isolated, AC Power Monitoring IC with Voltage Zero Crossing and Overcurrent Detection ACS71020 READING The timing diagram for an EEPROM read is shown in Figure 11 and Figure 12. CSN SCLK 0 MOSI 1 5 REGISTER ADDRESS MISO 6 0 RW 1 30 31 WRITE DATA OR DC PREVIOUS CMD DATA Figure 11: EEPROM Read - SPI Mode For SPI, the read data will be sent out during the above command. SDA SA[6:0] ST A[6:0] Slave W A 0 Register A ST address C address C K K SA[6:0] D[7:0] D[7:0] D[7:0] D[7:0] Slave R A Register A Register A Register A Register N address C Data C Data C Data C Data A K [7:0] K [15:8] K [23:16] K [31:24] C K SP Figure 12: EEPROM Read - I2C Mode Blue represents data sent by the master and orange is the data sent by the slave. Allegro MicroSystems 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com 18 ACS71020 Single Phase, Isolated, AC Power Monitoring IC with Voltage Zero Crossing and Overcurrent Detection EEPROM Error Checking and Correction (ECC) Hamming code methodology is implemented for EEPROM checking and correction (ECC). ECC is enabled after power-up. The ACS71020 analyzes message data sent by the controller and the ECC bits are added. The first 6 bits sent from the device to the controller are dedicated to ECC. The device always returns 32 bits. EEPROM ECC Errors Bits Name Description 31:28 - No meaning 27:26 ECC 25:0 D[25:0] 00 = No Error 01 = Error detected and message corrected 10 = Uncorrectable error 11 = No meaning EEPROM data Allegro MicroSystems 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com 19 Single Phase, Isolated, AC Power Monitoring IC with Voltage Zero Crossing and Overcurrent Detection ACS71020 MEMORY MAP Bits 0x1B crs_sns dio_0_sel 1 0 ichan_del_en qvo_fine overvreg unused rms_avg_1 ichan_del_en halfcycle_en 2 vevent_cycs pacc_trim vadc_rate_set delaycnt_sel undervreg 3 i2c_slv_addr sns_fine fault dio_1_sel 0x1F fltdly 4 pacc_trim rms_avg_2 squarewave_en Shadow 0x1E overvreg i2c_dis_slv_addr undervreg 0x1C 0x1D 5 vadc_rate_set fault chan_del_sel ECC fltdly i2c_dis_slv_addr 0x0F 6 rms_avg_1 chan_del_sel ECC 7 qvo_fine unused 0x0E 8 sns_fine dio_0_sel ECC 9 rms_avg_2 dio_1_sel 0x0D crs_sns delaycnt_sel ECC iavgselen 0x0C halfcycle_en ECC EEPROM 0x0B iavgselen 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 squarewave_en Address EEPROM/Shadow Memory vevent_cycs i2c_slv_addr Allegro MicroSystems 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com 20 Single Phase, Isolated, AC Power Monitoring IC with Voltage Zero Crossing and Overcurrent Detection ACS71020 Device Trim Flow The trim process for voltage, current, and power channels are depicted in Figure 13 through Figure 15. Refer to the "Register Details" Section for more information regarding trim fields. Gain Trim Delay Offset Trim adc_out_v Z VchanGainSel Saturaon -x + ichan_del_en vqvo chan_del_sel + + + vqvo_tc vcodes Factory Trim Figure 13: Voltage Channel Trim Flow Delay Offset Trim adc_out_i Gain Trim -x Z + Saturaon + icodes ichan_del_en qvo_fine ch an_del_sel + qvo_tc + sns_fine sns_tc Factory Trim Figure 14: Current Channel Trim Flow Offset Trim pacve_int + + pacve pacc_trim Figure 15: Power Channel Trim Flow Allegro MicroSystems 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com 21 Single Phase, Isolated, AC Power Monitoring IC with Voltage Zero Crossing and Overcurrent Detection ACS71020 Register Details - EEPROM Register 0x0B/0x1B Bits Name Default Value 8:0 qvo_fine - Description Offset fine trimming on current channel 17:9 sns_fine - Fine gain trimming on the current channel 20:18 crs_sns - Coarse gain setting 21 iavgselen - Current Averaging selection 25:22 unused - Unused 31:26 ecc - Error Code Correction qvo_fine crs_sns Offset adjustment for the current channel. This is a signed 9-bit number with an input range of -256 to 255. With a step size of 64LSB, this equates to an offset trim range of -16384 to 16320LSB, which is added to the icodes value. The trim is implemented as shown in Figure 14. The current channel's offset trim should be applied before the gain is trimmed. "qvo_fine" is further described in Table 1. Coarse gain adjustment for the current channel. This gain is implemented in the analog domain before the ADC. This is a 3-bit number that allows for 8 gain selections. Adjustments to "crs_sns" may impact the device's performance over temperature. Datasheet limits apply only to the factory settings for "crs_sns". The gain settings map to 1x, 2x, 3x, 3.5x, 4x, 4.5x, 5.5x, and 8x. "crs_sns" is further described in Table 3. Table 1: qvo_fine Table 3: crs_sns Range Value Units Range Value Units -256 to 255 -16,384 to 16,320 LSB 0 1x - 1 2x - 2 3x - 3 3.5x - 4 4x - 5 4.5x - 6 5.5x - 7 8x - sns_fine Gain adjustment for the current channel. This is a signed 9-bit number with an input range of -256 to 255. This gain adjustment is implemented as a percentage multiplier centered around 1 (i.e. writing a 0 to this field multiplies the gain by 1, leaving the gain unaffected). The fine sensitivity parameter ranges from 50% to 150% of IP. The current channel's offset trim should be applied before the gain is trimmed. "sns_fine" is further described in Table 2. Table 2: sns_fine Range Value Units -256 to 255 50 to 100 % iavgselen Current Averaging selection enable. 0 will select vrms for averaging. 1 will select irms for averaging. See Figure 8. Allegro MicroSystems 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com 22 Single Phase, Isolated, AC Power Monitoring IC with Voltage Zero Crossing and Overcurrent Detection ACS71020 Register 0x0C/0x1C Bits Name Default Value Description 6:0 rms_avg_1 0 Average of the rms voltage or current - stage 1 16:7 rms_avg_2 0 Average of the rms voltage or current - stage 2 25:17 - 0 Reserved 31:26 ecc - Error Code Correction rms_avg_1 Number of averages for the first averaging stage (vrmsavgonesec or irmsavgonesec). The value written into this field directly maps to the number of averages ranging from 0 to 127. For optimal performance, an even number of averages should be used. The channel to be averaged is selected by the "current average select enable" bit (iavgselen). "rms_avg_1" is further described in Table 4. Table 4: rms_avg_1 Range Value Units 0 to 127 0 to 127 number of averages rms_avg_2 Number of averages for the second averaging stage (vrmsavgonemin or irmsavgonemin). This stage averages the outputs of the first averaging stage. The value written into this field directly maps to the number of averages ranging from 0 to 1023. For optimal performance, an even number of averages should be used. The channel to be averaged is selected by the "current average select enable" bit (iavgselen). "rms_avg_2" is further described in Table 5. Table 5: rms_avg_2 Range Value Units 0 to 1023 0 to 1023 number of averages Allegro MicroSystems 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com 23 Single Phase, Isolated, AC Power Monitoring IC with Voltage Zero Crossing and Overcurrent Detection ACS71020 Register 0x0D/0x1D Bits Name Default Value Description 6:0 pacc_trim - Trims the active power 7 ichan_del_en 0 Enable phase delay on voltage or current channel 8 unused 0 unused 11:9 chan_del_sel 0 Sets phase delay on voltage or current channel 12 unused 0 unused 20:13 fault 255 23:21 fltdly 0 Sets the overcurrent fault delay 24 halfcycle_en 0 Outputs pulses at every zero crossing when enabled, and every rising edge when disabled 25 squarewave_en 0 Selects pulse or square wave output for the zero crossing reporting 31:26 ecc - Error Code Correction Sets the overcurrent fault threshold pacc_trim fault Offset trim in the active power calculation, and is implemented as shown in Figure 15. This is a signed 7-bit number with an input range of -64 to 63. This equates to a trim range of -384 to 378 LSB, which is added to the "pactive" value. "pacc_trim" is further described in Table 6. Overcurrent fault threshold. This is an usigned 8-bit number with an input range of 0 to 255, which equates to a fault range of 50% to 175% of IP. The factory setting of this field is 0. "fault" is further described in Table 9. Table 9: fault Table 6: pacc_trim Range Value Units -64 to 63 -384 to 378 LSB ichan_del_en Enables delay for either the voltage or current channel. Setting to 1 enables delay for the current channel. This behavior is depicted in Figure 13 and Figure 14. "ichan_del_en" is further described in Table 7. Table 7: ichan_del_en Range Value Units 0 0 - voltage channel LSB 1 1 - current channel LSB chan_del_sel Sets the amount of delay applied to the voltage or current channel (set by ichan_del_en). The step size of this field is determined by the value of vadc_rate_sel. "chan_del_sel" is further described in Table 8. Range Value Units 0 to 255 50 to 175 % of IP fltdly Fault delay setting of the amount of delay applied before flagging a fault condition. "fltdly" is further described in Table 10. Table 10: fltdly Range Value Units 0 0 s 1 0 s 2 4.75 s 3 9.25 s 4 13.75 s 5 18.5 s 6 23.25 s 7 27.75 s halfcycle_en Table 8: chan_del_sel vadc_rate_sel Range Value Units 0 0 to 7 0 to 219 s 1 0 to 7 0 to 875 s Setting for the voltage zero-crossing detection. When set to 0, the voltage zero-crossing will be indicated on every rising edge. When set to 1, the voltage zero-crossing will be indicated on both rising and falling edges. Allegro MicroSystems 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com 24 ACS71020 Single Phase, Isolated, AC Power Monitoring IC with Voltage Zero Crossing and Overcurrent Detection squarewave_en Setting for the Voltage Zero-Crossing Detection. When set to 0, the zero-crossing event will be indicated by a pulse on the DIO pin. When set to 1, the zero-crossing event will be indicated by a level change on the DIO pin. Note that the device must be configured to report Voltage-Zero-Crossing detection on the DIO pin. Allegro MicroSystems 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com 25 Single Phase, Isolated, AC Power Monitoring IC with Voltage Zero Crossing and Overcurrent Detection ACS71020 Register 0x0E/0x1E Bits Name Default Value Description 5:0 vevent_cycs 0 Sets the number of qualifying cycles needed to flag overvoltage or undervoltage 6 vadc_rate_set 0 Sample Frequency Selection 7 - 0 Reserved 13:8 overvreg 32 Sets the overvoltage fault threshold 19:14 undervreg 32 Sets the undervoltage fault threshold 20 delaycnt_sel 0 Sets the width of the voltage zero-crossing output pulse 25:21 unused 0 Unused 31:26 ecc - Error Code Correction vevent_cycs undervreg Sets the number of cycles required to assert the OVRMS flag or the UVRMS. This is an unsigned 6-bit number with an input range of 0 to 63. The value in this field directly maps to the number of cycles. "vevent_cycs" is further described in Table 11. Sets the threshold of the undervoltage rms flag (uvrms). This is a 6-bit number ranging from 0 to 63. This trip level spans one entire range of the vrms register. The flag is set if the rms value is below this threshold for the number of cycles selected in vevent_ cycs. "undervreg" is further described in Table 14. Table 11: vevent_cycs Range Value Units 0 to 63 1 to 64 cycles vadc_rate_set Sets the voltage ADC update rate. Setting this field to a 0 selects a 32kHz update. Setting this field to a 1 selects a 4 kHz update, which will reduce the number of samples used in each rms calculation, but will allow for a larger phase delay correction between channels (see chan_del_sel). "vadc_rate_set" is further described in Table 12. Table 12: vadc_rate_set Table 14: undervreg Range Value Units 0 to 63 0 to 32,768 LSB delaycnt_sel Selection bit for the width of pulse for a voltage zero-crossing event. When set to 0, the pulse is 32 s. When set to 1, the pulse is 256 s. When the squarewave_en bit is set, this field is ignored. "delaycnt_sel" is further described in Table 15. Table 15: delaycnt_sel Range Value Units Range Value Units 0 32 s 0 32 kHz 1 256 s 1 4 kHz overvreg Sets the threshold of the overvoltage rms flag (ovrms). This is a 6-bit number ranging from 0 to 63. This trip level spans the entire range of the vrms register. The flag is set if the rms value is above this threshold for the number of cycles selected in vevent_cycs. "overvreg" is further described in Table 13. Table 13: overvreg Range Value Units 0 to 63 0 to 32,768 LSB Allegro MicroSystems 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com 26 Single Phase, Isolated, AC Power Monitoring IC with Voltage Zero Crossing and Overcurrent Detection ACS71020 Register 0x0F/0x1F Bits Name Default Value Description 1:0 unused 0 Unused 8:2 i2c_slv_addr 0 I2C slave address selection 9 i2c_dis_slv_addr 0 Disable I2C slave address selection circuit 15:10 unused 0 Unused 17:16 dio_0_sel 0 Digital output 0 multiplexor selection bits 19:18 dio_1_sel 0 Digital output 1 multiplexor selection bits 25:20 unused 0 Unused 31:26 ecc - Error Code Correction i2c_slv_addr i2c_dis_slv_addr I2C Settings for the Slave Address. The Voltage on the DIO pins are measured at power and are used to set the device's slave address. Enables or disables the analog I2C slave address feature at power on. When this bit is set, the I2C slave address will map directly to i2c_slv_addr. Each DIO pin has 4 voltage "bins" which may be used to set the I2C slave address. These voltages may be set using resistor divider circuits from VCC to Ground. "i2c_slv_addr" is further described in Table 16. dio_0_sel Table 16: i2c_slv_addr DIO_1 (decimal) 0 0 0 0 1 1 1 1 2 2 2 2 3 3 3 3 DIO_0 (decimal) 0 1 2 3 0 1 2 3 0 1 2 3 0 1 2 3 Slave Address (decimal) 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 EEPROM value Determines which flags are output on the DIO0 pin. Only used when the device is in I2C programming mode. "dio_0_sel" is further described in Table 17. Table 17: dio_0_sel Value Selection 0 VZC: Voltage zero crossing 1 OVRMS: The VRMS overvoltage flag 2 UVRMS: The VRMS undervoltage flag 3 The OR of OVRMS and UVRMS (if either flag is triggered, the DIO_0 pin will be asserted) dio_1_sel Determines which flags are output on the DIO1 pin. Only used when the device is in I2C programming mode. "dio_1_sel" is further described in Table 18. Table 18: dio_1_sel Value Selection 0 OCF: Overcurrent fault 1 UVRMS: The VRMS undervoltage flag 2 OVRMS: The VRMS overvoltage flag 3 The OR of OVRMS, UVRMS, and OCF (if any of the three flags are triggered, the DIO_0 pin will be asserted). Ratio of VCC on DIO Pin Allegro MicroSystems 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com 27 ACS71020 Single Phase, Isolated, AC Power Monitoring IC with Voltage Zero Crossing and Overcurrent Detection 8 7 6 5 pactive 0x22 papparent 0x23 pimag 0x24 2 1 0 pfactor 0x25 numptsout 0x27 irmsavgonemin vrmsavgonesec vrmsavgonemin 0x28 pactavgonesec 0x29 pactavgonemin 0x2A vcodes 0x2B icodes pinstant 0x2D vzerocrossout irmsavgonesec overvoltage 0x26 pospf 0x2E 0x2F access_code customer_access VOLATILE 3 vrms 0x21 0x2C 4 faultout irms 9 faultlatched 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 undervoltage 0x20 Bits posangle Address Volatile Memory 0x30 0x31 Allegro MicroSystems 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com 28 Single Phase, Isolated, AC Power Monitoring IC with Voltage Zero Crossing and Overcurrent Detection ACS71020 Register Details - Volatile Register 0x20 Bits Name Description 14:0 vrms Voltage RMS value 30:16 irms Current RMS value vrms irms RMS voltage output. This field is an unsigned 15-bit fixed point number with 15 fractional bits. It ranges from 0 to ~1 with a step size of 1/215. This number should be multiplied by the overall full scale of the voltage path in order to get to volts. For example, the device is trimmed to a full scale input of 275 mV, and if a resistor divider network is used to create 275 mV when it has 250V across it, then the multiplier should be 250V. "vrms" is further described in Table 19. RMS current output. This field is an unsigned 15-bit fixed point number with 14 fractional bits. It ranges from 0 to ~2 with a step size of 1/214. This number should be multiplied by the overall full scale of the current path in order to get to amps. For example, if the device is trimmed to a full scale input of 30 A, then the multiplier should be 30A. "irms" is further described in Table 20. Table 19: vrms Range Value Units 0 to ~1 [0 to ~1] x VIN(MAX) V Table 20: irms Range Value Units 0 to ~2 [0 to ~2] x IPR(MAX) A Register 0x21 Bits Name Description 16:0 pactive Active power pactive Active power output. This field is a signed 17-bit fixed point number with 15 fractional bits. It ranges from -2 to ~2 with a step size of 1/215. This number should be multiplied by the overall full-scale power in order to get to watts. For example, if full-scale voltage is 250V and IPR is 30A, the multiplier will be 7500 W. "pactive" is further described in Table 21. Table 21: pactive Range Value Units -2 to ~2 [-2 to ~2] x MaxPow W Allegro MicroSystems 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com 29 Single Phase, Isolated, AC Power Monitoring IC with Voltage Zero Crossing and Overcurrent Detection ACS71020 Register 0x22 Bits Name Description 15:0 papparent Apparent power papparent Apparent power output. This field is an unsigned 16-bit fixed point number with 15 fractional bits. It ranges from 0 to ~2 with a step size of 1/215. This number should be multiplied by the overall full-scale power in order to get to VA. For example, if full scale voltage is 250V and IPR is 30A, then the multiplier will be 7500VA. "papparent" is further described in Table 22. Table 22: papparent Range Value Units 0 to ~2 [0 to ~2] x MaxPow VA Register 0x23 Bits Name Description 15:0 pimag Reactive power pimag Reactive power output. This field is an unsigned 16-bit fixed point number with 15 fractional bits. It ranges from 0 to ~2 with a step size of 1/215. This number should be multiplied by the overall full-scale power in order to get to VAR. For example, if full-scale voltage is 250V and IPR is 30A, then the multiplier will be 7500 VAR. "pimag" is further described in Table 23. Table 23: pimag Range Value Units 0 to ~2 [0 to ~2] x MaxPow VAR Allegro MicroSystems 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com 30 Single Phase, Isolated, AC Power Monitoring IC with Voltage Zero Crossing and Overcurrent Detection ACS71020 Register 0x24 Bits Name Description 10:0 pfactor Power factor pfactor Power factor output. This field is an signed 11-bit fixed point number with 9 fractional bits. It ranges from -2 to ~2 with a step size of 1/29. "pfactor" is further described in Table 24. Table 24: pfactor Range Value Units -2 to ~2 -2 to ~2 - Register 0x25 Bits Name 8:0 numptsout Description Number of samples of current and voltage used for calculations numptsout Number of points used in the rms calculation. This will be the dynamic value that is evaluated internal to the device based on zero crossings of the voltage channel. "numptsout" is further described in Table 25. Table 25: numptsout Range Value Units 0 to 511 0 to 511 - Allegro MicroSystems 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com 31 Single Phase, Isolated, AC Power Monitoring IC with Voltage Zero Crossing and Overcurrent Detection ACS71020 Register 0x26 Bits Name Description 14:0 vrmsavgonesec Averaged voltage RMS value - duration set by rms_avg_1 - This register will be zero if iavgselen = 1 30:16 irmsavgonesec Averaged current RMS value - duration set by rms_avg_1 - This register will be zero if iavgselen = 0 vrmsavgonesec irmsavgonesec Voltage RMS value averaged according to rms_avg_1. This register will be zero if iavgselen = 1. Current RMS value averaged according to rms_avg_1. This register will be zero if iavgselen = 0. Register 0x27 Bits Name 14:0 vrmsavgonemin Description Averaged voltage RMS value - duration set by rms_avg_2 - This register will be zero if iavgselen = 1 30:16 irmsavgonemin Averaged current RMS value - duration set by rms_avg_2 - This register will be zero if iavgselen = 0 vrmsavgonemin irmsavgonemin Voltage RMS value averaged according to rms_avg_2. This register will be zero if iavgselen = 1. Current RMS value averaged according to rms_avg_2. This register will be zero if iavgselen = 0. Register 0x28 Bits Name 16:0 pactavgonesec Description Active Power value averaged over up to one second -- duration set by rms_avg_1 pactavgonesec Active power value averaged according to rms_avg_1. Register 0x29 Bits Name 16:0 pactavgonemin Description Active Power value averaged over up to one minute -- duration set by rms_avg_2 pactavgonemin Active power value averaged according to rms_avg_2. Allegro MicroSystems 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com 32 Single Phase, Isolated, AC Power Monitoring IC with Voltage Zero Crossing and Overcurrent Detection ACS71020 Register 0x2A Bits Name Description 16:0 vcodes Instantaneous voltage measurement vcodes This field contains the instantaneous voltage measurement before any rms calculations are done. It is a 17-bit signed fixed point number with 16 fractional bits. It ranges from -1 to ~1 with a step size of 1/216. This number should be multiplied by the overall full scale of the voltage path in order to get volts. For example, the device is trimmed to a full-scale input of 275 mV, and if a resistor divider network is used to create 275 mV, when it has 250V across it, then the multiplier should be 250V. "vcodes" is further described in Table 26. Table 26: vcodes Range Value Units -1 to ~1 [-1 to ~1] x VIN(MAX) V Register 0x2B Bits Name Description 16:0 icodes Instantaneous current measurement icodes This field contains the instantaneous current measurement before any rms calculations are done. This field is a signed 17-bit fixed point number with 15 fractional bits. It ranges from -2 to ~2 with a step size of 1/215. This number should be multiplied by the overall full scale of the current path in order to get amps. For example, the device is trimmed to a full-scale input of 30 A, then the multiplier should be 30A. "icodes" is further described in Table 27. Table 27: icodes Range Value Units -2 to ~2 [-2 to ~2] x IPR(MAX) A Allegro MicroSystems 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com 33 Single Phase, Isolated, AC Power Monitoring IC with Voltage Zero Crossing and Overcurrent Detection ACS71020 Register 0x2C Bits Name 31:0 pinstant Description Instantaneous power - Multiplication of Vcodes and Icodes pinstant This field contains the instantaneous power measurement before any rms calculations are done. This field is a signed 32-bit fixed point number with 29 fractional bits. It ranges from -4 to ~4 with a step size of 1/229. This number should be multiplied by the overall full-scale power in order to get to watts. For example, if full scale voltage is 250V and IPR is 30A, then the multiplier will be 7500 W. "pinstant" is further described in Table 28. Table 28: pinstant Range Value Units -4 to ~4 [-4 to ~4] x MaxPow W Register 0x2D Bits Name 0 vzerocrossout 1 faultout Description Voltage zero-crossing output Current fault output 2 faultlatched Current fault output latched 3 overvoltage Overvoltage flag 4 undervoltage Undervoltage flag 5 posangle Sign of the power angle 6 pospf Sign of the power factor vzerocrossout overvoltage Flag for the voltage zero-crossing events. Will be present and active regardless of DIO_0_Sel and DIO_1_Sel. This flag will still follow the halfcycle_en and squarewave_en settings. Flag for the overvoltage events. Will be present and active regardless of DIO_0_Sel and DIO_1_Sel. Will only be set when fault is present. faultout undervoltage Flag for the overcurrent events. Will be present and active regardless of DIO_0_Sel and DIO_1_Sel. Will only be set when fault is present. Flag for the undervoltage events. Will be present and active regardless of DIO_0_Sel and DIO_1_Sel. Will only be set when fault is present. faultlatched posangle Flag for the overcurrent events. This bit will latch and will remain 1 as soon as an overcurrent event is detected. This can be reset by writing a 1 to this field. Will be present and active regardless of DIO settings. Bit to represent leading or lagging. A 0 represents the current leading and a 1 represents the current lagging. pospf Sign bit to represent if the power is being generated (0) or consumed (1). Allegro MicroSystems 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com 34 Single Phase, Isolated, AC Power Monitoring IC with Voltage Zero Crossing and Overcurrent Detection ACS71020 Register 0x2F Bits Name 31:0 access_code Description Access code register: Customer code: 0x4F70656E Register 0x30 Bits Name 0 customer_access Description Customer write access enabled. 0 = Non Customer mode. 1 = Customer mode. Allegro MicroSystems 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com 35 Single Phase, Isolated, AC Power Monitoring IC with Voltage Zero Crossing and Overcurrent Detection ACS71020 VOLTAGE INPUT APPLICATION CONNECTIONS Due to the input buffer Common Mode Input Voltage requirement there are possible two circuit configurations: VINN to 2/3 VCC. If the isolation state of the application is unknown, this schematic works in both cases. 1. In Figure 16: the neutral line must be isolated from the ground powering the device to allow the common mode voltage of VINN to sit at 2/3VCC. RSENSE should be sized according to the full-scale signal level that can be applied to the voltage channel 275mV and expected maximum measured voltage. 2. In Figure 17: capacitors block the DC component of the voltage input and allow the internal resistor divider to bias RSENSE values used in figures below are examples for AC 240Vrms input signal. VINP R1 R2 1 M 1 M RSENSE Vin VINN R3 R4 1 M 1 M Figure 16: Floating AC voltage source (device ground is isolated) C1 VINP 1 F R5 1 M R1 R2 1 M 1 M RSENSE Vin C2 Optional 1 F 1 M VINN 1 M Figure 17: Ground referenced AC voltage source (device GND is common with voltage source GND) Allegro MicroSystems 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com 36 Single Phase, Isolated, AC Power Monitoring IC with Voltage Zero Crossing and Overcurrent Detection ACS71020 APPLICATION INFORMATION Thermal Rise vs. Primary Current Self-heating due to the flow of current should be considered during the design of any current sensing system. The sensor, printed circuit board (PCB), and contacts to the PCB will generate heat as current moves through the system. The thermal response is highly dependent on PCB layout, copper thickness, cooling techniques, and the profile of the injected current. The current profile includes peak current, current "on-time", and duty cycle. While the data presented in this section was collected with direct current (DC), these numbers may be used to approximate thermal response for both AC signals and current pulses. The plot in Figure 18 shows the measured rise in steady-state die temperature of the ACS71020 versus continuous current at an ambient temperature, TA, of 25 C. The thermal offset curves may be directly applied to other values of TA. Conversely, Figure 19 shows the maximum continuous current at a given TA. Surges beyond the maximum current listed in Figure 19 are allowed given the maximum junction temperature, TJ(MAX) (165), is not exceeded. The thermal capacity of the ACS71020 should be verified by the end user in the application's specific conditions. The maximum junction temperature, TJ(MAX) (165), should not be exceeded. Further information on this application testing is available in the DC and Transient Current Capability application note on the Allegro website. ASEK71020 Evaluation Board Layout Thermal data shown in Figure 18 and Figure 19 was collected using the ASEK71020 Evaluation Board (TED-0002170). This board includes 1500 mm2 of 2 oz. copper (0.0694 mm) connected to pins 1 through 4, and to pins 5 through 8, with thermal vias connecting the layers. Top and Bottom layers of the PCB are shown below in Figure 20. Change in Die Temperature (C) 140 120 100 80 60 40 20 0 0 10 20 30 40 50 60 70 Continuous Current (A) Continuous Current (A) Figure 18: Self Heating in the MA Package Due to Current Flow 80 70 60 50 40 30 20 10 0 25 50 75 100 125 150 175 Ambient Temperature (C) Figure 19: Maximum Continuous Current at a Given TA Figure 20: Top and Bottom Layers for ASEK71020 Evaluation Board Gerber files for the ASEK71020 evaluation board are available for download from the Allegro website. See the technical documents section of the ACS71020 device webpage. Allegro MicroSystems 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com 37 Single Phase, Isolated, AC Power Monitoring IC with Voltage Zero Crossing and Overcurrent Detection ACS71020 RECOMMENDED PCB LAYOUT NOT TO SCALE All dimensions in millimeters. 15.75 9.54 0.65 1.27 Package Outline Slot in PCB to maintain >8 mm creepage once part is on PCB 2.25 7.25 1.27 3.56 17.27 Current Out Current In 21.51 Perimeter holes for stitching to the other, matching current trace design, layers of the PCB for enhanced thermal capability. Figure 21: Recommended PCB Layout Allegro MicroSystems 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com 38 Single Phase, Isolated, AC Power Monitoring IC with Voltage Zero Crossing and Overcurrent Detection ACS71020 PACKAGE OUTLINE DRAWING For Reference Only - Not for Tooling Use (Reference MS-013AA) NOT TO SCALE Dimensions in millimeters Dimensions exclusive of mold flash, gate burrs, and dambar protrusions Exact case and lead configuration at supplier discretion within limits shown 8 0 E 10.30 0.20 16 0.33 0.20 D D1 D2 7.50 0.10 10.30 0.33 A 1 1.27 1.40 REF 0.40 2 D 0.90 Branded Face 0.25 BSC SEATING PLANE 16x C 2.65 MAX 0.10 C GAUGE PLANE SEATING PLANE 0.30 0.10 1.27 BSC 0.51 0.31 0.65 1.27 16 XXXXXXX Lot Number 2.25 1 9.50 B Standard Branding Reference View Lines 1, 2 = 12 characters Line 1: Part Number Line 2: First 8 characters of Assembly Lot Number 1 C 2 PCB Layout Reference View A Terminal #1 mark area B Branding scale and appearance at supplier discretion C Reference land pattern layout (reference IPC7351 SOIC127P600X175-8M); all pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary to meet application process requirements and PCB layout tolerances D Hall elements (D1, D2), not to scale E Active Area Depth 0.293 mm Figure 22: Package MA, 16-Pin SOICW Allegro MicroSystems 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com 39 ACS71020 Single Phase, Isolated, AC Power Monitoring IC with Voltage Zero Crossing and Overcurrent Detection Revision History Number Date Description - June 20, 2018 Initial release 1 September 19, 2018 Updated Features and Benefits, Description (page 1), Isolation Characteristics, Thermal Characteristics (page 3), Power Calculations section (pages 13-14), Digital Communication (page 15), Register Details (pages 20-33), Applications Connections (page 34), and Package Outline Drawing (page 36). 2 December 14, 2018 Updated certification 3 January 10, 2019 4 March 15, 2019 5 April 29, 2019 Updated Figure 1 (page 1), Power Calculations section (page 14-16), Register 0x0C/0x1C (page 23), Table 16 (page27), Volatile Memory table (page 28), Register 28 (page 30), Register 0x2C (page 34), and Figure 17 (page 36); added Power-On Time (page 6) and DIO Pins characteristics (page 7). 6 May 15, 2019 Updated Creepage (page 3); added TUV certificate mark. 7 June 3, 2019 Updated Table 12 (page 26), register 0x28, and register 0x29 (page 32). 8 June 17, 2019 Updated posangle and pospf (page 34). 9 November 21, 2019 Updated register defaults (pages 20-22, 24-25), Voltage Input Application Connections section (page 34), bypass_n_en description (page 24), and pfactor description (page 29). Updated Title (all pages), Voltage Zero Crossing (page 6), ADCs section (page 12), Communication Interfaces section (page 15), Memory Map (page 18), Register 0x0C/0x1C (page 21), Register 0x0E/0x1E (page 24), Register 0x25 (page 29), and Application Connections (page 34). Added Operating Characteristics footnote (page 8). Added Maximum Continuous Current to Absolute Maximum Ratings table, Distance Through Insulation and Comparative Tracking Index to Isolation Characteristics table, ESD ratings table (page 3), and thermal data section (page 37) Copyright 2019, Allegro MicroSystems. Allegro MicroSystems reserves the right to make, from time to time, such departures from the detail specifications as may be required to permit improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the information being relied upon is current. Allegro's products are not to be used in any devices or systems, including but not limited to life support devices or systems, in which a failure of Allegro's product can reasonably be expected to cause bodily harm. The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems assumes no responsibility for its use; nor for any infringement of patents or other rights of third parties which may result from its use. Copies of this document are considered uncontrolled documents. For the latest version of this document, visit our website: www.allegromicro.com Allegro MicroSystems 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com 40