KM641001A CMOS SRAM
PRELIMINARY
Rev 5.0
- 1 - February 1998
Document Title
256Kx 4 High Speed Static RAM(5V Operating), Evolutionary Pin Out.
Operated at Commercial Temperature Range.
Revision History
The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the
specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters of this device. If you have any questions,
please contact the SAMSUNG branch office near your office, call or contact Headquarters.
Rev. No.
Rev. 0.0
Rev. 1.0
Rev. 2.0
Rev. 3.0
Rev. 4.0
Rev. 5.0
Remark
Design Target
Preliminary
Final
Final
Final
Final
History
Initial release with Design Target.
Release to Preliminary Data Sheet.
1.1. Replace Design Target to Preliminary
Release to final Data Sheet.
2.1. Delete Preliminary
Update D.C and A.C parameters.
3.1. Update D.C parameters
3.2. Update A.C parameters
Update D.C and A.C parameters
4.1. Update D.C and A.C parameters.
4.2. Add the test condition for VOH1 with VCC=5V±5% at 25°C
4.3. Add timing diagram to define tWP as ″(Timing Wave Form of
Write Cycle(CS=Controlled)″
5.1. Delete 17ns Part
Items Previous spec.
(15/17/20ns part) Updated spec.
(15/17/20ns part)
Icc 190/180/170mA 145/145/140mA
Isb 30mA 25mA
Isb1 10mA 8mA
Items Previous spec.
(15/17/20ns part) Updated spec.
(15/17/20ns part)
tCW 12/12/13ns 10/11/12ns
tAW 12/12/13ns 10/11/12ns
tWP1(OE=H) 12/12/13ns 10/11/12ns
tDW 8/9/10ns 7/8/9ns
Items Previous spec.
(15/17/20ns part) Updated spec.
(15/17/20ns part)
Icc 145/145/140mA 125/125/120mA
tOW 3/4/5ns 3/3/3ns
Draft Data
Jan. 18th, 1995
Apr. 22th, 1995
Feb. 29th, 1996
Jul. 16th, 1996
Jun. 2nd, 1997
Feb. 25th, 1998
KM641001A CMOS SRAM
PRELIMINARY
Rev 5.0
- 2 - February 1998
256K x 4 Bit (with OE)High-Speed CMOS Static RAM
GENERAL DESCRIPTIONFEATURES
• Fast Access Time 15, 20ns(Max.)
• Low Power Dissipation
Standby (TTL) : 25mA(Max.)
(CMOS) : 8mA(Max.)
Operating KM641001A - 15 : 125mA(Max.)
KM641001A - 20 : 120mA(Max.)
• Single 5.0V±10% Power Supply
• TTL Compatible Inputs and Outputs
• I/O Compatible with 3.3V Device
• Fully Static Operation
- No Clock or Refresh required
• Three State Outputs
• Standard Pin Configuration
KM641001AJ : 28-SOJ-400A
PIN FUNCTION
Pin Name Pin Function
A0 - A17 Address Inputs
WE Write Enable
CS Chip Select
OE Output Enable
I/O1 ~ I/O4Data Inputs/Outputs
VCC Power(+5.0V)
VSS Ground
N.C No Connection
The KM641001A is a 1,048,576-bit high-speed Static Random
Access Memory organized as 262,144 words by 4 bits. The
KM641001A uses 4 common input and output lines and has an
output enable pin which operates faster than address access
time at read cycle. The device is fabricated using SAMSUNG′s
advanced CMOS process and designed for high-speed circuit
technology. It is particularly well suited for use in high-density
high-speed system applications. The KM641001A is packaged
in a 400 mil 28-pin plastic SOJ.
PIN CONFIGURATION(Top View)
Clk Gen.
I/O1 ~ I/O4
CS
WE
OE
FUNCTIONAL BLOCK DIAGRAM
Row Select
Data
Cont. Column Select
CLK
Gen.
Pre-Charge Circuit
Memory Array
512 Rows
512x4 Columns
I/O Circuit &
SOJ
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
Vcc
A17
A16
A15
A14
A13
A12
A11
N.C
I/O4
I/O3
I/O2
I/O1
WE
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
CS
OE
Vss
A0 A11 A13 A15 A17
A1 A12 A14 A16
A2
A3
A4
A5
A6
A7
A8
A9
A10
KM641001A CMOS SRAM
PRELIMINARY
Rev 5.0
- 3 - February 1998
ABSOLUTE MAXIMUM RATINGS*
* Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect reliability.
Parameter Symbol Rating Unit
Voltage on Any Pin Relative to VSS VIN, VOUT -0.5 to 7.0 V
Voltage on VCC Supply Relative to VSS VCC -0.5 to 7.0 V
Power Dissipation PD1.0 W
Storage Temperature TSTG -65 to 150 °C
Operating Temperature TA0 to 70 °C
RECOMMENDED DC OPERATING CONDITIONS(TA=0 to 70°C)
* VIL(Min)=-2.0V a.c(Pulse Width ≤ 10ns) for I ≤ 20mA
** VIH(Max)=VCC + 2.0V a.c (Pulse Width ≤ 10ns) for I ≤ 20mA
Parameter Symbol Min Typ Max Unit
Supply Voltage VCC 4.5 5.0 5.5 V
Ground VSS 0 0 0 V
Input High Voltage VIH 2.2 -VCC + 0.5** V
Input Low Voltage VIL -0.5* -0.8 V
DC AND OPERATING CHARACTERISTICS(TA=0 to 70°C, Vcc=5.0V±10%, unless otherwise specified)
* VCC=5.0V, Temp =25°C
Parameter Symbol Test Conditions Min Max Unit
Input Leakage Current ILI VIN = VSS to VCC -2 2µA
Output Leakage Current ILO CS=VIH or OE=VIH or WE=VIL
VOUT=VSS to VCC -2 2µA
Operating Current ICC Min. Cycle, 100% Duty
CS=VIL, VIN = VIH or VIL, IOUT=0mA 15ns -125 mA
20ns -120
Standby Current ISB Min. Cycle, CS=VIH -25 mA
ISB1 f=0MHz, CS≥VCC-0.2V,
VIN≥VCC-0.2V or VIN≤ 0.2V -8mA
Output Low Voltage Level VOL IOL=8mA -0.4 V
Output High Voltage Level VOH IOH=-4mA 2.4 -V
VOH1*IOH1=-0.1mA -3.95 V
CAPACITANCE*(TA=25°C, f=1.0MHz)
* NOTE : Capacitance is sampled and not 100% tested.
Item Symbol Test Conditions MIN Max Unit
Input/Output Capacitance CI/O VI/O=0V -8pF
Input Capacitance CIN VIN=0V -6pF
KM641001A CMOS SRAM
PRELIMINARY
Rev 5.0
- 4 - February 1998
TEST CONDITIONS
Parameter Value
Input Pulse Levels 0V to 3V
Input Rise and Fall Times 3ns
Input and Output timing Reference Levels 1.5V
Output Loads See below
AC CHARACTERISTICS(TA=0 to 70°C, VCC=5.0V±10%, unless otherwise noted.)
READ CYCLE
Parameter Symbol KM641001A-15 KM641001A-20 Unit
Min Max Min Max
Read Cycle Time tRC 15 -20 -ns
Address Access Time tAA -15 -20 ns
Chip Select to Output tCO -15 -20 ns
Output Enable to Valid Output tOE -8-10 ns
Chip Enable to Low-Z Output tLZ 3-3-ns
Output Enable to Low-Z Output tOLZ 0-0-ns
Chip Disable to High-Z Output tHZ 0 6 0 8 ns
Output Disable to High-Z Output tOHZ 060 8 ns
Output Hold from Address Change tOH 3-3-ns
Chip Selection to Power Up Time tPU 0-0-ns
Chip Selection to Power DownTime tPD -15 -20 ns
Output Loads(A)
DOUT
30pF*
480Ω
255Ω
+5.0V
* Including Scope and Jig Capacitance
Output Loads(B)
DOUT
5pF*
480Ω
255Ω
for tHZ, tLZ, tWHZ, tOW, tOLZ & tOHZ
+5.0V
KM641001A CMOS SRAM
PRELIMINARY
Rev 5.0
- 5 - February 1998
WRITE CYCLE
Parameter Symbol KM641001A-15 KM641001A-20 Unit
Min Max Min Max
Write Cycle Time tWC 15 -20 -ns
Chip Select to End of Write tCW 10 -12 -ns
Address Set-up Time tAS 0-0-ns
Address Valid to End of Write tAW 10 -12 -ns
Write Pulse Width(OE High) tWP 10 -12 -ns
Write Pulse Width(OE Low) tWP1 15 -20 -ns
Write Recovery Time tWR 0-0-ns
Write to Output High-Z tWHZ 0 8 0 10 ns
Data to Write Time Overlap tDW 7-9-ns
Data Hold from Write Time tDH 0-0-ns
End Write to Output Low-Z tOW 3-3-ns
Address
Data Out Previous Valid Data Valid Data
TIMMING DIAGRAMS
TIMING WAVEFORM OF READ CYCLE(1) (Address Controlled, CS=OE=VIL, WE=VIH)
tAA
tRC
tOH
TIMING WAVEFORM OF READ CYCLE(2) (WE=VIH)
CS
Address
OE
Data out
tAA
tOLZ
tLZ(4,5)
tOH
tOHZ
tRC
tOE
tCO
tPU tPD
tHZ(3,4,5)
50%
50%
VCC
Current
ICC
ISB
Valid Data
KM641001A CMOS SRAM
PRELIMINARY
Rev 5.0
- 6 - February 1998
NOTES(READ CYCLE)
1. WE is high for read cycle.
2. All read cycle timing is referenced from the last valid address to the first transition address.
3. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit condition and are not referenced to
VOH or VOL levels.
4. At any given temperature and voltage condition, tHZ(Max.) is less than tLZ(Min.) both for a given device and from
device to device.
5. Transition is measured ±200mV from steady state voltage with Load(B). This parameter is sampled and not 100%
tested.
6. Device is continuously selected with CS=VIL.
7. Address valid prior to coincident with CS transition low.
8. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and
write cycle.
TIMING WAVEFORM OF WRITE CYCLE(1) (OE= Clock)
Address
CS
tWP(2)
tDW tDH
Valid Data
WE
Data in
Data out
tWC
tWR(5)
tAW
tCW(3)
High-Z(8)
High-Z
OE
tOHZ(6)
tAS(4)
TIMING WAVEFORM OF WRITE CYCLE(2) (OE=Low Fixed)
Address
CS
tWP1(2)
tDW tDH
tOW
tWHZ(6) Valid Data
WE
Data in
Data out
tWC
tAS(4)
tWR(5)
tAW tCW(3)
(10) (9)
High-Z(8)
High-Z
KM641001A CMOS SRAM
PRELIMINARY
Rev 5.0
- 7 - February 1998
NOTES(WRITE CYCLE)
1. All write cycle timing is referenced from the last valid address to the first transition address.
2. A write occurs during the overlap of a low CS and WE. A write begins at the latest transition CS going low and WE going low ;
A write ends at the earliest transition CS going high or WE going high. tWP is measured from the beginning of write to the end of
write.
3. tCW is measured from the later of CS going low to end of write.
4. tAS is measured from the address valid to the beginning of write.
5. tWR is measured from the end of write to the address change. tWR applied in case a write ends as CS or WE going high.
6. If OE, CS and WE are in the Read Mode during this period, the I/O pins are in the output low-Z state. Inputs of opposite phase of
the output must not be applied because bus contention can occur.
7. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycle.
8. If CS goes low simultaneously with WE going or after WE going low, the outputs remain high impedance state.
9. Dout is the read data of the new address.
10.When CS is low : I/O pins are in the output state. The input signals in the opposite phase leading to the output should not be
applied.
FUNCTIONAL DESCRIPTION
* NOTE : X means Don′t Care.
CS WE OE Mode I/O Pin Supply Current
HXX* Not Select High-Z ISB, ISB1
LH H Output Disable High-Z ICC
LHLRead DOUT ICC
L L XWrite DIN ICC
TIMING WAVEFORM OF WRITE CYCLE(3) (CS=Controlled)
Address
CS
tAW
tDW tDH
Valid Data
WE
Data in
Data out High-Z High-Z(8)
tCW(3)
tWP(2)
tAS(4)
tWC
tWR(5)
High-Z
High-Z
tLZ tWHZ(6)
KM641001A CMOS SRAM
PRELIMINARY
Rev 5.0
- 8 - February 1998
PACKAGE DIMENSIONS
Units:millimeters/Inches
0.95
#1
28-SOJ-400A
#28
18.41 ±0.12
0.725 ±0.005
( )
0.0375
10.16
0.400
+0.10
MAX
18.82
0.741
0.20 -0.05
+0.10
0.008 -0.002
9.40 ±0.25
0.370 ±0.010
MAX
0.148
3.76
1.27
( )
0.050
1.32
( )
0.052
+0.10
0.43 -0.05
+0.004
0.017 -0.002 +0.10
0.71 -0.05
+0.004
0.028 -0.002
#14
#15
11.18 ±0.12
0.440 ±0.005
MIN
0.69
0.027
1.27
0.050
0.004
0.10 MAX
